Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (257 commits)
[ARM] Update mach-types
ARM: 5636/1: Move vendor enum to AMBA include
ARM: Fix pfn_valid() for sparse memory
[ARM] orion5x: Add LaCie NAS 2Big Network support
[ARM] pxa/sharpsl_pm: zaurus c3000 aka spitz: fix resume
ARM: 5686/1: at91: Correct AC97 reset line in at91sam9263ek board
ARM: 5640/1: This patch modifies the support of AC97 on the at91sam9263 ek board
ARM: 5689/1: Update default config of HP Jornada 700-series machines
ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem
ARM: 5688/1: ks8695_serial: disable_irq() lockup
ARM: 5687/1: fix an oops with highmem
ARM: 5684/1: Add nuc960 platform to w90x900
ARM: 5683/1: Add nuc950 platform to w90x900
ARM: 5682/1: Add cpu.c and dev.c and modify some files of w90p910 platform
ARM: 5626/1: add suspend/resume functions to amba-pl011 serial driver
ARM: 5625/1: fix hard coded 4K resource size in amba bus detection
MMC: MMCI: convert realview MMC to use gpiolib
ARM: 5685/1: Make MMCI driver compile without gpiolib
ARM: implement highpte
ARM: Show FIQ in /proc/interrupts on CONFIG_FIQ
...
Fix up trivial conflict in arch/arm/kernel/signal.c.
It was due to the TIF_NOTIFY_RESUME addition in commit d0420c83f ("KEYS:
Extend TIF_NOTIFY_RESUME to (almost) all architectures") and follow-ups.
This commit is contained in:
@@ -36,6 +36,11 @@ struct amba_driver {
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struct amba_id *id_table;
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};
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enum amba_vendor {
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AMBA_VENDOR_ARM = 0x41,
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AMBA_VENDOR_ST = 0x80,
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};
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#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
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#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
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@@ -0,0 +1,80 @@
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/* linux/amba/pl093.h
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*
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* Copyright (c) 2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* AMBA PL093 SSMC (synchronous static memory controller)
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* See DDI0236.pdf (r0p4) for more details
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */
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/* Offsets for SMBxxxxRy registers */
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#define SMBIDCYR (0x00)
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#define SMBWSTRDR (0x04)
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#define SMBWSTWRR (0x08)
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#define SMBWSTOENR (0x0C)
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#define SMBWSTWENR (0x10)
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#define SMBCR (0x14)
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#define SMBSR (0x18)
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#define SMBWSTBRDR (0x1C)
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/* Masks for SMB registers */
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#define IDCY_MASK (0xf)
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#define WSTRD_MASK (0xf)
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#define WSTWR_MASK (0xf)
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#define WSTOEN_MASK (0xf)
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#define WSTWEN_MASK (0xf)
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/* Notes from datasheet:
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* WSTOEN <= WSTRD
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* WSTWEN <= WSTWR
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*
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* WSTOEN is not used with nWAIT
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*/
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/* SMBCR bit definitions */
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#define SMBCR_BIWRITEEN (1 << 21)
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#define SMBCR_ADDRVALIDWRITEEN (1 << 20)
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#define SMBCR_SYNCWRITE (1 << 17)
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#define SMBCR_BMWRITE (1 << 16)
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#define SMBCR_WRAPREAD (1 << 14)
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#define SMBCR_BIREADEN (1 << 13)
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#define SMBCR_ADDRVALIDREADEN (1 << 12)
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#define SMBCR_SYNCREAD (1 << 9)
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#define SMBCR_BMREAD (1 << 8)
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#define SMBCR_SMBLSPOL (1 << 6)
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#define SMBCR_WP (1 << 3)
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#define SMBCR_WAITEN (1 << 2)
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#define SMBCR_WAITPOL (1 << 1)
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#define SMBCR_RBLE (1 << 0)
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#define SMBCR_BURSTLENWRITE_MASK (3 << 18)
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#define SMBCR_BURSTLENWRITE_4 (0 << 18)
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#define SMBCR_BURSTLENWRITE_8 (1 << 18)
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#define SMBCR_BURSTLENWRITE_RESERVED (2 << 18)
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#define SMBCR_BURSTLENWRITE_CONTINUOUS (3 << 18)
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#define SMBCR_BURSTLENREAD_MASK (3 << 10)
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#define SMBCR_BURSTLENREAD_4 (0 << 10)
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#define SMBCR_BURSTLENREAD_8 (1 << 10)
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#define SMBCR_BURSTLENREAD_16 (2 << 10)
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#define SMBCR_BURSTLENREAD_CONTINUOUS (3 << 10)
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#define SMBCR_MW_MASK (3 << 4)
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#define SMBCR_MW_8BIT (0 << 4)
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#define SMBCR_MW_16BIT (1 << 4)
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#define SMBCR_MW_M32BIT (2 << 4)
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/* SSMC status registers */
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#define SSMCCSR (0x200)
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#define SSMCCR (0x204)
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#define SSMCITCR (0x208)
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#define SSMCITIP (0x20C)
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#define SSMCITIOP (0x210)
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