From a3fd10732d276d7cf372c6746a78a1c8b6aa7541 Mon Sep 17 00:00:00 2001 From: Zev Weiss Date: Thu, 23 Feb 2023 16:03:58 -0800 Subject: [PATCH 0001/1040] ARM: dts: aspeed: romed8hm3: Fix GPIO polarity of system-fault LED Turns out it's in fact not the same as the heartbeat LED. Signed-off-by: Zev Weiss Cc: stable@vger.kernel.org # v5.18+ Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC") Link: https://lore.kernel.org/r/20230224000400.12226-2-zev@bewilderbeest.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts index ff4c07c69af1..00efe1a93a69 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts @@ -31,7 +31,7 @@ }; system-fault { - gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; panic-indicator; }; }; From 8bc5ae1d2b207b855010591adeace94f9ec4caf2 Mon Sep 17 00:00:00 2001 From: Zev Weiss Date: Thu, 23 Feb 2023 16:03:59 -0800 Subject: [PATCH 0002/1040] ARM: dts: aspeed: e3c246d4i: Add PECI device Now that we've got driver support for it, we might as well enable and use it. Signed-off-by: Zev Weiss Link: https://lore.kernel.org/r/20230224000400.12226-3-zev@bewilderbeest.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index 9b4cf5ebe6d5..67a75aeafc2b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -202,3 +202,7 @@ status = "okay"; aspeed,lpc-io-reg = <0xca2>; }; + +&peci0 { + status = "okay"; +}; From 9dedb724446913ea7b1591b4b3d2e3e909090980 Mon Sep 17 00:00:00 2001 From: Zev Weiss Date: Thu, 23 Feb 2023 16:04:00 -0800 Subject: [PATCH 0003/1040] ARM: dts: aspeed: asrock: Correct firmware flash SPI clocks While I'm not aware of any problems that have occurred running these at 100 MHz, the official word from ASRock is that 50 MHz is the correct speed to use, so let's be safe and use that instead. Signed-off-by: Zev Weiss Cc: stable@vger.kernel.org Fixes: 2b81613ce417 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC") Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC") Link: https://lore.kernel.org/r/20230224000400.12226-4-zev@bewilderbeest.net Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 +- arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index 67a75aeafc2b..c4b2efbfdf56 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -63,7 +63,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-max-frequency = <100000000>; /* 100 MHz */ + spi-max-frequency = <50000000>; /* 50 MHz */ #include "openbmc-flash-layout.dtsi" }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts index 00efe1a93a69..4554abf0c7cd 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts @@ -51,7 +51,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; - spi-max-frequency = <100000000>; /* 100 MHz */ + spi-max-frequency = <50000000>; /* 50 MHz */ #include "openbmc-flash-layout-64.dtsi" }; }; From 4a25aa8a308831f137a542e2cedf7a507301b0fc Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Fri, 13 Jan 2023 10:54:14 +0100 Subject: [PATCH 0004/1040] ARM: dts: imx7d: add node for PXP The i.MX7d contains a Pixel Pipeline in version 3.0. Add the device tree node to make it available. Signed-off-by: Michael Tretter Reviewed-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 7ceb7c09f7ad..4b94b8afb55d 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -165,6 +165,15 @@ reg = <0x306d0000 0x10000>; status = "disabled"; }; + + pxp: pxp@30700000 { + compatible = "fsl,imx7d-pxp"; + reg = <0x30700000 0x10000>; + interrupts = , + ; + clocks = <&clks IMX7D_PXP_CLK>; + clock-names = "axi"; + }; }; &aips3 { From 006ab3142f313129e505375f68a0e5fda1c5a5d4 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:27 +0100 Subject: [PATCH 0005/1040] ARM: dts: imx6qdl: use enet_clk_ref instead of enet_out for the FEC node Old imx6q machine code makes RGMII/RMII clock direction decision based on configuration of "ptp" clock. "enet_out" is not used and make no real sense, since we can't configure it as output or use it as clock provider. Instead of "enet_out" use "enet_clk_ref" which is actual selector to choose between internal and external clock source: FEC MAC <---------- enet_clk_ref <--------- SoC PLL \ ^------<-> refclock PAD (bi directional) Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 41e08fa23cce..b72ec745f6d1 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1049,8 +1049,8 @@ clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; + <&clks IMX6QDL_CLK_ENET_REF_SEL>; + clock-names = "ipg", "ahb", "ptp", "enet_clk_ref"; fsl,stop-mode = <&gpr 0x34 27>; nvmem-cells = <&fec_mac_addr>; nvmem-cell-names = "mac-address"; From d289654fd62b5fc21b81e23ead100e4d47ee2db7 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:28 +0100 Subject: [PATCH 0006/1040] ARM: dts: imx6dl-lanmcu: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-lanmcu.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-lanmcu.dts b/arch/arm/boot/dts/imx6dl-lanmcu.dts index 6b6e6fcdea9c..fa823988312d 100644 --- a/arch/arm/boot/dts/imx6dl-lanmcu.dts +++ b/arch/arm/boot/dts/imx6dl-lanmcu.dts @@ -21,6 +21,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; backlight: backlight { @@ -109,14 +110,17 @@ status = "okay"; }; +&clks { + clocks = <&clock_ksz8081>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clock_ksz8081>; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clock_ksz8081>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rgmii_phy>; status = "okay"; From aad004c1382c186d1c787155f8ce8a5ee98a9974 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:29 +0100 Subject: [PATCH 0007/1040] ARM: dts: imx6dl-alti6p: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-alti6p.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts index e8325fd680d9..e6a4e2770640 100644 --- a/arch/arm/boot/dts/imx6dl-alti6p.dts +++ b/arch/arm/boot/dts/imx6dl-alti6p.dts @@ -22,6 +22,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; i2c2-mux { @@ -191,6 +192,13 @@ status = "okay"; }; +&clks { + clocks = <&clock_ksz8081>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clock_ksz8081>; +}; + &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -208,10 +216,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clock_ksz8081>; - clock-names = "ipg", "ahb", "ptp"; status = "okay"; mdio { From 5417c655b98ed385d18695a9fbb384883a0d1f47 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:30 +0100 Subject: [PATCH 0008/1040] ARM: dts: imx6dl-plybas: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plybas.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-plybas.dts b/arch/arm/boot/dts/imx6dl-plybas.dts index c52e6caf3996..e98046eea7a4 100644 --- a/arch/arm/boot/dts/imx6dl-plybas.dts +++ b/arch/arm/boot/dts/imx6dl-plybas.dts @@ -75,6 +75,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_5v0: regulator-5v0 { @@ -99,6 +100,13 @@ status = "okay"; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -116,10 +124,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rgmii_phy>; status = "okay"; From 887185649c7ee8a9cc2d4e94de92bbbae6cd3747 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:31 +0100 Subject: [PATCH 0009/1040] ARM: dts: imx6dl-plym2m: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-plym2m.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index 522660c912a0..e3c10483f33b 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -84,6 +84,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_3v3: regulator-3v3 { @@ -173,6 +174,13 @@ status = "okay"; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -254,10 +262,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rgmii_phy>; status = "okay"; From 03c8a3c719884cb6a7e0f1cb328d58ee13d445d7 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:32 +0100 Subject: [PATCH 0010/1040] ARM: dts: imx6dl-prtmvt: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtmvt.dts | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-prtmvt.dts b/arch/arm/boot/dts/imx6dl-prtmvt.dts index 1f8cddd83ccb..5f4fa796ca18 100644 --- a/arch/arm/boot/dts/imx6dl-prtmvt.dts +++ b/arch/arm/boot/dts/imx6dl-prtmvt.dts @@ -193,6 +193,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_1v8: regulator-1v8 { @@ -293,8 +294,10 @@ }; &clks { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>; + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, <&clk50m_phy>; }; &ecspi1 { @@ -314,10 +317,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rmii_phy>; status = "okay"; From 2c23a919d655700f2b567ced1ed0307bfdede05e Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:33 +0100 Subject: [PATCH 0011/1040] ARM: dts: imx6dl-victgo: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-victgo.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index 72df1dba83be..23274be08e61 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -54,6 +54,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; rotary-encoder { @@ -134,6 +135,13 @@ }; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &ecspi2 { cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -182,10 +190,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rmii_phy>; status = "okay"; From c812c91bda8d3b4d9ea23c52bf88a20de64f7487 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:34 +0100 Subject: [PATCH 0012/1040] ARM: dts: imx6q-prtwd2: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-prtwd2.dts | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-prtwd2.dts b/arch/arm/boot/dts/imx6q-prtwd2.dts index 349959d38020..54a57a4548e2 100644 --- a/arch/arm/boot/dts/imx6q-prtwd2.dts +++ b/arch/arm/boot/dts/imx6q-prtwd2.dts @@ -22,6 +22,13 @@ reg = <0x80000000 0x20000000>; }; + clk50m_phy: phy-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; + }; + usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -49,13 +56,17 @@ status = "okay"; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>; - clock-names = "ipg", "ahb"; status = "okay"; fixed-link { From c89614079e447824786a3064758ef7e53c3eddc3 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:35 +0100 Subject: [PATCH 0013/1040] ARM: dts: imx6qdl-skov-cpu: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi index 3def1b621c8e..2731faede1cb 100644 --- a/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/imx6qdl-skov-cpu.dtsi @@ -105,6 +105,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_3v3: regulator-3v3 { @@ -232,13 +233,16 @@ }; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-mode = "rmii"; phy-supply = <®_3v3>; status = "okay"; From 088e350d2bb29756671f73639e65ba2b897e57a4 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:36 +0100 Subject: [PATCH 0014/1040] ARM: dts: imx6dl-eckelmann-ci4x10: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts index 864dc5018451..33825b5a8f26 100644 --- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -28,6 +28,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_usb_h1_vbus: regulator-usb-h1-vbus { @@ -64,6 +65,13 @@ status = "okay"; }; +&clks { + clocks = <&rmii_clk>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&rmii_clk>; +}; + &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; @@ -297,11 +305,6 @@ phy-mode = "rmii"; phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; phy-handle = <&phy>; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&rmii_clk>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp", "enet_out"; status = "okay"; mdio { From 8940c105273fcde00a60023f68f8a5b75e1df0cc Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:40 +0100 Subject: [PATCH 0015/1040] ARM: dts: imx6ul: set enet_clk_ref to CLK_ENETx_REF_SEL IMX6UL_CLK_ENETx_REF is behind of CLK_ENETx_REF_SEL: FEC MAC <---------- CLK_ENETx_REF_SEL <--------- CLK_ENETx_REF \ ^------<-> CLK_ENETx_REF_PAD We should point to the clock selector instead. So, we will be able to use external clock source from CLK_ENETx_REF_PAD as well. At same time, remove enet_out clk. It is using always the same clock as enet_clk_ref and do not help to solve any challenges of this HW. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index f0a9139748b8..3d9d0f823568 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -531,10 +531,9 @@ clocks = <&clks IMX6UL_CLK_ENET>, <&clks IMX6UL_CLK_ENET_AHB>, <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET2_REF_125M>, - <&clks IMX6UL_CLK_ENET2_REF_125M>; + <&clks IMX6UL_CLK_ENET2_REF_SEL>; clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; + "enet_clk_ref"; fsl,num-tx-queues = <1>; fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 4>; @@ -879,10 +878,9 @@ clocks = <&clks IMX6UL_CLK_ENET>, <&clks IMX6UL_CLK_ENET_AHB>, <&clks IMX6UL_CLK_ENET_PTP>, - <&clks IMX6UL_CLK_ENET_REF>, - <&clks IMX6UL_CLK_ENET_REF>; + <&clks IMX6UL_CLK_ENET1_REF_SEL>; clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; + "enet_clk_ref"; fsl,num-tx-queues = <1>; fsl,num-rx-queues = <1>; fsl,stop-mode = <&gpr 0x10 3>; From 37c24ed660e4ddaa1a562c75b158128a5515571e Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:42 +0100 Subject: [PATCH 0016/1040] ARM: dts: imx6ul-prti6g: configure ethernet reference clock parent On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Without this patch we have relatively high amount of dropped packets. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-prti6g.dts | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-prti6g.dts b/arch/arm/boot/dts/imx6ul-prti6g.dts index c18390f238e1..b7c96fbe7a91 100644 --- a/arch/arm/boot/dts/imx6ul-prti6g.dts +++ b/arch/arm/boot/dts/imx6ul-prti6g.dts @@ -26,6 +26,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet1_ref_pad"; }; leds { @@ -60,6 +61,13 @@ status = "okay"; }; +&clks { + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&clock_ksz8081_out>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "enet1_ref_pad"; + assigned-clocks = <&clks IMX6UL_CLK_ENET1_REF_SEL>; + assigned-clock-parents = <&clock_ksz8081_out>; +}; + &ecspi1 { cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -85,12 +93,6 @@ pinctrl-0 = <&pinctrl_eth1>; phy-mode = "rmii"; phy-handle = <&rmii_phy>; - clocks = <&clks IMX6UL_CLK_ENET>, - <&clks IMX6UL_CLK_ENET_AHB>, - <&clks IMX6UL_CLK_ENET_PTP>, - <&clock_ksz8081_out>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref"; status = "okay"; mdio { From 189cfa849d22c6ec39e7fac8d573075b35f865a2 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 31 Jan 2023 10:53:40 +0100 Subject: [PATCH 0017/1040] firmware: imx: scu: use dev_err_probe This simplifies the code and silences -517 error messages. Also the reason is listed in /sys/kernel/debug/devices_deferred. Signed-off-by: Alexander Stein Reviewed-by: Mukesh Ojha Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/imx/imx-scu.c b/drivers/firmware/imx/imx-scu.c index dca79caccd01..47db49911e7b 100644 --- a/drivers/firmware/imx/imx-scu.c +++ b/drivers/firmware/imx/imx-scu.c @@ -310,9 +310,8 @@ static int imx_scu_probe(struct platform_device *pdev) sc_chan->ch = mbox_request_channel_byname(cl, chan_name); if (IS_ERR(sc_chan->ch)) { ret = PTR_ERR(sc_chan->ch); - if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to request mbox chan %s ret %d\n", - chan_name, ret); + dev_err_probe(dev, ret, "Failed to request mbox chan %s\n", + chan_name); kfree(chan_name); return ret; } From 2a88e4792c6df4b6a93f2bdb1eaf0df7408bd40d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2023 15:58:54 -0600 Subject: [PATCH 0018/1040] bus: imx-weim: Remove open coded "ranges" parsing "ranges" is a standard property and we have common helper functions for parsing it, so let's use them. Signed-off-by: Rob Herring Signed-off-by: Shawn Guo --- drivers/bus/imx-weim.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index 2a6b4f676458..a8fd41e8114e 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -86,8 +87,8 @@ MODULE_DEVICE_TABLE(of, weim_id_table); static int imx_weim_gpr_setup(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - struct property *prop; - const __be32 *p; + struct of_range_parser parser; + struct of_range range; struct regmap *gpr; u32 gprvals[4] = { 05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */ @@ -106,13 +107,13 @@ static int imx_weim_gpr_setup(struct platform_device *pdev) return 0; } - of_property_for_each_u32(np, "ranges", prop, p, val) { - if (i % 4 == 0) { - cs = val; - } else if (i % 4 == 3 && val) { - val = (val / SZ_32M) | 1; - gprval |= val << cs * 3; - } + if (of_range_parser_init(&parser, np)) + goto err; + + for_each_of_range(&parser, &range) { + cs = range.bus_addr >> 32; + val = (range.size / SZ_32M) | 1; + gprval |= val << cs * 3; i++; } From 300bd129f93ffc4dccb591cdd5aef378f0461467 Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Wed, 8 Feb 2023 07:56:35 +0100 Subject: [PATCH 0019/1040] firmware: imx: scu-pd: add missed lvds lpi2c and pwm power domains LVDS' lpi2c and pwm power domains definitions are missed. Add them here. Signed-off-by: Clark Wang Reviewed-by: Frank Li Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index 2a4f07423365..84b673427073 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -180,7 +180,11 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* LVDS SS */ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, + { "lvds0-pwm", IMX_SC_R_LVDS_0_PWM_0, 1, false, 0 }, + { "lvds0-lpi2c", IMX_SC_R_LVDS_0_I2C_0, 2, true, 0 }, { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, + { "lvds1-pwm", IMX_SC_R_LVDS_1_PWM_0, 1, false, 0 }, + { "lvds1-lpi2c", IMX_SC_R_LVDS_1_I2C_0, 2, true, 0 }, /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, From f88f3dcbb145a0133292d5c9d8da5935a36c8914 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:07:54 +0100 Subject: [PATCH 0020/1040] arm64: dts: amlogic: meson-sm1-bananapi: correct usb-hub hog node name Fixes the following bindings check error: usb-hub: $nodename:0: 'usb-hub' does not match '^(hog-[0-9]+|.+-hog(-[0-9]+)?)$' Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-1-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index bb492581f1b7..e1683e0630b0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -316,7 +316,7 @@ * be handled by a USB specific power sequence to reset the Hub * when the USB bus is powered down. */ - usb-hub { + usb-hub-hog { gpio-hog; gpios = ; output-high; From d7ff22a6ec9dd154d027d6bc6b4f172c22f8c00d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:07:55 +0100 Subject: [PATCH 0021/1040] arm64: dts: amlogic: meson-gxm-s912-libretech-pc: add simple connector node in fusb302 node Fixes the following bindings check error: fusb302@22: 'connector' is a required property Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-2-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts index 444c249863cb..4eda9f634c42 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-libretech-pc.dts @@ -54,6 +54,10 @@ vbus-supply = <&typec2_vbus>; status = "okay"; + + connector { + compatible = "usb-c-connector"; + }; }; }; From bd47319f999e6055124a2b4d2a0da495d52759c3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:07:56 +0100 Subject: [PATCH 0022/1040] arm64: dts: amlogic: meson-axg-jethome-jethub-j1xx: remove invalid #gpio-cells in onewire node Fixes the following bindings check errors: - #gpio-cells: [[1]] is not of type 'object' - 'gpio-controller' is a dependency of '#gpio-cells' Reviewed-by: Martin Blumenstingl Acked-by: Vyacheslav Bocharov Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-3-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi index e1605a9b0a13..db605f3a22b4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j1xx.dtsi @@ -159,7 +159,6 @@ onewire { compatible = "w1-gpio"; gpios = <&gpio GPIOA_14 GPIO_ACTIVE_HIGH>; - #gpio-cells = <1>; }; }; From db217e84d0a3f4183ea5b6d5929e55b73128fcb2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:07:57 +0100 Subject: [PATCH 0023/1040] arm64: dts: amlogic: meson-g12b-radxa-zero2: fix pwm clock names Fixes the following bindings check error: - pwm@2000: clock-names: 'oneOf' conditional failed, one must be fixed: ['clkin4'] is too short 'clkin4' is not one of ['clkin0', 'clkin1'] 'clkin0' was expected - pwm@7000: clock-names: 'oneOf' conditional failed, one must be fixed: ['clkin3'] is too short 'clkin3' is not one of ['clkin0', 'clkin1'] 'clkin0' was expected - pwm@19000: clock-names: 'oneOf' conditional failed, one must be fixed: ['clkin2'] is too short 'clkin2' is not one of ['clkin0', 'clkin1'] 'clkin0' was expected Fixes: d747e7f76a5f ("arm64: dts: meson: add support for Radxa Zero2") Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-4-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index 9a60c5ec2072..890f5bfebb03 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -360,7 +360,7 @@ pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; clocks = <&xtal>; - clock-names = "clkin2"; + clock-names = "clkin0"; status = "okay"; }; @@ -368,7 +368,7 @@ pinctrl-0 = <&pwm_ao_a_pins>; pinctrl-names = "default"; clocks = <&xtal>; - clock-names = "clkin3"; + clock-names = "clkin0"; status = "okay"; }; @@ -376,7 +376,7 @@ pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; clocks = <&xtal>; - clock-names = "clkin4"; + clock-names = "clkin1"; status = "okay"; }; From 50e7d712144e7246f4ad5ce0f8577aa09cd09bc6 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:07:58 +0100 Subject: [PATCH 0024/1040] arm64: dts: amlogic: meson-g12b-odroid-go-ultra: rename keypad-gpio pinctrl node Fixes the following bindings check error: pinctrl@40: keypad-gpio: {...} is not of type 'array' Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-5-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index c8e5a0a42b89..29d642e746d4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -620,7 +620,7 @@ }; &periphs_pinctrl { - keypad_gpio_pins: keypad-gpio { + keypad_gpio_pins: keypad-gpio-state { mux { groups = "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5", "GPIOX_6", "GPIOX_7", From d1e336eef1f4834bae0a54f203e9f74aa040726d Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:07:59 +0100 Subject: [PATCH 0025/1040] arm64: dts: amlogic: meson-s4: fix apb4 bus node name Fixes the following bindings check error: apb4@fe000000: $nodename:0: 'apb4@fe000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-6-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index ad50cba42d19..f24460186d3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -85,7 +85,7 @@ interrupts = ; }; - apb4: apb4@fe000000 { + apb4: bus@fe000000 { compatible = "simple-bus"; reg = <0x0 0xfe000000 0x0 0x480000>; #address-cells = <2>; From 4bddf79acdc7ef15f8b913e8ef7861461b235df2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:08:00 +0100 Subject: [PATCH 0026/1040] arm64: dts: amlogic: meson-sm1: use correct enable-gpios Replace enable-gpio by enable-gpios to match the bindings. Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-7-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index e1683e0630b0..17045ff81c69 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -105,7 +105,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - enable-gpio = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; + enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; enable-active-high; regulator-always-on; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index ddb1b345397f..2fce44939f45 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -48,7 +48,7 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc_5v>; - enable-gpio = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; + enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; enable-active-high; regulator-always-on; From 739e93e254e4797a29bdf397c10111a50a970734 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 7 Feb 2023 16:08:01 +0100 Subject: [PATCH 0027/1040] arm64: dts: amlogic: meson-gxm-s912-libretech-pc: remove unused pinctrl-names from phy node Fixes the following bindings check error: phy@78000: 'pinctrl-0' is a dependency of 'pinctrl-names' Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230207-b4-amlogic-bindings-fixups-v2-v1-8-93b7e50286e7@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 874f91c348ec..6c4e68e0e625 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -305,7 +305,6 @@ }; &usb2_phy0 { - pinctrl-names = "default"; phy-supply = <&vcc5v>; }; From 2227e738b30bf20380a48391a73752c52f5f5c6a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 9 Feb 2023 14:41:38 +0100 Subject: [PATCH 0028/1040] dt-bindings: soc: amlogic: convert clk-measure.txt to dt-schema Convert the Amlogic Internal Clock Measurer bindings to dt-schema. Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230209-b4-amlogic-bindings-convert-take2-v1-2-c4fe9049def9@linaro.org Signed-off-by: Neil Armstrong --- .../amlogic/amlogic,meson-gx-clk-measure.yaml | 40 +++++++++++++++++++ .../bindings/soc/amlogic/clk-measure.txt | 21 ---------- 2 files changed, 40 insertions(+), 21 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml delete mode 100644 Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml new file mode 100644 index 000000000000..77c281153010 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-clk-measure.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Internal Clock Measurer + +description: + The Amlogic SoCs contains an IP to measure the internal clocks. + The precision is multiple of MHz, useful to debug the clock states. + +maintainers: + - Neil Armstrong + +properties: + compatible: + enum: + - amlogic,meson-gx-clk-measure + - amlogic,meson8-clk-measure + - amlogic,meson8b-clk-measure + - amlogic,meson-axg-clk-measure + - amlogic,meson-g12a-clk-measure + - amlogic,meson-sm1-clk-measure + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + clock-measure@8758 { + compatible = "amlogic,meson-gx-clk-measure"; + reg = <0x8758 0x10>; + }; diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt deleted file mode 100644 index 3dd563cec794..000000000000 --- a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt +++ /dev/null @@ -1,21 +0,0 @@ -Amlogic Internal Clock Measurer -=============================== - -The Amlogic SoCs contains an IP to measure the internal clocks. -The precision is multiple of MHz, useful to debug the clock states. - -Required properties: -- compatible: Shall contain one of the following : - "amlogic,meson-gx-clk-measure" for GX SoCs - "amlogic,meson8-clk-measure" for Meson8 SoCs - "amlogic,meson8b-clk-measure" for Meson8b SoCs - "amlogic,meson-axg-clk-measure" for AXG SoCs - "amlogic,meson-g12a-clk-measure" for G12a SoCs - "amlogic,meson-sm1-clk-measure" for SM1 SoCs -- reg: base address and size of the Clock Measurer register space. - -Example: - clock-measure@8758 { - compatible = "amlogic,meson-gx-clk-measure"; - reg = <0x0 0x8758 0x0 0x10>; - }; From 0e1598a112f2e270bdd5771bb821f12852c548ac Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sun, 5 Mar 2023 13:45:11 +0000 Subject: [PATCH 0029/1040] dt-bindings: arm: amlogic: add support for BananaPi M2S variants BananaPi M2S ships in two variants with Amlogic S922X or A311D chips. Signed-off-by: Christian Hewitt Acked-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230305134512.1596572-2-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index b634d5b04e15..799a4bfff854 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -153,6 +153,7 @@ properties: - description: Boards with the Amlogic Meson G12B A311D SoC items: - enum: + - bananapi,bpi-m2s - khadas,vim3 - radxa,zero2 - const: amlogic,a311d @@ -164,6 +165,7 @@ properties: - azw,gsking-x - azw,gtking - azw,gtking-pro + - bananapi,bpi-m2s - hardkernel,odroid-go-ultra - hardkernel,odroid-n2 - hardkernel,odroid-n2l From 14e14723d2f58964f13e825738d01f62a8629e90 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sun, 5 Mar 2023 13:45:12 +0000 Subject: [PATCH 0030/1040] arm64: dts: meson: add support for BananaPi M2S variants BananaPi M2S ships in Amlogic S922X and A311D variants with the following common specifications: - 16GB eMMC - HDMI 2.1a video - 2x 10/100/1000 Base-T Ethernet (1x RTL8211F, 1x RTL811H) - 2x USB 2.0 ports - 2x Status LED's (green/blue) - 1x Power/Reset button - 1x micro SD card slot - 40-pin GPIO header - PWM fan header - UART header The S992X variant has: - 2GB LPDDR4 RAM The A311D variant has: - 4GB LPDDR4 RAM - NPU (5.0 TOPS) - MIPI DSI header - MIPI CSI header An optional RTL8822CS SDIO WiFi/BT mezzanine is available for both board variants. Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230305134512.1596572-3-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 2 + .../amlogic/meson-g12b-a311d-bananapi-m2s.dts | 37 ++ .../boot/dts/amlogic/meson-g12b-bananapi.dtsi | 521 ++++++++++++++++++ .../amlogic/meson-g12b-s922x-bananapi-m2s.dts | 14 + 4 files changed, 574 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index ccf1ba57fa87..2bb9f1d4bc1a 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-bananapi-m2s.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb @@ -17,6 +18,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-radxa-zero2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-bananapi-m2s.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts new file mode 100644 index 000000000000..ac6f7ae1d103 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-bananapi-m2s.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b-a311d.dtsi" +#include "meson-g12b-bananapi.dtsi" + +/ { + compatible = "bananapi,bpi-m2s", "amlogic,a311d", "amlogic,g12b"; + model = "BananaPi M2S"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + }; +}; + +/* Camera (CSI) bus */ +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>; + pinctrl-names = "default"; +}; + +/* Display (DSI) bus */ +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +&npu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi new file mode 100644 index 000000000000..83709787eb91 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -0,0 +1,521 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS + * Author: Neil Armstrong + * Copyright (c) 2023 Christian Hewitt + */ + +#include +#include +#include +#include + +/ { + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + rtc1 = &vrtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; /* 2 GiB or 4 GiB */ + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "RST"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-min-state = <0>; + cooling-max-state = <3>; + cooling-levels = <0 120 170 220>; + pwms = <&pwm_cd 1 40000 0>; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + dc_in: regulator-dc-in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc_5v: regulator-vcc-5v { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + + gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; + enable-active-high; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + vddao_1v8: regulator-vddao-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + }; + + vddcpu_a: regulator-vddcpu-a { + compatible = "pwm-regulator"; + regulator-name = "VDDCPU_A"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + pwm-supply = <&dc_in>; + pwms = <&pwm_ab 0 1250 0>; + pwm-dutycycle-range = <100 0>; + regulator-boot-on; + regulator-always-on; + }; + + vddcpu_b: regulator-vddcpu-b { + compatible = "pwm-regulator"; + regulator-name = "VDDCPU_B"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + pwm-supply = <&vsys_3v3>; + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + regulator-boot-on; + regulator-always-on; + }; + + vsys_3v3: regulator-vsys-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSYS_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + emmc_1v8: regulator-emmc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + + usb_pwr: regulator-usb-pwr { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_5v>; + + gpio = <&gpio GPIOA_6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "BPI-M2S"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu100 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu101 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu102 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu103 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&vcc_5v>; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +/* Main i2c bus */ +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; + pinctrl-names = "default"; +}; + +&pcie { + status = "okay"; + reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; +}; + +&pwm_ab { + status = "okay"; + pinctrl-0 = <&pwm_a_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&pwm_cd { + status = "okay"; + pinctrl-0 = <&pwm_d_x6_pins>; + pinctrl-names = "default"; + pwm-gpios = <&gpio GPIOAO_10 GPIO_ACTIVE_HIGH>; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddao_1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + /* enable if WiFi/BT board connected */ + status = "disabled"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + sd-uhs-sdr104; + max-frequency = <50000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vsys_3v3>; + vqmmc-supply = <&vddao_1v8>; + + rtl8822cs: wifi@1 { + reg = <1>; + }; +}; + +/* SD card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vsys_3v3>; + vqmmc-supply = <&vsys_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_A { + /* enable if WiFi/BT board connected */ + status = "disabled"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb2_phy0 { + phy-supply = <&dc_in>; +}; + +&usb2_phy1 { + phy-supply = <&usb_pwr>; +}; + +&usb3_pcie_phy { + phy-supply = <&usb_pwr>; +}; + +&usb { + status = "okay"; + dr_mode = "peripheral"; + phys = <&usb2_phy0>, <&usb2_phy1>; + phy-names = "usb2-phy0", "usb2-phy1"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts new file mode 100644 index 000000000000..7f66f263a2ce --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x-bananapi-m2s.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-g12b-s922x.dtsi" +#include "meson-g12b-bananapi.dtsi" + +/ { + compatible = "bananapi,bpi-m2s", "amlogic,s922x", "amlogic,g12b"; + model = "BananaPi M2S"; +}; From 4dcc844c99d3e47820f574911b495b58f7da1d94 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Wed, 1 Feb 2023 20:59:28 +0100 Subject: [PATCH 0031/1040] arm64: dts: meson: adjust order of some compatibles During review of a new yaml binding, affecting these dts, it turned out that some compatibles aren't ordered as they should be. Order should be most specific to least specific. Suggested-by: Rob Herring Signed-off-by: Heiner Kallweit Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/1ce888df-6096-73de-a98a-354d086428d4@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 923d2d8bbb9c..12ef6e81c8bd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -300,8 +300,8 @@ }; &gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxbb-gpio-intc"; + compatible = "amlogic,meson-gxbb-gpio-intc", + "amlogic,meson-gpio-intc"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 5905a6df09b0..6f3c2bc36919 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -312,8 +312,8 @@ }; &gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson-gxl-gpio-intc"; + compatible = "amlogic,meson-gxl-gpio-intc", + "amlogic,meson-gpio-intc"; status = "okay"; }; From 0c187cca73291f2c355fae31eed3fc7aa783b2de Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Wed, 1 Feb 2023 20:58:47 +0100 Subject: [PATCH 0032/1040] arm: dts: meson: adjust order of some compatibles During review of a new yaml binding, affecting these dts, it turned out that some compatibles aren't ordered as they should be. Order should be most specific to least specific. Suggested-by: Rob Herring Signed-off-by: Heiner Kallweit Reviewed-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/66f77c32-2678-3e31-fb00-1294ccaa6045@gmail.com Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/meson8b.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index d5a3fe21e8e7..5979209fe91e 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -580,8 +580,8 @@ }; &gpio_intc { - compatible = "amlogic,meson-gpio-intc", - "amlogic,meson8b-gpio-intc"; + compatible = "amlogic,meson8b-gpio-intc", + "amlogic,meson-gpio-intc"; status = "okay"; }; From 9aa8727b3b15c4d941353c784f61f49e33513b3e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 25 Feb 2023 17:40:49 +0100 Subject: [PATCH 0033/1040] ARM: dts: exynos: align STMPE ADC node name with bindings in P4 Note The node name should be generic thus rename STMPE ADC child to "adc". Bindings will expect such name as well. Link: https://lore.kernel.org/r/20230225164050.42522-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-p4note.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 3e05a49f29ff..84db696d543a 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -195,7 +195,7 @@ st,ref-sel = <0>; st,sample-time = <3>; - stmpe_adc { + adc { compatible = "st,stmpe-adc"; #io-channel-cells = <1>; st,norequest-mask = <0x2f>; From 74cbc0e6b2051a604c9bec8c825d83832def0462 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 25 Feb 2023 17:40:50 +0100 Subject: [PATCH 0034/1040] ARM: dts: exynos: drop fake align STMPE properties in P4 Note From STMPE device node in P4 Note remove unused irq-trigger property and incorrectly placed interrupt-controller (which would be a property of GPIO child). Link: https://lore.kernel.org/r/20230225164050.42522-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-p4note.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 84db696d543a..317e248f354b 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -188,8 +188,6 @@ pinctrl-names = "default"; interrupt-parent = <&gpx0>; interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - irq-trigger = <0x1>; st,adc-freq = <3>; st,mod-12b = <1>; st,ref-sel = <0>; From 704121ff1f6e05bd00ecb1ef2918ac309c18eb45 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 25 Feb 2023 17:02:52 +0100 Subject: [PATCH 0035/1040] ARM: dts: exynos: add ports to TC358764 bridge on Arndale The Toshiba TC358764 bridge binding expect up two ports as it is a bridge, thus add ports property to encapsulate them. Link: https://lore.kernel.org/r/20230225160252.18737-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 2e3da5670bc2..c03bb436bfed 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -192,12 +192,15 @@ vddio-supply = <&vcc_1v8_reg>; vddlvds-supply = <&vcc_3v3_reg>; reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>; - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - bridge_out_ep: endpoint { - remote-endpoint = <&panel_ep>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + bridge_out_ep: endpoint { + remote-endpoint = <&panel_ep>; + }; }; }; }; From 6c950c20da38debf1ed531e0b972bd8b53d1c11f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:06:27 +0100 Subject: [PATCH 0036/1040] ARM: dts: exynos: fix WM8960 clock name in Itop Elite The WM8960 Linux driver expects the clock to be named "mclk". Otherwise the clock will be ignored and not prepared/enabled by the driver. Cc: Fixes: 339b2fb36a67 ("ARM: dts: exynos: Add TOPEET itop elite based board") Link: https://lore.kernel.org/r/20230217150627.779764-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-itop-elite.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index b596e997e451..6260da187e92 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -182,7 +182,7 @@ compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; + clock-names = "mclk"; wlf,shared-lrclk; #sound-dai-cells = <0>; }; From 2beafeafeb4edce6540c37bc2117ea6e21c86d6a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Feb 2023 19:58:17 +0100 Subject: [PATCH 0037/1040] ARM: dts: exynos: correct whitespace in Midas Correct indentation and whitespace in Exynos4412 Midas board. Link: https://lore.kernel.org/r/20230212185818.43503-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 525f945c4b91..3fd7765799f6 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -497,8 +497,7 @@ pinctrl-0 = <&fimc_is_uart>; pinctrl-names = "default"; status = "okay"; - - }; +}; &fimc_lite_0 { status = "okay"; From 665b9459bb53b8f19bd1541567e1fe9782c83c4b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Feb 2023 19:58:18 +0100 Subject: [PATCH 0038/1040] ARM: dts: s5pv210: correct MIPI CSIS clock name The Samsung S5P/Exynos MIPI CSIS bindings and Linux driver expect first clock name to be "csis". Otherwise the driver fails to probe. Fixes: 94ad0f6d9278 ("ARM: dts: Add Device tree for s5pv210 SoC") Cc: Link: https://lore.kernel.org/r/20230212185818.43503-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 12e90a1cc6a1..1a9e4a96b2ff 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -566,7 +566,7 @@ interrupts = <29>; clocks = <&clocks CLK_CSIS>, <&clocks SCLK_CSIS>; - clock-names = "clk_csis", + clock-names = "csis", "sclk_csis"; bus-width = <4>; status = "disabled"; From cb8d0fcc5024981e1aed2516921f8bfb3476ffa7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Feb 2023 14:47:31 +0100 Subject: [PATCH 0039/1040] ARM: dts: exynos: drop unused samsung,camclk-out property in Midas The S5K6A3 camera sensor does not use nor allow samsung,camclk-out property. Link: https://lore.kernel.org/r/20230211134731.85957-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4412-midas.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 3fd7765799f6..3be48de5c130 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -591,7 +591,6 @@ /* CAM_B_CLKOUT */ clocks = <&camera 1>; clock-names = "extclk"; - samsung,camclk-out = <1>; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { From 37688852fd6f4fed2b3800a7652be87147137125 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 20:28:50 +0100 Subject: [PATCH 0040/1040] ARM: dts: exynos: move MIPI phy to PMU node in Exynos3250 The MIPI phy is actually part of the Power Management Unit system controller. It does not have its own address space, thus keeping the node under soc causes warnings: exynos3250-artik5-eval.dtb: soc: video-phy: {'compatible': ['samsung,s5pv210-mipi-video-phy'], '#phy-cells': [[1]], 'syscon': [[15]], 'phandle': [[23]]} should not be valid under {'type': 'object'} Link: https://lore.kernel.org/r/20230207192851.549242-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 28bb2ce8ccf7..cb2c59c98c4a 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -346,7 +346,7 @@ }; pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos3250-pmu", "syscon"; + compatible = "samsung,exynos3250-pmu", "simple-mfd", "syscon"; reg = <0x10020000 0x4000>; interrupt-controller; #interrupt-cells = <3>; @@ -354,12 +354,11 @@ clock-names = "clkout8"; clocks = <&cmu CLK_FIN_PLL>; #clock-cells = <1>; - }; - mipi_phy: video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; + mipi_phy: mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; }; pd_cam: power-domain@10023c00 { From d237b2270c68032ad3471ca82d1f3581398179c6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 20:28:51 +0100 Subject: [PATCH 0041/1040] ARM: dts: exynos: move MIPI phy to PMU node in Exynos4 The MIPI phy is actually part of the Power Management Unit system controller. It does not have its own address space, thus keeping the node under soc causes warnings: xynos4412-i9305.dtb: soc: video-phy: {'compatible': ['samsung,s5pv210-mipi-video-phy'], '#phy-cells': [[1]], 'syscon': [[11]], 'phandle': [[13]]} should not be valid under {'type': 'object'} Link: https://lore.kernel.org/r/20230207192851.549242-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4.dtsi | 13 ++++++------- arch/arm/boot/dts/exynos4412.dtsi | 2 +- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 44dcb1377475..8dd6976ab0a7 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -105,12 +105,6 @@ reg = <0x12570000 0x14>; }; - mipi_phy: video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - pd_mfc: power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; reg = <0x10023c40 0x20>; @@ -181,11 +175,16 @@ }; pmu_system_controller: system-controller@10020000 { - compatible = "samsung,exynos4210-pmu", "syscon"; + compatible = "samsung,exynos4210-pmu", "simple-mfd", "syscon"; reg = <0x10020000 0x4000>; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; + + mipi_phy: mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; }; dsi_0: dsi@11c80000 { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 11f9dd94b6b3..7fa3e5fd6801 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -798,7 +798,7 @@ }; &pmu_system_controller { - compatible = "samsung,exynos4412-pmu", "syscon"; + compatible = "samsung,exynos4412-pmu", "simple-mfd", "syscon"; clock-names = "clkout0", "clkout1", "clkout2", "clkout3", "clkout4", "clkout8", "clkout9"; clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, From da2102abcec034cf49fba9efa16596202a37710c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Thu, 9 Feb 2023 14:35:06 +0100 Subject: [PATCH 0042/1040] dt-bindings: soc: renesas: renesas.yaml: Add renesas,rzn1d400-eb compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add "renesas,rzn1d400-eb" which target the RZ/N1 EB board when an RZ/N1D-DB daughter board is plugged on it. Signed-off-by: Clément Léger Acked-by: Rob Herring Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230209133507.150571-2-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 2789022b52eb..76f6da46ff5c 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -431,6 +431,13 @@ properties: - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - const: renesas,r9a06g032 + - description: RZ/N1{D,S} EB + items: + - enum: + - renesas,rzn1d400-eb # RZN1D-EB (Expansion Board when using a RZN1D-DB) + - const: renesas,rzn1d400-db + - const: renesas,r9a06g032 + - description: RZ/Five and RZ/G2UL (R9A07G043) items: - enum: From 670e2a8b9b02ff52c7ca43204459693b3c574b00 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 21 Jan 2023 14:58:51 +0000 Subject: [PATCH 0043/1040] arm64: dts: renesas: r9a09g011: Add USB3 DRD, device and host nodes This patch add usb3 host and peripheral device node as child of usb3 drd node to RZ/V2M SoC dtsi. The host/device needs to issue reset release on DRD module before accessing host/device registers. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230121145853.4792-11-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index b5d6f7701ef1..46d67b200a66 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -117,6 +117,51 @@ status = "disabled"; }; + usb3drd: usb3drd@85070400 { + compatible = "renesas,r9a09g011-usb3drd", + "renesas,rzv2m-usb3drd"; + reg = <0x0 0x85070400 0x0 0x100>; + interrupts = , + , + ; + interrupt-names = "drd", "bc", "gpi"; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + resets = <&cpg R9A09G011_USB_DRD_RESET>; + power-domains = <&cpg>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + usb3host: usb@85060000 { + compatible = "renesas,r9a09g011-xhci", + "renesas,rzv2m-xhci"; + reg = <0 0x85060000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + resets = <&cpg R9A09G011_USB_ARESETN_H>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb3peri: usb3peri@85070000 { + compatible = "renesas,r9a09g011-usb3-peri", + "renesas,rzv2m-usb3-peri"; + reg = <0x0 0x85070000 0x0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>, + <&cpg CPG_MOD R9A09G011_USB_PCLK>; + clock-names = "axi", "reg"; + resets = <&cpg R9A09G011_USB_ARESETN_P>; + power-domains = <&cpg>; + status = "disabled"; + }; + }; + avb: ethernet@a3300000 { compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; reg = <0 0xa3300000 0 0x800>; From 967219e5d410ccb3e072c712ec3d665c6346876f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 21 Jan 2023 14:58:52 +0000 Subject: [PATCH 0044/1040] arm64: dts: renesas: rzv2mevk2: Enable USB3 DRD, Peripheral and Host Enable USB3 Host, Peripheral and DRD modules on RZ/V2M EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230121145853.4792-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index d6737395df67..20782ebf1cd6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -89,6 +89,18 @@ status = "okay"; }; +&usb3drd { + status = "okay"; +}; + +&usb3host { + status = "okay"; +}; + +&usb3peri { + status = "okay"; +}; + &wdt0 { status = "okay"; }; From a17039b630c59da98de153ef50cdf6a06393cfce Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 21 Jan 2023 14:58:53 +0000 Subject: [PATCH 0045/1040] arm64: dts: renesas: rzv2mevk2: Enable USB3 role switch Enable USB3 role switch on RZ/V2M EVK by linking USB3 peri node with hd3ss3220 controller node. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230121145853.4792-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index 20782ebf1cd6..b405914f5e11 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -22,6 +22,31 @@ stdout-path = "serial0:115200n8"; }; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb3_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + memory@58000000 { device_type = "memory"; /* @@ -59,6 +84,30 @@ pinctrl-names = "default"; clock-frequency = <400000>; status = "okay"; + + hd3ss3220@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; }; &i2c2 { @@ -98,7 +147,28 @@ }; &usb3peri { + companion = <&usb3host>; status = "okay"; + usb-role-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; }; &wdt0 { From 5056a0c7286237844d220c0f75f1a7099da6002c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 23 Jan 2023 20:06:18 +0100 Subject: [PATCH 0046/1040] arm64: dts: renesas: r8a779g0: Add CAN-FD node Add device nodes for the CAN-FD interface and the related external CAN clock on the Renesas R-Car V4H (R8A779G0) SoC. Based on a patch in the BSP by Kazuya Mizuguch. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/6c55d0995089917216ee261a8b8cbb980c7b5304.1674500205.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 57 +++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 7a87a5dc1b6a..70eaf7956925 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -14,6 +14,13 @@ #address-cells = <2>; #size-cells = <2>; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -682,6 +689,56 @@ status = "disabled"; }; + canfd: can@e6660000 { + compatible = "renesas,r8a779g0-canfd", + "renesas,rcar-gen4-canfd"; + reg = <0 0xe6660000 0 0x8500>; + interrupts = , + ; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 328>, + <&cpg CPG_CORE R8A779G0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A779G0_CLK_CANFD>; + assigned-clock-rates = <80000000>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + + channel2 { + status = "disabled"; + }; + + channel3 { + status = "disabled"; + }; + + channel4 { + status = "disabled"; + }; + + channel5 { + status = "disabled"; + }; + + channel6 { + status = "disabled"; + }; + + channel7 { + status = "disabled"; + }; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779g0", "renesas,etheravb-rcar-gen4"; From 548b2771111442fa15dd4c52a581ae3220d12b8c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 23 Jan 2023 20:06:19 +0100 Subject: [PATCH 0047/1040] arm64: dts: renesas: white-hawk: Add CAN-FD support Enable confirmed-working CAN-FD channels 0 and 1 on the White-Hawk development board: - Channel 0 uses an NXP TJR1443AT CAN transceiver, which must be enabled through a GPIO, - Channels 1-7 use Microchip MCP2558FD-H/SN CAN transceivers (not mounted for channels 4-7), which do not need explicit description, but channels 2-3 do not seem to work. Inspired by a patch in the BSP by Kazuya Mizuguch. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a19d0a70aacaf4c3517a226bf32ea49db3542da4.1674500205.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index 04a2b6b83e74..eff1ef6e2cc8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -13,6 +13,33 @@ / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; + + can_transceiver0: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + }; +}; + +&can_clk { + clock-frequency = <40000000>; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; + + channel0 { + status = "okay"; + phys = <&can_transceiver0>; + }; + + channel1 { + status = "okay"; + }; }; &i2c0 { @@ -23,3 +50,20 @@ pagesize = <8>; }; }; + +&pfc { + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; +}; From b6c0be722b0c0a7204b6289464a04cd7b4fdfca0 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Mon, 30 Jan 2023 19:11:52 +0000 Subject: [PATCH 0048/1040] arm64: dts: renesas: rzv2mevk2: Add uSD card and eMMC support The RZ/V2M EVK comes with a slot for a uSD card, and an eMMC. Add support for the both of them. Please note that the pinctrl driver for RZ/V2M doesn't support interrupts yet, therefore the card detect pin has been connected to the SDHI IP directly in this patch. We'll connect the card detect pin to its corresponding GPIO when we'll have driver support for interrupts in the RZ/V2M pinctrl driver. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230130191152.182826-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index b405914f5e11..3bb02264cb3e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r9a09g011.dtsi" +#include #include / { @@ -60,6 +61,36 @@ device_type = "memory"; reg = <0x1 0x80000000 0x0 0x80000000>; }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&pwc 0 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 0>, <1800000 1>; + }; }; &avb { @@ -75,6 +106,23 @@ }; }; +&emmc { + pinctrl-0 = <&emmc_pins>; + pinctrl-1 = <&emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3v3>; + vqmmc-supply = <®_1v8>; + bus-width = <8>; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + fixed-emmc-driver-type = <1>; + max-frequency = <200000000>; + status = "okay"; +}; + &extal_clk { clock-frequency = <48000000>; }; @@ -118,6 +166,26 @@ }; &pinctrl { + emmc_pins: emmc { + data { + pinmux = , /* MMDAT0 */ + , /* MMDAT1 */ + , /* MMDAT2 */ + , /* MMDAT3 */ + , /* MMDAT4 */ + , /* MMDAT5 */ + , /* MMDAT6 */ + ; /* MMDAT7 */ + power-source = <1800>; + }; + + ctrl { + pinmux = , /* MMCMD */ + ; /* MMCLK */ + power-source = <1800>; + }; + }; + i2c0_pins: i2c0 { pinmux = , /* SDA */ ; /* SCL */ @@ -127,6 +195,48 @@ pinmux = , /* SDA */ ; /* SCL */ }; + + sdhi0_pins: sd0 { + data { + pinmux = , /* SD0DAT0 */ + , /* SD0DAT1 */ + , /* SD0DAT2 */ + ; /* SD0DAT3 */ + power-source = <3300>; + }; + + ctrl { + pinmux = , /* SD0CMD */ + ; /* SD0CLK */ + power-source = <3300>; + }; + + cd { + pinmux = ; /* SD0CD */ + power-source = <3300>; + }; + }; + + sdhi0_pins_uhs: sd0-uhs { + data { + pinmux = , /* SD0DAT0 */ + , /* SD0DAT1 */ + , /* SD0DAT2 */ + ; /* SD0DAT3 */ + power-source = <1800>; + }; + + ctrl { + pinmux = , /* SD0CMD */ + ; /* SD0CLK */ + power-source = <1800>; + }; + + cd { + pinmux = ; /* SD0CD */ + power-source = <1800>; + }; + }; }; &pwc { @@ -134,6 +244,19 @@ status = "okay"; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3v3>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + &uart0 { status = "okay"; }; From 10fb3e2746eee0bf278c797a86fedc665bbb0ad2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 31 Jan 2023 12:32:33 +0100 Subject: [PATCH 0049/1040] arm64: dts: renesas: falcon: Describe CAN clock Describe the 40 MHz Crystal Clock Oscillator providing CAN_CLK. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/0bf36a1708ad87c00455b96ebaacc63fb7305b7a.1675164686.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index b2e67b82caf6..63db822e5f46 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -37,8 +37,12 @@ }; }; +&can_clk { + clock-frequency = <40000000>; +}; + &canfd { - pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>; + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; pinctrl-names = "default"; status = "okay"; @@ -80,6 +84,11 @@ }; + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + canfd0_pins: canfd0 { groups = "canfd0_data"; function = "canfd0"; From 79d9cfa9d3cf3f790bff384d2d3177c51e4a50cb Mon Sep 17 00:00:00 2001 From: Nam Nguyen Date: Thu, 2 Feb 2023 11:51:12 +0100 Subject: [PATCH 0050/1040] arm64: dts: renesas: v3hsk: Add clock-skew for GEther's Micrel PHY Add the missing clock-skew property for the GEther's Micrel KSZ9031 PHY. Signed-off-by: Nam Nguyen Signed-off-by: Phong Hoang Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/39ab4e92d2242e1d7e83db92f91fc6e0e7e76c47.1675334998.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index d168b0e7747d..77d22df25fff 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -122,6 +122,7 @@ phy0: ethernet-phy@0 { compatible = "ethernet-phy-id0022.1622", "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio4>; interrupts = <23 IRQ_TYPE_LEVEL_LOW>; From 320dfca630887173a605b3f51f22afd59f038bdb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 2 Feb 2023 11:52:41 +0100 Subject: [PATCH 0051/1040] arm64: dts: renesas: rcar-gen3: Remove bogus "turbo-mode" properties On several R-Car Gen3(e) SoCs, multiple (up to 4) operating points in the same cluster are marked with the "turbo-mode" property, which is meant only for operating points beyond "Normal Mode". Fix this by dropping the property from all operating points but the "High Performance" one. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/866d06aec09e5a86dba11970f93a728b3e34e9f5.1675335086.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 1 - arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a779m1.dtsi | 3 +++ arch/arm64/boot/dts/renesas/r8a779m3.dtsi | 3 +++ arch/arm64/boot/dts/renesas/r8a779m5.dtsi | 3 +++ 7 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index f770d160e948..10b91e9733bf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -75,7 +75,6 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 09c61696f7fb..3ea8572e917f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -70,13 +70,11 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 59a18dfcb8cc..d52cb0b67d80 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -70,13 +70,11 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 9b4f7ad95ca8..9584115c6b17 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -75,13 +75,11 @@ opp-hz = /bits/ 64 <1600000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; opp-microvolt = <900000>; clock-latency-ns = <300000>; - turbo-mode; }; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; diff --git a/arch/arm64/boot/dts/renesas/r8a779m1.dtsi b/arch/arm64/boot/dts/renesas/r8a779m1.dtsi index b6e855f52adf..1064a87a0c77 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m1.dtsi @@ -12,6 +12,9 @@ }; &cluster0_opp { + opp-1700000000 { + /delete-property/ turbo-mode; + }; opp-2000000000 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <960000>; diff --git a/arch/arm64/boot/dts/renesas/r8a779m3.dtsi b/arch/arm64/boot/dts/renesas/r8a779m3.dtsi index 6cff38a6d20b..7fdbdd97ed4b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m3.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m3.dtsi @@ -12,6 +12,9 @@ }; &cluster0_opp { + opp-1800000000 { + /delete-property/ turbo-mode; + }; opp-2000000000 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <960000>; diff --git a/arch/arm64/boot/dts/renesas/r8a779m5.dtsi b/arch/arm64/boot/dts/renesas/r8a779m5.dtsi index 8c9c0557fe77..df51e0ff5986 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m5.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m5.dtsi @@ -12,6 +12,9 @@ }; &cluster0_opp { + opp-1800000000 { + /delete-property/ turbo-mode; + }; opp-2000000000 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <960000>; From 805ed6d67b7b39b07fb65d4a76c986a1e49262cf Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 6 Feb 2023 00:11:33 +0000 Subject: [PATCH 0052/1040] arm64: dts: renesas: r9a07g043u: Add Cortex-A55 PMU node Enable the performance monitor unit for the Cortex-A55 core on the RZ/G2UL (r9a07g043u) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230206001133.28776-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 9d854706ada5..1c9d3193e4ff 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -35,6 +35,11 @@ }; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; From c2b92d7e90187faaa98f6312984724f27401af03 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 6 Feb 2023 00:13:00 +0000 Subject: [PATCH 0053/1040] arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU node Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L (r9a07g044) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230206001300.28937-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 487536696d90..67ee98cdc697 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -157,6 +157,11 @@ }; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; From 8b6a006c914aac1702ef85b4ea42ff566b157c85 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 6 Feb 2023 00:21:36 +0000 Subject: [PATCH 0054/1040] arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems The GICv3 interrupts binding does not have a cpumask. The CPU mask only applies to pre-GICv3. So just drop using them from GICv3 systems. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 11 +++++------ arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 11 +++++------ arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 11 +++++------ arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 8 ++++---- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++---- arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 7 ------- arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 7 ------- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 8 ++++---- arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 7 ------- 9 files changed, 27 insertions(+), 51 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 41fbb9998cf8..f04792baef80 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2209,8 +2209,7 @@ interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; - interrupts = ; + interrupts = ; }; fcpvd0: fcp@fea10000 { @@ -2857,9 +2856,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index f20b612b2b9a..52b09e347e13 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1108,8 +1108,7 @@ interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; - interrupts = ; + interrupts = ; }; prr: chipid@fff00044 { @@ -1164,10 +1163,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; ufs30_clk: ufs30-clk { diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 70eaf7956925..38580532e19d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1262,8 +1262,7 @@ interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; - interrupts = ; + interrupts = ; }; fcpvd0: fcp@fea10000 { @@ -1404,9 +1403,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 1c9d3193e4ff..2ab231572d95 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -47,10 +47,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 67ee98cdc697..447ebf90a10d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1066,9 +1066,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi index 1d57df706939..56a979e82c4f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi @@ -15,13 +15,6 @@ /delete-node/ cpu-map; /delete-node/ cpu@100; }; - - timer { - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; &soc { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi index 9d89d4590358..9cf27ca9f1d2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi @@ -15,11 +15,4 @@ /delete-node/ cpu-map; /delete-node/ cpu@100; }; - - timer { - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 304ade54425b..56f56a57749e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1067,9 +1067,9 @@ timer { compatible = "arm,armv8-timer"; - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi index c448cc6634c1..d85a6ac0f024 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi @@ -15,11 +15,4 @@ /delete-node/ cpu-map; /delete-node/ cpu@100; }; - - timer { - interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, - <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; - }; }; From 6ec5791375954411640871fec6a7df2cb5365a86 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 9 Feb 2023 13:14:22 +0000 Subject: [PATCH 0055/1040] arm64: dts: renesas: rzv2mevk2: Add uart0 pins Add uart0 pins in pinctrl node and update the uart0 node to include pinctrl and uart-has-rtscts properties. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230209131422.192941-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index 3bb02264cb3e..39fe3f94991e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -237,6 +237,13 @@ power-source = <1800>; }; }; + + uart0_pins: uart0 { + pinmux = , /* UATX0 */ + , /* UARX0 */ + , /* UACTS0N */ + ; /* UARTS0N */ + }; }; &pwc { @@ -258,6 +265,10 @@ }; &uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; status = "okay"; }; From d8ac71d29660028b143a6dab7497e70388d0ccb1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 9 Feb 2023 17:23:30 +0100 Subject: [PATCH 0056/1040] arm64: dts: renesas: r8a779g0: Add thermal nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device nodes for the Thermal Sensor/Chip Internal Voltage Monitor/Core Voltage Monitor (THS/CIVM/CVM) and the various thermal zones on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/b92a1a28afb9f75f24f0137af9f77e95d7ebaec3.1675959327.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 38580532e19d..7e2a575ea4dc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -438,6 +438,18 @@ #power-domain-cells = <1>; }; + tsc: thermal@e6198000 { + compatible = "renesas,r8a779g0-thermal"; + reg = <0 0xe6198000 0 0x200>, + <0 0xe61a0000 0 0x200>, + <0 0xe61a8000 0 0x200>, + <0 0xe61b0000 0 0x200>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 919>; + #thermal-sensor-cells = <1>; + }; + intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc"; #interrupt-cells = <2>; @@ -1401,6 +1413,64 @@ }; }; + thermal-zones { + sensor_thermal_cr52: sensor1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_cnn: sensor2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_ca76: sensor3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal_ddr1: sensor4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 3>; + + trips { + sensor4_crit: sensor4-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, From 109e28af2b89e0f92c2f0b5567b13502f72696bb Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 9 Feb 2023 21:07:35 +0100 Subject: [PATCH 0057/1040] arm64: dts: renesas: r8a779f0: Use proper labels for thermal zones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The documentation provides information about the placement of the zones, so that can be used for more descriptive labels. Signed-off-by: Wolfram Sang Reviewed-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230209200735.3882-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 52b09e347e13..dc4d23daa8e8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1118,7 +1118,7 @@ }; thermal-zones { - sensor_thermal1: sensor1-thermal { + sensor_thermal_rtcore: sensor1-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; @@ -1132,7 +1132,7 @@ }; }; - sensor_thermal2: sensor2-thermal { + sensor_thermal_apcore0: sensor2-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; @@ -1146,7 +1146,7 @@ }; }; - sensor_thermal3: sensor3-thermal { + sensor_thermal_apcore4: sensor3-thermal { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 2>; From d435d437ce31e69e023c691b71392abc30509c84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Sat, 11 Feb 2023 16:00:11 +0100 Subject: [PATCH 0058/1040] arm64: dts: renesas: r8a779g0: Add and connect all CSI-2, ISP and VIN nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The V4H have 16 VIN, 2 CSI-2 and 2 ISP nodes that interact with each other for video capture. Add all nodes and record how they are interconnected. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230211150012.3824154-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 666 ++++++++++++++++++++++ 1 file changed, 666 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 7e2a575ea4dc..f782a18c8dd3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1167,6 +1167,454 @@ status = "disabled"; }; + vin00: video@e6ef0000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 730>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 730>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin00isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin00>; + }; + }; + }; + }; + + vin01: video@e6ef1000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 731>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 731>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin01isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin01>; + }; + }; + }; + }; + + vin02: video@e6ef2000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 800>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 800>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin02isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin02>; + }; + }; + }; + }; + + vin03: video@e6ef3000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 801>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 801>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin03isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin03>; + }; + }; + }; + }; + + vin04: video@e6ef4000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 802>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin04isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin04>; + }; + }; + }; + }; + + vin05: video@e6ef5000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 803>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 803>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin05isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin05>; + }; + }; + }; + }; + + vin06: video@e6ef6000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin06isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin06>; + }; + }; + }; + }; + + vin07: video@e6ef7000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin07isp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0vin07>; + }; + }; + }; + }; + + vin08: video@e6ef8000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef8000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <8>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin08isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin08>; + }; + }; + }; + }; + + vin09: video@e6ef9000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6ef9000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <9>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin09isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin09>; + }; + }; + }; + }; + + vin10: video@e6efa000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efa000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <10>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin10isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin10>; + }; + }; + }; + }; + + vin11: video@e6efb000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efb000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <11>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin11isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin11>; + }; + }; + }; + }; + + vin12: video@e6efc000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efc000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <12>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin12isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin12>; + }; + }; + }; + }; + + vin13: video@e6efd000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efd000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <13>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin13isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin13>; + }; + }; + }; + }; + + vin14: video@e6efe000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6efe000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 812>; + renesas,id = <14>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin14isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin14>; + }; + }; + }; + }; + + vin15: video@e6eff000 { + compatible = "renesas,vin-r8a779g0"; + reg = <0 0xe6eff000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 813>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 813>; + renesas,id = <15>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vin15isp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp1vin15>; + }; + }; + }; + }; + dmac0: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779g0", "renesas,rcar-gen4-dmac"; @@ -1277,6 +1725,58 @@ interrupts = ; }; + csi40: csi2@fe500000 { + compatible = "renesas,r8a779g0-csi2"; + reg = <0 0xfe500000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 331>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi40isp0: endpoint { + remote-endpoint = <&isp0csi40>; + }; + }; + }; + }; + + csi41: csi2@fe540000 { + compatible = "renesas,r8a779g0-csi2"; + reg = <0 0xfe540000 0 0x40000>; + interrupts = ; + clocks = <&cpg CPG_MOD 400>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 400>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + csi41isp1: endpoint { + remote-endpoint = <&isp1csi41>; + }; + }; + }; + }; + fcpvd0: fcp@fea10000 { compatible = "renesas,fcpv"; reg = <0 0xfea10000 0 0x200>; @@ -1349,6 +1849,172 @@ }; }; + isp0: isp@fed00000 { + compatible = "renesas,r8a779g0-isp"; + reg = <0 0xfed00000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 612>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 612>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp0csi40: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi40isp0>; + }; + }; + + port@1 { + reg = <1>; + isp0vin00: endpoint { + remote-endpoint = <&vin00isp0>; + }; + }; + + port@2 { + reg = <2>; + isp0vin01: endpoint { + remote-endpoint = <&vin01isp0>; + }; + }; + + port@3 { + reg = <3>; + isp0vin02: endpoint { + remote-endpoint = <&vin02isp0>; + }; + }; + + port@4 { + reg = <4>; + isp0vin03: endpoint { + remote-endpoint = <&vin03isp0>; + }; + }; + + port@5 { + reg = <5>; + isp0vin04: endpoint { + remote-endpoint = <&vin04isp0>; + }; + }; + + port@6 { + reg = <6>; + isp0vin05: endpoint { + remote-endpoint = <&vin05isp0>; + }; + }; + + port@7 { + reg = <7>; + isp0vin06: endpoint { + remote-endpoint = <&vin06isp0>; + }; + }; + + port@8 { + reg = <8>; + isp0vin07: endpoint { + remote-endpoint = <&vin07isp0>; + }; + }; + }; + }; + + isp1: isp@fed20000 { + compatible = "renesas,r8a779g0-isp"; + reg = <0 0xfed20000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 613>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + + isp1csi41: endpoint@1 { + reg = <1>; + remote-endpoint = <&csi41isp1>; + }; + }; + + port@1 { + reg = <1>; + isp1vin08: endpoint { + remote-endpoint = <&vin08isp1>; + }; + }; + + port@2 { + reg = <2>; + isp1vin09: endpoint { + remote-endpoint = <&vin09isp1>; + }; + }; + + port@3 { + reg = <3>; + isp1vin10: endpoint { + remote-endpoint = <&vin10isp1>; + }; + }; + + port@4 { + reg = <4>; + isp1vin11: endpoint { + remote-endpoint = <&vin11isp1>; + }; + }; + + port@5 { + reg = <5>; + isp1vin12: endpoint { + remote-endpoint = <&vin12isp1>; + }; + }; + + port@6 { + reg = <6>; + isp1vin13: endpoint { + remote-endpoint = <&vin13isp1>; + }; + }; + + port@7 { + reg = <7>; + isp1vin14: endpoint { + remote-endpoint = <&vin14isp1>; + }; + }; + + port@8 { + reg = <8>; + isp1vin15: endpoint { + remote-endpoint = <&vin15isp1>; + }; + }; + }; + }; + dsi0: dsi-encoder@fed80000 { compatible = "renesas,r8a779g0-dsi-csi2-tx"; reg = <0 0xfed80000 0 0x10000>; From 4077043be27f4cadf1d2b3d1be8ae13657d963a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Sat, 11 Feb 2023 16:00:12 +0100 Subject: [PATCH 0059/1040] arm64: dts: renesas: white-hawk-csi-dsi: Add and connect MAX96712 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The sub-board contains two MAX96712 connected to the main-board using I2C and CSI-2, record the connections. Also enable all nodes (VIN, CSI-2 and ISP) that are part of the downstream video capture pipeline. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230211150012.3824154-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../renesas/r8a779g0-white-hawk-csi-dsi.dtsi | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi index ae7522b60e5d..f8537f7ea4de 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi @@ -5,7 +5,63 @@ * Copyright (C) 2022 Glider bv */ +#include + +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&max96712_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi41_in: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&max96712_out1>; + }; + }; + }; +}; + &i2c0 { + pca9654_a: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9654_b: gpio@22 { + compatible = "onnn,pca9654"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + eeprom@52 { compatible = "rohm,br24g01", "atmel,24c01"; label = "csi-dsi-sub-board-id"; @@ -13,3 +69,119 @@ pagesize = <8>; }; }; + +&i2c1 { + gmsl0: gmsl-deserializer@49 { + compatible = "maxim,max96712"; + reg = <0x49>; + enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out0: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + gmsl1: gmsl-deserializer@4b { + compatible = "maxim,max96712"; + reg = <0x4b>; + enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out1: endpoint { + bus-type = ; + clock-lanes = <0>; + data-lanes = <1 2 3>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; + +&vin08 { + status = "okay"; +}; + +&vin09 { + status = "okay"; +}; + +&vin10 { + status = "okay"; +}; + +&vin11 { + status = "okay"; +}; + +&vin12 { + status = "okay"; +}; + +&vin13 { + status = "okay"; +}; + +&vin14 { + status = "okay"; +}; + +&vin15 { + status = "okay"; +}; From 972b567075845a55d525f1ed5d7cd7b6d524afdc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 20:40:55 +0100 Subject: [PATCH 0060/1040] ARM: dts: exynos: move DP and MIPI phys to PMU node in Exynos5420 The DisplayPort and MIPI phys are actually part of the Power Management Unit system controller. They do not have their own address space, thus keeping the nodes under soc causes warnings: exynos5420-smdk5420.dtb: soc: dp-video-phy: {'compatible': ['samsung,exynos5420-dp-video-phy'], 'samsung,pmu-syscon': [[11]], '#phy-cells': [[0]], 'phandle': [[16]]} should not be valid under {'type': 'object'} Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230127194057.186458-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420.dtsi | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 13d7be236a23..17dec11fb773 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -696,18 +696,6 @@ status = "disabled"; }; - dp_phy: dp-video-phy { - compatible = "samsung,exynos5420-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - mipi_phy: mipi-video-phy { - compatible = "samsung,exynos5420-mipi-video-phy"; - syscon = <&pmu_system_controller>; - #phy-cells = <1>; - }; - dsi: dsi@14500000 { compatible = "samsung,exynos5410-mipi-dsi"; reg = <0x14500000 0x10000>; @@ -933,7 +921,7 @@ }; pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5420-pmu", "syscon"; + compatible = "samsung,exynos5420-pmu", "simple-mfd", "syscon"; reg = <0x10040000 0x5000>; clock-names = "clkout16"; clocks = <&clock CLK_FIN_PLL>; @@ -941,6 +929,16 @@ interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; + + dp_phy: dp-phy { + compatible = "samsung,exynos5420-dp-video-phy"; + #phy-cells = <0>; + }; + + mipi_phy: mipi-phy { + compatible = "samsung,exynos5420-mipi-video-phy"; + #phy-cells = <1>; + }; }; tmu_cpu0: tmu@10060000 { From 6dc01bc640b1278f225ed73b891645202be72b55 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 20:40:56 +0100 Subject: [PATCH 0061/1040] ARM: dts: exynos: move DP and MIPI phys to PMU node in Exynos5250 The DisplayPort and MIPI phys are actually part of the Power Management Unit system controller. They do not have their own address space, thus keeping the nodes under soc causes warnings: exynos5250-arndale.dtb: soc: video-phy-0: {'compatible': ['samsung,exynos5250-dp-video-phy'], 'samsung,pmu-syscon': [[20]], '#phy-cells': [[0]], 'phandle': [[24]]} should not be valid under {'type': 'object'} Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230127194057.186458-8-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250.dtsi | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 60a623e3a200..89c8665ac9aa 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -290,7 +290,7 @@ }; pmu_system_controller: system-controller@10040000 { - compatible = "samsung,exynos5250-pmu", "syscon"; + compatible = "samsung,exynos5250-pmu", "simple-mfd", "syscon"; reg = <0x10040000 0x5000>; clock-names = "clkout16"; clocks = <&clock CLK_FIN_PLL>; @@ -298,6 +298,16 @@ interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; + + dp_phy: dp-phy { + compatible = "samsung,exynos5250-dp-video-phy"; + #phy-cells = <0>; + }; + + mipi_phy: mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; }; watchdog@101d0000 { @@ -810,18 +820,6 @@ status = "disabled"; }; - dp_phy: video-phy-0 { - compatible = "samsung,exynos5250-dp-video-phy"; - samsung,pmu-syscon = <&pmu_system_controller>; - #phy-cells = <0>; - }; - - mipi_phy: video-phy-1 { - compatible = "samsung,s5pv210-mipi-video-phy"; - #phy-cells = <1>; - syscon = <&pmu_system_controller>; - }; - dsi_0: dsi@14500000 { compatible = "samsung,exynos4210-mipi-dsi"; reg = <0x14500000 0x10000>; From 815ad625ec4ea5de655f9c02ccf7f65ecf5e6e29 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 6 Mar 2023 12:13:49 +0000 Subject: [PATCH 0062/1040] arm64: dts: meson: gxbb-kii-pro: sort and tidy the dts Alpha-sort the nodes, move the default line in the LED node to where it's normally found, and remove excess spacing. No functional changes. Signed-off-by: Christian Hewitt Tested-by: Ferass El Hafidi Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230306121351.1606360-2-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-gxbb-kii-pro.dts | 31 ++++++++----------- 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts index 5f2d4317ecfb..73ad0f5110f3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts @@ -6,10 +6,10 @@ /dts-v1/; #include "meson-gxbb-p20x.dtsi" - #include #include #include + / { compatible = "videostrong,kii-pro", "amlogic,meson-gxbb"; model = "Videostrong KII Pro"; @@ -18,9 +18,9 @@ compatible = "gpio-leds"; led { gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; - default-state = "off"; color = ; function = LED_FUNCTION_STATUS; + default-state = "off"; }; }; @@ -34,24 +34,8 @@ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; }; }; - }; - - -&uart_A { - status = "okay"; - pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - - bluetooth { - compatible = "brcm,bcm4335a0"; - }; -}; - - - ðmac { status = "okay"; pinctrl-0 = <ð_rmii_pins>; @@ -78,3 +62,14 @@ &ir { linux,rc-map-name = "rc-videostrong-kii-pro"; }; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4335a0"; + }; +}; From dae485f52a65ce939b045cf480c401d434cacf2d Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 6 Mar 2023 12:13:50 +0000 Subject: [PATCH 0063/1040] arm64: dts: meson: gxbb-kii-pro: complete the bluetooth node Add missing content to the bluetooth node to align it with the content used in (all) other GXBB dts files. Signed-off-by: Christian Hewitt Tested-by: Ferass El Hafidi Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230306121351.1606360-3-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts index 73ad0f5110f3..a800e8955c4a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts @@ -71,5 +71,10 @@ bluetooth { compatible = "brcm,bcm4335a0"; + shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; }; }; From 914a3aa644cf50947a2dbb97738502ca9f025a10 Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Mon, 6 Mar 2023 12:13:51 +0000 Subject: [PATCH 0064/1040] arm64: dts: meson: gxbb-kii-pro: add initial audio support Add initial support for HDMI and S/PDIF audio output. Signed-off-by: Christian Hewitt Tested-by: Ferass El Hafidi Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230306121351.1606360-4-christianshewitt@gmail.com Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-gxbb-kii-pro.dts | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts index a800e8955c4a..e238f1f10124 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts @@ -9,11 +9,19 @@ #include #include #include +#include / { compatible = "videostrong,kii-pro", "amlogic,meson-gxbb"; model = "Videostrong KII Pro"; + spdif_dit: audio-codec-0 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + leds { compatible = "gpio-leds"; led { @@ -34,6 +42,58 @@ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; }; }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "KII-PRO"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link-4 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; + pinctrl-0 = <&spdif_out_y_pins>; + pinctrl-names = "default"; }; ðmac { From 0e3661de6a6593a2dd98cd0d5fe78210e260f823 Mon Sep 17 00:00:00 2001 From: Xiangsheng Hou Date: Wed, 1 Feb 2023 10:14:57 +0800 Subject: [PATCH 0065/1040] arm64: dts: mediatek: Fix existing NAND controller node name Change the existing node name in order to match NAND controller DT bindings. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230201021500.26769-3-xiangsheng.hou@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 879dff24dcd3..ed1a9d319415 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -559,7 +559,7 @@ status = "disabled"; }; - nandc: nfi@1100e000 { + nandc: nand-controller@1100e000 { compatible = "mediatek,mt2712-nfc"; reg = <0 0x1100e000 0 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 20129bc98e21..006cd639059f 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -539,7 +539,7 @@ }; }; - nandc: nfi@1100d000 { + nandc: nand-controller@1100d000 { compatible = "mediatek,mt7622-nfc"; reg = <0 0x1100D000 0 0x1000>; interrupts = ; From 981f808e641c624fdf4ece806b599ae66e875ee4 Mon Sep 17 00:00:00 2001 From: "Roy-CW.Yeh" Date: Mon, 6 Feb 2023 17:11:05 +0800 Subject: [PATCH 0066/1040] arm64: dts: mediatek: mt8195: add MMSYS configuration for VPPSYS With the change of the MMSYS binding file for MT8195, the compatible name of VPPSYS in dts need to be fixed to match the definition. Signed-off-by: Roy-CW.Yeh Signed-off-by: Moudy Ho Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230206091109.1324-3-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8f1264d5290b..526136703142 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1795,8 +1795,8 @@ #clock-cells = <1>; }; - vppsys0: clock-controller@14000000 { - compatible = "mediatek,mt8195-vppsys0"; + vppsys0: syscon@14000000 { + compatible = "mediatek,mt8195-vppsys0", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; @@ -1900,8 +1900,8 @@ power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; }; - vppsys1: clock-controller@14f00000 { - compatible = "mediatek,mt8195-vppsys1"; + vppsys1: syscon@14f00000 { + compatible = "mediatek,mt8195-vppsys1", "syscon"; reg = <0 0x14f00000 0 0x1000>; #clock-cells = <1>; }; From 018f1d4fa457af98c9618c0bd17a427745f872fa Mon Sep 17 00:00:00 2001 From: Moudy Ho Date: Mon, 6 Feb 2023 17:11:06 +0800 Subject: [PATCH 0067/1040] arm64: dts: mediatek: mt8195: add MUTEX configuration for VPPSYS In MT8195, the MMSYS has two Video Processor Pipepline Subsystems named VPPSYS0 and VPPSYS1, each with specific MUTEX to control Start of Frame(SOF) and End of Frame (EOF) signals. Before working with them, the addresses, interrupts, clocks and power domains need to be set up in dts. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230206091109.1324-4-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 526136703142..8fc527570791 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1801,6 +1801,15 @@ #clock-cells = <1>; }; + mutex@1400f000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x1400f000 0 0x1000>; + interrupts = ; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; + }; + smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { compatible = "mediatek,mt8195-smi-sub-common"; reg = <0 0x14010000 0 0x1000>; @@ -1906,6 +1915,15 @@ #clock-cells = <1>; }; + mutex@14f01000 { + compatible = "mediatek,mt8195-vpp-mutex"; + reg = <0 0x14f01000 0 0x1000>; + interrupts = ; + mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; + clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; + power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; + }; + larb5: larb@14f02000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x14f02000 0 0x1000>; From 404200964b24b19fe93325d24811f59a2a8b4de7 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Thu, 9 Feb 2023 17:03:55 +0100 Subject: [PATCH 0068/1040] arm64: dts: mt8167: Align mmsys node name with dtschema The node name should be generic and mmsys expcets 'syscon' Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230209160357.19307-2-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 6a54315cf650..2374c0953057 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -124,7 +124,7 @@ interrupts = ; }; - mmsys: mmsys@14000000 { + mmsys: syscon@14000000 { compatible = "mediatek,mt8167-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; From 90ae0327fb89f74024c46955dfc3184357bb5582 Mon Sep 17 00:00:00 2001 From: Xiangsheng Hou Date: Wed, 1 Feb 2023 10:14:58 +0800 Subject: [PATCH 0069/1040] arm: dts: mediatek: Fix existing NAND controller node name Change the existing node name in order to match NAND controller DT bindings. Signed-off-by: Xiangsheng Hou Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230201021500.26769-4-xiangsheng.hou@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt2701.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 0a0fe8c5a405..ce6a4015fed5 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -359,7 +359,7 @@ mediatek,apmixedsys = <&apmixedsys>; }; - nandc: nfi@1100d000 { + nandc: nand-controller@1100d000 { compatible = "mediatek,mt2701-nfc"; reg = <0 0x1100d000 0 0x1000>; interrupts = ; From 6154a79fdcb3b80fb91c25b4528df18c538f080d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Sun, 12 Feb 2023 15:13:54 +0300 Subject: [PATCH 0070/1040] arm: dts: mt7623: disable home key on Bananapi BPI-R2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's no home key on Bananapi BPI-R2. Disable it. Signed-off-by: Arınç ÜNAL Acked-by: Frank Wunderlich Link: https://lore.kernel.org/r/20230212121354.44590-1-arinc.unal@arinc9.com Signed-off-by: Matthias Brugger --- arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts index 5008115d2494..ece61a6a7a89 100644 --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts @@ -322,6 +322,12 @@ vqmmc-supply = <®_3p3v>; }; +&mt6323keys { + home { + status = "disabled"; + }; +}; + &mt6323_leds { status = "okay"; From 9f195f3a1e696b6576988c1e58fa7389beae3351 Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Thu, 2 Feb 2023 20:41:02 +0800 Subject: [PATCH 0071/1040] soc: mediatek: mtk-svs: use svs get efuse common function SVS might need to read both svs efuse and thermal efuse on the probe flow. Therefore, add a common efuse read function to remove the superfluous codes. Signed-off-by: Roger Lu Link: https://lore.kernel.org/r/20230202124104.16504-2-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 71 ++++++++++++---------------------- 1 file changed, 25 insertions(+), 46 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index f26eb2f637d5..c9899f5df60a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1729,26 +1729,28 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) return 0; } -static int svs_thermal_efuse_get_data(struct svs_platform *svsp) +static int svs_get_efuse_data(struct svs_platform *svsp, + const char *nvmem_cell_name, + u32 **svsp_efuse, size_t *svsp_efuse_max) { struct nvmem_cell *cell; - /* Thermal efuse parsing */ - cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + cell = nvmem_cell_get(svsp->dev, nvmem_cell_name); if (IS_ERR_OR_NULL(cell)) { - dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", PTR_ERR(cell)); + dev_err(svsp->dev, "no \"%s\"? %ld\n", + nvmem_cell_name, PTR_ERR(cell)); return PTR_ERR(cell); } - svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max); - if (IS_ERR(svsp->tefuse)) { - dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", - PTR_ERR(svsp->tefuse)); + *svsp_efuse = nvmem_cell_read(cell, svsp_efuse_max); + if (IS_ERR(*svsp_efuse)) { + dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n", + nvmem_cell_name, PTR_ERR(*svsp_efuse)); nvmem_cell_put(cell); - return PTR_ERR(svsp->tefuse); + return PTR_ERR(*svsp_efuse); } - svsp->tefuse_max /= sizeof(u32); + *svsp_efuse_max /= sizeof(u32); nvmem_cell_put(cell); return 0; @@ -1796,7 +1798,8 @@ static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) svsb->vmax += svsb->dvt_fixed; } - ret = svs_thermal_efuse_get_data(svsp); + ret = svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); if (ret) return false; @@ -1901,7 +1904,8 @@ static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) } } - ret = svs_thermal_efuse_get_data(svsp); + ret = svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); if (ret) return false; @@ -2003,32 +2007,6 @@ remove_mt8183_svsb_mon_mode: return true; } -static bool svs_is_efuse_data_correct(struct svs_platform *svsp) -{ - struct nvmem_cell *cell; - - /* Get svs efuse by nvmem */ - cell = nvmem_cell_get(svsp->dev, "svs-calibration-data"); - if (IS_ERR(cell)) { - dev_err(svsp->dev, "no \"svs-calibration-data\"? %ld\n", - PTR_ERR(cell)); - return false; - } - - svsp->efuse = nvmem_cell_read(cell, &svsp->efuse_max); - if (IS_ERR(svsp->efuse)) { - dev_err(svsp->dev, "cannot read svs efuse: %ld\n", - PTR_ERR(svsp->efuse)); - nvmem_cell_put(cell); - return false; - } - - svsp->efuse_max /= sizeof(u32); - nvmem_cell_put(cell); - - return true; -} - static struct device *svs_get_subsys_device(struct svs_platform *svsp, const char *node_name) { @@ -2364,8 +2342,9 @@ static int svs_probe(struct platform_device *pdev) if (ret) return ret; - if (!svs_is_efuse_data_correct(svsp)) { - dev_notice(svsp->dev, "efuse data isn't correct\n"); + ret = svs_get_efuse_data(svsp, "svs-calibration-data", + &svsp->efuse, &svsp->efuse_max); + if (ret) { ret = -EPERM; goto svs_probe_free_efuse; } @@ -2373,19 +2352,19 @@ static int svs_probe(struct platform_device *pdev) if (!svsp_data->efuse_parsing(svsp)) { dev_err(svsp->dev, "efuse data parsing failed\n"); ret = -EPERM; - goto svs_probe_free_resource; + goto svs_probe_free_tefuse; } ret = svs_bank_resource_setup(svsp); if (ret) { dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret); - goto svs_probe_free_resource; + goto svs_probe_free_tefuse; } svsp_irq = platform_get_irq(pdev, 0); if (svsp_irq < 0) { ret = svsp_irq; - goto svs_probe_free_resource; + goto svs_probe_free_tefuse; } svsp->main_clk = devm_clk_get(svsp->dev, "main"); @@ -2393,13 +2372,13 @@ static int svs_probe(struct platform_device *pdev) dev_err(svsp->dev, "failed to get clock: %ld\n", PTR_ERR(svsp->main_clk)); ret = PTR_ERR(svsp->main_clk); - goto svs_probe_free_resource; + goto svs_probe_free_tefuse; } ret = clk_prepare_enable(svsp->main_clk); if (ret) { dev_err(svsp->dev, "cannot enable main clk: %d\n", ret); - goto svs_probe_free_resource; + goto svs_probe_free_tefuse; } svsp->base = of_iomap(svsp->dev->of_node, 0); @@ -2439,7 +2418,7 @@ svs_probe_iounmap: svs_probe_clk_disable: clk_disable_unprepare(svsp->main_clk); -svs_probe_free_resource: +svs_probe_free_tefuse: if (!IS_ERR_OR_NULL(svsp->tefuse)) kfree(svsp->tefuse); From 5061c47ebf6edaf024fed1eaf63499fe7183c54e Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Thu, 2 Feb 2023 20:41:03 +0800 Subject: [PATCH 0072/1040] soc: mediatek: mtk-svs: use common function to disable restore voltages The timing of disabling SVS bank and restore default voltage is more than one place. Therefore, add a common function to use for removing the superfluous codes. Signed-off-by: Roger Lu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230202124104.16504-3-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 54 ++++++++++++++-------------------- 1 file changed, 22 insertions(+), 32 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index c9899f5df60a..299f580847bd 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -624,6 +624,25 @@ unlock_mutex: return ret; } +static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp, + struct svs_bank *svsb) +{ + unsigned long flags; + + if (svsb->mode_support == SVSB_MODE_ALL_DISABLE) + return; + + spin_lock_irqsave(&svs_lock, flags); + svsp->pbank = svsb; + svs_switch_bank(svsp); + svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); + svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); + spin_unlock_irqrestore(&svs_lock, flags); + + svsb->phase = SVSB_PHASE_ERROR; + svs_adjust_pm_opp_volts(svsb); +} + #ifdef CONFIG_DEBUG_FS static int svs_dump_debug_show(struct seq_file *m, void *p) { @@ -700,7 +719,6 @@ static ssize_t svs_enable_debug_write(struct file *filp, { struct svs_bank *svsb = file_inode(filp)->i_private; struct svs_platform *svsp = dev_get_drvdata(svsb->dev); - unsigned long flags; int enabled, ret; char *buf = NULL; @@ -716,16 +734,8 @@ static ssize_t svs_enable_debug_write(struct file *filp, return ret; if (!enabled) { - spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; + svs_bank_disable_and_restore_default_volts(svsp, svsb); svsb->mode_support = SVSB_MODE_ALL_DISABLE; - svs_switch_bank(svsp); - svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); - svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); - spin_unlock_irqrestore(&svs_lock, flags); - - svsb->phase = SVSB_PHASE_ERROR; - svs_adjust_pm_opp_volts(svsb); } kfree(buf); @@ -1508,16 +1518,7 @@ static int svs_init02(struct svs_platform *svsp) out_of_init02: for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - - spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_switch_bank(svsp); - svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); - svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); - spin_unlock_irqrestore(&svs_lock, flags); - - svsb->phase = SVSB_PHASE_ERROR; - svs_adjust_pm_opp_volts(svsb); + svs_bank_disable_and_restore_default_volts(svsp, svsb); } return ret; @@ -1563,23 +1564,12 @@ static int svs_suspend(struct device *dev) { struct svs_platform *svsp = dev_get_drvdata(dev); struct svs_bank *svsb; - unsigned long flags; int ret; u32 idx; for (idx = 0; idx < svsp->bank_max; idx++) { svsb = &svsp->banks[idx]; - - /* This might wait for svs_isr() process */ - spin_lock_irqsave(&svs_lock, flags); - svsp->pbank = svsb; - svs_switch_bank(svsp); - svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN); - svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS); - spin_unlock_irqrestore(&svs_lock, flags); - - svsb->phase = SVSB_PHASE_ERROR; - svs_adjust_pm_opp_volts(svsb); + svs_bank_disable_and_restore_default_volts(svsp, svsb); } ret = reset_control_assert(svsp->rst); From 7ceff25a184d64635ad911bc98f9497290708963 Mon Sep 17 00:00:00 2001 From: "Roy-CW.Yeh" Date: Mon, 6 Feb 2023 17:11:04 +0800 Subject: [PATCH 0073/1040] dt-bindings: soc: mediatek: Add support for MT8195 VPPSYS Add compatible for MT8195 VPPSYS on MUTEX. Signed-off-by: Roy-CW.Yeh Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230206091109.1324-2-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 15c133cac315..74c1061d32f1 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -35,6 +35,7 @@ properties: - mediatek,mt8188-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex + - mediatek,mt8195-vpp-mutex reg: maxItems: 1 From dd4f373ef94bd186e18a7366adfb7b98bc31b786 Mon Sep 17 00:00:00 2001 From: "Roy-CW.Yeh" Date: Mon, 6 Feb 2023 17:11:07 +0800 Subject: [PATCH 0074/1040] soc: mediatek: mmsys: add config api for RSZ switching and DCM Due to MT8195 HW design, some RSZs have additional settings that need to be configured in MMSYS. Signed-off-by: Roy-CW.Yeh Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Change-Id: I41978bf14951221c88abbe70d8c24cb0770e11e3 Link: https://lore.kernel.org/r/20230206091109.1324-5-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8195-mmsys.h | 13 ++++++++ drivers/soc/mediatek/mtk-mmsys.c | 44 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-mmsys.h | 6 ++++ 3 files changed, 63 insertions(+) diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index a6652ae63431..9be2df2832a4 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -146,6 +146,19 @@ #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER 0 +/* VPPSYS1 */ +#define MT8195_VPP1_HW_DCM_1ST_DIS0 0x150 +#define MT8195_VPP1_HW_DCM_1ST_DIS1 0x160 +#define MT8195_VPP1_HW_DCM_2ND_DIS0 0x1a0 +#define MT8195_VPP1_HW_DCM_2ND_DIS1 0x1b0 +#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH 0xf48 +#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH 0xf74 + +/* VPPSYS1 HW DCM client*/ +#define MT8195_SVPP1_MDP_RSZ BIT(25) +#define MT8195_SVPP2_MDP_RSZ BIT(4) +#define MT8195_SVPP3_MDP_RSZ BIT(5) + static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index eb4c7e57896c..fd2b37d451c8 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -242,6 +242,50 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config); +void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable, + struct cmdq_pkt *cmdq_pkt) +{ + u32 reg; + + switch (id) { + case 2: + reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH; + break; + case 3: + reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH; + break; + default: + dev_err(dev, "Invalid id %d\n", id); + return; + } + + mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable, cmdq_pkt); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_merge_config); + +void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable, + struct cmdq_pkt *cmdq_pkt) +{ + u32 client; + + client = MT8195_SVPP1_MDP_RSZ; + mtk_mmsys_update_bits(dev_get_drvdata(dev), + MT8195_VPP1_HW_DCM_1ST_DIS0, client, + ((enable) ? client : 0), cmdq_pkt); + mtk_mmsys_update_bits(dev_get_drvdata(dev), + MT8195_VPP1_HW_DCM_2ND_DIS0, client, + ((enable) ? client : 0), cmdq_pkt); + + client = MT8195_SVPP2_MDP_RSZ | MT8195_SVPP3_MDP_RSZ; + mtk_mmsys_update_bits(dev_get_drvdata(dev), + MT8195_VPP1_HW_DCM_1ST_DIS1, client, + ((enable) ? client : 0), cmdq_pkt); + mtk_mmsys_update_bits(dev_get_drvdata(dev), + MT8195_VPP1_HW_DCM_2ND_DIS1, client, + ((enable) ? client : 0), cmdq_pkt); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_dcm_config); + static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index dc2963a0a0f7..37544ea6286d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -99,4 +99,10 @@ void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap, struct cmdq_pkt *cmdq_pkt); +void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable, + struct cmdq_pkt *cmdq_pkt); + +void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable, + struct cmdq_pkt *cmdq_pkt); + #endif /* __MTK_MMSYS_H */ From c54d2b99c62ff6e371ce4a9ca925be22ed190de3 Mon Sep 17 00:00:00 2001 From: "Roy-CW.Yeh" Date: Mon, 6 Feb 2023 17:11:08 +0800 Subject: [PATCH 0075/1040] soc: mediatek: mutex: Add mtk_mutex_set_mod support to set MOD1 Add mtk_mutex_set_mod support to set MOD1 Signed-off-by: Roy-CW.Yeh Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230206091109.1324-6-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 33 +++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index c5b1b42303ac..a8d5fc3df5f0 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -23,6 +23,7 @@ #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4) #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n)) #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) @@ -828,7 +829,7 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex, struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, mutex[mutex->id]); unsigned int reg; - unsigned int offset; + u32 reg_offset, id_offset = 0; WARN_ON(&mtx->mutex[mutex->id] != mutex); @@ -838,16 +839,34 @@ int mtk_mutex_write_mod(struct mtk_mutex *mutex, return -EINVAL; } - offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, - mutex->id); - reg = readl_relaxed(mtx->regs + offset); + /* + * Some SoCs may have multiple MUTEX_MOD registers as more than 32 mods + * are present, hence requiring multiple 32-bits registers. + * + * The mutex_table_mod fully represents that by defining the number of + * the mod sequentially, later used as a bit number, which can be more + * than 0..31. + * + * In order to retain compatibility with older SoCs, we perform R/W on + * the single 32 bits registers, but this requires us to translate the + * mutex ID bit accordingly. + */ + if (mtx->data->mutex_table_mod[idx] < 32) { + reg_offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, + mutex->id); + } else { + reg_offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, + mutex->id); + id_offset = 32; + } + reg = readl_relaxed(mtx->regs + reg_offset); if (clear) - reg &= ~BIT(mtx->data->mutex_table_mod[idx]); + reg &= ~BIT(mtx->data->mutex_table_mod[idx] - id_offset); else - reg |= BIT(mtx->data->mutex_table_mod[idx]); + reg |= BIT(mtx->data->mutex_table_mod[idx] - id_offset); - writel_relaxed(reg, mtx->regs + offset); + writel_relaxed(reg, mtx->regs + reg_offset); return 0; } From 549053b69c54aecc6f44ddefe6c245a35f162cf4 Mon Sep 17 00:00:00 2001 From: "Roy-CW.Yeh" Date: Mon, 6 Feb 2023 17:11:09 +0800 Subject: [PATCH 0076/1040] soc: mediatek: mutex: support MT8195 VPPSYS Add MT8195 VPPSYS0 and VPPSYS1 mutex info to driver data Signed-off-by: Roy-CW.Yeh Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Change-Id: Ie371dc9dcf35ea308d9460acd60fb9c3d6475deb Link: https://lore.kernel.org/r/20230206091109.1324-7-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 102 +++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-mutex.h | 35 +++++++++ 2 files changed, 137 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index a8d5fc3df5f0..7751527fc30d 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -164,6 +164,53 @@ #define MT8195_MUTEX_MOD_DISP1_DPI1 26 #define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 +/* VPPSYS0 */ +#define MT8195_MUTEX_MOD_MDP_RDMA0 0 +#define MT8195_MUTEX_MOD_MDP_FG0 1 +#define MT8195_MUTEX_MOD_MDP_STITCH0 2 +#define MT8195_MUTEX_MOD_MDP_HDR0 3 +#define MT8195_MUTEX_MOD_MDP_AAL0 4 +#define MT8195_MUTEX_MOD_MDP_RSZ0 5 +#define MT8195_MUTEX_MOD_MDP_TDSHP0 6 +#define MT8195_MUTEX_MOD_MDP_COLOR0 7 +#define MT8195_MUTEX_MOD_MDP_OVL0 8 +#define MT8195_MUTEX_MOD_MDP_PAD0 9 +#define MT8195_MUTEX_MOD_MDP_TCC0 10 +#define MT8195_MUTEX_MOD_MDP_WROT0 11 + +/* VPPSYS1 */ +#define MT8195_MUTEX_MOD_MDP_TCC1 3 +#define MT8195_MUTEX_MOD_MDP_RDMA1 4 +#define MT8195_MUTEX_MOD_MDP_RDMA2 5 +#define MT8195_MUTEX_MOD_MDP_RDMA3 6 +#define MT8195_MUTEX_MOD_MDP_FG1 7 +#define MT8195_MUTEX_MOD_MDP_FG2 8 +#define MT8195_MUTEX_MOD_MDP_FG3 9 +#define MT8195_MUTEX_MOD_MDP_HDR1 10 +#define MT8195_MUTEX_MOD_MDP_HDR2 11 +#define MT8195_MUTEX_MOD_MDP_HDR3 12 +#define MT8195_MUTEX_MOD_MDP_AAL1 13 +#define MT8195_MUTEX_MOD_MDP_AAL2 14 +#define MT8195_MUTEX_MOD_MDP_AAL3 15 +#define MT8195_MUTEX_MOD_MDP_RSZ1 16 +#define MT8195_MUTEX_MOD_MDP_RSZ2 17 +#define MT8195_MUTEX_MOD_MDP_RSZ3 18 +#define MT8195_MUTEX_MOD_MDP_TDSHP1 19 +#define MT8195_MUTEX_MOD_MDP_TDSHP2 20 +#define MT8195_MUTEX_MOD_MDP_TDSHP3 21 +#define MT8195_MUTEX_MOD_MDP_MERGE2 22 +#define MT8195_MUTEX_MOD_MDP_MERGE3 23 +#define MT8195_MUTEX_MOD_MDP_COLOR1 24 +#define MT8195_MUTEX_MOD_MDP_COLOR2 25 +#define MT8195_MUTEX_MOD_MDP_COLOR3 26 +#define MT8195_MUTEX_MOD_MDP_OVL1 27 +#define MT8195_MUTEX_MOD_MDP_PAD1 28 +#define MT8195_MUTEX_MOD_MDP_PAD2 29 +#define MT8195_MUTEX_MOD_MDP_PAD3 30 +#define MT8195_MUTEX_MOD_MDP_WROT1 31 +#define MT8195_MUTEX_MOD_MDP_WROT2 32 +#define MT8195_MUTEX_MOD_MDP_WROT3 33 + #define MT8365_MUTEX_MOD_DISP_OVL0 7 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 #define MT8365_MUTEX_MOD_DISP_RDMA0 9 @@ -444,6 +491,52 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DP_INTF1] = MT8195_MUTEX_MOD_DISP1_DP_INTF0, }; +static const unsigned int mt8195_mutex_table_mod[MUTEX_MOD_IDX_MAX] = { + [MUTEX_MOD_IDX_MDP_RDMA0] = MT8195_MUTEX_MOD_MDP_RDMA0, + [MUTEX_MOD_IDX_MDP_RDMA1] = MT8195_MUTEX_MOD_MDP_RDMA1, + [MUTEX_MOD_IDX_MDP_RDMA2] = MT8195_MUTEX_MOD_MDP_RDMA2, + [MUTEX_MOD_IDX_MDP_RDMA3] = MT8195_MUTEX_MOD_MDP_RDMA3, + [MUTEX_MOD_IDX_MDP_STITCH0] = MT8195_MUTEX_MOD_MDP_STITCH0, + [MUTEX_MOD_IDX_MDP_FG0] = MT8195_MUTEX_MOD_MDP_FG0, + [MUTEX_MOD_IDX_MDP_FG1] = MT8195_MUTEX_MOD_MDP_FG1, + [MUTEX_MOD_IDX_MDP_FG2] = MT8195_MUTEX_MOD_MDP_FG2, + [MUTEX_MOD_IDX_MDP_FG3] = MT8195_MUTEX_MOD_MDP_FG3, + [MUTEX_MOD_IDX_MDP_HDR0] = MT8195_MUTEX_MOD_MDP_HDR0, + [MUTEX_MOD_IDX_MDP_HDR1] = MT8195_MUTEX_MOD_MDP_HDR1, + [MUTEX_MOD_IDX_MDP_HDR2] = MT8195_MUTEX_MOD_MDP_HDR2, + [MUTEX_MOD_IDX_MDP_HDR3] = MT8195_MUTEX_MOD_MDP_HDR3, + [MUTEX_MOD_IDX_MDP_AAL0] = MT8195_MUTEX_MOD_MDP_AAL0, + [MUTEX_MOD_IDX_MDP_AAL1] = MT8195_MUTEX_MOD_MDP_AAL1, + [MUTEX_MOD_IDX_MDP_AAL2] = MT8195_MUTEX_MOD_MDP_AAL2, + [MUTEX_MOD_IDX_MDP_AAL3] = MT8195_MUTEX_MOD_MDP_AAL3, + [MUTEX_MOD_IDX_MDP_RSZ0] = MT8195_MUTEX_MOD_MDP_RSZ0, + [MUTEX_MOD_IDX_MDP_RSZ1] = MT8195_MUTEX_MOD_MDP_RSZ1, + [MUTEX_MOD_IDX_MDP_RSZ2] = MT8195_MUTEX_MOD_MDP_RSZ2, + [MUTEX_MOD_IDX_MDP_RSZ3] = MT8195_MUTEX_MOD_MDP_RSZ3, + [MUTEX_MOD_IDX_MDP_MERGE2] = MT8195_MUTEX_MOD_MDP_MERGE2, + [MUTEX_MOD_IDX_MDP_MERGE3] = MT8195_MUTEX_MOD_MDP_MERGE3, + [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8195_MUTEX_MOD_MDP_TDSHP0, + [MUTEX_MOD_IDX_MDP_TDSHP1] = MT8195_MUTEX_MOD_MDP_TDSHP1, + [MUTEX_MOD_IDX_MDP_TDSHP2] = MT8195_MUTEX_MOD_MDP_TDSHP2, + [MUTEX_MOD_IDX_MDP_TDSHP3] = MT8195_MUTEX_MOD_MDP_TDSHP3, + [MUTEX_MOD_IDX_MDP_COLOR0] = MT8195_MUTEX_MOD_MDP_COLOR0, + [MUTEX_MOD_IDX_MDP_COLOR1] = MT8195_MUTEX_MOD_MDP_COLOR1, + [MUTEX_MOD_IDX_MDP_COLOR2] = MT8195_MUTEX_MOD_MDP_COLOR2, + [MUTEX_MOD_IDX_MDP_COLOR3] = MT8195_MUTEX_MOD_MDP_COLOR3, + [MUTEX_MOD_IDX_MDP_OVL0] = MT8195_MUTEX_MOD_MDP_OVL0, + [MUTEX_MOD_IDX_MDP_OVL1] = MT8195_MUTEX_MOD_MDP_OVL1, + [MUTEX_MOD_IDX_MDP_PAD0] = MT8195_MUTEX_MOD_MDP_PAD0, + [MUTEX_MOD_IDX_MDP_PAD1] = MT8195_MUTEX_MOD_MDP_PAD1, + [MUTEX_MOD_IDX_MDP_PAD2] = MT8195_MUTEX_MOD_MDP_PAD2, + [MUTEX_MOD_IDX_MDP_PAD3] = MT8195_MUTEX_MOD_MDP_PAD3, + [MUTEX_MOD_IDX_MDP_TCC0] = MT8195_MUTEX_MOD_MDP_TCC0, + [MUTEX_MOD_IDX_MDP_TCC1] = MT8195_MUTEX_MOD_MDP_TCC1, + [MUTEX_MOD_IDX_MDP_WROT0] = MT8195_MUTEX_MOD_MDP_WROT0, + [MUTEX_MOD_IDX_MDP_WROT1] = MT8195_MUTEX_MOD_MDP_WROT1, + [MUTEX_MOD_IDX_MDP_WROT2] = MT8195_MUTEX_MOD_MDP_WROT2, + [MUTEX_MOD_IDX_MDP_WROT3] = MT8195_MUTEX_MOD_MDP_WROT3, +}; + static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR, @@ -604,6 +697,13 @@ static const struct mtk_mutex_data mt8195_mutex_driver_data = { .mutex_sof_reg = MT8183_MUTEX0_SOF0, }; +static const struct mtk_mutex_data mt8195_vpp_mutex_driver_data = { + .mutex_sof = mt8195_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, + .mutex_table_mod = mt8195_mutex_table_mod, +}; + static const struct mtk_mutex_data mt8365_mutex_driver_data = { .mutex_mod = mt8365_mutex_mod, .mutex_sof = mt8183_mutex_sof, @@ -962,6 +1062,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8192_mutex_driver_data}, { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data}, + { .compatible = "mediatek,mt8195-vpp-mutex", + .data = &mt8195_vpp_mutex_driver_data}, { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data}, {}, diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h index b335c2837cd8..635218e3ac68 100644 --- a/include/linux/soc/mediatek/mtk-mutex.h +++ b/include/linux/soc/mediatek/mtk-mutex.h @@ -22,6 +22,41 @@ enum mtk_mutex_mod_index { MUTEX_MOD_IDX_MDP_CCORR0, MUTEX_MOD_IDX_MDP_HDR0, MUTEX_MOD_IDX_MDP_COLOR0, + MUTEX_MOD_IDX_MDP_RDMA1, + MUTEX_MOD_IDX_MDP_RDMA2, + MUTEX_MOD_IDX_MDP_RDMA3, + MUTEX_MOD_IDX_MDP_STITCH0, + MUTEX_MOD_IDX_MDP_FG0, + MUTEX_MOD_IDX_MDP_FG1, + MUTEX_MOD_IDX_MDP_FG2, + MUTEX_MOD_IDX_MDP_FG3, + MUTEX_MOD_IDX_MDP_HDR1, + MUTEX_MOD_IDX_MDP_HDR2, + MUTEX_MOD_IDX_MDP_HDR3, + MUTEX_MOD_IDX_MDP_AAL1, + MUTEX_MOD_IDX_MDP_AAL2, + MUTEX_MOD_IDX_MDP_AAL3, + MUTEX_MOD_IDX_MDP_RSZ2, + MUTEX_MOD_IDX_MDP_RSZ3, + MUTEX_MOD_IDX_MDP_MERGE2, + MUTEX_MOD_IDX_MDP_MERGE3, + MUTEX_MOD_IDX_MDP_TDSHP1, + MUTEX_MOD_IDX_MDP_TDSHP2, + MUTEX_MOD_IDX_MDP_TDSHP3, + MUTEX_MOD_IDX_MDP_COLOR1, + MUTEX_MOD_IDX_MDP_COLOR2, + MUTEX_MOD_IDX_MDP_COLOR3, + MUTEX_MOD_IDX_MDP_OVL0, + MUTEX_MOD_IDX_MDP_OVL1, + MUTEX_MOD_IDX_MDP_PAD0, + MUTEX_MOD_IDX_MDP_PAD1, + MUTEX_MOD_IDX_MDP_PAD2, + MUTEX_MOD_IDX_MDP_PAD3, + MUTEX_MOD_IDX_MDP_TCC0, + MUTEX_MOD_IDX_MDP_TCC1, + MUTEX_MOD_IDX_MDP_WROT1, + MUTEX_MOD_IDX_MDP_WROT2, + MUTEX_MOD_IDX_MDP_WROT3, MUTEX_MOD_IDX_MAX /* ALWAYS keep at the end */ }; From 2ba4e3bd65213f3eae75fcd316ae38d4286d333e Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Thu, 9 Feb 2023 17:24:03 +0100 Subject: [PATCH 0077/1040] soc: mediatek: mtk-svs: delete node name check The function svs_add_device_link is called only internally from the SoC specific probe functions. We don't need to check if the node_name is null because that would mean that we have a buggy SoC probe function in the first place. Reviewed-by: Roger Lu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230209162403.21113-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 299f580847bd..a7eb019b5157 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -2027,11 +2027,6 @@ static struct device *svs_add_device_link(struct svs_platform *svsp, struct device *dev; struct device_link *sup_link; - if (!node_name) { - dev_err(svsp->dev, "node name cannot be null\n"); - return ERR_PTR(-EINVAL); - } - dev = svs_get_subsys_device(svsp, node_name); if (IS_ERR(dev)) return dev; From 521568cff7065069bfb02b3a9945bac637d2e324 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 22 Feb 2023 22:21:28 -0600 Subject: [PATCH 0078/1040] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D. Add clock indices and binding documentation for CMU_G3D. Acked-by: Rob Herring Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20230223042133.26551-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../clock/samsung,exynos850-clock.yaml | 19 ++++++++++++++++++ include/dt-bindings/clock/exynos850.h | 20 ++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index 141cf173f87d..8aa87b8c1b33 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -37,6 +37,7 @@ properties: - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi - samsung,exynos850-cmu-is - samsung,exynos850-cmu-mfcmscl @@ -169,6 +170,24 @@ allOf: - const: oscclk - const: dout_dpu + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 88d5289883d3..8bb62e43fd60 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -85,7 +85,10 @@ #define CLK_DOUT_MFCMSCL_M2M 73 #define CLK_DOUT_MFCMSCL_MCSC 74 #define CLK_DOUT_MFCMSCL_JPEG 75 -#define TOP_NR_CLK 76 +#define CLK_MOUT_G3D_SWITCH 76 +#define CLK_GOUT_G3D_SWITCH 77 +#define CLK_DOUT_G3D_SWITCH 78 +#define TOP_NR_CLK 79 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +198,21 @@ #define CLK_GOUT_SYSREG_CMGP_PCLK 15 #define CMGP_NR_CLK 16 +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 +#define CLK_MOUT_G3D_PLL 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_BUSD 4 +#define CLK_DOUT_G3D_BUSP 5 +#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 +#define CLK_GOUT_G3D_GPU_CLK 7 +#define CLK_GOUT_G3D_TZPC_PCLK 8 +#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 +#define CLK_GOUT_G3D_BUSD_CLK 10 +#define CLK_GOUT_G3D_BUSP_CLK 11 +#define CLK_GOUT_G3D_SYSREG_PCLK 12 +#define G3D_NR_CLK 13 + /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 #define CLK_MOUT_HSI_MMC_CARD_USER 2 From 284f6dcb50ae7f25167617c89aa2d3f93323ee67 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 22 Feb 2023 22:21:29 -0600 Subject: [PATCH 0079/1040] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Acked-by: Rob Herring Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20230223042133.26551-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/clock/exynos850.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 8bb62e43fd60..afacba338c91 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -178,7 +178,8 @@ #define IOCLK_AUDIOCDCLK5 58 #define IOCLK_AUDIOCDCLK6 59 #define TICK_USB 60 -#define AUD_NR_CLK 61 +#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 +#define AUD_NR_CLK 62 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -227,7 +228,10 @@ #define CLK_GOUT_MMC_CARD_ACLK 11 #define CLK_GOUT_MMC_CARD_SDCLKIN 12 #define CLK_GOUT_SYSREG_HSI_PCLK 13 -#define HSI_NR_CLK 14 +#define CLK_GOUT_HSI_PPMU_ACLK 14 +#define CLK_GOUT_HSI_PPMU_PCLK 15 +#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 +#define HSI_NR_CLK 17 /* CMU_IS */ #define CLK_MOUT_IS_BUS_USER 1 From 017cdefe9dce8b241c3c506ef4cd51e90084e7c1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 20:40:57 +0100 Subject: [PATCH 0080/1040] arm64: dts: exynos: move MIPI phy to PMU node in Exynos5433 The MIPI phy is actually part of the Power Management Unit system controller. It does not have own address space, thus keeping the node under soc causes warnings: exynos5433-tm2e.dtb: soc@0: video-phy: {'compatible': ['samsung,exynos5433-mipi-video-phy'], ... should not be valid under {'type': 'object'} Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230127194057.186458-9-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 5519a80576c5..91ae0462a706 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -911,12 +911,20 @@ }; pmu_system_controller: system-controller@105c0000 { - compatible = "samsung,exynos5433-pmu", "syscon"; + compatible = "samsung,exynos5433-pmu", "simple-mfd", "syscon"; reg = <0x105c0000 0x5008>; #clock-cells = <1>; clock-names = "clkout16"; clocks = <&xxti>; + mipi_phy: mipi-phy { + compatible = "samsung,exynos5433-mipi-video-phy"; + #phy-cells = <1>; + samsung,cam0-sysreg = <&syscon_cam0>; + samsung,cam1-sysreg = <&syscon_cam1>; + samsung,disp-sysreg = <&syscon_disp>; + }; + reboot: syscon-reboot { compatible = "syscon-reboot"; regmap = <&pmu_system_controller>; @@ -936,15 +944,6 @@ interrupts = ; }; - mipi_phy: video-phy { - compatible = "samsung,exynos5433-mipi-video-phy"; - #phy-cells = <1>; - samsung,pmu-syscon = <&pmu_system_controller>; - samsung,cam0-sysreg = <&syscon_cam0>; - samsung,cam1-sysreg = <&syscon_cam1>; - samsung,disp-sysreg = <&syscon_disp>; - }; - decon: decon@13800000 { compatible = "samsung,exynos5433-decon"; reg = <0x13800000 0x2104>; From 35ade1eb465438cfd16fdc3a4905dd82f658fdce Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Wed, 22 Feb 2023 22:21:33 -0600 Subject: [PATCH 0081/1040] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC Add missing G3D clock domain to Exynos850 SoC device tree. Reviewed-by: Chanho Park Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20230223042133.26551-7-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index a38fe5129937..d67e98120313 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -245,6 +245,15 @@ "dout_peri_uart", "dout_peri_ip"; }; + cmu_g3d: clock-controller@11400000 { + compatible = "samsung,exynos850-cmu-g3d"; + reg = <0x11400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; + clock-names = "oscclk", "dout_g3d_switch"; + }; + cmu_apm: clock-controller@11800000 { compatible = "samsung,exynos850-cmu-apm"; reg = <0x11800000 0x8000>; From ea6dbf86b8d06b3902cb888dd4a75a794e9ef445 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 8 Feb 2023 07:56:39 +0100 Subject: [PATCH 0082/1040] dt-bindings: arm: fsl: add toradex,apalis-imx8 et al. Add toradex,apalis-imx8 for the Apalis iMX8 aka QuadMax modules and the carrier boards (Apalis Evaluation board as well as Ixora V1.1 and V1.2) they may be mated in. Signed-off-by: Marcel Ziswiler Acked-by: Rob Herring Signed-off-by: Shawn Guo --- .../devicetree/bindings/arm/fsl.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 442ce8f4d675..2c90455722f0 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1119,6 +1119,25 @@ properties: items: - enum: - fsl,imx8qm-mek # i.MX8QM MEK Board + - toradex,apalis-imx8 # Apalis iMX8 Modules + - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules + - const: fsl,imx8qm + + - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules + items: + - enum: + - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board + - toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board + - const: toradex,apalis-imx8 + - const: fsl,imx8qm + + - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules + items: + - enum: + - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board + - toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board + - toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board + - const: toradex,apalis-imx8-v1.1 - const: fsl,imx8qm - description: i.MX8QXP based Boards From 23fa99b205ea50f89c9db20e9afdddd8381d9ea0 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Wed, 8 Feb 2023 07:56:32 +0100 Subject: [PATCH 0083/1040] arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3 Add support for lsio_pwm0-3. Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-lsio.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 1f3d225e64ec..62b7f7a3e1bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -28,6 +28,54 @@ lsio_subsys: bus@5d000000 { clock-output-names = "lsio_bus_clk"; }; + lsio_pwm0: pwm@5d000000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d000000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm0_lpcg 4>, + <&pwm0_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + lsio_pwm1: pwm@5d010000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d010000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm1_lpcg 4>, + <&pwm1_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + lsio_pwm2: pwm@5d020000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d020000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm2_lpcg 4>, + <&pwm2_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + lsio_pwm3: pwm@5d030000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d030000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm3_lpcg 4>, + <&pwm3_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + lsio_gpio0: gpio@5d080000 { reg = <0x5d080000 0x10000>; interrupts = ; From b503c3c01c08acc54e8a5e8a41daafae023e56f0 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Wed, 8 Feb 2023 07:56:33 +0100 Subject: [PATCH 0084/1040] arm64: dts: imx8-ss-dma: add io-channel-cells to adc nodes This commit adds io-channel-cells property to the ADC nodes. This property is required in order for an IIO consumer driver to work. Especially required for Apalis iMX8 QM, as the touchscreen driver uses ADC channels with the ADC driver based on IIO framework. Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Marcel Ziswiler Acked-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index a943a1e2797f..6e5ef8b69bf8 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -270,6 +270,7 @@ dma_subsys: bus@5a000000 { adc0: adc@5a880000 { compatible = "nxp,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x5a880000 0x10000>; interrupts = ; interrupt-parent = <&gic>; @@ -284,6 +285,7 @@ dma_subsys: bus@5a000000 { adc1: adc@5a890000 { compatible = "nxp,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x5a890000 0x10000>; interrupts = ; interrupt-parent = <&gic>; From 033f5e7ef8540a6b5e3b59e1311683a6114c2d2e Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Wed, 8 Feb 2023 07:56:34 +0100 Subject: [PATCH 0085/1040] arm64: dts: freescale: imx8-ss-dma: set lpspi0 max frequency to 60mhz 60MHz is the maximum frequency mentioned in the datasheet for master mode. Set that to 60MHz to match lpspi2. Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6e5ef8b69bf8..6ccf926b77a5 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -31,7 +31,7 @@ dma_subsys: bus@5a000000 { <&spi0_lpcg 1>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <20000000>; + assigned-clock-rates = <60000000>; power-domains = <&pd IMX_SC_R_SPI_0>; status = "disabled"; }; From 5e7d5b023e032c30095deca9745fe8e82491ba64 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Wed, 8 Feb 2023 07:56:36 +0100 Subject: [PATCH 0086/1040] arm64: dts: imx8qxp: add flexcan in adma Add FlexCAN decive in adma subsystem. Signed-off-by: Joakim Zhang Signed-off-by: Marcel Ziswiler Tested-by: Alexander Stein # TQMa8XQP Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index 6ccf926b77a5..2dce8f2ee3ea 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -298,6 +298,65 @@ dma_subsys: bus@5a000000 { status = "disabled"; }; + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8d0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_0>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8e0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN1 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_1>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <1>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qm-flexcan"; + reg = <0x5a8f0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + /* CAN0 clock and PD is shared among all CAN instances as + * CAN2 shares CAN0's clock and to enable CAN0's clock it + * has to be powered on. + */ + clocks = <&can0_lpcg 1>, + <&can0_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <40000000>; + power-domains = <&pd IMX_SC_R_CAN_2>; + /* SLSlice[4] */ + fsl,clk-source = /bits/ 8 <0>; + fsl,scu-index = /bits/ 8 <2>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -369,4 +428,17 @@ dma_subsys: bus@5a000000 { "adc1_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_ADC_1>; }; + + can0_lpcg: clock-controller@5acd0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acd0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = , , ; + clock-output-names = "can0_lpcg_pe_clk", + "can0_lpcg_ipg_clk", + "can0_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_0>; + }; }; From be85831de020f3cfb6811ec64f41a70bb62374b3 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Wed, 8 Feb 2023 07:56:37 +0100 Subject: [PATCH 0087/1040] arm64: dts: imx8qm: add can node in devicetree Add CAN node for imx8qm in devicetree. Unlike on the i.MX 8QXP where the flexcan clocks are shared between multiple CAN instances, the i.MX 8QM has separate flexcan clock slices. Signed-off-by: Joakim Zhang Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8qm-ss-dma.dtsi | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index bbe5f5ecfb92..e9b198c13b2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -16,6 +16,50 @@ "uart4_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_UART_4>; }; + + can1_lpcg: clock-controller@5ace0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ace0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = , , ; + clock-output-names = "can1_lpcg_pe_clk", + "can1_lpcg_ipg_clk", + "can1_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_1>; + }; + + can2_lpcg: clock-controller@5acf0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5acf0000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>, <&dma_ipg_clk>; + clock-indices = , , ; + clock-output-names = "can2_lpcg_pe_clk", + "can2_lpcg_ipg_clk", + "can2_lpcg_chi_clk"; + power-domains = <&pd IMX_SC_R_CAN_2>; + }; +}; + +&flexcan1 { + fsl,clk-source = /bits/ 8 <1>; +}; + +&flexcan2 { + clocks = <&can1_lpcg 1>, + <&can1_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>; + fsl,clk-source = /bits/ 8 <1>; +}; + +&flexcan3 { + clocks = <&can2_lpcg 1>, + <&can2_lpcg 0>; + assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>; + fsl,clk-source = /bits/ 8 <1>; }; &lpuart0 { From b4efce453f0caca948df3faa8c8b816edd2240eb Mon Sep 17 00:00:00 2001 From: Zhou Peng Date: Wed, 8 Feb 2023 07:56:38 +0100 Subject: [PATCH 0088/1040] arm64: dts: imx8qm: add vpu decoder and encoder Enable VPU decoder and encoder functionality. Signed-off-by: Zhou Peng Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 41ce8336f29e..9fff867709f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -23,6 +23,9 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; cpus { @@ -212,6 +215,7 @@ }; /* sorted in register address */ + #include "imx8-ss-vpu.dtsi" #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" #include "imx8-ss-conn.dtsi" From ad0de4ceb706f140329f4dd310282e6fa2a1937a Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 8 Feb 2023 07:56:40 +0100 Subject: [PATCH 0089/1040] arm64: dts: freescale: add initial apalis imx8 aka quadmax module support This patch adds the device tree to support Toradex Apalis iMX8 [1] aka QuadMax a computer on module which can be used on different carrier boards. The module consists of an NXP i.MX 8 family SoC (either i.MX 8QuadMax or 8QuadPlus), two PF8100 PMICs, a KSZ9131 Gigabit Ethernet PHY, 2, 4 or 8 GB of LPDDR4 RAM, an eMMC, an SGTL5000 analogue audio codec, an USB3503A USB HSIC hub, an optional I2C EEPROM plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. The carrier board device trees in the next patch will include the module's device tree and enable the supported peripherals of the carrier board. Some level of display functionality just landed upstream but requires further integration/testing on our side. Therefore, currently only basic console UART, eMMC and Ethernet functionality work fine. As there is no i.MX 8QuadPlus device tree upstream those have been dropped. However, apart from an error message during boot about it failing to bring up the second Cortex-A72 core this boots fine on QuadPlus' as well. [1] https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-apalis-v1.1.dtsi | 1485 +++++++++++++++++ .../dts/freescale/imx8qm-apalis-v1.1.dtsi | 16 + .../boot/dts/freescale/imx8qm-apalis.dtsi | 340 ++++ 3 files changed, 1841 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi new file mode 100644 index 000000000000..486adf849452 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -0,0 +1,1485 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include + +/ { + chosen { + stdout-path = &lpuart1; + }; + + /* Apalis BKL1 */ + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bkl_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ + /* TODO: hook-up to Apalis BKL1_PWM */ + status = "disabled"; + }; + + gpio_fan: gpio-fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio8>; + gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + + /* TODO: LVDS Panel */ + + /* TODO: Shared PCIe/SATA Reference Clock */ + + /* TODO: PCIe Wi-Fi Reference Clock */ + + /* + * Power management bus used to control LDO1OUT of the + * second PMIC PF8100. This is used for controlling voltage levels of + * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS. + * + * IMX_SC_R_BOARD_R1 for 3.3V + * IMX_SC_R_BOARD_R2 for 1.8V + * IMX_SC_R_BOARD_R3 for 2.5V + * Note that for 2.5V operation the pad muxing needs to be changed, + * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD. + * + * those power domains are mutually exclusive. + */ + reg_ext_rgmii: regulator-ext-rgmii { + compatible = "regulator-fixed"; + power-domains = <&pd IMX_SC_R_BOARD_R1>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_EXT_RGMII (LDO1)"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_AUDIO"; + }; + + reg_module_wifi: regulator-module-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pdn>; + gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "wifi_pwrdn_fake_regulator"; + regulator-settling-time-us = <100>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "pcie_switch"; + startup-delay-us = <100000>; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + /* Apalis USBH_EN */ + gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-host-vbus"; + }; + + reg_usb_hsic: regulator-usb-hsic { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "usb-hsic-dummy"; + }; + + reg_usb_phy: regulator-usb-hsic1 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "usb-phy-dummy"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder1_boot: encoder1-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + encoder2_boot: encoder2-boot@86200000 { + reg = <0 0x86200000 0 0x200000>; + no-map; + }; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@88000000 { + reg = <0 0x88000000 0 0x8000000>; + no-map; + }; + + rpmsg_reserved: rpmsg@90200000 { + reg = <0 0x90200000 0 0x200000>; + no-map; + }; + + vdevbuffer: vdevbuffer@90400000 { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + dsp_reserved: dsp@92400000 { + reg = <0 0x92400000 0 0x2000000>; + no-map; + }; + + encoder1_rpc: encoder1-rpc@94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; + + encoder2_rpc: encoder2-rpc@94b00000 { + reg = <0 0x94b00000 0 0x700000>; + no-map; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0xc0000000 0 0x3c000000>; + linux,cma-default; + reusable; + size = <0 0x3c000000>; + }; + }; + + /* TODO: Apalis Analogue Audio */ + + /* TODO: HDMI Audio */ + + /* TODO: Apalis SPDIF1 */ + + touchscreen: touchscreen { + compatible = "toradex,vf50-touchscreen"; + interrupt-parent = <&lsio_gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "idle", "default"; + pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; + pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>; + io-channels = <&adc1 2>, <&adc1 1>, + <&adc1 0>, <&adc1 3>; + vf50-ts-min-pressure = <200>; + xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>; + xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>; + yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>; + ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>; + /* + * NOTE: you must remove the pinctrl-adc1 from the adc1 + * node below to use the touchscreen + */ + status = "disabled"; + }; + +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; +}; + +/* TODO: Asynchronous Sample Rate Converter (ASRC) */ + +/* Apalis ETH1 */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reset-assert-us = <2>; + reset-deassert-us = <2>; + reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; + reset-names = "phy-reset"; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Apalis CAN2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Apalis CAN3 (optional) */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* TODO: Apalis HDMI1 */ + +/* On-module I2C */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + /* TODO: Audio Codec */ + + /* USB3503A */ + usb-hub@8 { + compatible = "smsc,usb3503a"; + reg = <0x08>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; + refclk-frequency = <25000000>; + reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +/* Apalis I2C1 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + + atmel_mxt_ts: touch@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; + reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>; /* Apalis GPIO6 */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + status = "disabled"; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +/* TODO: Apalis LVDS1 */ + +/* Apalis SPI1 */ +&lpspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; +}; + +/* Apalis SPI2 */ +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; +}; + +/* Apalis UART3 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* Apalis UART4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Apalis UART2 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +&lsio_gpio0 { + gpio-line-names = "MXM3_279", + "MXM3_277", + "MXM3_135", + "MXM3_203", + "MXM3_201", + "MXM3_275", + "MXM3_110", + "MXM3_120", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_124", + "MXM3_122", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "", + "", + "MXM3_4", + "MXM3_211", + "MXM3_209", + "MXM3_2", + "MXM3_136", + "MXM3_134", + "MXM3_6", + "MXM3_8", + "MXM3_112", + "MXM3_118", + "MXM3_114", + "MXM3_116"; +}; + +&lsio_gpio1 { + gpio-line-names = "", + "", + "", + "", + "MXM3_286", + "", + "MXM3_87", + "MXM3_99", + "MXM3_138", + "MXM3_140", + "MXM3_239", + "", + "MXM3_281", + "MXM3_283", + "MXM3_126", + "MXM3_132", + "", + "", + "", + "", + "MXM3_173", + "MXM3_175", + "MXM3_123"; + + hdmi-ctrl-hog { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ctrl>; + gpio-hog; + gpios = <30 GPIO_ACTIVE_HIGH>; + line-name = "CONNECTOR_IS_HDMI"; + /* Set signals depending on HDP device type, 0 DP, 1 HDMI */ + output-high; + }; +}; + +&lsio_gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "MXM3_198", + "MXM3_35", + "MXM3_164", + "", + "", + "", + "", + "MXM3_217", + "MXM3_215", + "", + "", + "MXM3_193", + "MXM3_194", + "MXM3_37", + "", + "MXM3_271", + "MXM3_273", + "MXM3_195", + "MXM3_197", + "MXM3_177", + "MXM3_179", + "MXM3_181", + "MXM3_183", + "MXM3_185", + "MXM3_187"; + + /* + * Add GPIO2_20 as a wakeup source: + * Pin: 101 SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) + * Type: 5 SC_PAD_WAKEUP_FALL_EDGE + * Line: 20 + */ + pad-wakeup = ; + pad-wakeup-num = <1>; + + pcie-wifi-hog { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "PCIE_WIFI_CLK"; + output-high; + }; +}; + +&lsio_gpio3 { + gpio-line-names = "MXM3_191", + "", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_200", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_204", + "MXM3_196", + "", + "MXM3_202", + "", + "", + "", + "MXM3_305", + "MXM3_307", + "MXM3_309", + "MXM3_311", + "MXM3_315", + "MXM3_317", + "MXM3_319", + "MXM3_321", + "MXM3_15/GPIO7", + "MXM3_63", + "MXM3_17/GPIO8", + "MXM3_12", + "MXM3_14", + "MXM3_16"; +}; + +&lsio_gpio4 { + gpio-line-names = "MXM3_18", + "MXM3_11/GPIO5", + "MXM3_13/GPIO6", + "MXM3_274", + "MXM3_84", + "MXM3_262", + "MXM3_96", + "", + "", + "", + "", + "", + "MXM3_190", + "", + "", + "", + "MXM3_269", + "MXM3_251", + "MXM3_253", + "MXM3_295", + "MXM3_299", + "MXM3_301", + "MXM3_297", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287"; + + /* Enable pcie root / sata ref clock unconditionally */ + pcie-sata-hog { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_sata_refclk>; + gpio-hog; + gpios = <11 GPIO_ACTIVE_HIGH>; + line-name = "PCIE_SATA_CLK"; + output-high; + }; +}; + +&lsio_gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_150", + "MXM3_160", + "MXM3_162", + "MXM3_144", + "MXM3_146", + "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_159", + "MXM3_184", + "MXM3_180", + "MXM3_186", + "MXM3_188", + "MXM3_176", + "MXM3_178"; +}; + +&lsio_gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_261", + "MXM3_263", + "MXM3_259", + "MXM3_257", + "MXM3_255", + "MXM3_128", + "MXM3_130", + "MXM3_265", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_243"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&lsio_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + #pwm-cells = <3>; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&lsio_pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&lsio_pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&lsio_pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + #pwm-cells = <3>; +}; + +/* Messaging Units */ +&mu_m0{ + status = "okay"; +}; + +&mu1_m0{ + status = "okay"; +}; + +&mu2_m0{ + status = "okay"; +}; + +/* TODO: Apalis PCIE1 */ + +/* TODO: On-module Wi-Fi */ + +/* TODO: Apalis BKL1_PWM */ + +/* TODO: Apalis DAP1 */ + +/* TODO: Analogue Audio */ + +/* TODO: Apalis SATA1 */ + +/* TODO: Apalis SPDIF1 */ + +/* TODO: Thermal Zones */ + +/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ + +/* TODO: Apalis USBH4 */ + +/* Apalis USBO1 */ +&usbphy1 { + phy-3p0-supply = <®_usb_phy>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + adp-disable; + ci-disable-lpm; + hnp-disable; + over-current-active-low; + power-active-high; + srp-disable; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_4bit>, + <&pinctrl_usdhc2_8bit>, + <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, + <&pinctrl_usdhc2_8bit_100mhz>, + <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, + <&pinctrl_usdhc2_8bit_200mhz>, + <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, + <&pinctrl_usdhc2_8bit_sleep>, + <&pinctrl_mmc1_cd_sleep>; + bus-width = <8>; + cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ + no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>; + bus-width = <4>; + cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ + no-1-8-v; +}; + +/* Video Processing Unit */ +&vpu { + compatible = "nxp,imx8qm-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d080000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d090000 0x10000>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + status = "okay"; +}; + +&vpu_core2 { + reg = <0x2d0a0000 0x10000>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>, + <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>, + <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, + <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, + <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>, + <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>, + <&pinctrl_usdhc1_gpios>; + + /* Apalis AN1_ADC */ + pinctrl_adc0: adc0grp { + fsl,pins = /* Apalis AN1_ADC0 */ + , + /* Apalis AN1_ADC1 */ + , + /* Apalis AN1_ADC2 */ + , + /* Apalis AN1_TSWIP_ADC3 */ + ; + }; + + /* Apalis AN1_TS */ + pinctrl_adc1: adc1grp { + fsl,pins = /* Apalis AN1_TSPX */ + , + /* Apalis AN1_TSMX */ + , + /* Apalis AN1_TSPY */ + , + /* Apalis AN1_TSMY */ + ; + }; + + /* Apalis CAM1 */ + pinctrl_cam1_gpios: cam1gpiosgrp { + fsl,pins = /* Apalis CAM1_D7 */ + , + /* Apalis CAM1_D6 */ + , + /* Apalis CAM1_D5 */ + , + /* Apalis CAM1_D4 */ + , + /* Apalis CAM1_D3 */ + , + /* Apalis CAM1_D2 */ + , + /* Apalis CAM1_D1 */ + , + /* Apalis CAM1_D0 */ + , + /* Apalis CAM1_PCLK */ + , + /* Apalis CAM1_MCLK */ + , + /* Apalis CAM1_VSYNC */ + , + /* Apalis CAM1_HSYNC */ + ; + }; + + /* Apalis DAP1 */ + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = /* Apalis DAP1_MCLK */ + , + /* Apalis DAP1_D_OUT */ + , + /* Apalis DAP1_RESET */ + , + /* Apalis DAP1_BIT_CLK */ + , + /* Apalis DAP1_D_IN */ + , + /* Apalis DAP1_SYNC */ + , + /* On-module Wi-Fi_I2S_EN# */ + ; + }; + + /* Apalis LCD1_G1+2 */ + pinctrl_esai0_gpios: esai0gpiosgrp { + fsl,pins = /* Apalis LCD1_G1 */ + , + /* Apalis LCD1_G2 */ + ; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */ + pinctrl_fec1: fec1grp { + fsl,pins = /* Use pads in 3.3V mode */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + /* On-module ETH_RESET# */ + , + /* On-module ETH_INT# */ + ; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + /* Apalis LCD1_ */ + pinctrl_fec2_gpios: fec2gpiosgrp { + fsl,pins = , + /* Apalis LCD1_R1 */ + , + /* Apalis LCD1_R0 */ + , + /* Apalis LCD1_G0 */ + , + /* Apalis LCD1_R7 */ + , + /* Apalis LCD1_DE */ + , + /* Apalis LCD1_HSYNC */ + , + /* Apalis LCD1_VSYNC */ + , + /* Apalis LCD1_PCLK */ + , + /* Apalis LCD1_R6 */ + , + /* Apalis LCD1_R5 */ + , + /* Apalis LCD1_R4 */ + , + /* Apalis LCD1_R3 */ + , + /* Apalis LCD1_R2 */ + ; + }; + + /* Apalis CAN1 */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = , + ; + }; + + /* Apalis CAN2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = , + ; + }; + + /* Apalis CAN3 (optional) */ + pinctrl_flexcan3: flexcan2grp { + fsl,pins = , + ; + }; + + /* Apalis GPIO1 */ + pinctrl_gpio1: gpio1grp { + fsl,pins = ; + }; + + /* Apalis GPIO2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = ; + }; + + /* Apalis GPIO3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = ; + }; + + /* Apalis GPIO4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = ; + }; + + /* Apalis GPIO5 */ + pinctrl_gpio5: gpio5grp { + fsl,pins = ; + }; + + /* Apalis GPIO6 */ + pinctrl_gpio6: gpio6grp { + fsl,pins = ; + }; + + /* Apalis GPIO7 */ + pinctrl_gpio7: gpio7grp { + fsl,pins = ; + }; + + /* Apalis GPIO8 */ + pinctrl_gpio8: gpio8grp { + fsl,pins = ; + }; + + /* Apalis BKL1_ON */ + pinctrl_gpio_bkl_on: gpiobklongrp { + fsl,pins = ; + }; + + /* Apalis WAKE1_MICO */ + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = ; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocngrp { + fsl,pins = ; + }; + + /* On-module HDMI_CTRL */ + pinctrl_hdmi_ctrl: hdmictrlgrp { + fsl,pins = ; + }; + + /* On-module I2C */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = , + ; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = , + ; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , + ; + }; + + /* Apalis SPI1 */ + pinctrl_lpspi0: lpspi0grp { + fsl,pins = , + , + , + ; + }; + + /* Apalis SPI2 */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = , + , + , + ; + }; + + /* Apalis UART3 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = , + ; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = , + , + , + ; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1ctrl: lpuart1ctrlgrp { + fsl,pins = /* Apalis UART1_DTR */ + , + /* Apalis UART1_DSR */ + , + /* Apalis UART1_DCD */ + , + /* Apalis UART1_RI */ + ; + }; + + /* Apalis UART4 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = , + ; + }; + + /* Apalis UART2 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = , + , + , + ; + }; + + /* Apalis TS_2 */ + pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp { + fsl,pins = ; + }; + + /* Apalis LCD1_G6+7 */ + pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { + fsl,pins = /* Apalis LCD1_G6 */ + , + /* Apalis LCD1_G7 */ + ; + }; + + /* Apalis TS_3 */ + pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp { + fsl,pins = ; + }; + + /* Apalis TS_4 */ + pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { + fsl,pins = ; + }; + + /* Apalis TS_1 */ + pinctrl_mlb_gpios: mlbgpiosgrp { + fsl,pins = ; + }; + + /* Apalis MMC1_CD# */ + pinctrl_mmc1_cd: mmc1cdgrp { + fsl,pins = ; + }; + + pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp { + fsl,pins = ; + }; + + /* On-module PCIe_Wi-Fi */ + pinctrl_pcieb: pciebgrp { + fsl,pins = , + , + ; + }; + + /* On-module PCIe_CLK_EN1 */ + pinctrl_pcie_sata_refclk: pciesatarefclkgrp { + fsl,pins = ; + }; + + /* On-module PCIe_CLK_EN2 */ + pinctrl_pcie_wifi_refclk: pciewifirefclkgrp { + fsl,pins = ; + }; + + /* Apalis PWM3 */ + pinctrl_pwm0: pwm0grp { + fsl,pins = ; + }; + + /* Apalis PWM4 */ + pinctrl_pwm1: pwm1grp { + fsl,pins = ; + }; + + /* Apalis PWM1 */ + pinctrl_pwm2: pwm2grp { + fsl,pins = ; + }; + + /* Apalis PWM2 */ + pinctrl_pwm3: pwm3grp { + fsl,pins = ; + }; + + /* Apalis BKL1_PWM */ + pinctrl_pwm_bkl: pwmbklgrp { + fsl,pins = ; + }; + + /* Apalis LCD1_ */ + pinctrl_qspi1a_gpios: qspi1agpiosgrp { + fsl,pins = /* Apalis LCD1_B0 */ + , + /* Apalis LCD1_B1 */ + , + /* Apalis LCD1_B2 */ + , + /* Apalis LCD1_B3 */ + , + /* Apalis LCD1_B5 */ + , + /* Apalis LCD1_B7 */ + , + /* Apalis LCD1_B4 */ + , + /* Apalis LCD1_B6 */ + ; + }; + + /* On-module RESET_MOCI#_DRV */ + pinctrl_reset_moci: resetmocigrp { + fsl,pins = ; + }; + + /* On-module I2S SGTL5000 for Apalis Analogue Audio */ + pinctrl_sai1: sai1grp { + fsl,pins = , + , + , + ; + }; + + /* Apalis SATA1_ACT# */ + pinctrl_sata1_act: sata1actgrp { + fsl,pins = ; + }; + + /* Apalis SD1_CD# */ + pinctrl_sd1_cd: sd1cdgrp { + fsl,pins = ; + }; + + /* On-module I2S SGTL5000 SYS_MCLK */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = ; + }; + + /* Apalis LCD1_ */ + pinctrl_sim0_gpios: sim0gpiosgrp { + fsl,pins = /* Apalis LCD1_G5 */ + , + /* Apalis LCD1_G3 */ + , + /* Apalis TS_5 */ + , + /* Apalis LCD1_G4 */ + ; + }; + + /* Apalis SPDIF */ + pinctrl_spdif0: spdif0grp { + fsl,pins = , + ; + }; + + pinctrl_touchctrl_gpios: touchctrlgpiosgrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_touchctrl_idle: touchctrlidlegrp { + fsl,pins = , + , + , + ; + }; + + /* On-module USB HSIC HUB (active) */ + pinctrl_usb_hsic_active: usbh1activegrp { + fsl,pins = , + ; + }; + + /* On-module USB HSIC HUB (idle) */ + pinctrl_usb_hsic_idle: usbh1idlegrp { + fsl,pins = , + ; + }; + + /* On-module USB HSIC HUB */ + pinctrl_usb3503a: usb3503agrp { + fsl,pins = /* On-module HSIC_HUB_CONNECT */ + , + /* On-module HSIC_INT_N */ + , + /* On-module HSIC_RESET_N */ + ; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhengrp { + fsl,pins = ; + }; + + /* Apalis USBO1 */ + pinctrl_usbotg1: usbotg1grp { + fsl,pins = /* Apalis USBO1_EN */ + , + /* Apalis USBO1_OC# */ + ; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + /* Apalis TS_6 */ + pinctrl_usdhc1_gpios: usdhc1gpiosgrp { + fsl,pins = ; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2_4bit: usdhc2grp4bitgrp { + fsl,pins = , + , + , + , + , + , + /* On-module PMIC use */ + ; + }; + + pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp { + fsl,pins = , + , + , + , + , + , + /* On-module PMIC use */ + ; + }; + + pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp { + fsl,pins = , + , + , + , + , + , + /* On-module PMIC use */ + ; + }; + + pinctrl_usdhc2_8bit: usdhc2grp8bitgrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp { + fsl,pins = , + , + , + ; + }; + + pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp { + fsl,pins = , + , + , + , + , + , + /* On-module PMIC use */ + ; + }; + + pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp { + fsl,pins = , + , + , + ; + }; + + /* Apalis SD1 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = , + , + , + , + , + , + /* On-module PMIC use */ + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = , + , + , + , + , + , + /* On-module PMIC use */ + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = , + , + , + , + , + , + /* On-module PMIC use */ + ; + }; + + /* On-module Wi-Fi */ + pinctrl_wifi: wifigrp { + fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */ + , + /* On-module Wi-Fi_PCIE_W_DISABLE */ + ; + }; + + pinctrl_wifi_pdn: wifipdngrp { + fsl,pins = /* On-module Wi-Fi_POWER_DOWN */ + ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi new file mode 100644 index 000000000000..81ba8b2831ac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include +#include "imx8qm.dtsi" +#include "imx8-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1"; + compatible = "toradex,apalis-imx8-v1.1", + "fsl,imx8qm"; +}; + +/* TODO: Cooling Maps */ diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi new file mode 100644 index 000000000000..1c6af9f549a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -0,0 +1,340 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8qm-apalis-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM"; + compatible = "toradex,apalis-imx8", + "fsl,imx8qm"; +}; + +ðphy0 { + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; +}; + +/* + * Apalis iMX8QM V1.0 has PHY KSZ9031. the Micrel PHY driver + * doesn't support setting internal PHY delay for TXC line for + * this PHY model. Use delay on MAC side instead. + */ +&fec1 { + fsl,rgmii_txc_dly; + phy-mode = "rgmii-rxid"; +}; + +/* TODO: Apalis HDMI1 */ + +/* Apalis I2C2 (DDC) */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +&lsio_gpio0 { + gpio-line-names = "MXM3_279", + "MXM3_277", + "MXM3_135", + "MXM3_203", + "MXM3_201", + "MXM3_275", + "MXM3_110", + "MXM3_120", + "MXM3_1/GPIO1", + "MXM3_3/GPIO2", + "MXM3_124", + "MXM3_122", + "MXM3_5/GPIO3", + "MXM3_7/GPIO4", + "", + "", + "MXM3_4", + "MXM3_211", + "MXM3_209", + "MXM3_2", + "MXM3_136", + "MXM3_134", + "MXM3_6", + "MXM3_8", + "MXM3_112", + "MXM3_118", + "MXM3_114", + "MXM3_116"; +}; + +&lsio_gpio1 { + gpio-line-names = "", + "", + "", + "", + "MXM3_286", + "", + "MXM3_87", + "MXM3_99", + "MXM3_138", + "MXM3_140", + "MXM3_239", + "", + "MXM3_281", + "MXM3_283", + "MXM3_126", + "MXM3_132", + "", + "", + "", + "", + "MXM3_173", + "MXM3_175", + "MXM3_123"; +}; + +&lsio_gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "MXM3_198", + "MXM3_35", + "MXM3_164", + "", + "", + "", + "", + "MXM3_217", + "MXM3_215", + "", + "", + "MXM3_193", + "MXM3_194", + "MXM3_37", + "", + "MXM3_271", + "MXM3_273", + "MXM3_195", + "MXM3_197", + "MXM3_177", + "MXM3_179", + "MXM3_181", + "MXM3_183", + "MXM3_185", + "MXM3_187"; +}; + +&lsio_gpio3 { + gpio-line-names = "MXM3_191", + "", + "MXM3_221", + "MXM3_225", + "MXM3_223", + "MXM3_227", + "MXM3_200", + "MXM3_235", + "MXM3_231", + "MXM3_229", + "MXM3_233", + "MXM3_204", + "MXM3_196", + "", + "MXM3_202", + "", + "", + "", + "MXM3_305", + "MXM3_307", + "MXM3_309", + "MXM3_311", + "MXM3_315", + "MXM3_317", + "MXM3_319", + "MXM3_321", + "MXM3_15/GPIO7", + "MXM3_63", + "MXM3_17/GPIO8", + "MXM3_12", + "MXM3_14", + "MXM3_16"; +}; + +&lsio_gpio4 { + gpio-line-names = "MXM3_18", + "MXM3_11/GPIO5", + "MXM3_13/GPIO6", + "MXM3_274", + "MXM3_84", + "MXM3_262", + "MXM3_96", + "", + "", + "", + "", + "", + "MXM3_190", + "", + "", + "", + "MXM3_269", + "MXM3_251", + "MXM3_253", + "MXM3_295", + "MXM3_299", + "MXM3_301", + "MXM3_297", + "MXM3_293", + "MXM3_291", + "MXM3_289", + "MXM3_287"; + + /* Enable pcie root / sata ref clock unconditionally */ + pcie-sata-hog { + gpios = <27 GPIO_ACTIVE_HIGH>; + }; + +}; + +&lsio_gpio5 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_150", + "MXM3_160", + "MXM3_162", + "MXM3_144", + "MXM3_146", + "MXM3_148", + "MXM3_152", + "MXM3_156", + "MXM3_158", + "MXM3_159", + "MXM3_184", + "MXM3_180", + "MXM3_186", + "MXM3_188", + "MXM3_176", + "MXM3_178"; +}; + +&lsio_gpio6 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MXM3_261", + "MXM3_263", + "MXM3_259", + "MXM3_257", + "MXM3_255", + "MXM3_128", + "MXM3_130", + "MXM3_265", + "MXM3_249", + "MXM3_247", + "MXM3_245", + "MXM3_243"; +}; + +&pinctrl_fec1 { + fsl,pins = + /* Use pads in 1.8V mode */ + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + /* On-module ETH_RESET# */ + , + /* On-module ETH_INT# */ + ; +}; + +&pinctrl_fec1_sleep { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&iomuxc { + /* Apalis I2C2 (DDC) */ + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = + , + ; + }; +}; + +/* On-module PCIe_CTRL0_CLKREQ */ +&pinctrl_pcie_sata_refclk { + fsl,pins = + ; +}; + +/* TODO: On-module Wi-Fi */ + +/* Apalis MMC1 */ +&usdhc2 { + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +}; From c083131c9021ef40c655894f6130a1393bb8e2b2 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 8 Feb 2023 07:56:41 +0100 Subject: [PATCH 0090/1040] arm64: dts: freescale: add apalis imx8 aka quadmax carrier board support The previous patch added the device tree to support Toradex Apalis iMX8 [1] aka QuadMax a computer on module which can be used on different carrier boards which this patch introduces. The module consists of an NXP i.MX 8 family SoC (either i.MX 8QuadMax or 8QuadPlus), two PF8100 PMICs, a KSZ9131 Gigabit Ethernet PHY, 2, 4 or 8 GB of LPDDR4 RAM, an eMMC, an SGTL5000 analogue audio codec, an USB3503A USB HSIC hub, an optional I2C EEPROM plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. The carrier board device trees contained in this patch include the module's device tree and enable the supported peripherals of the carrier board. Some level of display functionality just landed upstream but requires further integration/testing on our side. Therefore, currently only basic console UART, eMMC and Ethernet functionality work fine. As there is no i.MX 8QuadPlus device tree upstream those have been dropped. However, apart from an error message during boot about it failing to bring up the second Cortex-A72 core this boots fine on QuadPlus' as well. [1] https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 5 + .../boot/dts/freescale/imx8-apalis-eval.dtsi | 144 ++++++++++ .../dts/freescale/imx8-apalis-ixora-v1.1.dtsi | 220 ++++++++++++++ .../dts/freescale/imx8-apalis-ixora-v1.2.dtsi | 270 ++++++++++++++++++ .../boot/dts/freescale/imx8qm-apalis-eval.dts | 16 ++ .../freescale/imx8qm-apalis-ixora-v1.1.dts | 16 ++ .../dts/freescale/imx8qm-apalis-v1.1-eval.dts | 16 ++ .../imx8qm-apalis-v1.1-ixora-v1.1.dts | 16 ++ .../imx8qm-apalis-v1.1-ixora-v1.2.dts | 16 ++ 9 files changed, 719 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 198fff3731ae..836dcc501e6f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -122,6 +122,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-ixora-v1.1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi new file mode 100644 index 000000000000..685d4294f4f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC USBH2(ABCD) / USBH(3|4)"; + }; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +/* TODO: Audio Mixer */ + +/* TODO: Asynchronous Sample Rate Converter (ASRC) */ + +/* TODO: Display Controller */ + +/* TODO: DPU */ + +/* Apalis ETH1 */ +&fec1 { + status = "okay"; +}; + +/* Apalis CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + status = "okay"; +}; + +/* TODO: GPU */ + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + status = "okay"; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&lsio_pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&lsio_pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&lsio_pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&lsio_pwm3 { + status = "okay"; +}; + +/* TODO: Apalis PCIE1 */ + +/* TODO: Apalis BKL1_PWM */ + +/* TODO: Apalis DAP1 */ + +/* TODO: Apalis Analogue Audio */ + +/* TODO: Apalis SATA1 */ + +/* TODO: Apalis SPDIF1 */ + +/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* TODO: Apalis USBH4 SuperSpeed */ + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi new file mode 100644 index 000000000000..c6d51f116298 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + /* LED_4_GREEN / MXM3_188 */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; + }; + + /* LED_4_RED / MXM3_178 */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; + }; + + /* LED_5_GREEN / MXM3_152 */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + }; + + /* LED_5_RED / MXM3_156 */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC_USBH(2|4)"; + }; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +/* TODO: Audio Mixer */ + +/* TODO: Asynchronous Sample Rate Converter (ASRC) */ + +/* TODO: Display Controller */ + +/* TODO: DPU */ + +/* Apalis ETH1 */ +&fec1 { + status = "okay"; +}; + +/* Apalis CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + status = "okay"; +}; + +/* TODO: GPU */ + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + status = "okay"; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_sim0_gpios>, <&pinctrl_uart24_forceoff>, + <&pinctrl_usdhc1_gpios>; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = , /* LED_4_GREEN */ + , /* LED_4_RED */ + , /* LED_5_GREEN */ + ; /* LED_5_RED */ + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = ; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +&lsio_gpio5 { + gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03", + "gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07", + "gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11", + "gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15", + "gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19", + "LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23", + "gpio5-24", "UART24-FORCEOFF", "gpio5-26", + "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30", + "gpio5-31"; + ngpios = <32>; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&lsio_pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&lsio_pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&lsio_pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&lsio_pwm3 { + status = "okay"; +}; + +/* TODO: Apalis PCIE1 */ + +/* TODO: Apalis BKL1_PWM */ + +/* TODO: Apalis DAP1 */ + +/* TODO: Apalis Analogue Audio */ + +/* TODO: Apalis SATA1 */ + +/* TODO: Apalis SPDIF1 */ + +/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* TODO: Apalis USBH4 SuperSpeed */ + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; + bus-width = <4>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi new file mode 100644 index 000000000000..40067ab8aa74 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + /* LED_4_GREEN / MXM3_188 */ + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; + }; + + /* LED_4_RED / MXM3_178 */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; + }; + + /* LED_5_GREEN / MXM3_152 */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + }; + + /* LED_5_RED / MXM3_156 */ + led-4 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + /* MMC1_PWR_CTRL */ + gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + }; + + reg_can1_supply: regulator-can1-supply { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "can1_supply"; + }; + + reg_can2_supply: regulator-can2-supply { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sata1_act>; + gpio = <&lsio_gpio2 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "can2_supply"; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC_USBH(2|4)"; + }; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +/* TODO: Audio Mixer */ + +/* TODO: Asynchronous Sample Rate Converter (ASRC) */ + +/* TODO: Display Controller */ + +/* TODO: DPU */ + +/* Apalis ETH1 */ +&fec1 { + status = "okay"; +}; + +/* Apalis CAN1 */ +&flexcan1 { + xceiver-supply = <®_can1_supply>; + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + xceiver-supply = <®_can2_supply>; + status = "okay"; +}; + +/* TODO: GPU */ + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + status = "okay"; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sim0_gpios>, + <&pinctrl_uart24_forceoff>, <&pinctrl_usdhc1_gpios>; + + /* PMIC MMC1 power-switch */ + pinctrl_enable_3v3_vmmc: enable3v3vmmcgrp { + fsl,pins = ; /* MXM3_148, PMIC */ + }; + + /* FlexCAN PMIC */ + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = ; /* MXM3_158, PMIC */ + }; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = , /* LED_4_GREEN */ + , /* LED_4_RED */ + , /* LED_5_GREEN */ + ; /* LED_5_RED */ + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = ; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +&lsio_gpio5 { + gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03", + "gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07", + "gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11", + "gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15", + "gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19", + "LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23", + "gpio5-24", "UART24-FORCEOFF", "gpio5-26", + "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30", + "gpio5-31"; + ngpios = <32>; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&lsio_pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&lsio_pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&lsio_pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&lsio_pwm3 { + status = "okay"; +}; + +/* TODO: Apalis PCIE1 */ + +/* TODO: Apalis BKL1_PWM */ + +/* TODO: Apalis DAP1 */ + +/* TODO: Apalis Analogue Audio */ + +/* TODO: Apalis SATA1 */ + +/* TODO: Apalis SPDIF1 */ + +/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* TODO: Apalis USBH4 SuperSpeed */ + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; + bus-width = <4>; + cap-power-off-card; + /delete-property/ no-1-8-v; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts new file mode 100644 index 000000000000..5ab0921eb599 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis.dtsi" +#include "imx8-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8-eval", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts new file mode 100644 index 000000000000..68ce58dc7102 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-ixora-v1.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8-ixora-v1.1", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..c8ff75831556 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8-v1.1-eval", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts new file mode 100644 index 000000000000..ad7f644968fa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts new file mode 100644 index 000000000000..3b2e8c93b846 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.2 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qm"; +}; From ea254644a228c90887a38de9637c414f7439bf66 Mon Sep 17 00:00:00 2001 From: Alexey Romanov Date: Thu, 2 Feb 2023 17:15:20 +0300 Subject: [PATCH 0091/1040] arm64: dts: meson-a1: add gpio_intc node Add gpio interrupt controller node. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230202141520.40003-1-avromanov@sberdevices.ru Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index d2f7cb4e5375..eed96f262844 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -125,6 +125,16 @@ clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + gpio_intc: interrupt-controller@0440 { + compatible = "amlogic,meson-a1-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x0440 0x0 0x14>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <49 50 51 52 53 54 55 56>; + }; }; gic: interrupt-controller@ff901000 { From c2e9012bb383f538186cf11d00d223d025d10c8d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 6 Mar 2023 16:13:54 +0100 Subject: [PATCH 0092/1040] arm64: dts: amlogic: gxl: use gxl mdio multiplexer So the far, GXL SoCs were using the generic mmio register based mdio multiplexer. This properly sets one of the glue register but the SoC actually has 3 of those registers. One of them sets the ID under which the internal phy will advertise itself. If nothing sets this register before linux boots (like u-boot), the internal phy path is broken. To address this problem, a dedicated MDIO mux driver has been introduced. Switch to this new driver. Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20230306151354.132973-1-jbrunet@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 6f3c2bc36919..17bcfa4702e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -773,16 +773,23 @@ }; }; - eth-phy-mux@55c { - compatible = "mdio-mux-mmioreg", "mdio-mux"; + eth_phy_mux: mdio@558 { + reg = <0x0 0x558 0x0 0xc>; + compatible = "amlogic,gxl-mdio-mux"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0x55c 0x0 0x4>; - mux-mask = <0xffffffff>; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "ref"; mdio-parent-bus = <&mdio0>; - internal_mdio: mdio@e40908ff { - reg = <0xe40908ff>; + external_mdio: mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + internal_mdio: mdio@1 { + reg = <0x1>; #address-cells = <1>; #size-cells = <0>; @@ -793,12 +800,6 @@ max-speed = <100>; }; }; - - external_mdio: mdio@2009087f { - reg = <0x2009087f>; - #address-cells = <1>; - #size-cells = <0>; - }; }; }; From 92c0b261c294f12e329976a6d4ef72651e8f07f2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 6 Mar 2023 09:31:38 +0100 Subject: [PATCH 0093/1040] dt-bindings: arm: amlogic: Document the boards with the BPI-CM4 connected The BPI-CM4 module with an Amlogic A311D SoC is a module compatible with the Raspberry Pi CM4 specifications. Document the boards using this module, by specifying the BananaPi CM4 compatible in addition to the baseboard compatible. Acked-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230303-topic-amlogic-upstream-bpi-cm4-v2-1-2ecfde76fc4d@linaro.org Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 799a4bfff854..274ee0890312 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -159,6 +159,14 @@ properties: - const: amlogic,a311d - const: amlogic,g12b + - description: Boards using the BPI-CM4 module with Amlogic Meson G12B A311D SoC + items: + - enum: + - bananapi,bpi-cm4io + - const: bananapi,bpi-cm4 + - const: amlogic,a311d + - const: amlogic,g12b + - description: Boards with the Amlogic Meson G12B S922X SoC items: - enum: From 0262f2736978b1763363224698f47112a148dab0 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 6 Mar 2023 09:31:39 +0100 Subject: [PATCH 0094/1040] arm64: dts: amlogic: Add initial support for BPI-CM4 module with BPI-CM4IO baseboard Add support for both the BananaPi BPI-CM4 module and the BananaPi baseboard which is compatible with the RaspberryPi CM4IO baseboard. The BananaPi BPI-CM4 module follows the CM4 specifications at [1], but with a single HDMI port and a single DSI output. The current CM4IO baseboard DT should work fine on the Raspberry CM4 baseboard and other derivatives baseboards, but proper DT should be written for other baseboards. The split is done so it's easy to describe a new CM4 baseboard, enabling only the necessary HW used on the baseboard. [1] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf Tested-by: Christian Hewitt Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230303-topic-amlogic-upstream-bpi-cm4-v2-2-2ecfde76fc4d@linaro.org [narmstrong: fixed typos in commit message] Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../amlogic/meson-g12b-bananapi-cm4-cm4io.dts | 165 ++++++++ .../dts/amlogic/meson-g12b-bananapi-cm4.dtsi | 388 ++++++++++++++++++ 3 files changed, 554 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 2bb9f1d4bc1a..cd1c5b04890a 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-bananapi-m2s.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-bananapi-cm4-cm4io.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts new file mode 100644 index 000000000000..1b0c3881c6a1 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong + */ + +/dts-v1/; + +#include "meson-g12b-bananapi-cm4.dtsi" +#include +#include +#include + +/ { + compatible = "bananapi,bpi-cm4io", "bananapi,bpi-cm4", "amlogic,a311d", "amlogic,g12b"; + model = "BananaPi BPI-CM4IO Baseboard with BPI-CM4 Module"; + + aliases { + ethernet0 = ðmac; + i2c0 = &i2c1; + i2c1 = &i2c3; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1710000>; + + button-function { + label = "Function"; + linux,code = ; + press-threshold-microvolt = <10000>; + }; + }; + + hdmi_connector: hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-green { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "BPI-CM4IO"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&cecb_AO { + status = "okay"; +}; + +ðmac { + status = "okay"; +}; + +&hdmi_tx { + status = "okay"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +/* CSI port */ +&i2c1 { + status = "okay"; +}; + +/* DSI port for touchscreen */ +&i2c3 { + status = "okay"; +}; + +/* miniPCIe port with USB + SIM slot */ +&pcie { + status = "okay"; +}; + +&sd_emmc_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +/* Peripheral Only USB-C port */ +&usb { + dr_mode = "peripheral"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi new file mode 100644 index 000000000000..97e522921b06 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Neil Armstrong + */ + +#include "meson-g12b-a311d.dtsi" +#include + +/ { + aliases { + serial0 = &uart_AO; + rtc1 = &vrtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOAO_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + emmc_1v8: regulator-emmc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + dc_in: regulator-dc-in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vddio_c: regulator-vddio-c { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_C"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; + enable-active-high; + regulator-always-on; + + gpios = <&gpio_ao GPIOAO_9 GPIO_OPEN_DRAIN>; + gpios-states = <1>; + + states = <1800000 0>, + <3300000 1>; + }; + + vddao_1v8: regulator-vddao-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vddcpu_a: regulator-vddcpu-a { + /* + * MP8756GD DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_A"; + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1040000>; + + pwm-supply = <&dc_in>; + + pwms = <&pwm_ab 0 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddcpu_b: regulator-vddcpu-b { + /* + * SY8120B1ABC DC/DC Regulator. + */ + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU_B"; + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1040000>; + + pwm-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1250 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cpu0 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu_b>; + operating-points-v2 = <&cpu_opp_table_0>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu100 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu101 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu102 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&cpu103 { + cpu-supply = <&vddcpu_a>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; + clock-latency = <50000>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* Ethernet to be enabled in baseboard DT */ +ðmac { + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +/* HDMI to be enabled in baseboard DT */ +&hdmi_tx { + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; + hdmi-supply = <&dc_in>; +}; + +/* "Camera" I2C bus */ +&i2c1 { + pinctrl-0 = <&i2c1_sda_h6_pins>, <&i2c1_sck_h7_pins>; + pinctrl-names = "default"; +}; + +/* Main I2C bus */ +&i2c2 { + pinctrl-0 = <&i2c2_sda_x_pins>, <&i2c2_sck_x_pins>; + pinctrl-names = "default"; +}; + +/* "ID" I2C bus */ +&i2c3 { + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; +}; + +&pcie { + reset-gpios = <&gpio GPIOA_8 GPIO_ACTIVE_LOW>; +}; + +&pwm_ab { + pinctrl-0 = <&pwm_a_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; + + status = "okay"; +}; + +&pwm_ef { + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + + status = "okay"; +}; + +&saradc { + vref-supply = <&vddao_1v8>; + + status = "okay"; +}; + +/* on-module SDIO WiFi */ +&sd_emmc_a { + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + sd-uhs-sdr104; + max-frequency = <50000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; + + status = "okay"; + + rtl8822cs: wifi@1 { + reg = <1>; + }; +}; + +/* SD card to be enabled in baseboard DT */ +&sd_emmc_b { + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <50000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_c>; +}; + +/* on-module eMMC */ +&sd_emmc_c { + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_1v8>; + + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +/* on-module UART BT */ +&uart_A { + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; +}; + +&uart_AO { + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb { + phys = <&usb2_phy0>, <&usb2_phy1>; + phy-names = "usb2-phy0", "usb2-phy1"; +}; From 0e9b70c1e3623fa110fb6be553e644524228ef60 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 9 Sep 2022 13:31:16 +0100 Subject: [PATCH 0095/1040] riscv: dts: microchip: add mpfs specific macb reset support The macb on PolarFire SoC has reset support which the generic compatible does not use. Add the newly introduced MPFS specific compatible as the primary compatible to avail of this support & wire up the reset to the clock controllers devicetree entry. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 0a9bb84af438..23b7b05ee291 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -234,6 +234,7 @@ reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; clocks = <&refclk>; #clock-cells = <1>; + #reset-cells = <1>; }; ccc_se: clock-controller@38010000 { @@ -415,7 +416,7 @@ }; mac0: ethernet@20110000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; #address-cells = <1>; #size-cells = <0>; @@ -424,11 +425,12 @@ local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC0>; status = "disabled"; }; mac1: ethernet@20112000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; #address-cells = <1>; #size-cells = <0>; @@ -437,6 +439,7 @@ local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC1>; status = "disabled"; }; From dbe406d1397ffccd4a0f85daef456291f265505a Mon Sep 17 00:00:00 2001 From: Lucas Tanure Date: Tue, 28 Feb 2023 10:36:10 +0000 Subject: [PATCH 0096/1040] arm64: dts: rockchip: Add sdmmc node to rk3588 Add SD Card node for RK3588s and RK3588. Co-developed-by: Shawn Lin Signed-off-by: Shawn Lin Signed-off-by: Lucas Tanure Link: https://lore.kernel.org/r/20230228103610.25108-1-lucas.tanure@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 005cde61b4b2..fca8503aed8c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1099,6 +1099,21 @@ }; }; + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power RK3588_PD_SDMMC>; + status = "disabled"; + }; + sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>; From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Thu, 23 Feb 2023 19:29:29 +0530 Subject: [PATCH 0097/1040] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3 Enable USB OTG support for Radxa Compute Module 3 IO Board Signed-off-by: Manoj Sai Signed-off-by: Jagan Teki Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts index d89d5263cb5e..5e4236af4fcb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts @@ -254,6 +254,14 @@ status = "okay"; }; +&usb2phy0_otg { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + &vop { assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; From f94c11ade1461b9cbae1e8d2e03efa7d4dc178f0 Mon Sep 17 00:00:00 2001 From: Maya Matuszczyk Date: Mon, 13 Feb 2023 16:38:16 +0100 Subject: [PATCH 0098/1040] arm64: dts: rockchip: Add display support to Odroid Go Super Note that orientation property in ST7701 driver is currently missing, And that ST7701 panel driver uses different regulator names compared to driver for Elida KD35T133 driver. Signed-off-by: Maya Matuszczyk Link: https://lore.kernel.org/r/20230213153816.213526-5-maccraft123mc@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts index 842efbaf1a6a..1b9769ccfdeb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts @@ -142,7 +142,9 @@ }; &internal_display { - status = "disabled"; + compatible = "elida,kd50t048a", "sitronix,st7701"; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + VCC-supply = <&vcc_lcd>; }; &rk817_charger { From 5f1732a8683c1da8faaa90d6ffc3bd6d33013a58 Mon Sep 17 00:00:00 2001 From: Nicolas Frayer Date: Fri, 30 Dec 2022 01:14:04 +0100 Subject: [PATCH 0099/1040] soc: ti: k3-ringacc: Add try_module_get() to k3_dmaring_request_dual_ring() When the k3 ring accelerator driver has been modified to add module build support, try_module_get() and module_put() have been added to update the module refcnt. One code path has not been updated and it has introduced an issue where the refcnt is decremented by module_put() in k3_ringacc_ring_free() without being incremented previously. Adding try_module_get() to k3_dmaring_request_dual_ring() ensures the refcnt is kept up to date. Fixes: c07f216a8b72 ("soc: ti: k3-ringacc: Allow the driver to be built as module") Signed-off-by: Nicolas Frayer Reviewed-by: Peter Ujfalusi Link: https://lore.kernel.org/r/20221230001404.10902-1-nfrayer@baylibre.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/k3-ringacc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index e01e4d815230..8f131368a758 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -406,6 +406,11 @@ static int k3_dmaring_request_dual_ring(struct k3_ringacc *ringacc, int fwd_id, mutex_lock(&ringacc->req_lock); + if (!try_module_get(ringacc->dev->driver->owner)) { + ret = -EINVAL; + goto err_module_get; + } + if (test_bit(fwd_id, ringacc->rings_inuse)) { ret = -EBUSY; goto error; @@ -421,6 +426,8 @@ static int k3_dmaring_request_dual_ring(struct k3_ringacc *ringacc, int fwd_id, return 0; error: + module_put(ringacc->dev->driver->owner); +err_module_get: mutex_unlock(&ringacc->req_lock); return ret; } From 8f3c307b580a4a6425896007325bddefc36e8d91 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Fri, 6 Jan 2023 09:40:22 +0400 Subject: [PATCH 0100/1040] soc: ti: pm33xx: Fix refcount leak in am33xx_pm_probe wkup_m3_ipc_get() takes refcount, which should be freed by wkup_m3_ipc_put(). Add missing refcount release in the error paths. Fixes: 5a99ae0092fe ("soc: ti: pm33xx: AM437X: Add rtc_only with ddr in self-refresh support") Signed-off-by: Miaoqian Lin Link: https://lore.kernel.org/r/20230106054022.947529-1-linmq006@gmail.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/pm33xx.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/pm33xx.c b/drivers/soc/ti/pm33xx.c index ce09c42eaed2..f04c21157904 100644 --- a/drivers/soc/ti/pm33xx.c +++ b/drivers/soc/ti/pm33xx.c @@ -527,7 +527,7 @@ static int am33xx_pm_probe(struct platform_device *pdev) ret = am33xx_pm_alloc_sram(); if (ret) - return ret; + goto err_wkup_m3_ipc_put; ret = am33xx_pm_rtc_setup(); if (ret) @@ -572,13 +572,14 @@ err_pm_runtime_put: pm_runtime_put_sync(dev); err_pm_runtime_disable: pm_runtime_disable(dev); - wkup_m3_ipc_put(m3_ipc); err_unsetup_rtc: iounmap(rtc_base_virt); clk_put(rtc_fck); err_free_sram: am33xx_pm_free_sram(); pm33xx_dev = NULL; +err_wkup_m3_ipc_put: + wkup_m3_ipc_put(m3_ipc); return ret; } From 695cb117ac2a3624eb4381c271a0376d9233df44 Mon Sep 17 00:00:00 2001 From: Chanh Nguyen Date: Tue, 28 Feb 2023 17:28:20 +0700 Subject: [PATCH 0101/1040] ARM: dts: aspeed: mtmitchell: Enable NCSI Use MAC3 (RGMII4) with the NC-SI stack instead of as an MDIO PHY. The OCP slot #0 and OCP slot #1 use a common BMC_NCSI signal, so we use only one of them at a time. The OCP slot #0 will be enabled by PCA9539's setting by default. Enable the OCP Auxiliary Power during booting to make the NCSI feature work. Signed-off-by: Chanh Nguyen Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20230228102820.18477-1-chanh@os.amperecomputing.com Signed-off-by: Joel Stanley --- .../boot/dts/aspeed-bmc-ampere-mtmitchell.dts | 37 ++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts index 4b91600eaf62..1e0e88465254 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts @@ -251,6 +251,14 @@ pinctrl-0 = <&pinctrl_rgmii1_default>; }; +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + &fmc { status = "okay"; flash@0 { @@ -439,6 +447,26 @@ status = "okay"; }; +&i2c8 { + status = "okay"; + + gpio@77 { + compatible = "nxp,pca9539"; + reg = <0x77>; + gpio-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <2>; + + bmc-ocp0-en-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_LOW>; + output-high; + line-name = "bmc-ocp0-en-n"; + }; + }; +}; + &i2c9 { status = "okay"; }; @@ -530,13 +558,20 @@ /*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n", "host0-reboot-ack-n","host0-ready","host0-shd-req-n", "host0-shd-ack-n","s0-overtemp-n", - /*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","", + /*W0-W7*/ "","ocp-main-pwren","ocp-pgood","", "bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel", /*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok", "s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n", "s1-overtemp-n","s1-spi-auth-fail-n", /*Y0-Y7*/ "","","","","","","","host0-special-boot", /*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","",""; + + ocp-aux-pwren-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "ocp-aux-pwren"; + }; }; &gpio1 { From e63b0663f0028b265201798d74de163140ac124e Mon Sep 17 00:00:00 2001 From: Nick Alcock Date: Wed, 8 Mar 2023 20:21:16 +0000 Subject: [PATCH 0102/1040] memory: tegra: remove MODULE_LICENSE in non-modules Since commit 8b41fc4454e3 ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Hitomi Hasegawa Cc: Thierry Reding Cc: Jonathan Hunter Link: https://lore.kernel.org/r/20230308202117.426808-1-nick.alcock@oracle.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 1 - drivers/memory/tegra/tegra186-emc.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 592907546ee6..237025ba811d 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -985,4 +985,3 @@ arch_initcall(tegra_mc_init); MODULE_AUTHOR("Thierry Reding "); MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 26e763bde92a..e935ad4e95b6 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -280,4 +280,3 @@ module_platform_driver(tegra186_emc_driver); MODULE_AUTHOR("Thierry Reding "); MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver"); -MODULE_LICENSE("GPL v2"); From d2456ddb2e7e1b89ed637e8190fcbbeadc7ea8a7 Mon Sep 17 00:00:00 2001 From: Nick Alcock Date: Wed, 8 Mar 2023 20:21:17 +0000 Subject: [PATCH 0103/1040] memory: remove MODULE_LICENSE in non-modules Since commit 8b41fc4454e3 ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Hitomi Hasegawa Link: https://lore.kernel.org/r/20230308202117.426808-2-nick.alcock@oracle.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/bt1-l2-ctl.c | 1 - drivers/memory/da8xx-ddrctl.c | 1 - drivers/memory/fsl_ifc.c | 1 - drivers/memory/mvebu-devbus.c | 1 - 4 files changed, 4 deletions(-) diff --git a/drivers/memory/bt1-l2-ctl.c b/drivers/memory/bt1-l2-ctl.c index 85965fa26e0b..78bd71b203f2 100644 --- a/drivers/memory/bt1-l2-ctl.c +++ b/drivers/memory/bt1-l2-ctl.c @@ -321,4 +321,3 @@ module_platform_driver(l2_ctl_driver); MODULE_AUTHOR("Serge Semin "); MODULE_DESCRIPTION("Baikal-T1 L2-cache driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c index b32005bf269c..0ef8cc878b95 100644 --- a/drivers/memory/da8xx-ddrctl.c +++ b/drivers/memory/da8xx-ddrctl.c @@ -164,4 +164,3 @@ module_platform_driver(da8xx_ddrctl_driver); MODULE_AUTHOR("Bartosz Golaszewski "); MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c index e83b61c925a4..9e8d8e9c5ad8 100644 --- a/drivers/memory/fsl_ifc.c +++ b/drivers/memory/fsl_ifc.c @@ -327,6 +327,5 @@ static int __init fsl_ifc_init(void) } subsys_initcall(fsl_ifc_init); -MODULE_LICENSE("GPL"); MODULE_AUTHOR("Freescale Semiconductor"); MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver"); diff --git a/drivers/memory/mvebu-devbus.c b/drivers/memory/mvebu-devbus.c index efc6c08db2b7..406fddcdba02 100644 --- a/drivers/memory/mvebu-devbus.c +++ b/drivers/memory/mvebu-devbus.c @@ -341,6 +341,5 @@ static int __init mvebu_devbus_init(void) } module_init(mvebu_devbus_init); -MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Ezequiel Garcia "); MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller"); From ed6f068330494e849b77a32b23842c6f73f57aa9 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Tue, 21 Feb 2023 19:50:56 -0600 Subject: [PATCH 0104/1040] ARM: dts: aspeed: everest: Add reserved memory for TPM event log Trusted boot support requires the platform event log passed up from the bootloader. In U-Boot, this can now be accomplished with a reserved memory region, so add a region for this purpose to the Everest BMC devicetree. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20230222015056.3903734-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index c3b0cd61ac85..c6f8f20914d1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -162,6 +162,11 @@ #size-cells = <1>; ranges; + event_log: tcg_event_log@b3d00000 { + no-map; + reg = <0xb3d00000 0x100000>; + }; + ramoops@b3e00000 { compatible = "ramoops"; reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */ @@ -1887,6 +1892,7 @@ tpm@2e { compatible = "nuvoton,npct75x", "tcg,tpm-tis-i2c"; reg = <0x2e>; + memory-region = <&event_log>; }; }; From f90f462964ff92eb28a469574df7eda1b2da595d Mon Sep 17 00:00:00 2001 From: Eddie James Date: Wed, 8 Mar 2023 16:24:03 -0600 Subject: [PATCH 0105/1040] ARM: dts: aspeed: bonnell: Remove MAC3 Bonnell is populated with only one ethernet controller. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20230308222403.1848795-1-eajames@linux.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index a5be0ee048ec..97dacbe75182 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -884,16 +884,6 @@ use-ncsi; }; -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, - <&syscon ASPEED_CLK_MAC4RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - &wdt1 { aspeed,reset-type = "none"; aspeed,external-signal; From bb13bd587d53033f1151699b7522f979e2930ea6 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Thu, 23 Feb 2023 09:48:26 -0600 Subject: [PATCH 0106/1040] ARM: dts: aspeed: bonnell: Update eeprom size An eeprom had an incorrect size. Signed-off-by: Eddie James Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index 97dacbe75182..79516dc21c01 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -686,7 +686,7 @@ }; eeprom@50 { - compatible = "atmel,24c64"; + compatible = "atmel,24c128"; reg = <0x50>; }; From fd9c55c0acac59013dae9f8eedb0e0eb2e82e276 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 7 Mar 2023 11:56:40 +0100 Subject: [PATCH 0107/1040] soc: renesas: rcar-sysc: Remove R-Car H3 ES1.* handling R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230307105645.5285-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/r8a7795-sysc.c | 10 ---------- include/dt-bindings/power/r8a7795-sysc.h | 1 - 2 files changed, 11 deletions(-) diff --git a/drivers/soc/renesas/r8a7795-sysc.c b/drivers/soc/renesas/r8a7795-sysc.c index 91074411b8cf..cbe1ff0fc583 100644 --- a/drivers/soc/renesas/r8a7795-sysc.c +++ b/drivers/soc/renesas/r8a7795-sysc.c @@ -38,8 +38,6 @@ static struct rcar_sysc_area r8a7795_areas[] __initdata = { { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON }, { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON }, { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON }, - /* A2VC0 exists on ES1.x only */ - { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC }, { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC }, { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON }, { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A }, @@ -54,14 +52,10 @@ static struct rcar_sysc_area r8a7795_areas[] __initdata = { * Fixups for R-Car H3 revisions */ -#define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */ #define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */ static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = { { - .soc_id = "r8a7795", .revision = "ES1.*", - .data = (void *)(HAS_A2VC0 | NO_EXTMASK), - }, { .soc_id = "r8a7795", .revision = "ES2.*", .data = (void *)(NO_EXTMASK), }, @@ -77,10 +71,6 @@ static int __init r8a7795_sysc_init(void) if (attr) quirks = (uintptr_t)attr->data; - if (!(quirks & HAS_A2VC0)) - rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas), - R8A7795_PD_A2VC0); - if (quirks & NO_EXTMASK) r8a7795_sysc_info.extmask_val = 0; diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h index eea6ad69f0b0..ff5323858572 100644 --- a/include/dt-bindings/power/r8a7795-sysc.h +++ b/include/dt-bindings/power/r8a7795-sysc.h @@ -30,7 +30,6 @@ #define R8A7795_PD_CA53_SCU 21 #define R8A7795_PD_3DG_E 22 #define R8A7795_PD_A3IR 24 -#define R8A7795_PD_A2VC0 25 /* ES1.x only */ #define R8A7795_PD_A2VC1 26 /* Always-on power area */ From 18ecaaea2174c9494ec1ce354f58846367c29f45 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 7 Mar 2023 11:56:41 +0100 Subject: [PATCH 0108/1040] soc: renesas: Remove r8a77950 arch R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Remove the architecture which describes H3 ES1.*. Signed-off-by: Wolfram Sang Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230307105645.5285-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 7 ------- drivers/soc/renesas/renesas-soc.c | 4 +--- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 4e8b51ba2266..de31589ed054 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -206,13 +206,6 @@ config ARCH_R8A77990 This enables support for the Renesas R-Car E3 SoC. This includes different gradings like R-Car E3e. -config ARCH_R8A77950 - bool "ARM64 Platform support for R-Car H3 ES1.x" - select ARCH_RCAR_GEN3 - select SYSC_R8A7795 - help - This enables support for the Renesas R-Car H3 SoC (revision 1.x). - config ARCH_R8A77951 bool "ARM64 Platform support for R-Car H3 ES2.0+" select ARCH_RCAR_GEN3 diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 468ebce1ea88..a22e65916e20 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -330,10 +330,8 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R8A7794 { .compatible = "renesas,r8a7794", .data = &soc_rcar_e2 }, #endif -#if defined(CONFIG_ARCH_R8A77950) || defined(CONFIG_ARCH_R8A77951) - { .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 }, -#endif #ifdef CONFIG_ARCH_R8A77951 + { .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 }, { .compatible = "renesas,r8a779m0", .data = &soc_rcar_h3 }, { .compatible = "renesas,r8a779m1", .data = &soc_rcar_h3 }, { .compatible = "renesas,r8a779m8", .data = &soc_rcar_h3 }, From b39d242dbfd925d9f6b262bf216518e28445570d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Mar 2023 11:48:17 +0100 Subject: [PATCH 0109/1040] soc: renesas: rmobile-sysc: Use of_fwnode_handle() helper Use the existing of_fwnode_handle() helper instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven Reviewed-by: Andy Shevchenko Reviewed-by: Saravana Kannan Link: https://lore.kernel.org/r/d49b9fb20d68709b12692558aca91997e6b06fb4.1678272276.git.geert+renesas@glider.be --- drivers/soc/renesas/rmobile-sysc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/renesas/rmobile-sysc.c b/drivers/soc/renesas/rmobile-sysc.c index 204e6135180b..728ebac98e14 100644 --- a/drivers/soc/renesas/rmobile-sysc.c +++ b/drivers/soc/renesas/rmobile-sysc.c @@ -343,7 +343,7 @@ static int __init rmobile_init_pm_domains(void) break; } - fwnode_dev_initialized(&np->fwnode, true); + fwnode_dev_initialized(of_fwnode_handle(np), true); } put_special_pds(); From 29dfd412ec9e08b05b65848174646353b58fb54d Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 6 Mar 2023 23:49:48 +0000 Subject: [PATCH 0110/1040] arm64: defconfig: Enable DA7213 Codec Enable the DA7213 Codec for ARD-AUDIO-DA7212 support on R-Car V4H White Hawk. Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/87mt4pl9sz.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..1923ea698796 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -872,6 +872,7 @@ CONFIG_SND_SOC_TEGRA210_ADX=m CONFIG_SND_SOC_TEGRA210_MIXER=m CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m CONFIG_SND_SOC_GTM601=m From d3b4fe74b904c6b8f819db13104e56cd0943d76b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 7 Mar 2023 11:56:41 +0100 Subject: [PATCH 0111/1040] arm64: defconfig: Disable R-Car H3 ES1.* R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230307105645.5285-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/configs/defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1923ea698796..b75f71fe6529 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1218,7 +1218,6 @@ CONFIG_QCOM_APR=m CONFIG_QCOM_ICC_BWMON=m CONFIG_ARCH_R8A77995=y CONFIG_ARCH_R8A77990=y -CONFIG_ARCH_R8A77950=y CONFIG_ARCH_R8A77951=y CONFIG_ARCH_R8A77965=y CONFIG_ARCH_R8A77960=y From 64ddc2c9c06711e3d64976ef9f4880284823f464 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Mar 2023 15:40:52 +0100 Subject: [PATCH 0112/1040] ARM: shmobile: defconfig: Refresh for v6.3-rc1 Refresh the defconfig for Renesas ARM systems: - Disable CONFIG_SERIAL_8250_PCI1XXXX (No Microchip 8250 based serial ports), - Enable RZ/N1 USB Function controller support. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b4bac37273be5287b0198abe0aafd16f08ed330d.1678286291.git.geert+renesas@glider.be --- arch/arm/configs/shmobile_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 751d939fcb76..0b21c0a47582 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -76,6 +76,7 @@ CONFIG_SERIAL_8250=y # CONFIG_SERIAL_8250_16550A_VARIANTS is not set CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_PCI1XXXX is not set CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_EM=y # CONFIG_SERIAL_8250_PERICOM is not set @@ -168,6 +169,7 @@ CONFIG_USB_R8A66597_HCD=y CONFIG_USB_RENESAS_USBHS=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=y +CONFIG_USB_RENESAS_USBF=y CONFIG_USB_ETH=y CONFIG_MMC=y CONFIG_MMC_SDHI=y From 0a06ad2056ad18e9d3de8fe8e3e8fe4f85aa86e1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Mar 2023 15:40:53 +0100 Subject: [PATCH 0113/1040] ARM: multi_v7_defconfig: Enable additional support for RZ/N1 platforms Increase build and test coverage by enabling support for the A5PSW Ethernet switch, pin, watchdog, USB Function, RTC, and DMA mux controllers on the Renesas RZ/N1 SoC and the RZN1D-DB development board. All drivers for the above are modular, except for the pin control driver. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a163e8a9c4ae9cb10b05409f2fc139d09fe440b9.1678286291.git.geert+renesas@glider.be --- arch/arm/configs/multi_v7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 084cc612ea23..42ff3d5a5198 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -251,6 +251,7 @@ CONFIG_B53_SPI_DRIVER=m CONFIG_B53_MDIO_DRIVER=m CONFIG_B53_MMAP_DRIVER=m CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_RZN1_A5PSW=m CONFIG_SUN4I_EMAC=y CONFIG_SPI_AX88796C=m CONFIG_BCMGENET=m @@ -474,6 +475,7 @@ CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y CONFIG_PINCTRL_RZA2=y +CONFIG_PINCTRL_RZN1=y CONFIG_GPIO_ASPEED_SGPIO=y CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y @@ -563,6 +565,7 @@ CONFIG_MESON_WATCHDOG=y CONFIG_DIGICOLOR_WATCHDOG=y CONFIG_RENESAS_WDT=m CONFIG_RENESAS_RZAWDT=m +CONFIG_RENESAS_RZN1WDT=m CONFIG_STPMIC1_WATCHDOG=y CONFIG_PM8916_WATCHDOG=m CONFIG_BCM47XX_WDT=y @@ -873,6 +876,7 @@ CONFIG_USB_ISP1301=y CONFIG_USB_MXS_PHY=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_RENESAS_USBF=m CONFIG_USB_ASPEED_VHUB=m CONFIG_USB_CONFIGFS=m CONFIG_USB_CONFIGFS_SERIAL=y @@ -989,6 +993,7 @@ CONFIG_RTC_DRV_SH=m CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_AT91RM9200=m CONFIG_RTC_DRV_AT91SAM9=m +CONFIG_RTC_DRV_RZN1=m CONFIG_RTC_DRV_VT8500=y CONFIG_RTC_DRV_SUNXI=y CONFIG_RTC_DRV_MV=y @@ -1020,6 +1025,7 @@ CONFIG_UNIPHIER_MDMAC=y CONFIG_XILINX_DMA=y CONFIG_QCOM_BAM_DMA=y CONFIG_DW_DMAC=y +CONFIG_RZN1_DMAMUX=m CONFIG_RCAR_DMAC=y CONFIG_RENESAS_USB_DMAC=m CONFIG_VIRTIO_PCI=y From 93582bdfd0cf5aeeb4451ade1076a455c53d8a85 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Mar 2023 15:40:54 +0100 Subject: [PATCH 0114/1040] arm64: defconfig: Enable RZ/V2M xHCI and USB3.1 DRD controller support Increase build and test coverage by enabling RZ/V2M xHCI and USB3.1 DRD controller support. Note that the latter cannot be modular, as USB_XHCI_RCAR is builtin. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/ff10d09c1a00f7024679a249e696e8c8a52d671e.1678286291.git.geert+renesas@glider.be --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b75f71fe6529..073df0f19b72 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -909,6 +909,7 @@ CONFIG_USB=y CONFIG_USB_OTG=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_RZV2M=y CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_BRCMSTB=m CONFIG_USB_EHCI_HCD=y @@ -944,6 +945,7 @@ CONFIG_USB_ONBOARD_HUB=m CONFIG_NOP_USB_XCEIV=y CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_RZV2M_USB3DRD=y CONFIG_USB_RENESAS_USB3=m CONFIG_USB_TEGRA_XUDC=m CONFIG_USB_CONFIGFS=m From 28924444f2736e34dfe52b6a7920cea6d0d89807 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 6 Feb 2023 00:13:00 +0000 Subject: [PATCH 0115/1040] arm64: dts: renesas: r9a07g054: Add Cortex-A55 PMU node Enable the performance monitor unit for the Cortex-A55 cores on the RZ/V2L (r9a07g054) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230206001300.28937-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 56f56a57749e..8592cddfd4e6 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -157,6 +157,11 @@ }; }; + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; From fb76b0fae3ca880363214e1dcd6513ab8bd529e7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 16 Feb 2023 16:30:31 +0100 Subject: [PATCH 0116/1040] arm64: dts: renesas: r8a77990: Remove bogus voltages from OPP table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the R-Car Series, 3rd Generation Hardware User’s Manual Rev. 2.30, the System CPU cores on R-Car E3 do not have their own power supply, but use the common internal power supply (typical 1.03V). Hence remove the "opp-microvolt" properties from the Operating Performance Points table. They are optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. Fixes: dd7188eb4ed128dc ("arm64: dts: renesas: r8a77990: Add OPPs table for cpu devices") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/9232578d9d395d529f64db3333a371e31327f459.1676560856.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index d4718f144e33..4529e9b57c33 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -49,17 +49,14 @@ opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; opp-suspend; }; From 554edc3e9239bb81e61be9f0f5dbbeb528a69e72 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 16 Feb 2023 16:30:32 +0100 Subject: [PATCH 0117/1040] arm64: dts: renesas: r8a774c0: Remove bogus voltages from OPP table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the RZ/G Series, 2nd Generation Hardware User’s Manual Rev. 1.11, the System CPU cores on RZ/G2E do not have their own power supply, but use the common internal power supply (typical 1.03V). Hence remove the "opp-microvolt" properties from the Operating Performance Points table. They are optional, and unused, when none of the CPU nodes is tied to a regulator using the "cpu-supply" property. Fixes: 231d8908a66fa98f ("arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/8348e18a011ded94e35919cd8e17c0be1f9acf2f.1676560856.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index e21653d86228..10abfde329d0 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -49,17 +49,14 @@ opp-shared; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <820000>; clock-latency-ns = <300000>; opp-suspend; }; From 5da750ddd96454757a3b467e968e3fb70bb12bc8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 17 Feb 2023 18:52:24 +0000 Subject: [PATCH 0118/1040] arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channels From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 92a341315afc9 ("arm64: dts: renesas: r9a07g044: Add SSI support") Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 447ebf90a10d..79cffbf20c55 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -180,9 +180,8 @@ reg = <0 0x10049c00 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -201,9 +200,8 @@ reg = <0 0x1004a000 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -221,10 +219,8 @@ "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; interrupts = , - , - , ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + interrupt-names = "int_req", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -243,9 +239,8 @@ reg = <0 0x1004a800 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; From c2b0dc0e83ef4a74cbe381fd0c84cea16cf067f0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 17 Feb 2023 18:52:24 +0000 Subject: [PATCH 0119/1040] arm64: dts: renesas: r9a07g054: Update IRQ numbers for SSI channels From R01UH0936EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: cd0339ec25895c0b ("arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 8592cddfd4e6..c0ae9c7c10fc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -180,9 +180,8 @@ reg = <0 0x10049c00 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -201,9 +200,8 @@ reg = <0 0x1004a000 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -221,10 +219,8 @@ "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; interrupts = , - , - , ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + interrupt-names = "int_req", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -243,9 +239,8 @@ reg = <0 0x1004a800 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; From 2a5c9891392dca47f6865a2add1986876e40849c Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 17 Feb 2023 18:52:25 +0000 Subject: [PATCH 0120/1040] arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels From R01UH0968EJ0100 Rev.1.00 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 559f2b0708c70 ("arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node") Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230217185225.43310-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c8a83e42c4f3..a9700654b421 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -80,9 +80,8 @@ reg = <0 0x10049c00 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -101,9 +100,8 @@ reg = <0 0x1004a000 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -121,10 +119,8 @@ "renesas,rz-ssi"; reg = <0 0x1004a400 0 0x400>; interrupts = , - , - , ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + interrupt-names = "int_req", "dma_rt"; clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; @@ -143,9 +139,8 @@ reg = <0 0x1004a800 0 0x400>; interrupts = , , - , - ; - interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + ; + interrupt-names = "int_req", "dma_rx", "dma_tx"; clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, <&audio_clk1>, <&audio_clk2>; From 6cf8e3d73ebe832492aa21d2d74b4404f897bb30 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 6 Mar 2023 23:48:58 +0000 Subject: [PATCH 0121/1040] arm64: dts: renesas: r8a779g0: R-Car Sound support Add sound support for R-Car V4H. Signed-off-by: Linh Phung Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/87pm9ll9ue.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 76 +++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index f782a18c8dd3..281f98fc3f16 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -14,6 +14,13 @@ #address-cells = <2>; #size-cells = <2>; + /* External Audio clock - to be overridden by boards that provide it */ + audio_clkin: audio_clkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; @@ -1685,6 +1692,75 @@ dma-channels = <16>; }; + rcar_sound: sound@ec5a0000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * audio_clkout0/1/2/3 : #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a779g0", "renesas,rcar_sound-gen4"; + reg = <0 0xec5a0000 0 0x020>, + <0 0xec540000 0 0x1000>, + <0 0xec541000 0 0x050>, + <0 0xec400000 0 0x40000>; + reg-names = "adg", "ssiu", "ssi", "sdmc"; + + clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; + clock-names = "ssiu.0", "ssi.0", "clkin"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 2926>, <&cpg 2927>; + reset-names = "ssiu.0", "ssi.0"; + status = "disabled"; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&dmac0 0x6e>, <&dmac0 0x6f>; + dma-names = "tx", "rx"; + }; + ssiu01: ssiu-1 { + dmas = <&dmac0 0x6c>, <&dmac0 0x6d>; + dma-names = "tx", "rx"; + }; + ssiu02: ssiu-2 { + dmas = <&dmac0 0x6a>, <&dmac0 0x6b>; + dma-names = "tx", "rx"; + }; + ssiu03: ssiu-3 { + dmas = <&dmac0 0x68>, <&dmac0 0x69>; + dma-names = "tx", "rx"; + }; + ssiu04: ssiu-4 { + dmas = <&dmac0 0x66>, <&dmac0 0x67>; + dma-names = "tx", "rx"; + }; + ssiu05: ssiu-5 { + dmas = <&dmac0 0x64>, <&dmac0 0x65>; + dma-names = "tx", "rx"; + }; + ssiu06: ssiu-6 { + dmas = <&dmac0 0x62>, <&dmac0 0x63>; + dma-names = "tx", "rx"; + }; + ssiu07: ssiu-7 { + dmas = <&dmac0 0x60>, <&dmac0 0x61>; + dma-names = "tx", "rx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + }; + }; + }; + mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a779g0", "renesas,rcar-gen4-sdhi"; From e0d1619f1230f7ce368d7775da5f3130e29cfb33 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 6 Mar 2023 23:49:40 +0000 Subject: [PATCH 0122/1040] arm64: dts: renesas: white-hawk: Add R-Car Sound support Add R-Car Sound support for the White Hawk board with the ARD-AUDIO-DA7212 external audio board, using a DT overlay. Signed-off-by: Linh Phung Signed-off-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/87o7p5l9t7.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../r8a779g0-white-hawk-ard-audio-da7212.dtso | 187 ++++++++++++++++++ 2 files changed, 188 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 0699b51c1247..22c1d20224ef 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -67,6 +67,7 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso new file mode 100644 index 000000000000..e6f53377ecd9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ard-audio-da7212.dtso @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the White Hawk board with ARD-AUDIO-DA7212 Board + * + * You can find and buy "ARD-AUDIO-DA7212" at Digi-Key + * + * https://www.digikey.jp/en/products/detail/ARD-AUDIO-DA7212/1564-1021-ND/5456357 + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + * + * [Connection] + * + * White Hawk ARD-AUDIO-DA7212 + * +----------------------------+ + * |CPU board | + * | | + * |CN40 (IO PIN HEADER) | + * | AUDIO_CLKIN_V pin1 |<--\ +---------------+ + * |(*) GP1_25/SL_SW2_V pin2 |<--/ |J2 | + * | AUDIO_CLKOUT_V pin5 |<----->| pin7 MCLK | + * | SSI_SCK_V pin9 |<----->| pin1 BCLK | + * | SSI_WS_V pin13 |<----->| pin3 WCLK | + * | SSI_SD_V pin15 |<----->| pin5 DATIN | (@) + * | | \-->| pin15 DATOUT | [CAPTURE] + * +----------------------------+ +---------------+ + * +----------------------------+ + * |Breakout board | + * | | +---------------+ + * |CN34 (I2C CN) | |J1 | + * | I2C0_SCL pin3 |<----->| pin20 SCL | + * | I2C0_SDA pin5 |<----->| pin18 SDA | + * | | +---------------+ + * | | +-----------------------+ + * |CN4 (Power) | |J7 | + * | 3v3 (v) pin9 |<----->| pin4 / pin8 3.3v | + * | GND (v) pin3 / pin4 |<----->| pin12 / pin14 GND | + * +----------------------------+ +-----------------------+ + * (*) GP1_25/SL_SW2_V is used as TPU + * (@) Connect to pin5 (DATIN = playback) or pin15 (DATOUT = capture) + * (v) These are just sample pins. You can find many 3v3 / GND pins on + * White Hawk board, not only CN4. You can use other pins for it. + * + * [How to enable] + * + * You need these configs + * + * CONFIG_PWM + * CONFIG_PWM_RENESAS_TPU + * CONFIG_COMMON_CLK_PWM + * CONFIG_SND_SOC_DA7213 + * + * [How to use] + * + * 44.1kHz groups sound is available by default. + * You need to update audio_clkin settings to switch to 48kHz groups sound. + * see + * [(C) clock] + * + * You can use capture if you change the settings + * see + * [CAPTURE] + * + * You need to setup Headphone + * + * > amixer set "Headphone" 40% + * > amixer set "Headphone" on + * > amixer set "Mixout Left DAC Left" on + * > amixer set "Mixout Right DAC Right" on + */ + +/dts-v1/; +/plugin/; +#include + +&{/} { + sound_card: sound { + compatible = "audio-graph-card"; + label = "rcar-sound"; + + dais = <&rsnd_port>; /* DA7212 Audio Codec */ + }; + + tpu_clk: tpu-clk { + compatible = "pwm-clock"; + #clock-cells = <0>; + + /* 44.1kHz groups [(C) clock] */ + clock-frequency = <11289600>; + pwms = <&tpu 0 88 0>; /* 1000000000 / 88 =~ 11289600 */ + + /* 48 kHz groups [(C) clock] */ +// clock-frequency = <12288000>; +// pwms = <&tpu 0 81 0>; /* 1000000000 / 81 =~ 12288000 */ + }; + +}; + +&pfc { + sound_pins: sound { + groups = "ssi_ctrl", "ssi_data"; + function = "ssi"; + }; + + sound_clk_pins: sound-clk { + groups = "audio_clkin", "audio_clkout"; + function = "audio_clk"; + }; + + tpu0_pins: tpu0 { + groups = "tpu_to0_a"; + function = "tpu"; + }; +}; + +&tpu { + pinctrl-0 = <&tpu0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + compatible = "dlg,da7212"; + + #sound-dai-cells = <0>; + reg = <0x1a>; + + clocks = <&rcar_sound>; + clock-names = "mclk"; + + dlg,micbias1-lvl = <2500>; + dlg,micbias2-lvl = <2500>; + dlg,dmic-data-sel = "lrise_rfall"; + dlg,dmic-samplephase = "between_clkedge"; + dlg,dmic-clkrate = <3000000>; + + VDDA-supply = <®_1p8v>; + VDDMIC-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + + port { + da7212_endpoint: endpoint { + remote-endpoint = <&rsnd_endpoint>; + }; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_clk_pins>, <&sound_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout */ + #clock-cells = <0>; + clock-frequency = <5644800>; /* 44.1kHz groups [(C) clock] */ +// clock-frequency = <6144000>; /* 48 kHz groups [(C) clock] */ + + status = "okay"; + + /* Update to */ + clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&tpu_clk>; + + ports { + rsnd_port: port { + rsnd_endpoint: endpoint { + remote-endpoint = <&da7212_endpoint>; + + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint>; + frame-master = <&rsnd_endpoint>; + + /* Mutually exclusive with 'capture' */ + playback = <&ssi0>; + /* [CAPTURE] */ + /* capture = <&ssi0>; */ + }; + }; + }; +}; From 27159fb3e00652c44ed5451ca9df50bffcbc5273 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 7 Mar 2023 11:56:38 +0100 Subject: [PATCH 0123/1040] arm64: dts: renesas: Remove R-Car H3 ES1.* devicetrees R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230307105645.5285-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 4 - .../boot/dts/renesas/r8a77950-salvator-x.dts | 49 --- .../boot/dts/renesas/r8a77950-ulcb-kf.dts | 16 - arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts | 37 -- arch/arm64/boot/dts/renesas/r8a77950.dtsi | 330 ------------------ 5 files changed, 436 deletions(-) delete mode 100644 arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts delete mode 100644 arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts delete mode 100644 arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts delete mode 100644 arch/arm64/boot/dts/renesas/r8a77950.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 22c1d20224ef..23b10c03091c 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -28,10 +28,6 @@ dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-idk-1110wr.dtb dtb-$(CONFIG_ARCH_R8A774E1) += r8a774e1-hihope-rzg2h-ex-mipi-2.1.dtb -dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-salvator-x.dtb -dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb.dtb -dtb-$(CONFIG_ARCH_R8A77950) += r8a77950-ulcb-kf.dtb - dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-x.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a77951-ulcb.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts deleted file mode 100644 index c6ca61a8ed40..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950-salvator-x.dts +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the Salvator-X board with R-Car H3 ES1.x - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "salvator-x.dtsi" - -/ { - model = "Renesas Salvator-X board based on r8a77950"; - compatible = "renesas,salvator-x", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&cpg CPG_MOD 723>, - <&cpg CPG_MOD 722>, - <&cpg CPG_MOD 721>, - <&versaclock5 1>, - <&x21_clk>, - <&x22_clk>, - <&versaclock5 2>; - clock-names = "du.0", "du.1", "du.2", "du.3", - "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts deleted file mode 100644 index 85f008ef63de..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950-ulcb-kf.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB Kingfisher board with R-Car H3 ES1.x - * - * Copyright (C) 2017 Renesas Electronics Corp. - * Copyright (C) 2017 Cogent Embedded, Inc. - */ - -#include "r8a77950-ulcb.dts" -#include "ulcb-kf.dtsi" - -/ { - model = "Renesas H3ULCB Kingfisher board based on r8a77950"; - compatible = "shimafuji,kingfisher", "renesas,h3ulcb", - "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts deleted file mode 100644 index 5340579931e3..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950-ulcb.dts +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board with R-Car H3 ES1.x - * - * Copyright (C) 2016 Renesas Electronics Corp. - * Copyright (C) 2016 Cogent Embedded, Inc. - */ - -/dts-v1/; -#include "r8a77950.dtsi" -#include "ulcb.dtsi" - -/ { - model = "Renesas H3ULCB board based on r8a77950"; - compatible = "renesas,h3ulcb", "renesas,r8a7795"; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; - }; - - memory@500000000 { - device_type = "memory"; - reg = <0x5 0x00000000 0x0 0x40000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x0 0x40000000>; - }; - - memory@700000000 { - device_type = "memory"; - reg = <0x7 0x00000000 0x0 0x40000000>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a77950.dtsi b/arch/arm64/boot/dts/renesas/r8a77950.dtsi deleted file mode 100644 index 57eb88177e92..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a77950.dtsi +++ /dev/null @@ -1,330 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the R-Car H3 (R8A77950) SoC - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -#include "r8a77951.dtsi" - -#undef SOC_HAS_USB2_CH3 - -&audma0 { - iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>, - <&ipmmu_mp1 2>, <&ipmmu_mp1 3>, - <&ipmmu_mp1 4>, <&ipmmu_mp1 5>, - <&ipmmu_mp1 6>, <&ipmmu_mp1 7>, - <&ipmmu_mp1 8>, <&ipmmu_mp1 9>, - <&ipmmu_mp1 10>, <&ipmmu_mp1 11>, - <&ipmmu_mp1 12>, <&ipmmu_mp1 13>, - <&ipmmu_mp1 14>, <&ipmmu_mp1 15>; -}; - -&audma1 { - iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>, - <&ipmmu_mp1 18>, <&ipmmu_mp1 19>, - <&ipmmu_mp1 20>, <&ipmmu_mp1 21>, - <&ipmmu_mp1 22>, <&ipmmu_mp1 23>, - <&ipmmu_mp1 24>, <&ipmmu_mp1 25>, - <&ipmmu_mp1 26>, <&ipmmu_mp1 27>, - <&ipmmu_mp1 28>, <&ipmmu_mp1 29>, - <&ipmmu_mp1 30>, <&ipmmu_mp1 31>; -}; - -&cluster0_opp { - /delete-node/ opp-1600000000; - /delete-node/ opp-1700000000; -}; - -&du { - renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd3 0>; -}; - -&fcpvb1 { - iommus = <&ipmmu_vp0 7>; -}; - -&fcpf1 { - iommus = <&ipmmu_vp0 1>; -}; - -&fcpvi1 { - iommus = <&ipmmu_vp0 9>; -}; - -&fcpvd2 { - iommus = <&ipmmu_vi0 10>; -}; - -&gpio1 { - gpio-ranges = <&pfc 0 32 28>; -}; - -&ipmmu_vi0 { - renesas,ipmmu-main = <&ipmmu_mm 11>; -}; - -&ipmmu_vp0 { - renesas,ipmmu-main = <&ipmmu_mm 12>; -}; - -&ipmmu_vc0 { - renesas,ipmmu-main = <&ipmmu_mm 9>; -}; - -&ipmmu_vc1 { - renesas,ipmmu-main = <&ipmmu_mm 10>; -}; - -&ipmmu_rt { - renesas,ipmmu-main = <&ipmmu_mm 7>; -}; - -&soc { - /delete-node/ dma-controller@e6460000; - /delete-node/ dma-controller@e6470000; - - ipmmu_mp1: iommu@ec680000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xec680000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - ipmmu_sy: iommu@e7730000 { - compatible = "renesas,ipmmu-r8a7795"; - reg = <0 0xe7730000 0 0x1000>; - renesas,ipmmu-main = <&ipmmu_mm 8>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - #iommu-cells = <1>; - }; - - /delete-node/ iommu@fd950000; - /delete-node/ iommu@fd960000; - /delete-node/ iommu@fd970000; - /delete-node/ iommu@febe0000; - /delete-node/ iommu@fe980000; - - xhci1: usb@ee040000 { - compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; - reg = <0 0xee040000 0 0xc00>; - interrupts = ; - clocks = <&cpg CPG_MOD 327>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 327>; - status = "disabled"; - }; - - /delete-node/ usb@e659c000; - /delete-node/ usb@ee0e0000; - /delete-node/ usb@ee0e0100; - - /delete-node/ usb-phy@ee0e0200; - - fdp1@fe948000 { - compatible = "renesas,fdp1"; - reg = <0 0xfe948000 0 0x2400>; - interrupts = ; - clocks = <&cpg CPG_MOD 117>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 117>; - renesas,fcp = <&fcpf2>; - }; - - fcpf2: fcp@fe952000 { - compatible = "renesas,fcpf"; - reg = <0 0xfe952000 0 0x200>; - clocks = <&cpg CPG_MOD 613>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 613>; - iommus = <&ipmmu_vp0 2>; - }; - - fcpvd3: fcp@fea3f000 { - compatible = "renesas,fcpv"; - reg = <0 0xfea3f000 0 0x200>; - clocks = <&cpg CPG_MOD 600>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 600>; - iommus = <&ipmmu_vi0 11>; - }; - - fcpvi2: fcp@fe9cf000 { - compatible = "renesas,fcpv"; - reg = <0 0xfe9cf000 0 0x200>; - clocks = <&cpg CPG_MOD 609>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 609>; - iommus = <&ipmmu_vp0 10>; - }; - - vspd3: vsp@fea38000 { - compatible = "renesas,vsp2"; - reg = <0 0xfea38000 0 0x5000>; - interrupts = ; - clocks = <&cpg CPG_MOD 620>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 620>; - - renesas,fcp = <&fcpvd3>; - }; - - vspi2: vsp@fe9c0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfe9c0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A7795_PD_A3VP>; - resets = <&cpg 629>; - - renesas,fcp = <&fcpvi2>; - }; - - csi21: csi2@fea90000 { - compatible = "renesas,r8a7795-csi2"; - reg = <0 0xfea90000 0 0x10000>; - interrupts = ; - clocks = <&cpg CPG_MOD 713>; - power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - resets = <&cpg 713>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - #address-cells = <1>; - #size-cells = <0>; - - reg = <1>; - - csi21vin0: endpoint@0 { - reg = <0>; - remote-endpoint = <&vin0csi21>; - }; - csi21vin1: endpoint@1 { - reg = <1>; - remote-endpoint = <&vin1csi21>; - }; - csi21vin2: endpoint@2 { - reg = <2>; - remote-endpoint = <&vin2csi21>; - }; - csi21vin3: endpoint@3 { - reg = <3>; - remote-endpoint = <&vin3csi21>; - }; - csi21vin4: endpoint@4 { - reg = <4>; - remote-endpoint = <&vin4csi21>; - }; - csi21vin5: endpoint@5 { - reg = <5>; - remote-endpoint = <&vin5csi21>; - }; - csi21vin6: endpoint@6 { - reg = <6>; - remote-endpoint = <&vin6csi21>; - }; - csi21vin7: endpoint@7 { - reg = <7>; - remote-endpoint = <&vin7csi21>; - }; - }; - }; - }; -}; - -&vin0 { - ports { - port@1 { - vin0csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin0>; - }; - }; - }; -}; - -&vin1 { - ports { - port@1 { - vin1csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin1>; - }; - }; - }; -}; - -&vin2 { - ports { - port@1 { - vin2csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin2>; - }; - }; - }; -}; - -&vin3 { - ports { - port@1 { - vin3csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin3>; - }; - }; - }; -}; - -&vin4 { - ports { - port@1 { - vin4csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin4>; - }; - }; - }; -}; - -&vin5 { - ports { - port@1 { - vin5csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin5>; - }; - }; - }; -}; - -&vin6 { - ports { - port@1 { - vin6csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin6>; - }; - }; - }; -}; - -&vin7 { - ports { - port@1 { - vin7csi21: endpoint@1 { - reg = <1>; - remote-endpoint = <&csi21vin7>; - }; - }; - }; -}; From d35ad1030a6bce57234b8eea14ab17560f3c9e1b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 7 Mar 2023 11:56:39 +0100 Subject: [PATCH 0124/1040] dt-bindings: soc: renesas: Remove R-Car H3 ES1.* R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support and disable booting for this SoC. Public users only have ES2 onwards. Signed-off-by: Wolfram Sang Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230307105645.5285-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/soc/renesas/renesas.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 76f6da46ff5c..60190d84d9b3 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -212,12 +212,12 @@ properties: - renesas,silk # SILK (RTP0RC7794LCB00011S) - const: renesas,r8a7794 - - description: R-Car H3 (R8A77950) + # Note: R-Car H3 ES1.* (R8A77950) is not supported upstream anymore! + + - description: R-Car H3 ES2.0 and later (R8A77951) items: - enum: - # H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKBX0010SA00 (H3 ES1.1)) - # H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - - renesas,h3ulcb + - renesas,h3ulcb # H3ULCB (R-Car Starter Kit Premier, RTP0RC77951SKBX010SA00 (H3 ES2.0)) - renesas,salvator-x # Salvator-X (RTP0RC7795SIPB0010S) - renesas,salvator-xs # Salvator-XS (Salvator-X 2nd version, RTP0RC7795SIPB0012S) - const: renesas,r8a7795 From 5fe5a7586c27a13a42b7946334d41a96c776a188 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 10 Mar 2023 17:07:53 +0100 Subject: [PATCH 0125/1040] Move COMPAT_ATM_ADDPARTY to net/atm/svc.c This used to be behind an #ifdef COMPAT_COMPAT, so most of userspace wouldn't have seen the definition before. Unfortunately this header file became visible to userspace, so the definition has instead been moved to net/atm/svc.c (the only user). Signed-off-by: Palmer Dabbelt Reviewed-by: Andrew Waterman Reviewed-by: Albert Ou Message-Id: <1447119071-19392-4-git-send-email-palmer@dabbelt.com> Reviewed-by: Arnd Bergmann Reviewed-by: Christoph Hellwig Signed-off-by: Thomas Huth Signed-off-by: Arnd Bergmann --- include/uapi/linux/atmdev.h | 4 ---- net/atm/svc.c | 5 +++++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/uapi/linux/atmdev.h b/include/uapi/linux/atmdev.h index a5c15cf23bd7..20b0215084fc 100644 --- a/include/uapi/linux/atmdev.h +++ b/include/uapi/linux/atmdev.h @@ -101,10 +101,6 @@ struct atm_dev_stats { /* use backend to make new if */ #define ATM_ADDPARTY _IOW('a', ATMIOC_SPECIAL+4,struct atm_iobuf) /* add party to p2mp call */ -#ifdef CONFIG_COMPAT -/* It actually takes struct sockaddr_atmsvc, not struct atm_iobuf */ -#define COMPAT_ATM_ADDPARTY _IOW('a', ATMIOC_SPECIAL+4,struct compat_atm_iobuf) -#endif #define ATM_DROPPARTY _IOW('a', ATMIOC_SPECIAL+5,int) /* drop party from p2mp call */ diff --git a/net/atm/svc.c b/net/atm/svc.c index 4a02bcaad279..d83556d8beb9 100644 --- a/net/atm/svc.c +++ b/net/atm/svc.c @@ -28,6 +28,11 @@ #include "signaling.h" #include "addr.h" +#ifdef CONFIG_COMPAT +/* It actually takes struct sockaddr_atmsvc, not struct atm_iobuf */ +#define COMPAT_ATM_ADDPARTY _IOW('a', ATMIOC_SPECIAL + 4, struct compat_atm_iobuf) +#endif + static int svc_create(struct net *net, struct socket *sock, int protocol, int kern); From 063f3ed9faf38e41449838bb3258a7d00f75c5d1 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 10 Mar 2023 17:07:54 +0100 Subject: [PATCH 0126/1040] Move ep_take_care_of_epollwakeup() to fs/eventpoll.c This doesn't make any sense to expose to userspace, so it's been moved to the one user. This was introduced by commit 95f19f658ce1 ("epoll: drop EPOLLWAKEUP if PM_SLEEP is disabled"). Signed-off-by: Palmer Dabbelt Reviewed-by: Andrew Waterman Reviewed-by: Albert Ou Message-Id: <1447119071-19392-7-git-send-email-palmer@dabbelt.com> [thuth: Rebased to fix contextual conflicts] Reviewed-by: Arnd Bergmann Reviewed-by: Christoph Hellwig Signed-off-by: Thomas Huth Signed-off-by: Arnd Bergmann --- fs/eventpoll.c | 13 +++++++++++++ include/uapi/linux/eventpoll.h | 12 ------------ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/fs/eventpoll.c b/fs/eventpoll.c index 64659b110973..e2a5d2cc9051 100644 --- a/fs/eventpoll.c +++ b/fs/eventpoll.c @@ -2042,6 +2042,19 @@ SYSCALL_DEFINE1(epoll_create, int, size) return do_epoll_create(0); } +#ifdef CONFIG_PM_SLEEP +static inline void ep_take_care_of_epollwakeup(struct epoll_event *epev) +{ + if ((epev->events & EPOLLWAKEUP) && !capable(CAP_BLOCK_SUSPEND)) + epev->events &= ~EPOLLWAKEUP; +} +#else +static inline void ep_take_care_of_epollwakeup(struct epoll_event *epev) +{ + epev->events &= ~EPOLLWAKEUP; +} +#endif + static inline int epoll_mutex_lock(struct mutex *mutex, int depth, bool nonblock) { diff --git a/include/uapi/linux/eventpoll.h b/include/uapi/linux/eventpoll.h index e687658843b1..cfbcc4cc49ac 100644 --- a/include/uapi/linux/eventpoll.h +++ b/include/uapi/linux/eventpoll.h @@ -85,16 +85,4 @@ struct epoll_event { __u64 data; } EPOLL_PACKED; -#ifdef CONFIG_PM_SLEEP -static inline void ep_take_care_of_epollwakeup(struct epoll_event *epev) -{ - if ((epev->events & EPOLLWAKEUP) && !capable(CAP_BLOCK_SUSPEND)) - epev->events &= ~EPOLLWAKEUP; -} -#else -static inline void ep_take_care_of_epollwakeup(struct epoll_event *epev) -{ - epev->events &= ~EPOLLWAKEUP; -} -#endif #endif /* _UAPI_LINUX_EVENTPOLL_H */ From d3c7ec7588508bd59bbb0e468d3820f3d3cba690 Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 10 Mar 2023 17:07:55 +0100 Subject: [PATCH 0127/1040] Move bp_type_idx to include/linux/hw_breakpoint.h This has a "#ifdef CONFIG_*" that used to be exposed to userspace. The names in here are so generic that I don't think it's a good idea to expose them to userspace (or even the rest of the kernel). There are multiple in-kernel users, so it's been moved to a kernel header file. Signed-off-by: Palmer Dabbelt Reviewed-by: Andrew Waterman Reviewed-by: Albert Ou Message-Id: <1447119071-19392-10-git-send-email-palmer@dabbelt.com> [thuth: Remove it also from tools/include/uapi/linux/hw_breakpoint.h] Reviewed-by: Arnd Bergmann Reviewed-by: Christoph Hellwig Signed-off-by: Thomas Huth Signed-off-by: Arnd Bergmann --- include/linux/hw_breakpoint.h | 10 ++++++++++ include/uapi/linux/hw_breakpoint.h | 10 ---------- tools/include/uapi/linux/hw_breakpoint.h | 10 ---------- 3 files changed, 10 insertions(+), 20 deletions(-) diff --git a/include/linux/hw_breakpoint.h b/include/linux/hw_breakpoint.h index f319bd26b030..7fbb45911273 100644 --- a/include/linux/hw_breakpoint.h +++ b/include/linux/hw_breakpoint.h @@ -7,6 +7,16 @@ #ifdef CONFIG_HAVE_HW_BREAKPOINT +enum bp_type_idx { + TYPE_INST = 0, +#if defined(CONFIG_HAVE_MIXED_BREAKPOINTS_REGS) + TYPE_DATA = 0, +#else + TYPE_DATA = 1, +#endif + TYPE_MAX +}; + extern int __init init_hw_breakpoint(void); static inline void hw_breakpoint_init(struct perf_event_attr *attr) diff --git a/include/uapi/linux/hw_breakpoint.h b/include/uapi/linux/hw_breakpoint.h index 965e4d8606d8..1575d3ca6f0d 100644 --- a/include/uapi/linux/hw_breakpoint.h +++ b/include/uapi/linux/hw_breakpoint.h @@ -22,14 +22,4 @@ enum { HW_BREAKPOINT_INVALID = HW_BREAKPOINT_RW | HW_BREAKPOINT_X, }; -enum bp_type_idx { - TYPE_INST = 0, -#ifdef CONFIG_HAVE_MIXED_BREAKPOINTS_REGS - TYPE_DATA = 0, -#else - TYPE_DATA = 1, -#endif - TYPE_MAX -}; - #endif /* _UAPI_LINUX_HW_BREAKPOINT_H */ diff --git a/tools/include/uapi/linux/hw_breakpoint.h b/tools/include/uapi/linux/hw_breakpoint.h index 965e4d8606d8..1575d3ca6f0d 100644 --- a/tools/include/uapi/linux/hw_breakpoint.h +++ b/tools/include/uapi/linux/hw_breakpoint.h @@ -22,14 +22,4 @@ enum { HW_BREAKPOINT_INVALID = HW_BREAKPOINT_RW | HW_BREAKPOINT_X, }; -enum bp_type_idx { - TYPE_INST = 0, -#ifdef CONFIG_HAVE_MIXED_BREAKPOINTS_REGS - TYPE_DATA = 0, -#else - TYPE_DATA = 1, -#endif - TYPE_MAX -}; - #endif /* _UAPI_LINUX_HW_BREAKPOINT_H */ From f5bdc61eb6089e10181b8f51b0a180bbd47a89fc Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 10 Mar 2023 17:07:56 +0100 Subject: [PATCH 0128/1040] pktcdvd: Remove CONFIG_CDROM_PKTCDVD_WCACHE from uapi header CONFIG_* switches should not be exposed in uapi headers, thus let's get rid of the USE_WCACHING macro here (which was also named way to generic) and integrate the logic directly in the only function that needs it. Suggested-by: Christoph Hellwig Signed-off-by: Thomas Huth Signed-off-by: Arnd Bergmann --- drivers/block/pktcdvd.c | 13 +++++++++---- include/uapi/linux/pktcdvd.h | 11 ----------- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c index 2f1a92509271..5ae2a80db2c3 100644 --- a/drivers/block/pktcdvd.c +++ b/drivers/block/pktcdvd.c @@ -1869,12 +1869,12 @@ static noinline_for_stack int pkt_probe_settings(struct pktcdvd_device *pd) /* * enable/disable write caching on drive */ -static noinline_for_stack int pkt_write_caching(struct pktcdvd_device *pd, - int set) +static noinline_for_stack int pkt_write_caching(struct pktcdvd_device *pd) { struct packet_command cgc; struct scsi_sense_hdr sshdr; unsigned char buf[64]; + bool set = IS_ENABLED(CONFIG_CDROM_PKTCDVD_WCACHE); int ret; init_cdrom_command(&cgc, buf, sizeof(buf), CGC_DATA_READ); @@ -1890,7 +1890,12 @@ static noinline_for_stack int pkt_write_caching(struct pktcdvd_device *pd, if (ret) return ret; - buf[pd->mode_offset + 10] |= (!!set << 2); + /* + * use drive write caching -- we need deferred error handling to be + * able to successfully recover with this option (drive will return good + * status as soon as the cdb is validated). + */ + buf[pd->mode_offset + 10] |= (set << 2); cgc.buflen = cgc.cmd[8] = 2 + ((buf[0] << 8) | (buf[1] & 0xff)); ret = pkt_mode_select(pd, &cgc); @@ -2085,7 +2090,7 @@ static int pkt_open_write(struct pktcdvd_device *pd) return -EIO; } - pkt_write_caching(pd, USE_WCACHING); + pkt_write_caching(pd); ret = pkt_get_max_speed(pd, &write_speed); if (ret) diff --git a/include/uapi/linux/pktcdvd.h b/include/uapi/linux/pktcdvd.h index 9cbb55d21c94..6a5552dfd6af 100644 --- a/include/uapi/linux/pktcdvd.h +++ b/include/uapi/linux/pktcdvd.h @@ -29,17 +29,6 @@ */ #define PACKET_WAIT_TIME (HZ * 5 / 1000) -/* - * use drive write caching -- we need deferred error handling to be - * able to successfully recover with this option (drive will return good - * status as soon as the cdb is validated). - */ -#if defined(CONFIG_CDROM_PKTCDVD_WCACHE) -#define USE_WCACHING 1 -#else -#define USE_WCACHING 0 -#endif - /* * No user-servicable parts beyond this point -> */ From bd81feb8cdbf0d9df27301c8fabbbd538519e8b3 Mon Sep 17 00:00:00 2001 From: Thomas Huth Date: Fri, 10 Mar 2023 17:07:57 +0100 Subject: [PATCH 0129/1040] scripts: Update the CONFIG_* ignore list in headers_install.sh The file in include/uapi/linux/ have been cleaned in the previous patches, so we can now remove these entries from the CONFIG_* ignore-list. Signed-off-by: Thomas Huth Signed-off-by: Arnd Bergmann --- scripts/headers_install.sh | 4 ---- 1 file changed, 4 deletions(-) diff --git a/scripts/headers_install.sh b/scripts/headers_install.sh index 4041881746ad..36b56b746fce 100755 --- a/scripts/headers_install.sh +++ b/scripts/headers_install.sh @@ -83,10 +83,6 @@ arch/nios2/include/uapi/asm/swab.h:CONFIG_NIOS2_CI_SWAB_SUPPORT arch/x86/include/uapi/asm/auxvec.h:CONFIG_IA32_EMULATION arch/x86/include/uapi/asm/auxvec.h:CONFIG_X86_64 arch/x86/include/uapi/asm/mman.h:CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS -include/uapi/linux/atmdev.h:CONFIG_COMPAT -include/uapi/linux/eventpoll.h:CONFIG_PM_SLEEP -include/uapi/linux/hw_breakpoint.h:CONFIG_HAVE_MIXED_BREAKPOINTS_REGS -include/uapi/linux/pktcdvd.h:CONFIG_CDROM_PKTCDVD_WCACHE " for c in $configs From 1b1b863a8898ad8348b7dfe812cab26cea9099bf Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:25 -0600 Subject: [PATCH 0130/1040] soc: ti: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230310144725.1545384-1-robh@kernel.org --- drivers/soc/ti/knav_qmss_queue.c | 2 +- drivers/soc/ti/omap_prm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index 8fb76908be70..48de98560093 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -1267,7 +1267,7 @@ static int knav_setup_queue_range(struct knav_device *kdev, if (of_get_property(node, "qalloc-by-id", NULL)) range->flags |= RANGE_RESERVED; - if (of_get_property(node, "accumulator", NULL)) { + if (of_property_present(node, "accumulator")) { ret = knav_init_acc_range(kdev, node, range); if (ret < 0) { devm_kfree(dev, range); diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 913b964374a4..ecd9a8bdd7c0 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -684,7 +684,7 @@ static int omap_prm_domain_init(struct device *dev, struct omap_prm *prm) const char *name; int error; - if (!of_find_property(dev->of_node, "#power-domain-cells", NULL)) + if (!of_property_present(dev->of_node, "#power-domain-cells")) return 0; of_node_put(dev->of_node); From 82e46bf71780940a5e060fcb02397ecf7f55e768 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:25 -0600 Subject: [PATCH 0131/1040] soc: ti: Use of_property_read_bool() for boolean properties It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to of_property_read_bool(). Signed-off-by: Rob Herring Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230310144726.1545453-1-robh@kernel.org --- drivers/soc/ti/knav_dma.c | 4 ++-- drivers/soc/ti/knav_qmss_acc.c | 2 +- drivers/soc/ti/knav_qmss_queue.c | 2 +- drivers/soc/ti/wkup_m3_ipc.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/soc/ti/knav_dma.c b/drivers/soc/ti/knav_dma.c index 84afebd355be..0fbc37cd5123 100644 --- a/drivers/soc/ti/knav_dma.c +++ b/drivers/soc/ti/knav_dma.c @@ -666,8 +666,8 @@ static int dma_init(struct device_node *cloud, struct device_node *dma_node) dma->rx_priority = DMA_PRIO_DEFAULT; dma->tx_priority = DMA_PRIO_DEFAULT; - dma->enable_all = (of_get_property(node, "ti,enable-all", NULL) != NULL); - dma->loopback = (of_get_property(node, "ti,loop-back", NULL) != NULL); + dma->enable_all = of_property_read_bool(node, "ti,enable-all"); + dma->loopback = of_property_read_bool(node, "ti,loop-back"); ret = of_property_read_u32(node, "ti,rx-retry-timeout", &timeout); if (ret < 0) { diff --git a/drivers/soc/ti/knav_qmss_acc.c b/drivers/soc/ti/knav_qmss_acc.c index fde66e28e046..3d388646ed43 100644 --- a/drivers/soc/ti/knav_qmss_acc.c +++ b/drivers/soc/ti/knav_qmss_acc.c @@ -521,7 +521,7 @@ int knav_init_acc_range(struct knav_device *kdev, info->pdsp = pdsp; channels = range->num_queues; - if (of_get_property(node, "multi-queue", NULL)) { + if (of_property_read_bool(node, "multi-queue")) { range->flags |= RANGE_MULTI_QUEUE; channels = 1; if (range->queue_base & (32 - 1)) { diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index 48de98560093..0f252c2549ba 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -1264,7 +1264,7 @@ static int knav_setup_queue_range(struct knav_device *kdev, if (range->num_irqs) range->flags |= RANGE_HAS_IRQ; - if (of_get_property(node, "qalloc-by-id", NULL)) + if (of_property_read_bool(node, "qalloc-by-id")) range->flags |= RANGE_RESERVED; if (of_property_present(node, "accumulator")) { diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 343c58ed5896..6970478b40f3 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -681,7 +681,7 @@ static int wkup_m3_ipc_probe(struct platform_device *pdev) dev_warn(dev, "Invalid VTT GPIO(%d) pin\n", temp); } - if (of_find_property(np, "ti,set-io-isolation", NULL)) + if (of_property_read_bool(np, "ti,set-io-isolation")) wkup_m3_set_io_isolation(m3_ipc); ret = of_property_read_string(np, "firmware-name", From 8a922b7728a93d837954315c98b84f6b78de0c4f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 26 May 2022 22:46:05 +0200 Subject: [PATCH 0132/1040] arm64: dts: toshiba: adjust whitespace around '=' Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Link: https://lore.kernel.org/r/20220526204606.833054-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 0fc32c036f30..b04829b3175d 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -485,7 +485,7 @@ <0x0 0x28050000 0x0 0x00010000>, <0x0 0x24200000 0x0 0x00002000>, <0x0 0x24162000 0x0 0x00001000>; - reg-names = "dbi", "config", "ulreg", "smu", "mpu"; + reg-names = "dbi", "config", "ulreg", "smu", "mpu"; device_type = "pci"; bus-range = <0x00 0xff>; num-lanes = <2>; From f7ec6efef4560edeebdca10b73a92f37c6fb16cf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 23 Jan 2023 16:15:31 +0100 Subject: [PATCH 0133/1040] ARM: dts: omap: align UART node name with bindings Bindings expect UART/serial node names to be "serial". Link: https://lore.kernel.org/r/20230123151531.369419-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/omap-zoom-common.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi index 1e96c865d41d..8adc0ef01f6c 100644 --- a/arch/arm/boot/dts/omap-zoom-common.dtsi +++ b/arch/arm/boot/dts/omap-zoom-common.dtsi @@ -14,7 +14,7 @@ * they probably share the same GPIO IRQ * REVISIT: Add timing support from slls644g.pdf */ - uart@3,0 { + serial@3,0 { compatible = "ns16550a"; reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ bank-width = <2>; @@ -50,7 +50,7 @@ gpmc,wr-data-mux-bus-ns = <45>; gpmc,wr-access-ns = <145>; }; - uart@3,1 { + serial@3,1 { compatible = "ns16550a"; reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ bank-width = <2>; @@ -61,7 +61,7 @@ clock-frequency = <1843200>; current-speed = <115200>; }; - uart@3,2 { + serial@3,2 { compatible = "ns16550a"; reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ bank-width = <2>; @@ -72,7 +72,7 @@ clock-frequency = <1843200>; current-speed = <115200>; }; - uart@3,3 { + serial@3,3 { compatible = "ns16550a"; reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ bank-width = <2>; From 90bf48c6ddd3afc406e41a1a193d412f61d2a976 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 11:18:38 +0100 Subject: [PATCH 0134/1040] ARM: dts: marvell: use "okay" for status "okay" over "ok" is preferred for status property. Link: https://lore.kernel.org/r/20230127101839.93873-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/armada-388-db.dts | 2 +- arch/arm/boot/dts/dove.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts index 2bcec5419b66..45cc784659fd 100644 --- a/arch/arm/boot/dts/armada-388-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -62,7 +62,7 @@ }; usb@58000 { - status = "ok"; + status = "okay"; }; ethernet@70000 { diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 85408d4c6f2e..062c86361640 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -422,7 +422,7 @@ clocks = <&gate_clk 3>; clock-names = "sata"; #phy-cells = <0>; - status = "ok"; + status = "okay"; }; audio0: audio-controller@b0000 { From 1792375be092b4d9da34b43240319264363540dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 11:18:36 +0100 Subject: [PATCH 0135/1040] ARM: dts: ti: use "okay" for status "okay" over "ok" is preferred for status property. Acked-by: Nishanth Menon Acked-by: Bartosz Golaszewski Link: https://lore.kernel.org/r/20230127101836.93845-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/da850-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2e-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2g-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2hk-evm.dts | 2 +- arch/arm/boot/dts/keystone-k2l-evm.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 1fdd9a249165..0ca849885d1f 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -415,7 +415,7 @@ &aemif { pinctrl-names = "default"; pinctrl-0 = <&nand_pins>; - status = "ok"; + status = "okay"; cs3 { #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index 5d6d074011df..abd5aef8b87d 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -159,7 +159,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts index 88be868cf71e..3a87b7943c70 100644 --- a/arch/arm/boot/dts/keystone-k2g-evm.dts +++ b/arch/arm/boot/dts/keystone-k2g-evm.dts @@ -534,7 +534,7 @@ &dss { pinctrl-names = "default"; pinctrl-0 = <&vout_pins>; - status = "ok"; + status = "okay"; port { dpi_out: endpoint { diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index 4352397b4f52..1f762af6f502 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -183,7 +183,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22"; reg = <0>; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index 1c880cf8fa91..3a69f65de81e 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -132,7 +132,7 @@ }; &mdio { - status = "ok"; + status = "okay"; ethphy0: ethernet-phy@0 { compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; reg = <0>; From aff750faa5ac699df7ade5a31b6ba52ab1072d8a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 27 Jan 2023 11:18:34 +0100 Subject: [PATCH 0136/1040] ARM: dts: hisilicon: use "okay" for status "okay" over "ok" is preferred for status property. Link: https://lore.kernel.org/r/20230127101834.93818-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/hi3620-hi4511.dts | 12 ++++++------ arch/arm/boot/dts/hip04-d01.dts | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/hi3620-hi4511.dts b/arch/arm/boot/dts/hi3620-hi4511.dts index ce356c469e1e..d7f5daecc9dc 100644 --- a/arch/arm/boot/dts/hi3620-hi4511.dts +++ b/arch/arm/boot/dts/hi3620-hi4511.dts @@ -24,42 +24,42 @@ amba-bus { dual_timer0: dual_timer@800000 { - status = "ok"; + status = "okay"; }; uart0: serial@b00000 { /* console */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>; - status = "ok"; + status = "okay"; }; uart1: serial@b01000 { /* modem */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>; - status = "ok"; + status = "okay"; }; uart2: serial@b02000 { /* audience */ pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>; - status = "ok"; + status = "okay"; }; uart3: serial@b03000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>; - status = "ok"; + status = "okay"; }; uart4: serial@b04000 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>; - status = "ok"; + status = "okay"; }; pmx0: pinmux@803000 { diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts index f5691dbc26d2..0210064bf6a5 100644 --- a/arch/arm/boot/dts/hip04-d01.dts +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -23,7 +23,7 @@ soc { uart0: serial@4007000 { - status = "ok"; + status = "okay"; }; }; }; From 0e84f3493a37d50f2f629dbea670135b8a8ee391 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 21 Feb 2023 17:16:53 +0100 Subject: [PATCH 0137/1040] ARM: dts: exynos: fix MCT compatible in Universal C210 When desired, nodes should be disabled instead of changing their compatible to a fake one: exynos4210-universal_c210.dtb: /soc/timer@10050000: failed to match any schema with compatible: ['none'] Tested-by: Marek Szyprowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20230221161653.56574-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 62bf335d5bed..140abfb38e1d 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -516,7 +516,7 @@ }; &mct { - compatible = "none"; + status = "disabled"; }; &mdma1 { From 538c7b5b5d8b5364454494e5fe4125b0b47195f1 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:11 -0600 Subject: [PATCH 0138/1040] memory: atmel-ebi: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230310144711.1543295-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- drivers/memory/atmel-ebi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/atmel-ebi.c b/drivers/memory/atmel-ebi.c index e749dcb3ddea..635966d705cb 100644 --- a/drivers/memory/atmel-ebi.c +++ b/drivers/memory/atmel-ebi.c @@ -598,7 +598,7 @@ static int atmel_ebi_probe(struct platform_device *pdev) reg_cells += val; for_each_available_child_of_node(np, child) { - if (!of_find_property(child, "reg", NULL)) + if (!of_property_present(child, "reg")) continue; ret = atmel_ebi_dev_setup(ebi, child, reg_cells); From 93ba667d6a7b1740877a44c203a3973b894808ad Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 8 Feb 2023 07:59:46 +0100 Subject: [PATCH 0139/1040] arm64: dts: verdin-imx8mp: add pcie support Add PCIe support on the Verdin iMX8M Plus. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 9 ++++++++- .../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 9 ++++++++- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 15 ++++++++++++++- 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 80db1ad7c230..56b0e4b865c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -67,7 +67,14 @@ /* TODO: Audio Codec */ }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; /* Verdin PWM_1 */ &pwm1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index 361426c0da0a..096a6f2300f9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -91,7 +91,14 @@ /* TODO: Audio Codec */ }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; /* Verdin PWM_1 */ &pwm1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index 0dd6180a8e39..00faaf9a02b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -748,7 +748,20 @@ }; }; -/* TODO: Verdin PCIE_1 */ +/* Verdin PCIE_1 */ +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + clocks = <&hsio_blk_ctrl>; + clock-names = "ref"; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; +}; /* Verdin PWM_1 */ &pwm1 { From a39e724e6b2eeb08839cb2f9f6d65852b8a14f1e Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 8 Feb 2023 07:59:47 +0100 Subject: [PATCH 0140/1040] arm64: dts: imx8mp-verdin-yavia: trivial minor updates Capitalise Yavia in comment and add missing whitespace. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index bd7b31cc3760..de5489c2b3e8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -87,7 +87,7 @@ status = "okay"; }; -/* EEPROM on Verdin yavia board */ +/* EEPROM on Verdin Yavia board */ &eeprom_carrier_board { status = "okay"; }; @@ -122,7 +122,7 @@ status = "okay"; }; -&pcie_phy{ +&pcie_phy { status = "okay"; }; From 04b09f6e5d005101b72fdac4c486a578841d7c53 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 8 Feb 2023 12:34:38 -0600 Subject: [PATCH 0141/1040] arm64: dts: layerscape: Fix GICv3 ITS node names The GICv3 ITS is an MSI controller, therefore its node name should be 'msi-controller'. Signed-off-by: Rob Herring Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9e50976bcb8e..678bb0358751 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -131,7 +131,7 @@ interrupt-controller; interrupts = ; - its: gic-its@6020000 { + its: msi-controller@6020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index e5fb137ac02b..8f6090a9aef2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -123,7 +123,7 @@ #size-cells = <2>; ranges; - its: gic-its@6020000 { + its: msi-controller@6020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x6020000 0 0x20000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 348d9e3a9125..d2f5345d0560 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -60,7 +60,7 @@ interrupt-controller; interrupts = <1 9 0x4>; - its: gic-its@6020000 { + its: msi-controller@6020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x6020000 0 0x20000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 50c19e8405d5..ea6a94b57aeb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -395,7 +395,7 @@ interrupt-controller; interrupts = ; - its: gic-its@6020000 { + its: msi-controller@6020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x6020000 0 0x20000>; From 486136566778e995ffcd2fcc7ce39f5928217bca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Fri, 10 Feb 2023 16:48:50 +0100 Subject: [PATCH 0142/1040] dt-bindings: arm: fsl: Fix copy-paste error in comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The imx6dl-yapp4-draco board is actually based on the i.MX6Solo SoC. Fix the comment to match reality. Fixes: 24ef3b6e22fe ("dt-bindings: arm: Add Y Soft IOTA Draco, Hydra and Ursa boards") Signed-off-by: Michal Vokáč Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 2c90455722f0..67a325ed5794 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -474,7 +474,7 @@ properties: - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board - - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board + - ysoft,imx6dl-yapp4-draco # i.MX6 Solo Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board - ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board From 9e39a2c93e68bbf39f83b4125acae91dca0c3119 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Fri, 10 Feb 2023 16:48:52 +0100 Subject: [PATCH 0143/1040] ARM: dts: imx6dl-yapp4: Use reset-gpios property name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the gpios instead of gpio suffix that is mandated by the binding. This dtbs_check warning is fixed now: touchscreen@5c: Unevaluated properties are not allowed ('reset-gpio' was unexpected) The reset signal worked correctly as both the "gpio" and "gpios" suffixes are actually allowed by the gpiolib. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index aacbf317feea..c6afc51bb22b 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -313,7 +313,7 @@ interrupt-parent = <&gpio4>; interrupts = <5 IRQ_TYPE_EDGE_FALLING>; attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; - reset-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; touchscreen-size-x = <800>; touchscreen-size-y = <480>; status = "disabled"; From 903caf42eabec2e39d836cb0aa8bbc23717408e7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Mar 2023 22:44:13 +0100 Subject: [PATCH 0144/1040] soc: qcom: gsbi: mark OF related data as maybe unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver can be compile tested with !CONFIG_OF making certain data unused: drivers/soc/qcom/qcom_gsbi.c:117:34: error: ‘tcsr_dt_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230310214413.275054-1-krzysztof.kozlowski@linaro.org --- drivers/soc/qcom/qcom_gsbi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c index 290bdefbf28a..f1742e5bddb9 100644 --- a/drivers/soc/qcom/qcom_gsbi.c +++ b/drivers/soc/qcom/qcom_gsbi.c @@ -114,7 +114,7 @@ struct gsbi_info { struct regmap *tcsr; }; -static const struct of_device_id tcsr_dt_match[] = { +static const struct of_device_id tcsr_dt_match[] __maybe_unused = { { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064}, { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064}, { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960}, From 4a1b9f4eb122f3e36fdfe62dce96091d3e45132f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:24 -0600 Subject: [PATCH 0145/1040] soc: qcom: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230310144724.1545153-1-robh@kernel.org --- drivers/soc/qcom/qcom_aoss.c | 2 +- drivers/soc/qcom/smem.c | 2 +- drivers/soc/qcom/smsm.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 18c856056475..e376c32cc16e 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -395,7 +395,7 @@ static int qmp_cooling_devices_register(struct qmp *qmp) return -ENOMEM; for_each_available_child_of_node(np, child) { - if (!of_find_property(child, "#cooling-cells", NULL)) + if (!of_property_present(child, "#cooling-cells")) continue; ret = qmp_cooling_device_add(qmp, &qmp->cooling_devs[count++], child); diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 4f163d62942c..25f5925a8d51 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -1045,7 +1045,7 @@ static int qcom_smem_probe(struct platform_device *pdev) int i; num_regions = 1; - if (of_find_property(pdev->dev.of_node, "qcom,rpm-msg-ram", NULL)) + if (of_property_present(pdev->dev.of_node, "qcom,rpm-msg-ram")) num_regions++; array_size = num_regions * sizeof(struct smem_region); diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 3e8994d6110e..8c137dff7dac 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -510,7 +510,7 @@ static int qcom_smsm_probe(struct platform_device *pdev) return -ENOMEM; for_each_child_of_node(pdev->dev.of_node, local_node) { - if (of_find_property(local_node, "#qcom,smem-state-cells", NULL)) + if (of_property_present(local_node, "#qcom,smem-state-cells")) break; } if (!local_node) { From 9a01befe3d0cda5645f36b71f955c62c54c1b74c Mon Sep 17 00:00:00 2001 From: Stefan Eichenberger Date: Mon, 13 Feb 2023 13:09:26 +0100 Subject: [PATCH 0146/1040] arm64: dts: imx8mp-verdin: add 88W8997 serdev to uart4 Use the serdev feature to load the driver for the 88W8997 bluetooth driver. Signed-off-by: Stefan Eichenberger Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi index 36289c175e6e..ef94f9a57e20 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi @@ -65,6 +65,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt_uart>; status = "okay"; + + bluetooth { + compatible = "mrvl,88w8997"; + max-speed = <921600>; + }; }; /* On-module Wi-Fi */ From 10d900a834da29cf753f1e45f66982e322a177c1 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 15:35:50 +0100 Subject: [PATCH 0147/1040] arm64: dts: sm8150: add the QUPv3 high-speed UART node Add the high-speed UART node to the dtsi for sm8150. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309143551.200694-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index fd20096cfc6e..bfa19414c4be 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1334,6 +1334,20 @@ status = "disabled"; }; + uart9: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a84000 0x0 0x4000>; + reg-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart9_default>; + pinctrl-names = "default"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; @@ -2425,6 +2439,13 @@ bias-disable; }; + qup_uart9_default: qup-uart9-default-state { + pins = "gpio41", "gpio42"; + function = "qup9"; + drive-strength = <2>; + bias-disable; + }; + qup_i2c10_default: qup-i2c10-default-state { pins = "gpio9", "gpio10"; function = "qup10"; From d97ba0b040b1aee7c2a7a7155b7752413a965d1f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 15:35:51 +0100 Subject: [PATCH 0148/1040] arm64: dts: qcom: sa8155p-adp: enable the GNSS high-speed UART Enable the high-speed UART port that's connected to the GNSS controller on the board. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309143551.200694-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 459384ec8f23..339fea522509 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -17,6 +17,7 @@ aliases { serial0 = &uart2; + serial1 = &uart9; }; chosen { @@ -400,6 +401,10 @@ status = "okay"; }; +&uart9 { + status = "okay"; +}; + &ufs_mem_hc { status = "okay"; From 34bb2c1c1bb5d36487c1e7ff00dbf49bb91056e2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 23 Jan 2023 21:26:01 +0100 Subject: [PATCH 0149/1040] soc: qcom: restrict L2 accessors to ARM64 build tests The QCOM_KRYO_L2_ACCESSORS can be compile tested only on ARM64 because it references asm/sysreg.h present only on ARM64. Mark the dependency correct, even though as a non-selectable option it does not have real effect. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230123202601.1296983-1-krzysztof.kozlowski@linaro.org --- drivers/soc/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a8f283086a21..a25df9e3c70e 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -72,7 +72,7 @@ config QCOM_LLCC config QCOM_KRYO_L2_ACCESSORS bool - depends on ARCH_QCOM && ARM64 || COMPILE_TEST + depends on (ARCH_QCOM || COMPILE_TEST) && ARM64 config QCOM_MDT_LOADER tristate From 96ce9227fdbcfe32265ffb2803bfbbfa692cb445 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 28 Jan 2023 11:12:56 +0530 Subject: [PATCH 0150/1040] arm64: dts: qcom: sm6115: Add remoteproc nodes Add the adsp, cdsp and modem remoteproc nodes to sm6115. Signed-off-by: Bhupesh Sharma [bjorn: Extended regs to match #address/size-cells to 2] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230128054256.2100501-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 184 +++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 4d6ec815b78b..e463dd3b0f11 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1322,6 +1322,39 @@ #power-domain-cells = <1>; }; + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,sm6115-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6115_VDDCX>; + + memory-region = <&pil_modem_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 12>; + }; + }; + stm@8002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x08002000 0x0 0x1000>, @@ -1934,6 +1967,157 @@ }; }; + remoteproc_adsp: remoteproc@ab00000 { + compatible = "qcom,sm6115-adsp-pas"; + reg = <0x0 0x0ab00000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6115_VDD_LPI_CX>, + <&rpmpd SM6115_VDD_LPI_MX>; + + memory-region = <&pil_adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x01c3 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x01c4 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x01c5 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x01c6 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x01c7 0x0>; + }; + }; + }; + }; + + remoteproc_cdsp: remoteproc@b300000 { + compatible = "qcom,sm6115-cdsp-pas"; + reg = <0x0 0x0b300000 0x0 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6115_VDDCX>; + + memory-region = <&pil_cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "cdsp"; + qcom,remote-pid = <5>; + mboxes = <&apcs_glb 28>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0c01 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0c02 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0c03 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x0c04 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x0c05 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x0c06 0x0>; + }; + + /* note: secure cb9 in downstream */ + }; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x0c600000 0x0 0x80000>; From 17289c0165bdb61a585e8e937b80defc376dbfde Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 31 Jan 2023 20:00:20 -0500 Subject: [PATCH 0151/1040] arm64: dts: qcom: sdm670: add opps for peripherals The interconnects are now in place. Add Operating Performance Points for them to allow the kernel to properly manage them. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230201010020.84586-3-mailingradian@gmail.com --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 109 +++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 02f14692dd9d..c5f839dd1c6e 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -430,6 +431,10 @@ <&gcc GCC_SDCC1_ICE_CORE_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; clock-names = "iface", "core", "xo", "ice", "bus"; + interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + operating-points-v2 = <&sdhc1_opp_table>; iommus = <&apps_smmu 0x140 0xf>; @@ -442,6 +447,38 @@ non-removable; status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_min_svs>; + opp-peak-kBps = <80000 80000>; + opp-avg-kBps = <52286 80000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <200000 100000>; + opp-avg-kBps = <130718 100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <200000 130000>; + opp-avg-kBps = <130718 130000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <4096000 4096000>; + opp-avg-kBps = <1338562 1338562>; + }; + }; }; gpi_dma0: dma-controller@800000 { @@ -477,6 +514,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c0: i2c@880000 { @@ -490,6 +529,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, <&gpi_dma0 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -507,6 +550,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, <&gpi_dma0 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -524,6 +571,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, <&gpi_dma0 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -541,6 +592,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, <&gpi_dma0 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -558,6 +613,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, <&gpi_dma0 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -575,6 +634,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, <&gpi_dma0 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -592,6 +655,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, <&gpi_dma0 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -609,6 +676,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, + <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, <&gpi_dma0 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -649,6 +720,8 @@ #address-cells = <2>; #size-cells = <2>; ranges; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; + interconnect-names = "qup-core"; status = "disabled"; i2c8: i2c@a80000 { @@ -662,6 +735,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, <&gpi_dma1 1 0 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -679,6 +756,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, <&gpi_dma1 1 1 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -696,6 +777,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, <&gpi_dma1 1 2 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -713,6 +798,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, <&gpi_dma1 1 3 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -730,6 +819,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, <&gpi_dma1 1 4 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -747,6 +840,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, <&gpi_dma1 1 5 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -764,6 +861,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, <&gpi_dma1 1 6 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -781,6 +882,10 @@ #address-cells = <1>; #size-cells = <0>; power-domains = <&rpmhpd SDM670_CX>; + interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, + <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, <&gpi_dma1 1 7 QCOM_GPI_I2C>; dma-names = "tx", "rx"; @@ -1028,6 +1133,10 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; + interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, + <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; + interconnect-names = "usb-ddr", "apps-usb"; + status = "disabled"; usb_1_dwc3: usb@a600000 { From 009d936f15fd3597dbc762595ac8a864b5396611 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:45 +0100 Subject: [PATCH 0152/1040] arm64: dts: qcom: sc8280xp-pmics: add pmk8280 rtc The PMK8280 has an RTC which can also be used as a wakeup source. Note that the RTC can not be disabled and updating the time is not permitted either. Instead an offset can be stored in some other machine- specific non-volatile memory which a driver can take into account. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-20-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index df7d28f7ae60..d2518ffdf7f8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -95,6 +95,15 @@ #thermal-sensor-cells = <1>; status = "disabled"; }; + + pmk8280_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + wakeup-source; + status = "disabled"; + }; }; pmc8280_1: pmic@1 { From d6dbbda37ab5ab83dccf634fe082eb48d81b4899 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:46 +0100 Subject: [PATCH 0153/1040] arm64: dts: qcom: sc8280xp-pmics: add pmk8280 sdam nvram Add one of the PMK8280 SDAM blocks which can be used to store an RTC offset. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-21-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index d2518ffdf7f8..1411edd42b25 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -104,6 +104,15 @@ wakeup-source; status = "disabled"; }; + + pmk8280_sdam_6: nvram@8500 { + compatible = "qcom,spmi-sdam"; + reg = <0x8500 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8500 0x100>; + status = "disabled"; + }; }; pmc8280_1: pmic@1 { From e67b45582c5e2ca829f4bb4c0042f75cdec62b80 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:47 +0100 Subject: [PATCH 0154/1040] arm64: dts: qcom: sc8280xp-crd: enable rtc The SC8280XP CRD firmware does not implement the UEFI time runtime services so the RTC in the PM8280K PMIC needs to be accessed directly. To complicate things further, the RTC control and time registers are read-only on this platform so an offset must be stored in some other machine-specific non-volatile memory which an RTC driver can take into account when reading or updating the time. The UEFI firmware (and Windows) use a UEFI variable for this: 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo but the offset can only be accessed via the Qualcomm UEFI Secure Application residing in the TEE as the firmware does not implement the variable runtime services either. While it is possible to access this UEFI variable from Linux on the CRD, this requires using a fairly complex and reverse-engineered firmware interface. As the only benefit of doing so is to make sure that the UEFI (Windows) and Linux time never gets out of sync, it seems preferable to use the PMIC scratch registers for storing an offset instead. This also avoids flash wear in case of RTC drift, etc. Also note that setting variables using this interface does not work on at least one CRD for reasons not yet known. So instead of using the UEFI RTC offset, reserve four bytes in one of the PMIC SDAM scratch-register blocks to hold the RTC offset. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-22-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 98a0f1f9f01e..d7b537284990 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -563,6 +563,21 @@ status = "okay"; }; +&pmk8280_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmk8280_sdam_6 { + status = "okay"; + + rtc_offset: rtc-offset@bc { + reg = <0xbc 0x4>; + }; +}; + &qup0 { status = "okay"; }; From 5fef1b434aa35e7e34f16bc5cb389d783f5a832f Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:48 +0100 Subject: [PATCH 0155/1040] arm64: dts: qcom: sc8280xp-x13s: enable rtc The Lenovo X13s firmware does not implement the UEFI time runtime services so the RTC in the PM8280K PMIC needs to be accessed directly. To complicate things further, the RTC control and time registers are read-only on this platform so an offset must be stored in some other machine-specific non-volatile memory which an RTC driver can take into account when reading or updating the time. The UEFI firmware (and Windows) use a UEFI variable for this: 882f8c2b-9646-435f-8de5-f208ff80c1bd-RTCInfo but the offset can only be accessed via the Qualcomm UEFI Secure Application residing in the TEE as the firmware does not implement the variable runtime services either. While it is possible to access this UEFI variable from Linux on the X13s, this requires using a fairly complex and reverse-engineered firmware interface. As the only benefit of doing so is to make sure that the UEFI (Windows) and Linux time never gets out of sync, it seems preferable to use the PMIC scratch registers for storing an offset instead. This also avoids flash wear in case of RTC drift, etc. So instead of using the UEFI RTC offset, reserve four bytes in one of the PMIC SDAM scratch-register blocks to hold the RTC offset. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230202155448.6715-23-johan+linaro@kernel.org --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 98e71b933437..9b674686943d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -766,6 +766,21 @@ status = "okay"; }; +&pmk8280_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmk8280_sdam_6 { + status = "okay"; + + rtc_offset: rtc-offset@bc { + reg = <0xbc 0x4>; + }; +}; + &pmk8280_vadc { status = "okay"; From a5b9c5c548bd2c6997581e6a8991cea264cfd657 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Feb 2023 10:13:35 +0100 Subject: [PATCH 0156/1040] dt-bindings: clock: Add Qcom SM6125 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6125 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208091340.124641-6-konrad.dybcio@linaro.org --- .../bindings/clock/qcom,sm6125-gpucc.yaml | 64 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6125-gpucc.h | 31 +++++++++ 2 files changed, 95 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6125-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml new file mode 100644 index 000000000000..374a1844a159 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6125 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks and power domains on + Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6125-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6125-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6125-gpucc.h b/include/dt-bindings/clock/qcom,sm6125-gpucc.h new file mode 100644 index 000000000000..ce5bd920f2c4 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6125-gpucc.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6125_H + +/* Clocks */ +#define GPU_CC_PLL0_OUT_AUX2 0 +#define GPU_CC_PLL1_OUT_AUX2 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GFX3D_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_SLEEP_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_AHB_CLK 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From 94329ce6e38fc420a7cc67b4174c7c8254e1493f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Feb 2023 10:13:37 +0100 Subject: [PATCH 0157/1040] dt-bindings: clock: Add Qcom SM6375 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6375 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208091340.124641-8-konrad.dybcio@linaro.org --- .../bindings/clock/qcom,sm6375-gpucc.yaml | 60 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6375-gpucc.h | 36 +++++++++++ 2 files changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6375-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml new file mode 100644 index 000000000000..b480ead5bd69 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6375 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6375-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@5990000 { + compatible = "qcom,sm6375-gpucc"; + reg = <0 0x05990000 0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6375-gpucc.h b/include/dt-bindings/clock/qcom,sm6375-gpucc.h new file mode 100644 index 000000000000..0887ac03825e --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6375-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_BLAIR_H + +/* GPU CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +/* Resets */ +#define GPU_GX_BCR 0 +#define GPU_ACD_BCR 1 +#define GPU_GX_ACD_MISC_BCR 2 + +#endif From c413f34e7aafbabdab16fd8014ac4c87038dfd08 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Feb 2023 10:13:39 +0100 Subject: [PATCH 0158/1040] dt-bindings: clock: Add Qcom SM6115 GPUCC Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM6115 SoCs. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208091340.124641-10-konrad.dybcio@linaro.org --- .../bindings/clock/qcom,sm6115-gpucc.yaml | 58 +++++++++++++++++++ include/dt-bindings/clock/qcom,sm6115-gpucc.h | 36 ++++++++++++ 2 files changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sm6115-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml new file mode 100644 index 000000000000..cf19f44af774 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SM6115 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h + +properties: + compatible: + enum: + - qcom,sm6115-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 main div source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x05990000 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sm6115-gpucc.h b/include/dt-bindings/clock/qcom,sm6115-gpucc.h new file mode 100644 index 000000000000..945f21a7d745 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm6115-gpucc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM6115_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL0_OUT_AUX2 1 +#define GPU_CC_PLL1 2 +#define GPU_CC_PLL1_OUT_AUX 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CRC_AHB_CLK 5 +#define GPU_CC_CX_GFX3D_CLK 6 +#define GPU_CC_CX_GMU_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_GMU_CLK_SRC 11 +#define GPU_CC_GX_CXO_CLK 12 +#define GPU_CC_GX_GFX3D_CLK 13 +#define GPU_CC_GX_GFX3D_CLK_SRC 14 +#define GPU_CC_SLEEP_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 + +/* Resets */ +#define GPU_GX_BCR 0 + +/* GDSCs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From b5bec0f00ee1c52ff0965a5dba4c91c413a6f3de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Feb 2023 11:15:43 +0100 Subject: [PATCH 0159/1040] dt-bindings: soc: qcom,apr: correct qcom,intents type The qcom,intents property is a list of pairs, thus it should be defined as uint32-matrix. Fixes: b2d7616e13c4 ("dt-bindings: soc: qcom: apr: add missing properties") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208101545.45711-5-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index 6026c21736d8..4502458b0669 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -62,7 +62,14 @@ properties: maxItems: 1 qcom,intents: - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 32 + items: + items: + - description: size of each intent to preallocate + - description: amount of intents to preallocate + minimum: 1 description: List of (size, amount) pairs describing what intents should be preallocated for this virtual channel. This can be used to tweak the From b302c64a3c0a005f39155e9aef5e99ad8a9abbb7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Feb 2023 10:57:51 +0100 Subject: [PATCH 0160/1040] soc: qcom: smem: update max processor count Update max processor count to reflect the number of co-processors on SA8775P SoCs. Signed-off-by: Bartosz Golaszewski Reviewed-by: Eric Chanudet Tested-by: Eric Chanudet Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209095753.447347-2-brgl@bgdev.pl --- drivers/soc/qcom/smem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 25f5925a8d51..6be7ea93c78c 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -85,7 +85,7 @@ #define SMEM_GLOBAL_HOST 0xfffe /* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 15 +#define SMEM_HOST_COUNT 20 /** * struct smem_proc_comm - proc_comm communication struct (legacy) From 26a4bf805c6cd88847dd045f6b29d8a20f02d8df Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Feb 2023 10:57:52 +0100 Subject: [PATCH 0161/1040] dt-bindings: arm: qcom: add the SoC ID for SA8775P Add the SoC ID entry for SA8775P. Signed-off-by: Bartosz Golaszewski Acked-by: Krzysztof Kozlowski Reviewed-by: Eric Chanudet Tested-by: Eric Chanudet Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209095753.447347-3-brgl@bgdev.pl --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index aa95439708dc..c3c078a8c0da 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -229,6 +229,7 @@ #define QCOM_ID_SC7180P 495 #define QCOM_ID_SM6375 507 #define QCOM_ID_SM8550 519 +#define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 #define QCOM_ID_QDU1010 587 From 7fa9c5fc1a753ac593904ebe9c4e8628a4240096 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Feb 2023 10:57:53 +0100 Subject: [PATCH 0162/1040] soc: qcom: socinfo: add support for SA8775P Add SocInfo support for SA8775P. Signed-off-by: Bartosz Golaszewski Reviewed-by: Eric Chanudet Tested-by: Eric Chanudet # sa8775p-ride Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230209095753.447347-4-brgl@bgdev.pl --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index e9012ca1a87b..6929bef72514 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -442,6 +442,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SC7180P) }, { qcom_board_id(SM6375) }, { qcom_board_id(SM8550) }, + { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, { qcom_board_id(QDU1010) }, From 06668b6f7d5b0bdbda30673785d7540c72caae17 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Feb 2023 17:38:43 +0100 Subject: [PATCH 0163/1040] dt-bindings: arm: qcom: add QRD8550 Add board compatible for QRD8550 - a mobile-like development board with SM8550. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210163844.765074-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 1bb24d46e4ee..23c9c9ba5d52 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -913,6 +913,7 @@ properties: - items: - enum: - qcom,sm8550-mtp + - qcom,sm8550-qrd - const: qcom,sm8550 # Board compatibles go above From 112d96fd29272726b2a4bc59d027f76fe1e78af3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Feb 2023 22:55:00 +0100 Subject: [PATCH 0164/1040] soc: qcom: socinfo: Add some PMICs Add some missing PMICs based on the _SUBTYPE defines in include/soc/qcom/qcom-spmi-pmic.h Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213215500.2131511-1-konrad.dybcio@linaro.org --- drivers/soc/qcom/socinfo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 6929bef72514..89081ec34dba 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -109,15 +109,20 @@ static const char *const pmic_models[] = { [32] = "PM8150B", [33] = "PMK8002", [36] = "PM8009", + [37] = "PMI632", [38] = "PM8150C", + [40] = "PM6150", [41] = "SMB2351", + [44] = "PM8008", [45] = "PM6125", + [46] = "PM7250B", [47] = "PMK8350", [48] = "PM8350", [49] = "PM8350C", [50] = "PM8350B", [51] = "PMR735A", [52] = "PMR735B", + [55] = "PM2250", [58] = "PM8450", [65] = "PM8010", }; From 131731c44f2cea44135e93bfb0a2920829910625 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:08 +0100 Subject: [PATCH 0165/1040] ARM: dts: qcom: ipq4018-ap120c-ac: setup serial console Add the required alias and stdout property so that kernel can setup the console based off DTS and not have to set it in the cmdline. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-1-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index a5a6f3ebb274..38efd45433da 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -8,6 +8,14 @@ model = "ALFA Network AP120C-AC"; compatible = "alfa-network,ap120c-ac", "qcom,ipq4018"; + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + keys { compatible = "gpio-keys"; From a7d2715df2845560302aea9d9922b4bfdf4fe09a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:09 +0100 Subject: [PATCH 0166/1040] ARM: dts: qcom: ipq4018-ap120c-ac: align GPIO hog with DT schema Align USB power GPIO hog node to DT schema. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-2-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index 38efd45433da..cd2a32d0d554 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -76,7 +76,7 @@ }; }; - usb-power { + usb-power-hog { line-name = "USB-power"; gpios = <1 GPIO_ACTIVE_HIGH>; gpio-hog; From fabc476a6cff40119365014e84aa2d2bbdf7756a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:10 +0100 Subject: [PATCH 0167/1040] ARM: dts: qcom: ipq4018-ap120c-ac: align SPI-NAND with DT schema SPI-NAND node name should be flash@1 and not nand@1 according to schema. Signed-off-by: Robert Marko Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-3-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index cd2a32d0d554..bb0c888b048e 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -186,7 +186,7 @@ }; }; - nand@1 { + flash@1 { compatible = "spi-nand"; reg = <1>; spi-max-frequency = <40000000>; From d64f94249c689962b895aa650a30c29ac3b41cd3 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:12:11 +0100 Subject: [PATCH 0168/1040] ARM: dts: qcom: ipq4018-ap120c-ac: use NVMEM for ath10k caldata Since ath10k now supports loading the pre-cal via NVMEM instead of having to use userspace scripts, lets use it. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214161211.306462-4-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index bb0c888b048e..d90b4f4c63af 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -170,6 +170,17 @@ label = "ART"; reg = <0x00170000 0x00010000>; read-only; + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; partition@180000 { @@ -233,10 +244,14 @@ &wifi0 { status = "okay"; + nvmem-cell-names = "pre-calibration"; + nvmem-cells = <&precal_art_1000>; }; &wifi1 { status = "okay"; + nvmem-cell-names = "pre-calibration"; + nvmem-cells = <&precal_art_5000>; qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC"; }; From 66e4811ab3967332c52a72f04d615f0faabb145e Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:23:21 +0100 Subject: [PATCH 0169/1040] ARM: dts: qcom: ipq4019: pass XO and sleep clocks to GCC Directly pass XO and sleep clocks to GCC via phandles. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214162325.312057-3-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 02e9ea78405d..6aaa6da5498d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -190,6 +190,8 @@ #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; + clocks = <&xo>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; }; prng: rng@22000 { From 2a41c611f21751150cf4c0132a02828700e58e2d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 14 Feb 2023 17:23:22 +0100 Subject: [PATCH 0170/1040] ARM: dts: qcom: ipq4019: remove clk-output-names for sleep clock Now that sleep clock is being passed directly to GCC, there is no need for global name matching, so remove clk-output-names for sleep clock. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214162325.312057-4-robert.marko@sartura.hr --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 6aaa6da5498d..44beeb90c306 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -143,7 +143,6 @@ sleep_clk: sleep_clk { compatible = "fixed-clock"; clock-frequency = <32000>; - clock-output-names = "gcc_sleep_clk_src"; #clock-cells = <0>; }; From fe8aa1ba078366ba23fc676efab57183b12a3a81 Mon Sep 17 00:00:00 2001 From: Visweswara Tanuku Date: Tue, 14 Feb 2023 21:05:28 -0800 Subject: [PATCH 0171/1040] soc: qcom: geni-se: Update Tx and Rx fifo depth based on QUP HW version From QUP HW Version 3.10 and above the Tx and Rx fifo depth bits are increased to 23:16 bits from 21:16 bits in SE_HW_PARAM registers accomodating 256bytes of fifo depth. Updated geni_se_get_tx_fifo_depth and geni_se_get_rx_fifo_depth to retrieve right fifo depth based on QUP HW version. Signed-off-by: Visweswara Tanuku Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215050528.9507-1-quic_vtanuku@quicinc.com --- include/linux/soc/qcom/geni-se.h | 42 +++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 400213daa461..c55a0bc8cb0e 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -245,12 +245,22 @@ struct geni_se { /* SE_HW_PARAM_0 fields */ #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) #define TX_FIFO_WIDTH_SHFT 24 +/* + * For QUP HW Version >= 3.10 Tx fifo depth support is increased + * to 256bytes and corresponding bits are 16 to 23 + */ +#define TX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) #define TX_FIFO_DEPTH_MSK GENMASK(21, 16) #define TX_FIFO_DEPTH_SHFT 16 /* SE_HW_PARAM_1 fields */ #define RX_FIFO_WIDTH_MSK GENMASK(29, 24) #define RX_FIFO_WIDTH_SHFT 24 +/* + * For QUP HW Version >= 3.10 Rx fifo depth support is increased + * to 256bytes and corresponding bits are 16 to 23 + */ +#define RX_FIFO_DEPTH_MSK_256_BYTES GENMASK(23, 16) #define RX_FIFO_DEPTH_MSK GENMASK(21, 16) #define RX_FIFO_DEPTH_SHFT 16 @@ -391,7 +401,8 @@ static inline void geni_se_abort_s_cmd(struct geni_se *se) /** * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine - * @se: Pointer to the concerned serial engine. + * based on QUP HW version + * @se: Pointer to the concerned serial engine. * * This function is used to get the depth i.e. number of elements in the * TX fifo of the serial engine. @@ -400,11 +411,20 @@ static inline void geni_se_abort_s_cmd(struct geni_se *se) */ static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se) { - u32 val; + u32 val, hw_version, hw_major, hw_minor, tx_fifo_depth_mask; + + hw_version = geni_se_get_qup_hw_version(se); + hw_major = GENI_SE_VERSION_MAJOR(hw_version); + hw_minor = GENI_SE_VERSION_MINOR(hw_version); + + if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) + tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK_256_BYTES; + else + tx_fifo_depth_mask = TX_FIFO_DEPTH_MSK; val = readl_relaxed(se->base + SE_HW_PARAM_0); - return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT; + return (val & tx_fifo_depth_mask) >> TX_FIFO_DEPTH_SHFT; } /** @@ -427,7 +447,8 @@ static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) /** * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine - * @se: Pointer to the concerned serial engine. + * based on QUP HW version + * @se: Pointer to the concerned serial engine. * * This function is used to get the depth i.e. number of elements in the * RX fifo of the serial engine. @@ -436,11 +457,20 @@ static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se) */ static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se) { - u32 val; + u32 val, hw_version, hw_major, hw_minor, rx_fifo_depth_mask; + + hw_version = geni_se_get_qup_hw_version(se); + hw_major = GENI_SE_VERSION_MAJOR(hw_version); + hw_minor = GENI_SE_VERSION_MINOR(hw_version); + + if ((hw_major == 3 && hw_minor >= 10) || hw_major > 3) + rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK_256_BYTES; + else + rx_fifo_depth_mask = RX_FIFO_DEPTH_MSK; val = readl_relaxed(se->base + SE_HW_PARAM_1); - return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT; + return (val & rx_fifo_depth_mask) >> RX_FIFO_DEPTH_SHFT; } void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr); From b9745c275246a7e43c34d1b3be5ff9a9f3cf9305 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 20 Feb 2023 13:08:31 +0100 Subject: [PATCH 0172/1040] ARM: dts: qcom-apq8064: Fix opp table child name The opp-320000000 name is rather misleading with the opp-hz value of 450 MHz. Fix it! Fixes: 8db0b6c7b636 ("ARM: dts: qcom: apq8064: Convert adreno from legacy gpu-pwrlevels to opp-v2") Signed-off-by: Konrad Dybcio Reviewed-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230220120831.1591820-1-konrad.dybcio@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 92aa2b081901..3aeac0cabb28 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1260,7 +1260,7 @@ gpu_opp_table: opp-table { compatible = "operating-points-v2"; - opp-320000000 { + opp-450000000 { opp-hz = /bits/ 64 <450000000>; }; From cc3cb392cd4b4299ad52860831d66e523ba5a51f Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Wed, 15 Feb 2023 10:41:17 +0800 Subject: [PATCH 0173/1040] arm64: dts: imx93: Add the bbnsm dts node Add the bbnsm node for RTC & ON/OFF button support Signed-off-by: Jacky Bai Tested-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 2076f9c9983a..e772c136e895 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -243,6 +243,22 @@ status = "okay"; }; + bbnsm: bbnsm@44440000 { + compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; + reg = <0x44440000 0x10000>; + + bbnsm_rtc: rtc { + compatible = "nxp,imx93-bbnsm-rtc"; + interrupts = ; + }; + + bbnsm_pwrkey: pwrkey { + compatible = "nxp,imx93-bbnsm-pwrkey"; + interrupts = ; + linux,code = ; + }; + }; + clk: clock-controller@44450000 { compatible = "fsl,imx93-ccm"; reg = <0x44450000 0x10000>; From 6eabc54cdf323a87da68aef511b402daf0f6d8d4 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 15 Feb 2023 14:18:33 +0800 Subject: [PATCH 0174/1040] arm64: dts: Add i.MX8MM PCIe EP support Add i.MX8MM PCIe EP support. Signed-off-by: Richard Zhu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 31f4548f85cf..a9552867e547 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1315,6 +1315,30 @@ status = "disabled"; }; + pcie0_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x400000>, + <0x18000000 0x8000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gpu_3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; From 1601bb4538c6e04f52a00ba249250cde8a396aec Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 15 Feb 2023 14:18:34 +0800 Subject: [PATCH 0175/1040] arm64: dts: Add i.MX8MQ PCIe EP support Add i.MX8MQ PCIe EP support. Signed-off-by: Richard Zhu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 98fbba4c99a9..9f950a6ac6c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1605,6 +1605,38 @@ status = "disabled"; }; + pcie1_ep: pcie-ep@33c00000 { + compatible = "fsl,imx8mq-pcie-ep"; + reg = <0x33c00000 0x000400000>, + <0x20000000 0x08000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ From 23f59eb178b78fe2609e4dd0a2901a263b93ce3e Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Wed, 15 Feb 2023 14:18:35 +0800 Subject: [PATCH 0176/1040] arm64: dts: Add i.MX8MP PCIe EP support Add i.MX8MP PCIe EP support. Signed-off-by: Richard Zhu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a19224fe1a6a..2f84b8b0118e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1309,6 +1309,32 @@ status = "disabled"; }; + pcie_ep: pcie-ep@33800000 { + compatible = "fsl,imx8mp-pcie-ep"; + reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; + reg-names = "dbi", "addr_space"; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "pcie", "pcie_bus", "pcie_aux"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-rates = <10000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <3>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; From e752a4f9589cd8444a5ec6baa2d096cc4164c508 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 16 Feb 2023 01:32:26 +0200 Subject: [PATCH 0177/1040] arm64: dts: freescale: imx8mm-phyboard: Add I2C4 pinmuxing The I2C4 bus is exposed on the camera connector. Add and select the corresponding pinmux entries and set the default frequency. The device is left disabled, to be enabled from camera overlays. Signed-off-by: Laurent Pinchart Acked-by: Teresa Remmet Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-phyboard-polis-rdk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 266129b4a70d..03e7679217b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -168,6 +168,12 @@ "", "ECSPI1_SS0"; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; +}; + /* PCIe */ &pcie0 { assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, @@ -333,6 +339,13 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 + >; + }; + pinctrl_leds: leds1grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 From 2a136ee0efdd4d50b1fb6810d1cb942dcecaf16a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Feb 2023 20:24:44 +0100 Subject: [PATCH 0178/1040] arm64: dts: imx8mp: Add PCIe support to DH electronics i.MX8M Plus DHCOM and PDK2 Add PCIe support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index 382fbedaf6ba..fdf18b7f208d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -151,6 +151,20 @@ status = "okay"; }; +&pcie_phy { + clock-names = "ref"; + clocks = <&clk IMX8MP_SYS_PLL2_100M>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pcie { + fsl,max-link-speed = <1>; + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; /* GPIO J */ + status = "okay"; +}; + &usb3_1 { fsl,over-current-active-low; }; From 3e431f255dc8c9c571b62490d4f6ddc2ec47bdb1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Feb 2023 20:25:45 +0100 Subject: [PATCH 0179/1040] arm64: dts: imx8mp: Update GPIO M to CLKOUT1 on DH electronics i.MX8M Plus DHCOM and PDK2 The GPIO M SoM pin is connected to CLKOUT1, while CLKOUT2 is used as a supply for TC9595 bridge chip clock. Update the comment. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index fdf18b7f208d..b657ac6adddb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -173,7 +173,7 @@ /* * GPIO_A,B,C,D are connected to buttons. * GPIO_E,F,H,I are connected to LEDs. - * GPIO_M is connected to CLKOUT2. + * GPIO_M is connected to CLKOUT1. */ pinctrl-0 = <&pinctrl_hog_base &pinctrl_dhcom_g &pinctrl_dhcom_j diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 9cdd4234c4ca..cc8e086ff7b6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -547,7 +547,7 @@ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l - /* GPIO_M is connected to CLKOUT2 */ + /* GPIO_M is connected to CLKOUT1 */ &pinctrl_dhcom_int>; pinctrl-names = "default"; From 5a649aa9fb73c88765890b84cb265f6caba8a403 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Feb 2023 20:26:43 +0100 Subject: [PATCH 0180/1040] arm64: dts: imx8mp: Do not delete PHY nodes on i.MX8MP DHCOM PDK2 The PHY nodes may be activated via DTO in case another SoM variant is populated into the development kit. Do not delete the nodes. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index b657ac6adddb..1cbf49ec138b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -104,18 +104,6 @@ }; }; -/* - * PDK2 carrier board uses SoM with KSZ9131 populated and connected to - * SoM EQoS ethernet RGMII interface. Remove the other SoM PHY DT node. - */ -/delete-node/ ðphy0f; - -/* - * PDK2 carrier board has KSZ9021 PHY populated and connected to SoM FEC - * ethernet RGMII interface. The SoM is not populated with second FEC PHY. - */ -/delete-node/ ðphy1f; - &fec { /* Second ethernet */ phy-handle = <ðphypdk>; From 6ef0184237ad21b1a2e6b5436cd651def239eb5e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Feb 2023 20:26:44 +0100 Subject: [PATCH 0181/1040] arm64: dts: imx8mp: Adjust EQoS reset comment on i.MX8MP DHCOM Fix copy-paste error in the EQoS reset comment, align with SoM schematic. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index cc8e086ff7b6..1471a17045f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -700,9 +700,9 @@ pinctrl_ethphy0: dhcom-ethphy0-grp { fsl,pins = < - /* ENET1_#RST Reset */ + /* ENET_QOS_#RST Reset */ MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 - /* ENET1_#INT Interrupt */ + /* ENET_QOS_#INT Interrupt */ MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 >; }; From 15a03a2225af52da1f3e152593740f1a78b9dd62 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Feb 2023 20:26:45 +0100 Subject: [PATCH 0182/1040] arm64: dts: imx8mp: Adjust EQoS PHY address on i.MX8MP DHCOM The current variant of the SoM has LAN8740Ai PHY connected to EQoS strapped to MDIO address 0 , adjust the MDIO address to match the hardware. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index 1471a17045f7..d34020e83bbd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -94,14 +94,14 @@ #size-cells = <0>; /* Up to one of these two PHYs may be populated. */ - ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ + ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */ compatible = "ethernet-phy-id0007.c110", "ethernet-phy-ieee802.3-c22"; interrupt-parent = <&gpio3>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; pinctrl-0 = <&pinctrl_ethphy0>; pinctrl-names = "default"; - reg = <1>; + reg = <0>; reset-assert-us = <1000>; reset-deassert-us = <1000>; reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; From f4662e0cee6cbe338261646343f94d2c0137d0cf Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Feb 2023 20:26:46 +0100 Subject: [PATCH 0183/1040] arm64: dts: imx8mp: Add EQoS RMII pin mux on i.MX8MP DHCOM The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin mux settings for both options, so that DT overlay can override these settings on SoM variant with the LAN8740Ai PHY. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index d34020e83bbd..cd285df84d31 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -83,7 +83,7 @@ &eqos { /* First ethernet */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; + pinctrl-0 = <&pinctrl_eqos_rgmii>; phy-handle = <ðphy0g>; phy-mode = "rgmii-id"; status = "okay"; @@ -673,7 +673,7 @@ >; }; - pinctrl_eqos: dhcom-eqos-grp { /* RGMII */ + pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */ fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 @@ -692,6 +692,22 @@ >; }; + pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */ + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x1f + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + /* Clock */ + MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f + >; + }; + pinctrl_enet_vio: dhcom-enet-vio-grp { fsl,pins = < MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 From 3d274f8bb7184c18ad6e9b2c54fb059c5f9086a2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Feb 2023 20:26:47 +0100 Subject: [PATCH 0184/1040] arm64: dts: imx8mp: Add FEC RMII pin mux on i.MX8MP DHCOM The i.MX8MP DHCOM SoM may come with either external RGMII PHY or LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux settings for both options, so that DT overlay can override these settings on SoM variant with the LAN8740Ai PHY. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-dhcom-pdk2.dts | 2 ++ .../boot/dts/freescale/imx8mp-dhcom-som.dtsi | 22 ++++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index 1cbf49ec138b..92df6c1277c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -105,7 +105,9 @@ }; &fec { /* Second ethernet */ + pinctrl-0 = <&pinctrl_fec_rgmii>; phy-handle = <ðphypdk>; + phy-mode = "rgmii"; mdio { ethphypdk: ethernet-phy@7 { /* KSZ 9021 */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index cd285df84d31..7e804f650784 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -129,9 +129,9 @@ &fec { /* Second ethernet */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; + pinctrl-0 = <&pinctrl_fec_rmii>; phy-handle = <ðphy1f>; - phy-mode = "rgmii"; + phy-mode = "rmii"; fsl,magic-packet; status = "okay"; @@ -732,7 +732,7 @@ >; }; - pinctrl_fec: dhcom-fec-grp { + pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */ fsl,pins = < MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x1f MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 @@ -753,6 +753,22 @@ >; }; + pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */ + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + /* Clock */ + MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x4000001f + >; + }; + pinctrl_flexcan1: dhcom-flexcan1-grp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 From 578e75d14d220b9efdff981b42a63b7c50fa52cc Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Tue, 21 Feb 2023 09:04:08 +0100 Subject: [PATCH 0185/1040] arm64: dts: imx8mq: Add UART DMA support UART ports have DMA capability. Describe the UART DMA properties. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9f950a6ac6c9..cd925c0ac911 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -940,6 +940,8 @@ clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, <&clk IMX8MQ_CLK_UART1_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -951,6 +953,8 @@ clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, <&clk IMX8MQ_CLK_UART3_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -962,6 +966,8 @@ clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, <&clk IMX8MQ_CLK_UART2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1157,6 +1163,8 @@ clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, <&clk IMX8MQ_CLK_UART4_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; From 9628655b1407d810c6b51ad0fba81cc31d0bdb76 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 27 Feb 2023 14:50:21 +1000 Subject: [PATCH 0186/1040] ARM: dts: imx7d-remarkable2: Enable the cyttsp5 Add support for the cyttsp5 touchscreen controller for the reMarkable 2. Signed-off-by: Alistair Francis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-remarkable2.dts | 97 +++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts index 8b2f11e85e05..288fc8611117 100644 --- a/arch/arm/boot/dts/imx7d-remarkable2.dts +++ b/arch/arm/boot/dts/imx7d-remarkable2.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "imx7d.dtsi" +#include / { model = "reMarkable 2.0"; @@ -69,6 +70,17 @@ startup-delay-us = <100000>; /* 100 ms */ }; + reg_touch: regulator-touch { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_TOUCH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_reg>; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -106,6 +118,68 @@ }; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreen@24 { + compatible = "cypress,tt21000"; + reg = <0x24>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + vdd-supply = <®_touch>; + touchscreen-size-x = <880>; + touchscreen-size-y = <1280>; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + reg = <0>; + linux,keycodes = ; + }; + + button@1 { + reg = <1>; + linux,keycodes = ; + }; + + button@2 { + reg = <2>; + linux,keycodes = ; + }; + + button@3 { + reg = <3>; + linux,keycodes = ; + }; + + button@4 { + reg = <4>; + linux,keycodes = ; + }; + + button@5 { + reg = <5>; + linux,keycodes = ; + }; + + button@6 { + reg = <6>; + linux,keycodes = ; + }; + + button@7 { + reg = <7>; + linux,keycodes = ; + }; + }; +}; + &i2c4 { clock-frequency = <100000>; pinctrl-names = "default", "sleep"; @@ -232,6 +306,15 @@ >; }; + pinctrl_touch: touchgrp { + fsl,pins = < + /* CYTTSP interrupt */ + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x54 + /* CYTTSP reset */ + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x04 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f @@ -239,6 +322,13 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f @@ -246,6 +336,13 @@ >; }; + pinctrl_touch_reg: touchreggrp { + fsl,pins = < + /* TOUCH_PWR_EN */ + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x14 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 From 615e841dc791aa90111c732cc790221dabe4832d Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 27 Feb 2023 14:50:23 +1000 Subject: [PATCH 0187/1040] ARM: dts: imx7d-remarkable2: Enable the rohm,bd71815 Add support for the rohm,bd71815 power controller controller for the reMarkable 2. Signed-off-by: Alistair Francis Reviewed-by: Matti Vaittinen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-remarkable2.dts | 142 ++++++++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm/boot/dts/imx7d-remarkable2.dts b/arch/arm/boot/dts/imx7d-remarkable2.dts index 288fc8611117..dc954e4f63e0 100644 --- a/arch/arm/boot/dts/imx7d-remarkable2.dts +++ b/arch/arm/boot/dts/imx7d-remarkable2.dts @@ -91,6 +91,10 @@ }; }; +&cpu0 { + cpu-supply = <&buck1>; +}; + &clks { assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>, <&clks IMX7D_CLKO2_ROOT_DIV>; @@ -118,6 +122,131 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + bd71815: pmic@4b { + compatible = "rohm,bd71815"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bd71815>; + interrupt-parent = <&gpio6>; /* PMIC_INT_B GPIO6_IO16 */ + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + clocks = <&clks IMX7D_CLKO2_ROOT_SRC>; + clock-output-names = "bd71815-32k-out"; + #clock-cells = <0>; + #gpio-cells = <2>; + + regulators { + buck1: buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2: buck2 { + regulator-name = "buck2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3: buck3 { + regulator-name = "buck3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2700000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4: buck4 { + regulator-name = "buck4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: buck5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6: ldodvref { + regulator-name = "ldodvref"; + regulator-boot-on; + regulator-always-on; + }; + + ldo7: ldolpsr { + regulator-name = "ldolpsr"; + regulator-boot-on; + regulator-always-on; + }; + + boost: wled { + regulator-name = "wled"; + regulator-min-microamp = <10>; + regulator-max-microamp = <25000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -292,6 +421,12 @@ }; &iomuxc { + pinctrl_bd71815: bd71815grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x59 + >; + }; + pinctrl_brcm_reg: brcmreggrp { fsl,pins = < /* WIFI_PWR_EN */ @@ -322,6 +457,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f From 9159025bea6e5f53ab85ab846c9d6cd28e505a8c Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 27 Feb 2023 14:50:22 +1000 Subject: [PATCH 0188/1040] ARM: imx_v6_v7_defconfig: Enable rohm,bd71815 The reMarkable 2 uses the rohm,bd71815 power controller, so enable it in the defconfig. Signed-off-by: Alistair Francis Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 6dc6fed12af8..02ccc86a8d4a 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -213,6 +213,7 @@ CONFIG_GPIO_SIOX=m CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCF857X=y +CONFIG_GPIO_BD71815=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_74X164=y CONFIG_POWER_RESET=y @@ -242,8 +243,10 @@ CONFIG_MFD_MC13XXX_I2C=y CONFIG_MFD_SY7636A=y CONFIG_MFD_RN5T618=y CONFIG_MFD_STMPE=y +CONFIG_MFD_ROHM_BD71828=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_BD71815=y CONFIG_REGULATOR_DA9052=y CONFIG_REGULATOR_DA9062=y CONFIG_REGULATOR_DA9063=y @@ -380,6 +383,7 @@ CONFIG_RTC_DRV_ISL1208=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_M41T80=y +CONFIG_RTC_DRV_BD70528=y CONFIG_RTC_DRV_RC5T619=y CONFIG_RTC_DRV_RV3029C2=y CONFIG_RTC_DRV_DA9063=y @@ -396,6 +400,7 @@ CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_IMX_MEDIA=y CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_BD718XX=y CONFIG_CLK_IMX8MM=y CONFIG_CLK_IMX8MN=y CONFIG_CLK_IMX8MP=y From 0d2c843ce5adbe98998844613eb8a8e1127616fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2023 16:54:19 +0100 Subject: [PATCH 0189/1040] dt-bindings: soc: imx8mp-media-blk-ctrl: Align block controller example name Align the block controller example node name with Linux imx8mp.dtsi . No functional change. Acked-by: Krzysztof Kozlowski Reviewed-by: Alexander Stein Reviewed-by: Liu Ying Tested-by: Alexander Stein Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml index dadb6108e321..a0f7c73510d0 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml @@ -94,7 +94,7 @@ examples: #include #include - media_blk_ctl: blk-ctl@32ec0000 { + blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", "syscon"; reg = <0x32ec0000 0x138>; power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>, From 1cb0c87d27dcc54537233b1810349889a214494e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2023 16:54:20 +0100 Subject: [PATCH 0190/1040] dt-bindings: soc: imx8mp-media-blk-ctrl: Add LDB subnode into schema and example Document the LDB bridge subnode and add the subnode into the example. For the subnode to work, the block control must scan its subnodes and bind drivers to them, do not misuse either simple-bus or simple-mfd here. Acked-by: Alexander Stein Reviewed-by: Krzysztof Kozlowski Reviewed-by: Liu Ying Tested-by: Alexander Stein Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml index a0f7c73510d0..ea9aa876ed13 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml @@ -23,6 +23,12 @@ properties: reg: maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#power-domain-cells': const: 1 @@ -78,9 +84,16 @@ properties: - const: isp1 - const: dwe + bridge@5c: + type: object + $ref: /schemas/display/bridge/fsl,ldb.yaml# + unevaluatedProperties: false + required: - compatible - reg + - '#address-cells' + - '#size-cells' - '#power-domain-cells' - power-domains - power-domain-names @@ -114,5 +127,43 @@ examples: clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2", "isp", "phy"; #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + + bridge@5c { + compatible = "fsl,imx8mp-ldb"; + reg = <0x5c 0x4>, <0x128 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + clock-names = "ldb"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ldb_from_lcdif2: endpoint { + remote-endpoint = <&lcdif2_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + remote-endpoint = <&ldb_to_lvdsx4panel>; + }; + }; + + port@2 { + reg = <2>; + + ldb_lvds_ch1: endpoint { + }; + }; + }; + }; }; ... From 9cb6d1b39a8f5086bbebb01357ba1e4ada2169e5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2023 16:54:21 +0100 Subject: [PATCH 0191/1040] soc: imx: imx8m-blk-ctrl: Scan subnodes and bind drivers to them This particular block can have DT subnodes describing the LVDS LDB bridge. Instead of misusing simple-bus to scan for those nodes, do the scan within the driver. Tested-by: Alexander Stein Signed-off-by: Marek Vasut Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 399cb85105a1..8bee7280303c 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -310,6 +310,10 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev) dev_set_drvdata(dev, bc); + ret = devm_of_platform_populate(dev); + if (ret) + goto cleanup_provider; + return 0; cleanup_provider: From 5a51e1f2b083423f75145c512ee284862ab33854 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2023 16:54:22 +0100 Subject: [PATCH 0192/1040] arm64: dts: imx8mp: Drop simple-bus from fsl,imx8mp-media-blk-ctrl This block should not be compatible with simple-bus and misuse it that way. Instead, the driver should scan its subnodes and bind drivers to them. Reviewed-by: Alexander Stein Reviewed-by: Liu Ying Tested-by: Alexander Stein Fixes: 94e6197dadc9 ("arm64: dts: imx8mp: Add LCDIF2 & LDB nodes") Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 2f84b8b0118e..d4886141bd9d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1151,7 +1151,7 @@ media_blk_ctrl: blk-ctrl@32ec0000 { compatible = "fsl,imx8mp-media-blk-ctrl", - "simple-bus", "syscon"; + "syscon"; reg = <0x32ec0000 0x10000>; #address-cells = <1>; #size-cells = <1>; From e7567840ecd323425e7bd1e97f1945bf811fecdc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2023 16:54:23 +0100 Subject: [PATCH 0193/1040] arm64: dts: imx8mp: Reorder clock and reg properties Align the clock and reg properties order with example bindings and the rest of the imx8mp.dtsi . No functional change. Signed-off-by: Marek Vasut Reviewed-by: Lucas Stach Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index d4886141bd9d..1b6757148516 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1202,10 +1202,10 @@ lvds_bridge: bridge@5c { compatible = "fsl,imx8mp-ldb"; - clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; - clock-names = "ldb"; reg = <0x5c 0x4>, <0x128 0x4>; reg-names = "ldb", "lvds"; + clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; + clock-names = "ldb"; assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; status = "disabled"; From 09220adf9c337544bc7404ae666a8c5a2c5ca862 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 28 Feb 2023 10:17:57 +0100 Subject: [PATCH 0194/1040] arm64: dts: imx93: Add FlexSPI support Add FlexSPI node for i.MX93. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index e772c136e895..84f7de0608de 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -450,6 +450,21 @@ status = "disabled"; }; + flexspi1: spi@425e0000 { + compatible = "nxp,imx8mm-fspi"; + reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, + <&clk IMX93_CLK_FLEXSPI1_GATE>; + clock-names = "fspi_en", "fspi"; + assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; + status = "disabled"; + }; + lpuart7: serial@42690000 { compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42690000 0x1000>; From edac60e149714cc05c32b49472740988c197543d Mon Sep 17 00:00:00 2001 From: Jindong Yue Date: Wed, 1 Mar 2023 21:05:51 +0800 Subject: [PATCH 0195/1040] soc: imx: imx8mp-blk-ctrl: Use dev_pm_domain_attach_by_name The genpd_dev_pm_attach_by_name() is not exported, following error occurs when building imx8mp-blk-ctrl as a module: ERROR: modpost: "genpd_dev_pm_attach_by_name" [drivers/soc/imx/imx8mp-blk-ctrl.ko] undefined! Fix this by using dev_pm_domain_attach_by_name() instead. Signed-off-by: Jindong Yue Reviewed-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8mp-blk-ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index a0592db8fa86..1892c2c78831 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -642,7 +642,7 @@ static int imx8mp_blk_ctrl_probe(struct platform_device *pdev) if (!bc->onecell_data.domains) return -ENOMEM; - bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); + bc->bus_power_dev = dev_pm_domain_attach_by_name(dev, "bus"); if (IS_ERR(bc->bus_power_dev)) return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), "failed to attach bus power domain\n"); From d77369ad8cb10bedd244e6dfd8414ebdd8594ba6 Mon Sep 17 00:00:00 2001 From: Jindong Yue Date: Wed, 1 Mar 2023 21:05:52 +0800 Subject: [PATCH 0196/1040] soc: imx: imx8mp-blk-ctrl: Fix typo of imx8m_blk_ctrl_of_match MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Once set CONFIG_SOC_IMX8M as m, following error occurs: drivers/soc/imx/imx8mp-blk-ctrl.c:747:25: error: ‘imx8m_blk_ctrl_of_match’ undeclared here (not in a function); did you mean ‘imx8mp_blk_ctrl_of_match’? 747 | MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match); | ^~~~~~~~~~~~~~~~~~~~~~~ Fix the typo. Signed-off-by: Jindong Yue Reviewed-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8mp-blk-ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index 1892c2c78831..f109c7bd6658 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -852,7 +852,7 @@ static const struct of_device_id imx8mp_blk_ctrl_of_match[] = { /* Sentinel */ } }; -MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match); +MODULE_DEVICE_TABLE(of, imx8mp_blk_ctrl_of_match); static struct platform_driver imx8mp_blk_ctrl_driver = { .probe = imx8mp_blk_ctrl_probe, From 56c017f64d76e3c7fd525014f811349092e1c022 Mon Sep 17 00:00:00 2001 From: Jindong Yue Date: Wed, 1 Mar 2023 21:05:53 +0800 Subject: [PATCH 0197/1040] soc: imx: imx8mp-blk-ctrl: Add MODULE_LICENSE Add MODULE_LICENSE to support building as a module. Signed-off-by: Jindong Yue Reviewed-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8mp-blk-ctrl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index f109c7bd6658..870aecc0202a 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -864,3 +864,4 @@ static struct platform_driver imx8mp_blk_ctrl_driver = { }, }; module_platform_driver(imx8mp_blk_ctrl_driver); +MODULE_LICENSE("GPL"); From 31ef51a4ae5e6e6745aae119a2836d7386652a2b Mon Sep 17 00:00:00 2001 From: Jindong Yue Date: Wed, 1 Mar 2023 21:05:54 +0800 Subject: [PATCH 0198/1040] soc: imx: imx8m-blk-ctrl: Use dev_pm_domain_attach_by_name The genpd_dev_pm_attach_by_name() is not exported, following error occurs when building imx8m-blk-ctrl as a module: ERROR: modpost: "genpd_dev_pm_attach_by_name" [drivers/soc/imx/imx8m-blk-ctrl.ko] undefined! Fix this by using dev_pm_domain_attach_by_name() instead. Signed-off-by: Jindong Yue Reviewed-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 8bee7280303c..c8cf57337bbe 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -210,7 +210,7 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev) if (!bc->onecell_data.domains) return -ENOMEM; - bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); + bc->bus_power_dev = dev_pm_domain_attach_by_name(dev, "bus"); if (IS_ERR(bc->bus_power_dev)) { if (PTR_ERR(bc->bus_power_dev) == -ENODEV) return dev_err_probe(dev, -EPROBE_DEFER, From 78710a72dc08da4cb2f65707acf4943e2b14c2e1 Mon Sep 17 00:00:00 2001 From: Jindong Yue Date: Wed, 1 Mar 2023 21:05:55 +0800 Subject: [PATCH 0199/1040] soc: imx: imx8m-blk-ctrl: Add MODULE_LICENSE Add MODULE_LICENSE to support building as a module. Signed-off-by: Jindong Yue Reviewed-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index c8cf57337bbe..9129c97b7a01 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -895,3 +895,4 @@ static struct platform_driver imx8m_blk_ctrl_driver = { }, }; module_platform_driver(imx8m_blk_ctrl_driver); +MODULE_LICENSE("GPL"); From 280fe269059f8d3c127dd4c1ce24297d8e20d1e2 Mon Sep 17 00:00:00 2001 From: Jindong Yue Date: Wed, 1 Mar 2023 21:05:56 +0800 Subject: [PATCH 0200/1040] soc: imx8m: Add MODULE_LICENSE Add MODULE_LICENSE to support building as module. Signed-off-by: Jindong Yue Reviewed-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/soc-imx8m.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/imx/soc-imx8m.c b/drivers/soc/imx/soc-imx8m.c index 32ed9dc88e45..1dcd243df567 100644 --- a/drivers/soc/imx/soc-imx8m.c +++ b/drivers/soc/imx/soc-imx8m.c @@ -242,3 +242,4 @@ free_soc: return ret; } device_initcall(imx8_soc_init); +MODULE_LICENSE("GPL"); From 8191455c38dd009f15e2fa9ce6c2e3cd337918a0 Mon Sep 17 00:00:00 2001 From: Jindong Yue Date: Wed, 1 Mar 2023 21:05:57 +0800 Subject: [PATCH 0201/1040] soc: imx8m: Support building imx8m soc driver as module Make the imx8m soc driver as tristate so that it can be built as loadable module, module names are: soc-imx8m.ko, imx8m-blk-ctrl.ko and imx8mp-blk-ctrl.ko Signed-off-by: Jindong Yue Reviewed-by: Peng Fan Reviewed-by: Marco Felsch Signed-off-by: Shawn Guo --- drivers/soc/imx/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index a8742fc58f01..76a4593baf0a 100644 --- a/drivers/soc/imx/Kconfig +++ b/drivers/soc/imx/Kconfig @@ -10,7 +10,7 @@ config IMX_GPCV2_PM_DOMAINS default y if SOC_IMX7D config SOC_IMX8M - bool "i.MX8M SoC family support" + tristate "i.MX8M SoC family support" depends on ARCH_MXC || COMPILE_TEST default ARCH_MXC && ARM64 select SOC_BUS From 75a21ed9d0a959c979c5300950bf60dfca20b90e Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:39:59 +0100 Subject: [PATCH 0202/1040] ARM: dts: imx28-apf28: Convert to use label references These Armadeus board files still use node name and unit address to reference parts from the imx28.dtsi . This causes a lot of redundancy. So use label references in order to make it easier to maintain. Signed-off-by: Stefan Wahren Cc: Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-apf28.dts | 106 +++++---- arch/arm/boot/dts/imx28-apf28dev.dts | 312 +++++++++++++-------------- 2 files changed, 201 insertions(+), 217 deletions(-) diff --git a/arch/arm/boot/dts/imx28-apf28.dts b/arch/arm/boot/dts/imx28-apf28.dts index 14a92fe59770..98672932e41b 100644 --- a/arch/arm/boot/dts/imx28-apf28.dts +++ b/arch/arm/boot/dts/imx28-apf28.dts @@ -14,67 +14,59 @@ device_type = "memory"; reg = <0x40000000 0x08000000>; }; +}; - apb@80000000 { - apbh@80000000 { - nand-controller@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; - partition@0 { - label = "u-boot"; - reg = <0x0 0x300000>; - }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; - partition@300000 { - label = "env"; - reg = <0x300000 0x80000>; - }; - - partition@380000 { - label = "env2"; - reg = <0x380000 0x80000>; - }; - - partition@400000 { - label = "dtb"; - reg = <0x400000 0x80000>; - }; - - partition@480000 { - label = "splash"; - reg = <0x480000 0x80000>; - }; - - partition@500000 { - label = "kernel"; - reg = <0x500000 0x800000>; - }; - - partition@d00000 { - label = "rootfs"; - reg = <0xd00000 0xf300000>; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; + partition@0 { + label = "u-boot"; + reg = <0x0 0x300000>; }; - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - status = "okay"; - }; + partition@300000 { + label = "env"; + reg = <0x300000 0x80000>; + }; + + partition@380000 { + label = "env2"; + reg = <0x380000 0x80000>; + }; + + partition@400000 { + label = "dtb"; + reg = <0x400000 0x80000>; + }; + + partition@480000 { + label = "splash"; + reg = <0x480000 0x80000>; + }; + + partition@500000 { + label = "kernel"; + reg = <0x500000 0x800000>; + }; + + partition@d00000 { + label = "rootfs"; + reg = <0xd00000 0xf300000>; }; }; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 1b253b47006c..4704b6141836 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -10,166 +10,6 @@ model = "Armadeus Systems APF28Dev docking/development board"; compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_apf28dev>; - - hog_pins_apf28dev: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D16__GPIO_1_16 - MX28_PAD_LCD_D17__GPIO_1_17 - MX28_PAD_LCD_D18__GPIO_1_18 - MX28_PAD_LCD_D19__GPIO_1_19 - MX28_PAD_LCD_D20__GPIO_1_20 - MX28_PAD_LCD_D21__GPIO_1_21 - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apf28dev: lcdif-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_apf28dev: otg-apf28dev@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_16bit_pins_a - &lcdif_pins_apf28dev>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <16>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33000033>; - hactive = <800>; - vactive = <480>; - hback-porch = <96>; - hfront-porch = <96>; - vback-porch = <20>; - vfront-porch = <21>; - hsync-len = <64>; - vsync-len = <4>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can0_vcc>; - status = "okay"; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_apf28dev - &usb0_id_pins_b>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - - usb1: usb@80090000 { - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -223,3 +63,155 @@ }; }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can0_vcc>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_16bit_pins_a + &lcdif_pins_apf28dev>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <16>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33000033>; + hactive = <800>; + vactive = <480>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <20>; + vfront-porch = <21>; + hsync-len = <64>; + vsync-len = <4>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_apf28dev>; + + hog_pins_apf28dev: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D16__GPIO_1_16 + MX28_PAD_LCD_D17__GPIO_1_17 + MX28_PAD_LCD_D18__GPIO_1_18 + MX28_PAD_LCD_D19__GPIO_1_19 + MX28_PAD_LCD_D20__GPIO_1_20 + MX28_PAD_LCD_D21__GPIO_1_21 + MX28_PAD_LCD_D22__GPIO_1_22 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_apf28dev: lcdif-apf28dev@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_otg_apf28dev: otg-apf28dev@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D23__GPIO_1_23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a &pwm4_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_otg_apf28dev + &usb0_id_pins_b>; + vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; From 0bde5d3f8416e83f9e7fbbf00f3075b7fbecf6f5 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:00 +0100 Subject: [PATCH 0203/1040] ARM: dts: imx28-m28/sps1: Convert to use label references These board files still use node name and unit address to reference parts from the imx28.dtsi . This causes a lot of redundancy. So use label references in orer to make it easier to maintain. Signed-off-by: Stefan Wahren Cc: Marek Vasut Cc: Wolfgang Grandegger Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-m28.dtsi | 44 ++- arch/arm/boot/dts/imx28-m28cu3.dts | 354 ++++++++++++------------ arch/arm/boot/dts/imx28-m28evk.dts | 420 ++++++++++++++--------------- arch/arm/boot/dts/imx28-sps1.dts | 201 +++++++------- 4 files changed, 494 insertions(+), 525 deletions(-) diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi index 2bdb4c093545..c08b14ad7cd5 100644 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -14,31 +14,6 @@ reg = <0x40000000 0x08000000>; }; - apb@80000000 { - apbh@80000000 { - nand-controller@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - }; - }; - - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@68 { - compatible = "st,m41t62"; - reg = <0x68>; - }; - }; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -54,3 +29,22 @@ }; }; }; + +&gpmi { + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + rtc: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index 865ac3d573c7..6b01de9efd02 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -15,187 +15,6 @@ reg = <0x40000000 0x08000000>; }; - apb@80000000 { - apbh@80000000 { - nand-controller@8000c000 { - #address-cells = <1>; - #size-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - - partition@0 { - label = "gpmi-nfc-0-boot"; - reg = <0x00000000 0x01400000>; - read-only; - }; - - partition@1 { - label = "gpmi-nfc-general-use"; - reg = <0x01400000 0x0ec00000>; - }; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_a - &mmc2_cd_cfg - &mmc2_sck_cfg_a>; - bus-width = <4>; - vmmc-supply = <®_vddio_sd1>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - MX28_PAD_PWM4__GPIO_3_29 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_VSYNC__LCD_VSYNC - MX28_PAD_LCD_HSYNC__LCD_HSYNC - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_RESET__LCD_RESET - MX28_PAD_LCD_CS__LCD_ENABLE - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_gpio: leds-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP3_MISO__GPIO_2_26 - MX28_PAD_SSP3_SCK__GPIO_2_24 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - ocotp@8002c000 { - status = "okay"; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <6410256>; - hactive = <320>; - vactive = <240>; - hback-porch = <38>; - hfront-porch = <20>; - vback-porch = <15>; - vfront-porch = <5>; - hsync-len = <30>; - vsync-len = <3>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_2pins_b>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - disable-over-current; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - backlight { compatible = "pwm-backlight"; pwms = <&pwm 3 5000000>; @@ -264,3 +83,176 @@ }; }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_2pins_b>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; +}; + +&gpmi { + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; + + partition@0 { + label = "gpmi-nfc-0-boot"; + reg = <0x00000000 0x01400000>; + read-only; + }; + + partition@1 { + label = "gpmi-nfc-general-use"; + reg = <0x01400000 0x0ec00000>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <6410256>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hfront-porch = <20>; + vback-porch = <15>; + vfront-porch = <5>; + hsync-len = <30>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&ocotp { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS0__GPIO_2_19 + MX28_PAD_PWM4__GPIO_3_29 + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_VSYNC__LCD_VSYNC + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_RESET__LCD_RESET + MX28_PAD_LCD_CS__LCD_ENABLE + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins_gpio: leds-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP3_MISO__GPIO_2_26 + MX28_PAD_SSP3_SCK__GPIO_2_24 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_a + &mmc2_cd_cfg + &mmc2_sck_cfg_a>; + bus-width = <4>; + vmmc-supply = <®_vddio_sd1>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_a>; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index 13acdc7916b9..e350d57a4cec 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -11,220 +11,6 @@ model = "Aries/DENX M28EVK"; compatible = "aries,m28evk", "denx,m28evk", "fsl,imx28"; - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg - &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio3 10 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p80", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_AUART2_CTS__GPIO_3_10 - MX28_PAD_AUART2_RTS__GPIO_3_11 - MX28_PAD_AUART3_RX__GPIO_3_12 - MX28_PAD_AUART3_TX__GPIO_3_13 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_m28: lcdif-m28@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_DOTCLK__LCD_DOTCLK - MX28_PAD_LCD_ENABLE__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_m28>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <16>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33260000>; - hactive = <800>; - vactive = <480>; - hback-porch = <0>; - hfront-porch = <256>; - vback-porch = <0>; - vfront-porch = <45>; - hsync-len = <1>; - vsync-len = <1>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - eeprom: eeprom@51 { - compatible = "atmel,24c128"; - reg = <0x51>; - pagesize = <32>; - }; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_pins_a>; - status = "okay"; - }; - - auart2: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_b>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_a>; - status = "okay"; - }; - - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - clocks = <&clks 57>, <&clks 57>; - clock-names = "ipg", "ahb"; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - backlight { compatible = "pwm-backlight"; pwms = <&pwm 4 5000000>; @@ -269,3 +55,209 @@ audio-codec = <&sgtl5000>; }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; +}; + +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + status = "okay"; +}; + +&auart2 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_b>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; + + eeprom: eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_m28>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <0>; + hfront-porch = <256>; + vback-porch = <0>; + vfront-porch = <45>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + status = "okay"; + fsl,lradc-touchscreen-wires = <4>; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + clocks = <&clks 57>, <&clks 57>; + clock-names = "ipg", "ahb"; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_AUART2_CTS__GPIO_3_10 + MX28_PAD_AUART2_RTS__GPIO_3_11 + MX28_PAD_AUART3_RX__GPIO_3_12 + MX28_PAD_AUART3_TX__GPIO_3_13 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_m28: lcdif-m28@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <8>; + wp-gpios = <&gpio3 10 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; + +&ssp2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p80", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_a>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_a>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-sps1.dts b/arch/arm/boot/dts/imx28-sps1.dts index 90928db0df70..5d74a68c56ff 100644 --- a/arch/arm/boot/dts/imx28-sps1.dts +++ b/arch/arm/boot/dts/imx28-sps1.dts @@ -15,111 +15,6 @@ reg = <0x40000000 0x08000000>; }; - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog-gpios@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D00__GPIO_0_0 - MX28_PAD_GPMI_D03__GPIO_0_3 - MX28_PAD_GPMI_D06__GPIO_0_6 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256", "mr25h256"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - }; - - apbx@80040000 { - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - rtc: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - eeprom: eeprom@52 { - compatible = "atmel,24c64"; - reg = <0x52>; - pagesize = <32>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - vbus-supply = <®_usb0_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins_b>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -164,3 +59,99 @@ }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + + eeprom: eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D06__GPIO_0_6 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a>; + bus-width = <4>; + status = "okay"; +}; + +&ssp2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256", "mr25h256"; + spi-max-frequency = <40000000>; + reg = <0>; + }; +}; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_b>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; From d9355d58217b687f02671169040e2934c8726192 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:01 +0100 Subject: [PATCH 0204/1040] ARM: dts: imx28-apx4devkit: Convert to use label references This board file still use node name and unit address to reference parts from the imx28.dtsi . This causes a lot of redundancy. So use label references in orer to make it easier to maintain. Signed-off-by: Stefan Wahren Cc: Aapo Vienamo Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-apx4devkit.dts | 380 ++++++++++++------------- 1 file changed, 186 insertions(+), 194 deletions(-) diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index b86be320496b..f9bf40d96568 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -11,200 +11,6 @@ reg = <0x40000000 0x04000000>; }; - apb@80000000 { - apbh@80000000 { - nand-controller@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; - status = "okay"; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; - bus-width = <4>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; - bus-width = <4>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_RDY1__GPIO_0_21 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_JTAG_RTCK__GPIO_4_20 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_apx4: lcdif-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA4__SSP2_D0 - MX28_PAD_SSP0_DATA5__SSP2_D3 - MX28_PAD_SSP0_DATA6__SSP2_CMD - MX28_PAD_SSP0_DATA7__SSP2_SCK - MX28_PAD_SSP2_SS1__SSP2_D1 - MX28_PAD_SSP2_SS2__SSP2_D2 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__SSP2_SCK - >; - fsl,drive-strength = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_apx4>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <88>; - hfront-porch = <40>; - vback-porch = <32>; - vfront-porch = <13>; - hsync-len = <48>; - vsync-len = <3>; - hsync-active = <1>; - vsync-active = <1>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - pcf8563: rtc@51 { - compatible = "phg,pcf8563"; - reg = <0x51>; - }; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - status = "okay"; - }; - - auart1: serial@8006c000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart1_2pins_a>; - status = "okay"; - }; - - auart2: serial@8006e000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart2_2pins_a>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins_a>; - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - status = "okay"; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -238,3 +44,189 @@ }; }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + status = "okay"; +}; + +&auart1 { + pinctrl-names = "default"; + pinctrl-0 = <&auart1_2pins_a>; + status = "okay"; +}; + +&auart2 { + pinctrl-names = "default"; + pinctrl-0 = <&auart2_2pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_apx4>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <32>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; + + pcf8563: rtc@51 { + compatible = "phg,pcf8563"; + reg = <0x51>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_RDY1__GPIO_0_21 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_SSP2_SS0__AUART3_TX /* was: 0x2131 - MX28_PAD_SSP2_SS0__GPIO_2_19 */ + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_LCD_RESET__GPIO_3_30 + MX28_PAD_JTAG_RTCK__GPIO_4_20 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_apx4: lcdif-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA4__SSP2_D0 + MX28_PAD_SSP0_DATA5__SSP2_D3 + MX28_PAD_SSP0_DATA6__SSP2_CMD + MX28_PAD_SSP0_DATA7__SSP2_SCK + MX28_PAD_SSP2_SS1__SSP2_D1 + MX28_PAD_SSP2_SS2__SSP2_D2 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__SSP2_SCK + >; + fsl,drive-strength = ; + fsl,pull-up = ; + }; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; + bus-width = <4>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usbphy1 { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_a>; + status = "okay"; +}; From 0b80d1ab87a4aa598919270096c2a39e98d6f7e7 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:02 +0100 Subject: [PATCH 0205/1040] ARM: dts: imx28-cfa10036: Convert to use label references MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These Crystal fontz board files still use node name and unit address to reference parts from the imx28.dtsi . This causes a lot of redundancy. So use label references in order to make it easier to maintain. Signed-off-by: Stefan Wahren Cc: Brian Lilly Cc: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-cfa10036.dts | 193 ++++++------ arch/arm/boot/dts/imx28-cfa10049.dts | 454 +++++++++++++-------------- arch/arm/boot/dts/imx28-cfa10055.dts | 224 +++++++------ arch/arm/boot/dts/imx28-cfa10056.dts | 146 +++++---- arch/arm/boot/dts/imx28-cfa10057.dts | 252 +++++++-------- arch/arm/boot/dts/imx28-cfa10058.dts | 186 ++++++----- 6 files changed, 703 insertions(+), 752 deletions(-) diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts index 85aa1cc3ff66..d004b1cbb4ae 100644 --- a/arch/arm/boot/dts/imx28-cfa10036.dts +++ b/arch/arm/boot/dts/imx28-cfa10036.dts @@ -16,107 +16,6 @@ reg = <0x40000000 0x08000000>; }; - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - ssd1306_cfa10036: ssd1306-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins_cfa10036: leds-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - usb0_otg_cfa10036: otg-10036@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDY0__USB0_ID - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { - reg = <0>; - fsl,pinmux-ids = < - 0x31c3 /* - MX28_PAD_PWM3__GPIO_3_28 */ - >; - fsl,drive-strength = <0>; - fsl,voltage = <1>; - fsl,pull-up = <0>; - }; - - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - vmmc-supply = <®_vddio_sd0>; - bus-width = <4>; - status = "okay"; - }; - }; - - apbx@80040000 { - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_b>; - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_b>; - clock-frequency = <400000>; - status = "okay"; - - ssd1306: oled@3c { - compatible = "solomon,ssd1306fb-i2c"; - pinctrl-names = "default"; - pinctrl-0 = <&ssd1306_cfa10036>; - reg = <0x3c>; - reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - solomon,height = <32>; - solomon,width = <128>; - solomon,page-offset = <0>; - solomon,com-lrremap; - solomon,com-invdir; - solomon,com-offset = <32>; - }; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_otg_cfa10036>; - dr_mode = "peripheral"; - phy_type = "utmi"; - status = "okay"; - }; - }; - leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -138,3 +37,95 @@ gpio = <&gpio3 28 0>; }; }; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_b>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_b>; + clock-frequency = <400000>; + status = "okay"; + + ssd1306: oled@3c { + compatible = "solomon,ssd1306fb-i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&ssd1306_cfa10036>; + reg = <0x3c>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + solomon,height = <32>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,com-lrremap; + solomon,com-invdir; + solomon,com-offset = <32>; + }; +}; + +&pinctrl { + ssd1306_cfa10036: ssd1306-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__GPIO_2_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins_cfa10036: leds-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__GPIO_3_4 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + usb0_otg_cfa10036: otg-10036@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY0__USB0_ID + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31c3 /* + MX28_PAD_PWM3__GPIO_3_28 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + vmmc-supply = <®_vddio_sd0>; + bus-width = <4>; + status = "okay"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_otg_cfa10036>; + dr_mode = "peripheral"; + phy_type = "utmi"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 9ef0d567ea48..94d6614c1983 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -78,226 +78,6 @@ }; }; - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10049: usb-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - i2cmux_pins_cfa10049: i2cmux-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D22__GPIO_1_22 - MX28_PAD_LCD_D23__GPIO_1_23 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_pins_cfa10049: mac0-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS2__GPIO_2_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - pca_pins_cfa10049: pca-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SS0__GPIO_2_19 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_pins_cfa10049: rotary-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - rotary_btn_pins_cfa10049: rotary-btn-10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF1_SDATA0__GPIO_3_26 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi2_pins_cfa10049: spi2-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - spi3_pins_cfa10049: spi3-cfa10049@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_RDN__GPIO_0_24 - MX28_PAD_GPMI_RESETN__GPIO_0_28 - MX28_PAD_GPMI_CE1N__GPIO_0_17 - MX28_PAD_GPMI_ALE__GPIO_0_26 - MX28_PAD_GPMI_CLE__GPIO_0_27 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - w1_gpio_pins: w1-gpio@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D21__GPIO_1_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; /* 0 will enable the keeper */ - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10049 - &lcdif_pins_cfa10049 - &lcdif_pins_cfa10049_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - - i2c1: i2c@8005a000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -315,18 +95,6 @@ }; }; - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a - &mac0_pins_cfa10049>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; @@ -426,3 +194,225 @@ gpios = <&gpio1 21 0>; }; }; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10049 + &lcdif_pins_cfa10049 + &lcdif_pins_cfa10049_pullup>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9216000>; + hactive = <320>; + vactive = <480>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <15>; + vsync-len = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a + &mac0_pins_cfa10049>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&pinctrl { + usb_pins_cfa10049: usb-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + i2cmux_pins_cfa10049: i2cmux-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D22__GPIO_1_22 + MX28_PAD_LCD_D23__GPIO_1_23 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_pins_cfa10049: mac0-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS2__GPIO_2_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + pca_pins_cfa10049: pca-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SS0__GPIO_2_19 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + rotary_pins_cfa10049: rotary-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + rotary_btn_pins_cfa10049: rotary-btn-10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF1_SDATA0__GPIO_3_26 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi2_pins_cfa10049: spi2-cfa10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + spi3_pins_cfa10049: spi3-cfa10049@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_GPMI_RESETN__GPIO_0_28 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_ALE__GPIO_0_26 + MX28_PAD_GPMI_CLE__GPIO_0_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_18bit_pins_cfa10049: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10049: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + w1_gpio_pins: w1-gpio@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D21__GPIO_1_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; /* 0 will enable the keeper */ + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usb1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index fac5bbda7a93..42ba7da48beb 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -14,121 +14,6 @@ model = "Crystalfontz CFA-10055 Board"; compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - spi2_pins_cfa10055: spi2-cfa10055@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10055 - &lcdif_pins_cfa10055 - &lcdif_pins_cfa10055_pullup>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9216000>; - hactive = <320>; - vactive = <480>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <15>; - vsync-len = <15>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - }; - }; - spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; @@ -159,3 +44,112 @@ default-brightness-level = <6>; }; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10055 + &lcdif_pins_cfa10055 + &lcdif_pins_cfa10055_pullup>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9216000>; + hactive = <320>; + vactive = <480>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <15>; + vsync-len = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&pinctrl { + spi2_pins_cfa10055: spi2-cfa10055@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_18bit_pins_cfa10055: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10055: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index c5f3337e8b39..0e15bdfd7281 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -13,81 +13,6 @@ model = "Crystalfontz CFA-10056 Board"; compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28"; - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - spi2_pins_cfa10056: spi2-cfa10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP2_SCK__GPIO_2_16 - MX28_PAD_SSP2_MOSI__GPIO_2_17 - MX28_PAD_SSP2_MISO__GPIO_2_18 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056: lcdif-10056@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RESET__GPIO_3_30 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10056 - &lcdif_pins_cfa10056_pullup >; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <32000000>; - hactive = <480>; - vactive = <800>; - hback-porch = <2>; - hfront-porch = <2>; - vback-porch = <2>; - vfront-porch = <2>; - hsync-len = <5>; - vsync-len = <5>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - }; - spi-2 { compatible = "spi-gpio"; pinctrl-names = "default"; @@ -111,3 +36,74 @@ }; }; }; + +&pinctrl { + spi2_pins_cfa10056: spi2-cfa10056@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP2_SCK__GPIO_2_16 + MX28_PAD_SSP2_MOSI__GPIO_2_17 + MX28_PAD_SSP2_MISO__GPIO_2_18 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10056: lcdif-10056@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_cfa10056 + &lcdif_pins_cfa10056_pullup >; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <32000000>; + hactive = <480>; + vactive = <800>; + hback-porch = <2>; + hfront-porch = <2>; + vback-porch = <2>; + vfront-porch = <2>; + hsync-len = <5>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index 2f7e479dbc74..27602c01f162 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -14,126 +14,6 @@ model = "Crystalfontz CFA-10057 Board"; compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10057: usb-10057@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D00__LCD_D0 - MX28_PAD_LCD_D01__LCD_D1 - MX28_PAD_LCD_D02__LCD_D2 - MX28_PAD_LCD_D03__LCD_D3 - MX28_PAD_LCD_D04__LCD_D4 - MX28_PAD_LCD_D05__LCD_D5 - MX28_PAD_LCD_D06__LCD_D6 - MX28_PAD_LCD_D07__LCD_D7 - MX28_PAD_LCD_D08__LCD_D8 - MX28_PAD_LCD_D09__LCD_D9 - MX28_PAD_LCD_D10__LCD_D10 - MX28_PAD_LCD_D11__LCD_D11 - MX28_PAD_LCD_D12__LCD_D12 - MX28_PAD_LCD_D13__LCD_D13 - MX28_PAD_LCD_D14__LCD_D14 - MX28_PAD_LCD_D15__LCD_D15 - MX28_PAD_LCD_D16__LCD_D16 - MX28_PAD_LCD_D17__LCD_D17 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10057: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_18bit_pins_cfa10057 - &lcdif_pins_cfa10057>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <18>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <480>; - vactive = <800>; - hfront-porch = <12>; - hback-porch = <2>; - vfront-porch = <5>; - vback-porch = <3>; - hsync-len = <2>; - vsync-len = <2>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm4_pins_a>; - status = "okay"; - }; - - i2c1: i2c@8005a000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -151,17 +31,6 @@ }; }; - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - backlight { compatible = "pwm-backlight"; pwms = <&pwm 4 5000000>; @@ -169,3 +38,124 @@ default-brightness-level = <7>; }; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_18bit_pins_cfa10057 + &lcdif_pins_cfa10057>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <18>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <480>; + vactive = <800>; + hfront-porch = <12>; + hback-porch = <2>; + vfront-porch = <5>; + vback-porch = <3>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&pinctrl { + usb_pins_cfa10057: usb-10057@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D00__LCD_D0 + MX28_PAD_LCD_D01__LCD_D1 + MX28_PAD_LCD_D02__LCD_D2 + MX28_PAD_LCD_D03__LCD_D3 + MX28_PAD_LCD_D04__LCD_D4 + MX28_PAD_LCD_D05__LCD_D5 + MX28_PAD_LCD_D06__LCD_D6 + MX28_PAD_LCD_D07__LCD_D7 + MX28_PAD_LCD_D08__LCD_D8 + MX28_PAD_LCD_D09__LCD_D9 + MX28_PAD_LCD_D10__LCD_D10 + MX28_PAD_LCD_D11__LCD_D11 + MX28_PAD_LCD_D12__LCD_D12 + MX28_PAD_LCD_D13__LCD_D13 + MX28_PAD_LCD_D14__LCD_D14 + MX28_PAD_LCD_D15__LCD_D15 + MX28_PAD_LCD_D16__LCD_D16 + MX28_PAD_LCD_D17__LCD_D17 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10057: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4_pins_a>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usb1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index 4465fd86785a..931c4d089b26 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -14,93 +14,6 @@ model = "Crystalfontz CFA-10058 Board"; compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; - apb@80000000 { - apbh@80000000 { - pinctrl@80018000 { - usb_pins_cfa10058: usb-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_cfa10058: lcdif-10058@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_cfa10058>; - display = <&display0>; - status = "okay"; - - display0: display0 { - bits-per-pixel = <32>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <30000000>; - hactive = <800>; - vactive = <480>; - hback-porch = <40>; - hfront-porch = <40>; - vback-porch = <13>; - vfront-porch = <29>; - hsync-len = <8>; - vsync-len = <8>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; - }; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - fsl,lradc-touchscreen-wires = <4>; - status = "okay"; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_b>; - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - pinctrl-0 = <&usb1_pins_a>; - pinctrl-names = "default"; - status = "okay"; - }; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -118,17 +31,6 @@ }; }; - ahb@80080000 { - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - }; - backlight { compatible = "pwm-backlight"; pwms = <&pwm 3 5000000>; @@ -136,3 +38,91 @@ default-brightness-level = <6>; }; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_cfa10058>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <30000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <13>; + vfront-porch = <29>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&pinctrl { + usb_pins_cfa10058: usb-10058@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_cfa10058: lcdif-10058@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_b>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + pinctrl-0 = <&usb1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; From bad4d335d7c1b6be43e22adf5c5a279a4f5035e5 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:03 +0100 Subject: [PATCH 0206/1040] ARM: dts: imx28-duckbill: Convert to use label references These I2SE board files still use node name and unit address to reference parts from the imx28.dtsi . This causes a lot of redundancy. So use label references in order to make it easier to maintain. Signed-off-by: Stefan Wahren Cc: Michael Heimpold Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-duckbill-2.dts | 256 ++++++++++++------------- arch/arm/boot/dts/imx28-duckbill.dts | 196 +++++++++---------- 2 files changed, 218 insertions(+), 234 deletions(-) diff --git a/arch/arm/boot/dts/imx28-duckbill-2.dts b/arch/arm/boot/dts/imx28-duckbill-2.dts index 23fd3036404d..4e28212e9626 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2.dts @@ -18,138 +18,6 @@ reg = <0x40000000 0x08000000>; }; - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_b - &mmc2_cd_cfg &mmc2_sck_cfg_b>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -176,3 +44,127 @@ }; }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&lradc { + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; + phy-supply = <®_3p3v>; + phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_phy_int_pin>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + max-speed = <100>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_phy_reset_pin: mac0-phy-reset@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_phy_int_pin: mac0-phy-int@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins: leds@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 + MX28_PAD_SAIF0_LRCLK__GPIO_3_21 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <8>; + vmmc-supply = <®_3p3v>; + status = "okay"; + non-removable; +}; + +&ssp2 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_4bit_pins_b + &mmc2_cd_cfg &mmc2_sck_cfg_b>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&usbphy0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts index c666afb12445..13ffd533fdea 100644 --- a/arch/arm/boot/dts/imx28-duckbill.dts +++ b/arch/arm/boot/dts/imx28-duckbill.dts @@ -17,108 +17,6 @@ reg = <0x40000000 0x08000000>; }; - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_RX__GPIO_3_4 - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - status = "okay"; - }; - }; - reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -145,3 +43,97 @@ }; }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&lradc { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; + phy-supply = <®_3p3v>; + phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + mac0_phy_reset_pin: mac0-phy-reset@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pins: leds@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_RX__GPIO_3_4 + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; From 1e899432085ac811748c7f3fee967471ed4a75d6 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:04 +0100 Subject: [PATCH 0207/1040] ARM: dts: imx28-duckbill-2: Include base board All additional I2SE Duckbill 2 variants always have the same base board in common. So consider this by including the base board and avoid a lot of redundancy. Special care needs to be taken of the SPI variant. ssp2 is used as SD card interface on the base board, but on the SPI variant it's downgrade to a SPI interface to connect the QCA7000. So the SD card properties must be deleted. Signed-off-by: Stefan Wahren Cc: Michael Heimpold Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-duckbill-2-485.dts | 174 ++------------ .../arm/boot/dts/imx28-duckbill-2-enocean.dts | 198 +++------------- arch/arm/boot/dts/imx28-duckbill-2-spi.dts | 217 ++++-------------- 3 files changed, 84 insertions(+), 505 deletions(-) diff --git a/arch/arm/boot/dts/imx28-duckbill-2-485.dts b/arch/arm/boot/dts/imx28-duckbill-2-485.dts index d451fa018d83..b73020ff1053 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2-485.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2-485.dts @@ -5,172 +5,13 @@ */ /dts-v1/; -#include -#include -#include "imx28.dtsi" +#include "imx28-duckbill-2.dts" / { model = "I2SE Duckbill 2 485"; compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28"; - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_b - &mmc2_cd_cfg &mmc2_sck_cfg_b>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - rs485-red { label = "duckbill:red:rs485"; gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; @@ -182,3 +23,16 @@ }; }; }; + +&i2c0 { + status = "disabled"; +}; + +&led_pins { + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 + MX28_PAD_SAIF0_LRCLK__GPIO_3_21 + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; +}; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts index 73f521c46c1e..473d99b9b42f 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2-enocean.dts @@ -5,184 +5,14 @@ */ /dts-v1/; -#include #include -#include -#include "imx28.dtsi" +#include "imx28-duckbill-2.dts" / { model = "I2SE Duckbill 2 EnOcean"; compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28"; - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; - - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; - - ssp2: spi@80014000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_4bit_pins_b - &mmc2_cd_cfg &mmc2_sck_cfg_b>; - bus-width = <4>; - vmmc-supply = <®_3p3v>; - status = "okay"; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: leds@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - MX28_PAD_AUART0_CTS__GPIO_3_2 - MX28_PAD_I2C0_SCL__GPIO_3_24 - MX28_PAD_I2C0_SDA__GPIO_3_25 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - enocean_button: enocean-button@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RTS__GPIO_3_3 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_2pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - enocean-blue { label = "duckbill:blue:enocean"; gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; @@ -211,3 +41,29 @@ }; }; }; + +&i2c0 { + status = "disabled"; +}; + +&led_pins { + fsl,pinmux-ids = < + MX28_PAD_SAIF0_MCLK__GPIO_3_20 + MX28_PAD_SAIF0_LRCLK__GPIO_3_21 + MX28_PAD_AUART0_CTS__GPIO_3_2 + MX28_PAD_I2C0_SCL__GPIO_3_24 + MX28_PAD_I2C0_SDA__GPIO_3_25 + >; +}; + +&pinctrl { + enocean_button: enocean-button@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RTS__GPIO_3_3 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; diff --git a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts index 0e8be5975709..859d97a5a775 100644 --- a/arch/arm/boot/dts/imx28-duckbill-2-spi.dts +++ b/arch/arm/boot/dts/imx28-duckbill-2-spi.dts @@ -5,9 +5,7 @@ */ /dts-v1/; -#include -#include -#include "imx28.dtsi" +#include "imx28-duckbill-2.dts" / { model = "I2SE Duckbill 2 SPI"; @@ -16,179 +14,50 @@ aliases { ethernet1 = &qca7000; }; +}; - memory@40000000 { - device_type = "memory"; - reg = <0x40000000 0x08000000>; - }; +&auart0 { + status = "disabled"; +}; - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - vmmc-supply = <®_3p3v>; - status = "okay"; - non-removable; - }; +&i2c0 { + status = "disabled"; +}; - ssp2: spi@80014000 { - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - qca7000: ethernet@0 { - reg = <0>; - compatible = "qca,qca7000"; - pinctrl-names = "default"; - pinctrl-0 = <&qca7000_pins>; - interrupt-parent = <&gpio3>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; - spi-cpha; - spi-cpol; - spi-max-frequency = <8000000>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_D17__GPIO_1_17 /* Revision detection */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_reset_pin: mac0-phy-reset@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_ALE__GPIO_0_26 /* PHY Reset */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - mac0_phy_int_pin: mac0-phy-int@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_D07__GPIO_0_7 /* PHY Interrupt */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pins: led@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SAIF0_MCLK__GPIO_3_20 - MX28_PAD_SAIF0_LRCLK__GPIO_3_21 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - qca7000_pins: qca7000@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ - MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */ - MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */ - MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */ - MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */ - MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */ - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - }; - - apbx@80040000 { - lradc@80050000 { - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - status = "okay"; - dr_mode = "peripheral"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>, <&mac0_phy_reset_pin>; - phy-supply = <®_3p3v>; - phy-reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; - phy-reset-duration = <25>; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_phy_int_pin>; - interrupt-parent = <&gpio0>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - max-speed = <100>; - }; - }; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - status-red { - label = "duckbill:red:status"; - gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-on"; - }; - - status-green { - label = "duckbill:green:status"; - gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; +&pinctrl { + qca7000_pins: qca7000@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ + MX28_PAD_LCD_D13__GPIO_1_13 /* QCA7K reset */ + MX28_PAD_LCD_D14__GPIO_1_14 /* GPIO 0 */ + MX28_PAD_LCD_D15__GPIO_1_15 /* GPIO 1 */ + MX28_PAD_LCD_D18__GPIO_1_18 /* GPIO 2 */ + MX28_PAD_LCD_D21__GPIO_1_21 /* GPIO 3 */ + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + /delete-property/ bus-width; + /delete-property/ vmmc-supply; + status = "okay"; + + qca7000: ethernet@0 { + reg = <0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&qca7000_pins>; + interrupt-parent = <&gpio3>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <8000000>; }; }; From 89b83148b34bf0719f9a650586c2ef28040d8efb Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:05 +0100 Subject: [PATCH 0208/1040] ARM: dts: imx28-evk: Convert to use label references This Freescale board file still use node name and unit address to reference parts from the imx28.dtsi . This causes a lot of redundancy. So use label references in order to make it easier to maintain. Signed-off-by: Stefan Wahren Cc: NXP Linux Team Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-evk.dts | 464 ++++++++++++++++---------------- 1 file changed, 228 insertions(+), 236 deletions(-) diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index 1053b7c584d8..783abb82b2a8 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -95,242 +95,6 @@ }; }; - apb@80000000 { - apbh@80000000 { - nand-controller@8000c000 { - pinctrl-names = "default"; - pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg - &gpmi_pins_evk>; - status = "okay"; - }; - - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_8bit_pins_a - &mmc0_cd_cfg &mmc0_sck_cfg>; - bus-width = <8>; - wp-gpios = <&gpio2 12 0>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - ssp1: spi@80012000 { - compatible = "fsl,imx28-mmc"; - bus-width = <8>; - wp-gpios = <&gpio0 28 0>; - }; - - ssp2: spi@80014000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-spi"; - pinctrl-names = "default"; - pinctrl-0 = <&spi2_pins_a>; - status = "okay"; - - flash: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "sst,sst25vf016b", "jedec,spi-nor"; - spi-max-frequency = <40000000>; - reg = <0>; - }; - }; - - pinctrl@80018000 { - pinctrl-names = "default"; - pinctrl-0 = <&hog_pins_a>; - - hog_pins_a: hog@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP1_CMD__GPIO_2_13 - MX28_PAD_SSP1_DATA3__GPIO_2_15 - MX28_PAD_ENET0_RX_CLK__GPIO_4_13 - MX28_PAD_SSP1_SCK__GPIO_2_12 - MX28_PAD_PWM3__GPIO_3_28 - MX28_PAD_LCD_RESET__GPIO_3_30 - MX28_PAD_AUART2_RX__GPIO_3_8 - MX28_PAD_AUART2_TX__GPIO_3_9 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - led_pin_gpio3_5: led_gpio3_5@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_AUART1_TX__GPIO_3_5 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - gpmi_pins_evk: gpmi-nand-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_GPMI_CE1N__GPMI_CE1N - MX28_PAD_GPMI_RDY1__GPMI_READY1 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - lcdif_pins_evk: lcdif-evk@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_LCD_RD_E__LCD_VSYNC - MX28_PAD_LCD_WR_RWN__LCD_HSYNC - MX28_PAD_LCD_RS__LCD_DOTCLK - MX28_PAD_LCD_CS__LCD_ENABLE - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - }; - - lcdif@80030000 { - pinctrl-names = "default"; - pinctrl-0 = <&lcdif_24bit_pins_a - &lcdif_pins_evk>; - status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - - can0: can@80032000 { - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; - }; - - can1: can@80034000 { - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins_a>; - xceiver-supply = <®_can_3v3>; - status = "okay"; - }; - }; - - apbx@80040000 { - saif0: saif@80042000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif0_pins_a>; - status = "okay"; - }; - - saif1: saif@80046000 { - pinctrl-names = "default"; - pinctrl-0 = <&saif1_pins_a>; - fsl,saif-master = <&saif0>; - status = "okay"; - }; - - lradc@80050000 { - status = "okay"; - fsl,lradc-touchscreen-wires = <4>; - fsl,ave-ctrl = <4>; - fsl,ave-delay = <2>; - fsl,settling = <10>; - }; - - i2c0: i2c@80058000 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - #sound-dai-cells = <0>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; - clocks = <&saif0>; - }; - - at24@51 { - compatible = "atmel,24c32"; - pagesize = <32>; - reg = <0x51>; - }; - }; - - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - - auart0: serial@8006a000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart0_pins_a>; - uart-has-rtscts; - status = "okay"; - }; - - auart3: serial@80070000 { - pinctrl-names = "default"; - pinctrl-0 = <&auart3_pins_a>; - status = "okay"; - }; - - usbphy0: usbphy@8007c000 { - status = "okay"; - }; - - usbphy1: usbphy@8007e000 { - status = "okay"; - }; - }; - }; - - ahb@80080000 { - usb0: usb@80080000 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_pins_a>; - vbus-supply = <®_usb0_vbus>; - status = "okay"; - }; - - usb1: usb@80090000 { - vbus-supply = <®_usb1_vbus>; - status = "okay"; - }; - - mac0: ethernet@800f0000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac0_pins_a>; - phy-supply = <®_fec_3v3>; - phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - phy-reset-duration = <100>; - status = "okay"; - }; - - mac1: ethernet@800f4000 { - phy-mode = "rmii"; - pinctrl-names = "default"; - pinctrl-0 = <&mac1_pins_a>; - status = "okay"; - }; - }; - sound { compatible = "fsl,imx28-evk-sgtl5000", "fsl,mxs-audio-sgtl5000"; @@ -358,3 +122,231 @@ default-brightness-level = <6>; }; }; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + xceiver-supply = <®_can_3v3>; + status = "okay"; +}; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg + &gpmi_pins_evk>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_evk>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&lradc { + fsl,lradc-touchscreen-wires = <4>; + fsl,ave-ctrl = <4>; + fsl,ave-delay = <2>; + fsl,settling = <10>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + clocks = <&saif0>; + }; + + at24@51 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x51>; + }; +}; + +&mac0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + phy-supply = <®_fec_3v3>; + phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + phy-reset-duration = <100>; + status = "okay"; +}; + +&mac1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP1_CMD__GPIO_2_13 + MX28_PAD_SSP1_DATA3__GPIO_2_15 + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 + MX28_PAD_SSP1_SCK__GPIO_2_12 + MX28_PAD_PWM3__GPIO_3_28 + MX28_PAD_LCD_RESET__GPIO_3_30 + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_AUART2_TX__GPIO_3_9 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + led_pin_gpio3_5: led_gpio3_5@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_AUART1_TX__GPIO_3_5 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + gpmi_pins_evk: gpmi-nand-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CE1N__GPMI_CE1N + MX28_PAD_GPMI_RDY1__GPMI_READY1 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_pins_evk: lcdif-evk@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RD_E__LCD_VSYNC + MX28_PAD_LCD_WR_RWN__LCD_HSYNC + MX28_PAD_LCD_RS__LCD_DOTCLK + MX28_PAD_LCD_CS__LCD_ENABLE + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_8bit_pins_a + &mmc0_cd_cfg &mmc0_sck_cfg>; + bus-width = <8>; + wp-gpios = <&gpio2 12 0>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; + +&ssp1 { + compatible = "fsl,imx28-mmc"; + bus-width = <8>; + wp-gpios = <&gpio0 28 0>; +}; + +&ssp2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; + + flash: flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + spi-max-frequency = <40000000>; + }; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_pins_a>; + vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; + +&usb1 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; From 8d59bf1568ede4b239e1ee3335307cf228a76410 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:06 +0100 Subject: [PATCH 0209/1040] ARM: dts: imx28-ts4600: Convert to use label references This Technologic board file still use node name and unit address to reference parts from the imx28.dtsi . This causes a lot of redundancy. So use label references in order to make it easier to maintain. Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-ts4600.dts | 80 ++++++++++++++---------------- 1 file changed, 36 insertions(+), 44 deletions(-) diff --git a/arch/arm/boot/dts/imx28-ts4600.dts b/arch/arm/boot/dts/imx28-ts4600.dts index 0d58da1c0cc5..ae6ed5c41be3 100644 --- a/arch/arm/boot/dts/imx28-ts4600.dts +++ b/arch/arm/boot/dts/imx28-ts4600.dts @@ -18,50 +18,6 @@ reg = <0x40000000 0x10000000>; /* 256MB */ }; - apb@80000000 { - apbh@80000000 { - ssp0: spi@80010000 { - compatible = "fsl,imx28-mmc"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_4bit_pins_a - &mmc0_sck_cfg - &en_sd_pwr>; - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vddio_sd0>; - status = "okay"; - }; - - pinctrl@80018000 { - - en_sd_pwr: en-sd-pwr@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_PWM3__GPIO_3_28 - >; - fsl,drive-strength = ; - fsl,voltage = ; - fsl,pull-up = ; - }; - - }; - }; - - apbx@80040000 { - pwm: pwm@80064000 { - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pins_a>; - status = "okay"; - }; - - duart: serial@80074000 { - pinctrl-names = "default"; - pinctrl-0 = <&duart_pins_a>; - status = "okay"; - }; - }; - }; - reg_vddio_sd0: regulator-vddio-sd0 { compatible = "regulator-fixed"; regulator-name = "vddio-sd0"; @@ -72,3 +28,39 @@ }; }; + +&duart { + pinctrl-names = "default"; + pinctrl-0 = <&duart_pins_a>; + status = "okay"; +}; + +&pinctrl { + en_sd_pwr: en-sd-pwr@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_PWM3__GPIO_3_28 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pins_a>; + status = "okay"; +}; + +&ssp0 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_sck_cfg + &en_sd_pwr>; + broken-cd; + bus-width = <4>; + vmmc-supply = <®_vddio_sd0>; + status = "okay"; +}; From f3bf9c153642ec8b87804a4e8582dd6f6ed0ad10 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 7 Mar 2023 19:40:07 +0100 Subject: [PATCH 0210/1040] ARM: dts: imx28-tx28: add SPDX-License-Identifier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the license blob by a clean SPDX-License-Identifier with GPL2 or MIT even if X11 is specified in the original blob since the actual license text corresponds to a MIT license. Signed-off-by: Stefan Wahren Cc: Lothar Waßmann Acked-by: Lothar Waßmann Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx28-tx28.dts | 38 +------------------------------- 1 file changed, 1 insertion(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 096f246032c6..ffe58c7093e1 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -1,43 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright 2012 Shawn Guo * Copyright 2013-2017 Lothar Waßmann - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; From d7e2ebf484a30570a2ed77719a91d87fdbbdb1ee Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 7 Mar 2023 22:16:28 -0300 Subject: [PATCH 0211/1040] arm64: defconfig: Enable i.MX93 ADC support Enable the i.MX93 ADC driver by default. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..9709fdad8f8d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1252,6 +1252,7 @@ CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_RENESAS_RPCIF=m CONFIG_IIO=y CONFIG_EXYNOS_ADC=y +CONFIG_IMX93_ADC=m CONFIG_MAX9611=m CONFIG_MEDIATEK_MT6577_AUXADC=m CONFIG_QCOM_SPMI_VADC=m From 0253e1cb6300d50c6f6b3edd7b5a570fa92e8fcd Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 28 Feb 2023 18:02:47 +0100 Subject: [PATCH 0212/1040] arm64: dts: imx8mp-debix: add USB host support This adds support for the 4 USB3 host ports on the board, which are connected to the i.MX8MP SoC via a Realtek RTS5411 hub. As the schematic for the board is not available, I could not validate that this really reflects the reality, but I modeled things after the hacked in usage of the GPIOs in the downstream kernel. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-debix-model-a.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index 2876d18f2a38..b4409349eb3f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -43,6 +43,17 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_usb_hub: regulator-usb-hub { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_hub>; + regulator-name = "USB_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &A53_0 { @@ -254,6 +265,41 @@ status = "okay"; }; +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "okay"; + + /* 2.x hub on port 1 */ + usb_hub_2_x: hub@1 { + compatible = "usbbda,5411"; + reg = <1>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + vdd-supply = <®_usb_hub>; + peer-hub = <&usb_hub_3_x>; + }; + + /* 3.x hub on port 2 */ + usb_hub_3_x: hub@2 { + compatible = "usbbda,411"; + reg = <2>; + reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + vdd-supply = <®_usb_hub>; + peer-hub = <&usb_hub_2_x>; + }; +}; + /* SD Card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -384,6 +430,12 @@ >; }; + pinctrl_reg_usb_hub: regusbhubgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x19 + >; + }; + pinctrl_rtc_int: rtcintgrp { fsl,pins = < MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140 @@ -411,6 +463,13 @@ >; }; + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 From 20d4640bd0d7f3b23acdbf83d1440a49ec29b724 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Wed, 8 Mar 2023 13:48:29 +0100 Subject: [PATCH 0213/1040] arm64: dts: imx93: add missing tpm pwm instances TPM1/TPM3 are missing, add them. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 84f7de0608de..282374d011f6 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -153,6 +153,14 @@ nxp,no-divider; }; + tpm1: pwm@44310000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x44310000 0x1000>; + clocks = <&clk IMX93_CLK_TPM1_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + tpm2: pwm@44320000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x44320000 0x10000>; @@ -332,6 +340,14 @@ status = "disabled"; }; + tpm3: pwm@424e0000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x424e0000 0x1000>; + clocks = <&clk IMX93_CLK_TPM3_GATE>; + #pwm-cells = <3>; + status = "disabled"; + }; + tpm4: pwm@424f0000 { compatible = "fsl,imx7ulp-pwm"; reg = <0x424f0000 0x10000>; From 132401ccab235150bcbf25bfc704eb8b84908707 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 9 Mar 2023 16:04:10 +0100 Subject: [PATCH 0214/1040] arm64: dts: imx8mp-tqma8mpql-mba8mpxl: Enable wakeup-source for GPIO buttons These buttons are capable of waking up a suspended system, add the appropriate property for both. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 3fa6cca9a043..d8fb29e7e148 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -80,12 +80,14 @@ label = "S12"; linux,code = ; gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; + wakeup-source; }; switch-2 { label = "S13"; linux,code = ; gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; From ba179ae131c9f998709fc6887ad0f875f23d393a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 21:13:35 +0100 Subject: [PATCH 0215/1040] arm64: dts: imx8: align thermal node names with bindings Bindings expect thermal node names to end with '-thermal': imx8qxp-mek.dtb: thermal-zones: 'pmic-thermal0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 2 +- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 1bcf228a22b8..57099ac0d773 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -276,7 +276,7 @@ }; &thermal_zones { - pmic-thermal0 { + pmic-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 214f21bd0cb4..97d7df0813a5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -188,7 +188,7 @@ }; thermal_zones: thermal-zones { - cpu-thermal0 { + cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index afa883389456..a56c8d0974ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -148,7 +148,7 @@ }; &thermal_zones { - pmic-thermal0 { + pmic-thermal { polling-delay-passive = <250>; polling-delay = <2000>; thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; From fce7defb8a46c31cf9384fee6e4b1e4920c46ff7 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 7 Feb 2023 17:47:35 -0600 Subject: [PATCH 0216/1040] arm64: dts: marvell: armada-ap810: Fix GICv3 ITS node name The GICv3 ITS is an MSI controller, therefore its node name should be 'msi-controller'. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230207234735.201812-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi index 8107d120a8a7..2f9ab6b4a2c9 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi @@ -54,7 +54,7 @@ <0x00d0000 0x1000>, /* GICH */ <0x00e0000 0x2000>; /* GICV */ - gic_its_ap0: interrupt-controller@3040000 { + gic_its_ap0: msi-controller@3040000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; From 28c8f2189d80c8b37068c367e9864b5aa530f208 Mon Sep 17 00:00:00 2001 From: Nitin Yadav Date: Thu, 2 Feb 2023 14:29:17 +0530 Subject: [PATCH 0217/1040] arm64: dts: ti: k3-am62-main: Fix GPIO numbers in DT Fix number of gpio pins in main_gpio0 & main_gpio1 DT nodes according to AM62x SK datasheet. The Link of datasheet is in the following line: https://www.ti.com/lit/ds/symlink/am625.pdf?ts=1673852494660 Section: 6.3.10 GPIO (Page No. 63-67) Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Nitin Yadav Signed-off-by: Nishanth Menon Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230202085917.3044567-1-n-yadav@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index ea683fd77d6a..a143ea5e78a5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -461,7 +461,7 @@ <193>, <194>, <195>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <87>; + ti,ngpio = <92>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 77 0>; @@ -478,7 +478,7 @@ <183>, <184>, <185>; interrupt-controller; #interrupt-cells = <2>; - ti,ngpio = <88>; + ti,ngpio = <52>; ti,davinci-gpio-unbanked = <0>; power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 78 0>; From a1bc0d6084dba8a31831c65318a8a8e46f00906f Mon Sep 17 00:00:00 2001 From: Devarsh Thakkar Date: Tue, 14 Mar 2023 15:16:45 +0530 Subject: [PATCH 0218/1040] arm64: dts: ti: k3-am62a7-sk: Fix DDR size to full 4GB All revisions of AM62A7-SK board have 4GB LPDDR4 Micron MT53E2G32D4DE-046 AUT:B memory. Commit 38c4a08c820c ("arm64: dts: ti: Add support for AM62A7-SK") enabled just 2GB due to a schematics error in early revision of the board. Fix it by enabling full 4GB available on the platform. Design docs: https://www.ti.com/lit/zip/sprr459 Fixes: 38c4a08c820c ("arm64: dts: ti: Add support for AM62A7-SK") Signed-off-by: Devarsh Thakkar Signed-off-by: Nishanth Menon Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230314094645.3411599-1-devarsht@ti.com --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 5c9012141ee2..f6a67f072dca 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -27,8 +27,9 @@ memory@80000000 { device_type = "memory"; - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + /* 4G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; }; reserved-memory { From 4f4b30a777d3e61603119297965343a37be36435 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Fri, 3 Feb 2023 13:07:24 +0530 Subject: [PATCH 0219/1040] arm64: dts: ti: k3-j721e-main: Remove ti,strobe-sel property According to latest errata of J721e [1], (i2024) 'MMCSD: Peripherals Do Not Support HS400' which applies to MMCSD0 subsystem. Speed modes supported has been already updated but missed dropping 'ti,strobe-sel' property which is only required by HS400 speed mode. Thus, drop 'ti,strobe-sel' property from kernel dtsi for J721e SoC. [1] https://www.ti.com/lit/er/sprz455/sprz455.pdf Fixes: eb8f6194e807 ("arm64: dts: ti: k3-j721e-main: Update the speed modes supported and their itap delay values for MMCSD subsystems") Signed-off-by: Bhavya Kapoor Signed-off-by: Nishanth Menon Reviewed-by: Diwakar Dhyani Reviewed-by: Nitin Yadav Link: https://lore.kernel.org/r/20230203073724.29529-1-b-kapoor@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index c935622f0102..bfa296dce3a3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1180,7 +1180,6 @@ ti,itap-del-sel-mmc-hs = <0xa>; ti,itap-del-sel-ddr52 = <0x3>; ti,trm-icp = <0x8>; - ti,strobe-sel = <0x77>; dma-coherent; }; From 436b288687176bf4d2c1cd25b86173e5a1649a60 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 14 Mar 2023 20:56:10 +0530 Subject: [PATCH 0220/1040] arm64: dts: ti: k3-j784s4-*: Add 'ti,sci-dev-id' for NAVSS nodes TISCI device ID for main_navss and mcu_navss nodes are missing in the device tree. Add them. Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Jayesh Choudhary Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 7edf324ac159..80a1b08c51a8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -398,6 +398,7 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; + ti,sci-dev-id = <280>; dma-coherent; dma-ranges; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 93952af618f6..64bd3dee14aa 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -209,6 +209,7 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; + ti,sci-dev-id = <323>; dma-coherent; dma-ranges; From a9c6a1fcc338f4d97c87a3487b371652edba00c5 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:24 -0600 Subject: [PATCH 0221/1040] soc: sunxi: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Reviewed-by: Jernej Skrabec Reviewed-by: Andre Przywara Link: https://lore.kernel.org/r/20230310144724.1545223-1-robh@kernel.org Signed-off-by: Jernej Skrabec --- drivers/soc/sunxi/sunxi_mbus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/sunxi/sunxi_mbus.c b/drivers/soc/sunxi/sunxi_mbus.c index d90e4a264b6f..1734da357ca2 100644 --- a/drivers/soc/sunxi/sunxi_mbus.c +++ b/drivers/soc/sunxi/sunxi_mbus.c @@ -82,7 +82,7 @@ static int sunxi_mbus_notifier(struct notifier_block *nb, * Older DTs or SoCs who are not clearly understood need to set * that DMA offset though. */ - if (of_find_property(dev->of_node, "interconnects", NULL)) + if (of_property_present(dev->of_node, "interconnects")) return NOTIFY_DONE; ret = dma_direct_set_offset(dev, PHYS_OFFSET, 0, SZ_4G); From 9ebdff9aac5ded7bb515e80478afacaaa3abd799 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 31 Dec 2022 16:01:45 -0600 Subject: [PATCH 0222/1040] riscv: dts: allwinner: d1: Add crypto engine node D1 contains a crypto engine which is supported by the sun8i-ce driver. Signed-off-by: Samuel Holland Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20221231220146.646-4-samuel@sholland.org Signed-off-by: Jernej Skrabec --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 6fadcee7800f..951810d46307 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -367,6 +367,18 @@ #size-cells = <1>; }; + crypto: crypto@3040000 { + compatible = "allwinner,sun20i-d1-crypto"; + reg = <0x3040000 0x800>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, + <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, + <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + }; + mbus: dram-controller@3102000 { compatible = "allwinner,sun20i-d1-mbus"; reg = <0x3102000 0x1000>, From 23ca1dd442249727abed6ac523b37d737ea5bdc0 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 28 Feb 2023 11:41:12 +0000 Subject: [PATCH 0223/1040] arm64: dts: allwinner: h5: OrangePi PC2: add OPP table to enable DVFS So far the OrangePi PC2 board was running at a fixed frequency, set by U-Boot to 816 MHz, which is the best achievable frequency at the 1.1V CPU voltage provided by the PMIC at reset. We already describe the CPU voltage regulator in the DT, but were missing the OPP table. Just include the default H5 OPP table, as used by other boards. My OrangePi PC2 runs just fine with those values, and now goes up to 1.15 GHz. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230228114112.3340715-1-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index b5c1ff19b4c4..ce3ae19e72db 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" +#include "sun50i-h5-cpu-opp.dtsi" #include #include From c014377bd053fad2f42b39626939560df1d5fc7d Mon Sep 17 00:00:00 2001 From: Nick Alcock Date: Fri, 17 Feb 2023 14:10:47 +0000 Subject: [PATCH 0224/1040] kbuild, soc: sunxi: sram: remove MODULE_LICENSE in non-modules Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Luis Chamberlain Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa Cc: Chen-Yu Tsai Cc: Jernej Skrabec Cc: Samuel Holland Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230217141059.392471-13-nick.alcock@oracle.com Signed-off-by: Jernej Skrabec --- drivers/soc/sunxi/sunxi_sram.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index f09918c59042..4c4864cd2342 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -424,4 +424,3 @@ builtin_platform_driver_probe(sunxi_sram_driver, sunxi_sram_probe); MODULE_AUTHOR("Maxime Ripard "); MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver"); -MODULE_LICENSE("GPL"); From fce449f5ba9735a80a83fe636e0d6507902084a0 Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 9 Feb 2023 21:51:32 -0500 Subject: [PATCH 0225/1040] riscv: dts: nezha-d1: add gpio-line-names Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics. Signed-off-by: Trevor Woerner Link: http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230210025132.36605-2-twoerner@gmail.com Signed-off-by: Jernej Skrabec --- .../boot/dts/allwinner/sun20i-d1-nezha.dts | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts index a0769185be97..4ed33c1e7c9c 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -1,6 +1,25 @@ // SPDX-License-Identifier: (GPL-2.0+ or MIT) // Copyright (C) 2021-2022 Samuel Holland +/* + * gpio line names + * + * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed + * directly to pads on the SoC, others come from an 8-bit pcf857x IO + * expander. Therefore, these line names are specified in two places: + * one set for the pcf857x, and one set for the pio controller. + * + * Lines which are routed to the 40-pin header are named as follows: + * [] + * where: + * is the actual pin number of the 40-pin header + * is the name of the pin by function/gpio# + * + * For details regarding pin numbers and names see the schematics (under + * "IO EXPAND"): + * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf + */ + #include #include @@ -90,6 +109,15 @@ gpio-controller; #gpio-cells = <2>; #interrupt-cells = <2>; + gpio-line-names = + "pin13 [gpio8]", + "pin16 [gpio10]", + "pin18 [gpio11]", + "pin26 [gpio17]", + "pin22 [gpio14]", + "pin28 [gpio19]", + "pin37 [gpio23]", + "pin11 [gpio6]"; }; }; @@ -164,3 +192,47 @@ usb1_vbus-supply = <®_vcc>; status = "okay"; }; + +&pio { + gpio-line-names = + /* Port A */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* Port B */ + "pin5 [gpio2/twi2-sck]", + "pin3 [gpio1/twi2-sda]", + "", + "pin38 [gpio24/i2s2-din]", + "pin40 [gpio25/i2s2-dout]", + "pin12 [gpio7/i2s-clk]", + "pin35 [gpio22/i2s2-lrck]", + "", + "pin8 [gpio4/uart0-txd]", + "pin10 [gpio5/uart0-rxd]", + "", + "", + "pin15 [gpio9]", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* Port C */ + "", + "pin31 [gpio21]", + "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* Port D */ + "", "", "", "", "", "", "", "", + "", "", + "pin24 [gpio16/spi1-ce0]", + "pin23 [gpio15/spi1-clk]", + "pin19 [gpio12/spi1-mosi]", + "pin21 [gpio13/spi1-miso]", + "pin27 [gpio18/spi1-hold]", + "pin29 [gpio20/spi1-wp]", + "", "", "", "", "", "", + "pin7 [gpio3/pwm]"; +}; From 47600f84a8bfe4c57e3bd9ed928c14e957679c8a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 7 Feb 2023 17:47:09 -0600 Subject: [PATCH 0226/1040] arm64: dts: broadcom: stringray: Fix GICv3 ITS node name The GICv3 ITS is an MSI controller, therefore its node name should be 'msi-controller'. While we're here, fix the unit-address which shouldn't have a comma. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230207234709.201229-1-robh@kernel.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index a9186166c068..388424b3e1d3 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -178,7 +178,7 @@ <0x02e00000 0x600000>; /* GICR */ interrupts = ; - gic_its: gic-its@63c20000 { + gic_its: msi-controller@63c20000 { compatible = "arm,gic-v3-its"; msi-controller; #msi-cells = <1>; From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001 From: William Zhang Date: Mon, 6 Feb 2023 22:58:15 -0800 Subject: [PATCH 0227/1040] arm64: dts: broadcom: bcmbca: Add spi controller node Add support for HSSPI controller in ARMv8 chip dts files. Signed-off-by: William Zhang Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 18 +++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 20 +++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 19 ++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 19 ++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 20 +++++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 18 +++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 18 +++++++++++++++++ .../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++ .../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++ 14 files changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index eb2a78f4e033..fc96ee7ab39d 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -107,6 +107,12 @@ clock-frequency = <50000000>; clock-output-names = "periph"; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; soc { @@ -531,6 +537,18 @@ #size-cells = <0>; }; + hsspi: spi@1000{ + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + nand-controller@1800 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi index d5bc31980f03..46aa8c0b7971 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi @@ -79,6 +79,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -86,6 +87,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -117,6 +124,19 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi index 6f805266d3c9..7020f2e995e2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi @@ -60,6 +60,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -67,6 +68,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -99,6 +106,18 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi index b982249b80a2..6a0242cbea57 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi @@ -79,6 +79,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -86,6 +87,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -117,6 +124,18 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi index a996d436e977..1a12905266ef 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi @@ -79,6 +79,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -86,6 +87,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -117,6 +124,19 @@ #size-cells = <1>; ranges = <0x0 0x0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi index 62c530d4b103..f41ebc30666f 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi @@ -60,6 +60,12 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -100,5 +106,17 @@ clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi index 34c7b513d363..fa2688f41f06 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi @@ -78,6 +78,12 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -137,5 +143,17 @@ clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts index fcbd3c430ace..c4e6e71f6310 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts index a3623e6f6919..e69cd683211a 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts index e39f1e6d4774..db2c82d6dfd8 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts index eba07e0b1ca6..25c12bc63545 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts index af17091ae764..faba21f03120 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts index 032aeb75c983..9808331eede2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts index 0cbf582f5d54..1f561c8e13b0 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; From 7858dded8c1e983740b46857660526575583d2a2 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Mon, 6 Feb 2023 22:58:14 -0800 Subject: [PATCH 0228/1040] ARM: dts: broadcom: bcmbca: Add spi controller node Add support for HSSPI controller in ARMv7 chip dts files. Signed-off-by: William Zhang Link: https://lore.kernel.org/r/20230207065826.285013-4-william.zhang@broadcom.com Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm47622.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm63138.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm63148.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm63178.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/bcm6756.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/bcm6846.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm6855.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/bcm6878.dtsi | 19 +++++++++++++++++++ arch/arm/boot/dts/bcm947622.dts | 4 ++++ arch/arm/boot/dts/bcm963138.dts | 4 ++++ arch/arm/boot/dts/bcm963138dvt.dts | 4 ++++ arch/arm/boot/dts/bcm963148.dts | 4 ++++ arch/arm/boot/dts/bcm963178.dts | 4 ++++ arch/arm/boot/dts/bcm96756.dts | 4 ++++ arch/arm/boot/dts/bcm96846.dts | 4 ++++ arch/arm/boot/dts/bcm96855.dts | 4 ++++ arch/arm/boot/dts/bcm96878.dts | 4 ++++ 17 files changed, 184 insertions(+) diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi index f4b2db9bc4ab..cd25ed2757b7 100644 --- a/arch/arm/boot/dts/bcm47622.dtsi +++ b/arch/arm/boot/dts/bcm47622.dtsi @@ -88,6 +88,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -119,6 +125,18 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm47622-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi index b774a8d63813..93281c47c9ba 100644 --- a/arch/arm/boot/dts/bcm63138.dtsi +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -66,6 +66,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; /* ARM bus */ @@ -203,6 +209,18 @@ status = "disabled"; }; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63138-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + nand_controller: nand-controller@2000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi index 7cd55d64de71..ba7f265db121 100644 --- a/arch/arm/boot/dts/bcm63148.dtsi +++ b/arch/arm/boot/dts/bcm63148.dtsi @@ -60,6 +60,12 @@ #clock-cells = <0>; clock-frequency = <50000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -100,5 +106,17 @@ clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index 043e699cbc27..d8268a1e889b 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -71,6 +71,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -78,6 +79,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -109,6 +116,18 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm63178-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi index 5c72219bc194..49ecc1f0c18c 100644 --- a/arch/arm/boot/dts/bcm6756.dtsi +++ b/arch/arm/boot/dts/bcm6756.dtsi @@ -88,6 +88,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -119,6 +125,19 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index 81513a793815..fbc7d3a5dc5f 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -61,6 +61,12 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; psci { @@ -100,5 +106,17 @@ clock-names = "refclk"; status = "disabled"; }; + + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6846-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi index 5fa5feac0e29..5e0fe26530f1 100644 --- a/arch/arm/boot/dts/bcm6855.dtsi +++ b/arch/arm/boot/dts/bcm6855.dtsi @@ -78,6 +78,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -109,6 +115,19 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6855-hsspi", "brcm,bcmbca-hsspi-v1.1"; + reg = <0x1000 0x600>, <0x2610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi index 4ec836ac4baf..96529d3d4dc2 100644 --- a/arch/arm/boot/dts/bcm6878.dtsi +++ b/arch/arm/boot/dts/bcm6878.dtsi @@ -61,6 +61,7 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + uart_clk: uart-clk { compatible = "fixed-factor-clock"; #clock-cells = <0>; @@ -68,6 +69,12 @@ clock-div = <4>; clock-mult = <1>; }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; }; psci { @@ -100,6 +107,18 @@ #size-cells = <1>; ranges = <0 0xff800000 0x800000>; + hsspi: spi@1000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0"; + reg = <0x1000 0x600>; + interrupts = ; + clocks = <&hsspi_pll &hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + status = "disabled"; + }; + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x12000 0x1000>; diff --git a/arch/arm/boot/dts/bcm947622.dts b/arch/arm/boot/dts/bcm947622.dts index 6f083724ab8e..93b8ce22678d 100644 --- a/arch/arm/boot/dts/bcm947622.dts +++ b/arch/arm/boot/dts/bcm947622.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963138.dts b/arch/arm/boot/dts/bcm963138.dts index d28c4f130ca2..1b405c249213 100644 --- a/arch/arm/boot/dts/bcm963138.dts +++ b/arch/arm/boot/dts/bcm963138.dts @@ -25,3 +25,7 @@ &serial0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts index 15bec75be74c..b5af61853a07 100644 --- a/arch/arm/boot/dts/bcm963138dvt.dts +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -50,3 +50,7 @@ &sata_phy { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963148.dts b/arch/arm/boot/dts/bcm963148.dts index 98f6a6d09f50..1f5d6d783f09 100644 --- a/arch/arm/boot/dts/bcm963148.dts +++ b/arch/arm/boot/dts/bcm963148.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts index fa096e9cde23..d036e99dd8d1 100644 --- a/arch/arm/boot/dts/bcm963178.dts +++ b/arch/arm/boot/dts/bcm963178.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96756.dts b/arch/arm/boot/dts/bcm96756.dts index 9a4a87ba9c8a..8b104f3fb14a 100644 --- a/arch/arm/boot/dts/bcm96756.dts +++ b/arch/arm/boot/dts/bcm96756.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96846.dts b/arch/arm/boot/dts/bcm96846.dts index c70ebccabc19..55852c229608 100644 --- a/arch/arm/boot/dts/bcm96846.dts +++ b/arch/arm/boot/dts/bcm96846.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96855.dts b/arch/arm/boot/dts/bcm96855.dts index 4438152561ac..2ad880af2104 100644 --- a/arch/arm/boot/dts/bcm96855.dts +++ b/arch/arm/boot/dts/bcm96855.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm96878.dts b/arch/arm/boot/dts/bcm96878.dts index 8fbc175cb452..b7af8ade7a9d 100644 --- a/arch/arm/boot/dts/bcm96878.dts +++ b/arch/arm/boot/dts/bcm96878.dts @@ -28,3 +28,7 @@ &uart0 { status = "okay"; }; + +&hsspi { + status = "okay"; +}; From 9cf38a0914f0891e43bf88dcbb704d18dc5d4b21 Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Wed, 8 Feb 2023 15:37:15 +0800 Subject: [PATCH 0229/1040] =?UTF-8?q?bus:=20brcmstb=5Fgisb:=20Use=C2=A0dev?= =?UTF-8?q?m=5Fplatform=5Fget=5Fand=5Fioremap=5Fresource()?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Ye Xingchen Link: https://lore.kernel.org/r/202302081537158530029@zte.com.cn Signed-off-by: Florian Fainelli --- drivers/bus/brcmstb_gisb.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c index b0c3704777e9..b6dfe4340da2 100644 --- a/drivers/bus/brcmstb_gisb.c +++ b/drivers/bus/brcmstb_gisb.c @@ -401,12 +401,10 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev) struct device_node *dn = pdev->dev.of_node; struct brcmstb_gisb_arb_device *gdev; const struct of_device_id *of_id; - struct resource *r; int err, timeout_irq, tea_irq, bp_irq; unsigned int num_masters, j = 0; int i, first, last; - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); timeout_irq = platform_get_irq(pdev, 0); tea_irq = platform_get_irq(pdev, 1); bp_irq = platform_get_irq(pdev, 2); @@ -418,7 +416,7 @@ static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev) mutex_init(&gdev->lock); INIT_LIST_HEAD(&gdev->next); - gdev->base = devm_ioremap_resource(&pdev->dev, r); + gdev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(gdev->base)) return PTR_ERR(gdev->base); From 89cc9abe55dfb24647f3730ad218adc1bfad27ac Mon Sep 17 00:00:00 2001 From: Nick Alcock Date: Wed, 22 Feb 2023 12:14:30 +0000 Subject: [PATCH 0230/1040] kbuild, soc: bcm: raspberrypi-power: remove MODULE_LICENSE in non-modules Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Luis Chamberlain Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa Cc: Florian Fainelli Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Florian Fainelli --- drivers/soc/bcm/raspberrypi-power.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/bcm/raspberrypi-power.c b/drivers/soc/bcm/raspberrypi-power.c index 068715d6e66d..58175af982a0 100644 --- a/drivers/soc/bcm/raspberrypi-power.c +++ b/drivers/soc/bcm/raspberrypi-power.c @@ -243,4 +243,3 @@ builtin_platform_driver(rpi_power_driver); MODULE_AUTHOR("Alexander Aring "); MODULE_AUTHOR("Eric Anholt "); MODULE_DESCRIPTION("Raspberry Pi power domain driver"); -MODULE_LICENSE("GPL v2"); From 122b084d16bda75de74421ede63cb86a24289808 Mon Sep 17 00:00:00 2001 From: Nick Alcock Date: Wed, 22 Feb 2023 12:14:31 +0000 Subject: [PATCH 0231/1040] kbuild, soc: bcm: bcm2835-power: remove MODULE_LICENSE in non-modules Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Luis Chamberlain Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa Cc: Florian Fainelli Cc: Ray Jui Cc: Scott Branden Cc: Philipp Zabel Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Florian Fainelli --- drivers/soc/bcm/bcm2835-power.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/bcm/bcm2835-power.c b/drivers/soc/bcm/bcm2835-power.c index bf51f03f77d6..1a179d4e011c 100644 --- a/drivers/soc/bcm/bcm2835-power.c +++ b/drivers/soc/bcm/bcm2835-power.c @@ -711,4 +711,3 @@ module_platform_driver(bcm2835_power_driver); MODULE_AUTHOR("Eric Anholt "); MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM power domains and reset"); -MODULE_LICENSE("GPL"); From 69160dd0aa6832b98d272c1a224b1aaf67cf843d Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 24 Feb 2023 13:52:39 -0800 Subject: [PATCH 0232/1040] soc: bcm: brcmstb: Remove bare-metal ARM suspend/resume code Since 2018 these platforms have supported entry via the ARM Trusted Firmware using the standard PSCI SYSTEM_SUSPEND function calls. Remove this legacy code. Link: https://lore.kernel.org/r/20230224215249.239405-1-f.fainelli@gmail.com Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/Kconfig | 4 +- drivers/soc/bcm/brcmstb/pm/Makefile | 1 - drivers/soc/bcm/brcmstb/pm/aon_defs.h | 105 ---- drivers/soc/bcm/brcmstb/pm/pm-arm.c | 874 -------------------------- drivers/soc/bcm/brcmstb/pm/s2-arm.S | 69 -- 5 files changed, 1 insertion(+), 1052 deletions(-) delete mode 100644 drivers/soc/bcm/brcmstb/pm/aon_defs.h delete mode 100644 drivers/soc/bcm/brcmstb/pm/pm-arm.c delete mode 100644 drivers/soc/bcm/brcmstb/pm/s2-arm.S diff --git a/drivers/soc/bcm/brcmstb/Kconfig b/drivers/soc/bcm/brcmstb/Kconfig index 38e476905d96..c68d0e5267c4 100644 --- a/drivers/soc/bcm/brcmstb/Kconfig +++ b/drivers/soc/bcm/brcmstb/Kconfig @@ -4,8 +4,6 @@ if SOC_BRCMSTB config BRCMSTB_PM bool "Support suspend/resume for STB platforms" default y - depends on PM - depends on ARCH_BRCMSTB || BMIPS_GENERIC - select ARM_CPU_SUSPEND if ARM + depends on PM && BMIPS_GENERIC endif # SOC_BRCMSTB diff --git a/drivers/soc/bcm/brcmstb/pm/Makefile b/drivers/soc/bcm/brcmstb/pm/Makefile index f849cfa69446..9133a9ee0782 100644 --- a/drivers/soc/bcm/brcmstb/pm/Makefile +++ b/drivers/soc/bcm/brcmstb/pm/Makefile @@ -1,3 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_ARM) += s2-arm.o pm-arm.o obj-$(CONFIG_BMIPS_GENERIC) += s2-mips.o s3-mips.o pm-mips.o diff --git a/drivers/soc/bcm/brcmstb/pm/aon_defs.h b/drivers/soc/bcm/brcmstb/pm/aon_defs.h deleted file mode 100644 index f695262ac930..000000000000 --- a/drivers/soc/bcm/brcmstb/pm/aon_defs.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Always ON (AON) register interface between bootloader and Linux - * - * Copyright © 2014-2017 Broadcom - */ - -#ifndef __BRCMSTB_AON_DEFS_H__ -#define __BRCMSTB_AON_DEFS_H__ - -#include - -/* Magic number in upper 16-bits */ -#define BRCMSTB_S3_MAGIC_MASK 0xffff0000 -#define BRCMSTB_S3_MAGIC_SHORT 0x5AFE0000 - -enum { - /* Restore random key for AES memory verification (off = fixed key) */ - S3_FLAG_LOAD_RANDKEY = (1 << 0), - - /* Scratch buffer page table is present */ - S3_FLAG_SCRATCH_BUFFER_TABLE = (1 << 1), - - /* Skip all memory verification */ - S3_FLAG_NO_MEM_VERIFY = (1 << 2), - - /* - * Modification of this bit reserved for bootloader only. - * 1=PSCI started Linux, 0=Direct jump to Linux. - */ - S3_FLAG_PSCI_BOOT = (1 << 3), - - /* - * Modification of this bit reserved for bootloader only. - * 1=64 bit boot, 0=32 bit boot. - */ - S3_FLAG_BOOTED64 = (1 << 4), -}; - -#define BRCMSTB_HASH_LEN (128 / 8) /* 128-bit hash */ - -#define AON_REG_MAGIC_FLAGS 0x00 -#define AON_REG_CONTROL_LOW 0x04 -#define AON_REG_CONTROL_HIGH 0x08 -#define AON_REG_S3_HASH 0x0c /* hash of S3 params */ -#define AON_REG_CONTROL_HASH_LEN 0x1c -#define AON_REG_PANIC 0x20 - -#define BRCMSTB_S3_MAGIC 0x5AFEB007 -#define BRCMSTB_PANIC_MAGIC 0x512E115E -#define BOOTLOADER_SCRATCH_SIZE 64 -#define BRCMSTB_DTU_STATE_MAP_ENTRIES (8*1024) -#define BRCMSTB_DTU_CONFIG_ENTRIES (512) -#define BRCMSTB_DTU_COUNT (2) - -#define IMAGE_DESCRIPTORS_BUFSIZE (2 * 1024) -#define S3_BOOTLOADER_RESERVED (S3_FLAG_PSCI_BOOT | S3_FLAG_BOOTED64) - -struct brcmstb_bootloader_dtu_table { - uint32_t dtu_state_map[BRCMSTB_DTU_STATE_MAP_ENTRIES]; - uint32_t dtu_config[BRCMSTB_DTU_CONFIG_ENTRIES]; -}; - -/* - * Bootloader utilizes a custom parameter block left in DRAM for handling S3 - * warm resume - */ -struct brcmstb_s3_params { - /* scratch memory for bootloader */ - uint8_t scratch[BOOTLOADER_SCRATCH_SIZE]; - - uint32_t magic; /* BRCMSTB_S3_MAGIC */ - uint64_t reentry; /* PA */ - - /* descriptors */ - uint32_t hash[BRCMSTB_HASH_LEN / 4]; - - /* - * If 0, then ignore this parameter (there is only one set of - * descriptors) - * - * If non-0, then a second set of descriptors is stored at: - * - * descriptors + desc_offset_2 - * - * The MAC result of both descriptors is XOR'd and stored in @hash - */ - uint32_t desc_offset_2; - - /* - * (Physical) address of a brcmstb_bootloader_scratch_table, for - * providing a large DRAM buffer to the bootloader - */ - uint64_t buffer_table; - - uint32_t spare[70]; - - uint8_t descriptors[IMAGE_DESCRIPTORS_BUFSIZE]; - /* - * Must be last member of struct. See brcmstb_pm_s3_finish() for reason. - */ - struct brcmstb_bootloader_dtu_table dtu[BRCMSTB_DTU_COUNT]; -} __packed; - -#endif /* __BRCMSTB_AON_DEFS_H__ */ diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c deleted file mode 100644 index d681cd24c6e1..000000000000 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ /dev/null @@ -1,874 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ARM-specific support for Broadcom STB S2/S3/S5 power management - * - * S2: clock gate CPUs and as many peripherals as possible - * S3: power off all of the chip except the Always ON (AON) island; keep DDR is - * self-refresh - * S5: (a.k.a. S3 cold boot) much like S3, except DDR is powered down, so we - * treat this mode like a soft power-off, with wakeup allowed from AON - * - * Copyright © 2014-2017 Broadcom - */ - -#define pr_fmt(fmt) "brcmstb-pm: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "pm.h" -#include "aon_defs.h" - -#define SHIMPHY_DDR_PAD_CNTRL 0x8c - -/* Method #0 */ -#define SHIMPHY_PAD_PLL_SEQUENCE BIT(8) -#define SHIMPHY_PAD_GATE_PLL_S3 BIT(9) - -/* Method #1 */ -#define PWRDWN_SEQ_NO_SEQUENCING 0 -#define PWRDWN_SEQ_HOLD_CHANNEL 1 -#define PWRDWN_SEQ_RESET_PLL 2 -#define PWRDWN_SEQ_POWERDOWN_PLL 3 - -#define SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK 0x00f00000 -#define SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT 20 - -#define DDR_FORCE_CKE_RST_N BIT(3) -#define DDR_PHY_RST_N BIT(2) -#define DDR_PHY_CKE BIT(1) - -#define DDR_PHY_NO_CHANNEL 0xffffffff - -#define MAX_NUM_MEMC 3 - -struct brcmstb_memc { - void __iomem *ddr_phy_base; - void __iomem *ddr_shimphy_base; - void __iomem *ddr_ctrl; -}; - -struct brcmstb_pm_control { - void __iomem *aon_ctrl_base; - void __iomem *aon_sram; - struct brcmstb_memc memcs[MAX_NUM_MEMC]; - - void __iomem *boot_sram; - size_t boot_sram_len; - - bool support_warm_boot; - size_t pll_status_offset; - int num_memc; - - struct brcmstb_s3_params *s3_params; - dma_addr_t s3_params_pa; - int s3entry_method; - u32 warm_boot_offset; - u32 phy_a_standby_ctrl_offs; - u32 phy_b_standby_ctrl_offs; - bool needs_ddr_pad; - struct platform_device *pdev; -}; - -enum bsp_initiate_command { - BSP_CLOCK_STOP = 0x00, - BSP_GEN_RANDOM_KEY = 0x4A, - BSP_RESTORE_RANDOM_KEY = 0x55, - BSP_GEN_FIXED_KEY = 0x63, -}; - -#define PM_INITIATE 0x01 -#define PM_INITIATE_SUCCESS 0x00 -#define PM_INITIATE_FAIL 0xfe - -static struct brcmstb_pm_control ctrl; - -noinline int brcmstb_pm_s3_finish(void); - -static int (*brcmstb_pm_do_s2_sram)(void __iomem *aon_ctrl_base, - void __iomem *ddr_phy_pll_status); - -static int brcmstb_init_sram(struct device_node *dn) -{ - void __iomem *sram; - struct resource res; - int ret; - - ret = of_address_to_resource(dn, 0, &res); - if (ret) - return ret; - - /* Uncached, executable remapping of SRAM */ - sram = __arm_ioremap_exec(res.start, resource_size(&res), false); - if (!sram) - return -ENOMEM; - - ctrl.boot_sram = sram; - ctrl.boot_sram_len = resource_size(&res); - - return 0; -} - -static const struct of_device_id sram_dt_ids[] = { - { .compatible = "mmio-sram" }, - { /* sentinel */ } -}; - -static int do_bsp_initiate_command(enum bsp_initiate_command cmd) -{ - void __iomem *base = ctrl.aon_ctrl_base; - int ret; - int timeo = 1000 * 1000; /* 1 second */ - - writel_relaxed(0, base + AON_CTRL_PM_INITIATE); - (void)readl_relaxed(base + AON_CTRL_PM_INITIATE); - - /* Go! */ - writel_relaxed((cmd << 1) | PM_INITIATE, base + AON_CTRL_PM_INITIATE); - - /* - * If firmware doesn't support the 'ack', then just assume it's done - * after 10ms. Note that this only works for command 0, BSP_CLOCK_STOP - */ - if (of_machine_is_compatible("brcm,bcm74371a0")) { - (void)readl_relaxed(base + AON_CTRL_PM_INITIATE); - mdelay(10); - return 0; - } - - for (;;) { - ret = readl_relaxed(base + AON_CTRL_PM_INITIATE); - if (!(ret & PM_INITIATE)) - break; - if (timeo <= 0) { - pr_err("error: timeout waiting for BSP (%x)\n", ret); - break; - } - timeo -= 50; - udelay(50); - } - - return (ret & 0xff) != PM_INITIATE_SUCCESS; -} - -static int brcmstb_pm_handshake(void) -{ - void __iomem *base = ctrl.aon_ctrl_base; - u32 tmp; - int ret; - - /* BSP power handshake, v1 */ - tmp = readl_relaxed(base + AON_CTRL_HOST_MISC_CMDS); - tmp &= ~1UL; - writel_relaxed(tmp, base + AON_CTRL_HOST_MISC_CMDS); - (void)readl_relaxed(base + AON_CTRL_HOST_MISC_CMDS); - - ret = do_bsp_initiate_command(BSP_CLOCK_STOP); - if (ret) - pr_err("BSP handshake failed\n"); - - /* - * HACK: BSP may have internal race on the CLOCK_STOP command. - * Avoid touching the BSP for a few milliseconds. - */ - mdelay(3); - - return ret; -} - -static inline void shimphy_set(u32 value, u32 mask) -{ - int i; - - if (!ctrl.needs_ddr_pad) - return; - - for (i = 0; i < ctrl.num_memc; i++) { - u32 tmp; - - tmp = readl_relaxed(ctrl.memcs[i].ddr_shimphy_base + - SHIMPHY_DDR_PAD_CNTRL); - tmp = value | (tmp & mask); - writel_relaxed(tmp, ctrl.memcs[i].ddr_shimphy_base + - SHIMPHY_DDR_PAD_CNTRL); - } - wmb(); /* Complete sequence in order. */ -} - -static inline void ddr_ctrl_set(bool warmboot) -{ - int i; - - for (i = 0; i < ctrl.num_memc; i++) { - u32 tmp; - - tmp = readl_relaxed(ctrl.memcs[i].ddr_ctrl + - ctrl.warm_boot_offset); - if (warmboot) - tmp |= 1; - else - tmp &= ~1; /* Cold boot */ - writel_relaxed(tmp, ctrl.memcs[i].ddr_ctrl + - ctrl.warm_boot_offset); - } - /* Complete sequence in order */ - wmb(); -} - -static inline void s3entry_method0(void) -{ - shimphy_set(SHIMPHY_PAD_GATE_PLL_S3 | SHIMPHY_PAD_PLL_SEQUENCE, - 0xffffffff); -} - -static inline void s3entry_method1(void) -{ - /* - * S3 Entry Sequence - * ----------------- - * Step 1: SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL [ S3_PWRDWN_SEQ ] = 3 - * Step 2: MEMC_DDR_0_WARM_BOOT [ WARM_BOOT ] = 1 - */ - shimphy_set((PWRDWN_SEQ_POWERDOWN_PLL << - SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), - ~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); - - ddr_ctrl_set(true); -} - -static inline void s5entry_method1(void) -{ - int i; - - /* - * S5 Entry Sequence - * ----------------- - * Step 1: SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL [ S3_PWRDWN_SEQ ] = 3 - * Step 2: MEMC_DDR_0_WARM_BOOT [ WARM_BOOT ] = 0 - * Step 3: DDR_PHY_CONTROL_REGS_[AB]_0_STANDBY_CONTROL[ CKE ] = 0 - * DDR_PHY_CONTROL_REGS_[AB]_0_STANDBY_CONTROL[ RST_N ] = 0 - */ - shimphy_set((PWRDWN_SEQ_POWERDOWN_PLL << - SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), - ~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); - - ddr_ctrl_set(false); - - for (i = 0; i < ctrl.num_memc; i++) { - u32 tmp; - - /* Step 3: Channel A (RST_N = CKE = 0) */ - tmp = readl_relaxed(ctrl.memcs[i].ddr_phy_base + - ctrl.phy_a_standby_ctrl_offs); - tmp &= ~(DDR_PHY_RST_N | DDR_PHY_RST_N); - writel_relaxed(tmp, ctrl.memcs[i].ddr_phy_base + - ctrl.phy_a_standby_ctrl_offs); - - /* Step 3: Channel B? */ - if (ctrl.phy_b_standby_ctrl_offs != DDR_PHY_NO_CHANNEL) { - tmp = readl_relaxed(ctrl.memcs[i].ddr_phy_base + - ctrl.phy_b_standby_ctrl_offs); - tmp &= ~(DDR_PHY_RST_N | DDR_PHY_RST_N); - writel_relaxed(tmp, ctrl.memcs[i].ddr_phy_base + - ctrl.phy_b_standby_ctrl_offs); - } - } - /* Must complete */ - wmb(); -} - -/* - * Run a Power Management State Machine (PMSM) shutdown command and put the CPU - * into a low-power mode - */ -static void brcmstb_do_pmsm_power_down(unsigned long base_cmd, bool onewrite) -{ - void __iomem *base = ctrl.aon_ctrl_base; - - if ((ctrl.s3entry_method == 1) && (base_cmd == PM_COLD_CONFIG)) - s5entry_method1(); - - /* pm_start_pwrdn transition 0->1 */ - writel_relaxed(base_cmd, base + AON_CTRL_PM_CTRL); - - if (!onewrite) { - (void)readl_relaxed(base + AON_CTRL_PM_CTRL); - - writel_relaxed(base_cmd | PM_PWR_DOWN, base + AON_CTRL_PM_CTRL); - (void)readl_relaxed(base + AON_CTRL_PM_CTRL); - } - wfi(); -} - -/* Support S5 cold boot out of "poweroff" */ -static void brcmstb_pm_poweroff(void) -{ - brcmstb_pm_handshake(); - - /* Clear magic S3 warm-boot value */ - writel_relaxed(0, ctrl.aon_sram + AON_REG_MAGIC_FLAGS); - (void)readl_relaxed(ctrl.aon_sram + AON_REG_MAGIC_FLAGS); - - /* Skip wait-for-interrupt signal; just use a countdown */ - writel_relaxed(0x10, ctrl.aon_ctrl_base + AON_CTRL_PM_CPU_WAIT_COUNT); - (void)readl_relaxed(ctrl.aon_ctrl_base + AON_CTRL_PM_CPU_WAIT_COUNT); - - if (ctrl.s3entry_method == 1) { - shimphy_set((PWRDWN_SEQ_POWERDOWN_PLL << - SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), - ~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); - ddr_ctrl_set(false); - brcmstb_do_pmsm_power_down(M1_PM_COLD_CONFIG, true); - return; /* We should never actually get here */ - } - - brcmstb_do_pmsm_power_down(PM_COLD_CONFIG, false); -} - -static void *brcmstb_pm_copy_to_sram(void *fn, size_t len) -{ - unsigned int size = ALIGN(len, FNCPY_ALIGN); - - if (ctrl.boot_sram_len < size) { - pr_err("standby code will not fit in SRAM\n"); - return NULL; - } - - return fncpy(ctrl.boot_sram, fn, size); -} - -/* - * S2 suspend/resume picks up where we left off, so we must execute carefully - * from SRAM, in order to allow DDR to come back up safely before we continue. - */ -static int brcmstb_pm_s2(void) -{ - /* A previous S3 can set a value hazardous to S2, so make sure. */ - if (ctrl.s3entry_method == 1) { - shimphy_set((PWRDWN_SEQ_NO_SEQUENCING << - SHIMPHY_PAD_S3_PWRDWN_SEQ_SHIFT), - ~SHIMPHY_PAD_S3_PWRDWN_SEQ_MASK); - ddr_ctrl_set(false); - } - - brcmstb_pm_do_s2_sram = brcmstb_pm_copy_to_sram(&brcmstb_pm_do_s2, - brcmstb_pm_do_s2_sz); - if (!brcmstb_pm_do_s2_sram) - return -EINVAL; - - return brcmstb_pm_do_s2_sram(ctrl.aon_ctrl_base, - ctrl.memcs[0].ddr_phy_base + - ctrl.pll_status_offset); -} - -/* - * This function is called on a new stack, so don't allow inlining (which will - * generate stack references on the old stack). It cannot be made static because - * it is referenced from brcmstb_pm_s3() - */ -noinline int brcmstb_pm_s3_finish(void) -{ - struct brcmstb_s3_params *params = ctrl.s3_params; - dma_addr_t params_pa = ctrl.s3_params_pa; - phys_addr_t reentry = virt_to_phys(&cpu_resume_arm); - enum bsp_initiate_command cmd; - u32 flags; - - /* - * Clear parameter structure, but not DTU area, which has already been - * filled in. We know DTU is a the end, so we can just subtract its - * size. - */ - memset(params, 0, sizeof(*params) - sizeof(params->dtu)); - - flags = readl_relaxed(ctrl.aon_sram + AON_REG_MAGIC_FLAGS); - - flags &= S3_BOOTLOADER_RESERVED; - flags |= S3_FLAG_NO_MEM_VERIFY; - flags |= S3_FLAG_LOAD_RANDKEY; - - /* Load random / fixed key */ - if (flags & S3_FLAG_LOAD_RANDKEY) - cmd = BSP_GEN_RANDOM_KEY; - else - cmd = BSP_GEN_FIXED_KEY; - if (do_bsp_initiate_command(cmd)) { - pr_info("key loading failed\n"); - return -EIO; - } - - params->magic = BRCMSTB_S3_MAGIC; - params->reentry = reentry; - - /* No more writes to DRAM */ - flush_cache_all(); - - flags |= BRCMSTB_S3_MAGIC_SHORT; - - writel_relaxed(flags, ctrl.aon_sram + AON_REG_MAGIC_FLAGS); - writel_relaxed(lower_32_bits(params_pa), - ctrl.aon_sram + AON_REG_CONTROL_LOW); - writel_relaxed(upper_32_bits(params_pa), - ctrl.aon_sram + AON_REG_CONTROL_HIGH); - - switch (ctrl.s3entry_method) { - case 0: - s3entry_method0(); - brcmstb_do_pmsm_power_down(PM_WARM_CONFIG, false); - break; - case 1: - s3entry_method1(); - brcmstb_do_pmsm_power_down(M1_PM_WARM_CONFIG, true); - break; - default: - return -EINVAL; - } - - /* Must have been interrupted from wfi()? */ - return -EINTR; -} - -static int brcmstb_pm_do_s3(unsigned long sp) -{ - unsigned long save_sp; - int ret; - - asm volatile ( - "mov %[save], sp\n" - "mov sp, %[new]\n" - "bl brcmstb_pm_s3_finish\n" - "mov %[ret], r0\n" - "mov %[new], sp\n" - "mov sp, %[save]\n" - : [save] "=&r" (save_sp), [ret] "=&r" (ret) - : [new] "r" (sp) - ); - - return ret; -} - -static int brcmstb_pm_s3(void) -{ - void __iomem *sp = ctrl.boot_sram + ctrl.boot_sram_len; - - return cpu_suspend((unsigned long)sp, brcmstb_pm_do_s3); -} - -static int brcmstb_pm_standby(bool deep_standby) -{ - int ret; - - if (brcmstb_pm_handshake()) - return -EIO; - - if (deep_standby) - ret = brcmstb_pm_s3(); - else - ret = brcmstb_pm_s2(); - if (ret) - pr_err("%s: standby failed\n", __func__); - - return ret; -} - -static int brcmstb_pm_enter(suspend_state_t state) -{ - int ret = -EINVAL; - - switch (state) { - case PM_SUSPEND_STANDBY: - ret = brcmstb_pm_standby(false); - break; - case PM_SUSPEND_MEM: - ret = brcmstb_pm_standby(true); - break; - } - - return ret; -} - -static int brcmstb_pm_valid(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_STANDBY: - return true; - case PM_SUSPEND_MEM: - return ctrl.support_warm_boot; - default: - return false; - } -} - -static const struct platform_suspend_ops brcmstb_pm_ops = { - .enter = brcmstb_pm_enter, - .valid = brcmstb_pm_valid, -}; - -static const struct of_device_id aon_ctrl_dt_ids[] = { - { .compatible = "brcm,brcmstb-aon-ctrl" }, - {} -}; - -struct ddr_phy_ofdata { - bool supports_warm_boot; - size_t pll_status_offset; - int s3entry_method; - u32 warm_boot_offset; - u32 phy_a_standby_ctrl_offs; - u32 phy_b_standby_ctrl_offs; -}; - -static struct ddr_phy_ofdata ddr_phy_71_1 = { - .supports_warm_boot = true, - .pll_status_offset = 0x0c, - .s3entry_method = 1, - .warm_boot_offset = 0x2c, - .phy_a_standby_ctrl_offs = 0x198, - .phy_b_standby_ctrl_offs = DDR_PHY_NO_CHANNEL -}; - -static struct ddr_phy_ofdata ddr_phy_72_0 = { - .supports_warm_boot = true, - .pll_status_offset = 0x10, - .s3entry_method = 1, - .warm_boot_offset = 0x40, - .phy_a_standby_ctrl_offs = 0x2a4, - .phy_b_standby_ctrl_offs = 0x8a4 -}; - -static struct ddr_phy_ofdata ddr_phy_225_1 = { - .supports_warm_boot = false, - .pll_status_offset = 0x4, - .s3entry_method = 0 -}; - -static struct ddr_phy_ofdata ddr_phy_240_1 = { - .supports_warm_boot = true, - .pll_status_offset = 0x4, - .s3entry_method = 0 -}; - -static const struct of_device_id ddr_phy_dt_ids[] = { - { - .compatible = "brcm,brcmstb-ddr-phy-v71.1", - .data = &ddr_phy_71_1, - }, - { - .compatible = "brcm,brcmstb-ddr-phy-v72.0", - .data = &ddr_phy_72_0, - }, - { - .compatible = "brcm,brcmstb-ddr-phy-v225.1", - .data = &ddr_phy_225_1, - }, - { - .compatible = "brcm,brcmstb-ddr-phy-v240.1", - .data = &ddr_phy_240_1, - }, - { - /* Same as v240.1, for the registers we care about */ - .compatible = "brcm,brcmstb-ddr-phy-v240.2", - .data = &ddr_phy_240_1, - }, - {} -}; - -struct ddr_seq_ofdata { - bool needs_ddr_pad; - u32 warm_boot_offset; -}; - -static const struct ddr_seq_ofdata ddr_seq_b22 = { - .needs_ddr_pad = false, - .warm_boot_offset = 0x2c, -}; - -static const struct ddr_seq_ofdata ddr_seq = { - .needs_ddr_pad = true, -}; - -static const struct of_device_id ddr_shimphy_dt_ids[] = { - { .compatible = "brcm,brcmstb-ddr-shimphy-v1.0" }, - {} -}; - -static const struct of_device_id brcmstb_memc_of_match[] = { - { - .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", - .data = &ddr_seq, - }, - { - .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", - .data = &ddr_seq_b22, - }, - { - .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", - .data = &ddr_seq_b22, - }, - { - .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", - .data = &ddr_seq_b22, - }, - { - .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", - .data = &ddr_seq_b22, - }, - { - .compatible = "brcm,brcmstb-memc-ddr", - .data = &ddr_seq, - }, - {}, -}; - -static void __iomem *brcmstb_ioremap_match(const struct of_device_id *matches, - int index, const void **ofdata) -{ - struct device_node *dn; - const struct of_device_id *match; - - dn = of_find_matching_node_and_match(NULL, matches, &match); - if (!dn) - return ERR_PTR(-EINVAL); - - if (ofdata) - *ofdata = match->data; - - return of_io_request_and_map(dn, index, dn->full_name); -} -/* - * The AON is a small domain in the SoC that can retain its state across - * various system wide sleep states and specific reset conditions; the - * AON DATA RAM is a small RAM of a few words (< 1KB) which can store - * persistent information across such events. - * - * The purpose of the below panic notifier is to help with notifying - * the bootloader that a panic occurred and so that it should try its - * best to preserve the DRAM contents holding that buffer for recovery - * by the kernel as opposed to wiping out DRAM clean again. - * - * Reference: comment from Florian Fainelli, at - * https://lore.kernel.org/lkml/781cafb0-8d06-8b56-907a-5175c2da196a@gmail.com - */ -static int brcmstb_pm_panic_notify(struct notifier_block *nb, - unsigned long action, void *data) -{ - writel_relaxed(BRCMSTB_PANIC_MAGIC, ctrl.aon_sram + AON_REG_PANIC); - - return NOTIFY_DONE; -} - -static struct notifier_block brcmstb_pm_panic_nb = { - .notifier_call = brcmstb_pm_panic_notify, -}; - -static int brcmstb_pm_probe(struct platform_device *pdev) -{ - const struct ddr_phy_ofdata *ddr_phy_data; - const struct ddr_seq_ofdata *ddr_seq_data; - const struct of_device_id *of_id = NULL; - struct device_node *dn; - void __iomem *base; - int ret, i, s; - - /* AON ctrl registers */ - base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 0, NULL); - if (IS_ERR(base)) { - pr_err("error mapping AON_CTRL\n"); - ret = PTR_ERR(base); - goto aon_err; - } - ctrl.aon_ctrl_base = base; - - /* AON SRAM registers */ - base = brcmstb_ioremap_match(aon_ctrl_dt_ids, 1, NULL); - if (IS_ERR(base)) { - /* Assume standard offset */ - ctrl.aon_sram = ctrl.aon_ctrl_base + - AON_CTRL_SYSTEM_DATA_RAM_OFS; - s = 0; - } else { - ctrl.aon_sram = base; - s = 1; - } - - writel_relaxed(0, ctrl.aon_sram + AON_REG_PANIC); - - /* DDR PHY registers */ - base = brcmstb_ioremap_match(ddr_phy_dt_ids, 0, - (const void **)&ddr_phy_data); - if (IS_ERR(base)) { - pr_err("error mapping DDR PHY\n"); - ret = PTR_ERR(base); - goto ddr_phy_err; - } - ctrl.support_warm_boot = ddr_phy_data->supports_warm_boot; - ctrl.pll_status_offset = ddr_phy_data->pll_status_offset; - /* Only need DDR PHY 0 for now? */ - ctrl.memcs[0].ddr_phy_base = base; - ctrl.s3entry_method = ddr_phy_data->s3entry_method; - ctrl.phy_a_standby_ctrl_offs = ddr_phy_data->phy_a_standby_ctrl_offs; - ctrl.phy_b_standby_ctrl_offs = ddr_phy_data->phy_b_standby_ctrl_offs; - /* - * Slightly gross to use the phy ver to get a memc, - * offset but that is the only versioned things so far - * we can test for. - */ - ctrl.warm_boot_offset = ddr_phy_data->warm_boot_offset; - - /* DDR SHIM-PHY registers */ - for_each_matching_node(dn, ddr_shimphy_dt_ids) { - i = ctrl.num_memc; - if (i >= MAX_NUM_MEMC) { - of_node_put(dn); - pr_warn("too many MEMCs (max %d)\n", MAX_NUM_MEMC); - break; - } - - base = of_io_request_and_map(dn, 0, dn->full_name); - if (IS_ERR(base)) { - of_node_put(dn); - if (!ctrl.support_warm_boot) - break; - - pr_err("error mapping DDR SHIMPHY %d\n", i); - ret = PTR_ERR(base); - goto ddr_shimphy_err; - } - ctrl.memcs[i].ddr_shimphy_base = base; - ctrl.num_memc++; - } - - /* Sequencer DRAM Param and Control Registers */ - i = 0; - for_each_matching_node(dn, brcmstb_memc_of_match) { - base = of_iomap(dn, 0); - if (!base) { - of_node_put(dn); - pr_err("error mapping DDR Sequencer %d\n", i); - ret = -ENOMEM; - goto brcmstb_memc_err; - } - - of_id = of_match_node(brcmstb_memc_of_match, dn); - if (!of_id) { - iounmap(base); - of_node_put(dn); - ret = -EINVAL; - goto brcmstb_memc_err; - } - - ddr_seq_data = of_id->data; - ctrl.needs_ddr_pad = ddr_seq_data->needs_ddr_pad; - /* Adjust warm boot offset based on the DDR sequencer */ - if (ddr_seq_data->warm_boot_offset) - ctrl.warm_boot_offset = ddr_seq_data->warm_boot_offset; - - ctrl.memcs[i].ddr_ctrl = base; - i++; - } - - pr_debug("PM: supports warm boot:%d, method:%d, wboffs:%x\n", - ctrl.support_warm_boot, ctrl.s3entry_method, - ctrl.warm_boot_offset); - - dn = of_find_matching_node(NULL, sram_dt_ids); - if (!dn) { - pr_err("SRAM not found\n"); - ret = -EINVAL; - goto brcmstb_memc_err; - } - - ret = brcmstb_init_sram(dn); - of_node_put(dn); - if (ret) { - pr_err("error setting up SRAM for PM\n"); - goto brcmstb_memc_err; - } - - ctrl.pdev = pdev; - - ctrl.s3_params = kmalloc(sizeof(*ctrl.s3_params), GFP_KERNEL); - if (!ctrl.s3_params) { - ret = -ENOMEM; - goto s3_params_err; - } - ctrl.s3_params_pa = dma_map_single(&pdev->dev, ctrl.s3_params, - sizeof(*ctrl.s3_params), - DMA_TO_DEVICE); - if (dma_mapping_error(&pdev->dev, ctrl.s3_params_pa)) { - pr_err("error mapping DMA memory\n"); - ret = -ENOMEM; - goto out; - } - - atomic_notifier_chain_register(&panic_notifier_list, - &brcmstb_pm_panic_nb); - - pm_power_off = brcmstb_pm_poweroff; - suspend_set_ops(&brcmstb_pm_ops); - - return 0; - -out: - kfree(ctrl.s3_params); -s3_params_err: - iounmap(ctrl.boot_sram); -brcmstb_memc_err: - for (i--; i >= 0; i--) - iounmap(ctrl.memcs[i].ddr_ctrl); -ddr_shimphy_err: - for (i = 0; i < ctrl.num_memc; i++) - iounmap(ctrl.memcs[i].ddr_shimphy_base); - - iounmap(ctrl.memcs[0].ddr_phy_base); -ddr_phy_err: - iounmap(ctrl.aon_ctrl_base); - if (s) - iounmap(ctrl.aon_sram); -aon_err: - pr_warn("PM: initialization failed with code %d\n", ret); - - return ret; -} - -static struct platform_driver brcmstb_pm_driver = { - .driver = { - .name = "brcmstb-pm", - .of_match_table = aon_ctrl_dt_ids, - }, -}; - -static int __init brcmstb_pm_init(void) -{ - return platform_driver_probe(&brcmstb_pm_driver, - brcmstb_pm_probe); -} -module_init(brcmstb_pm_init); diff --git a/drivers/soc/bcm/brcmstb/pm/s2-arm.S b/drivers/soc/bcm/brcmstb/pm/s2-arm.S deleted file mode 100644 index 0d693795de27..000000000000 --- a/drivers/soc/bcm/brcmstb/pm/s2-arm.S +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright © 2014-2017 Broadcom - */ - -#include -#include - -#include "pm.h" - - .arch armv7-a - .text - .align 3 - -#define AON_CTRL_REG r10 -#define DDR_PHY_STATUS_REG r11 - -/* - * r0: AON_CTRL base address - * r1: DDRY PHY PLL status register address - */ -ENTRY(brcmstb_pm_do_s2) - stmfd sp!, {r4-r11, lr} - mov AON_CTRL_REG, r0 - mov DDR_PHY_STATUS_REG, r1 - - /* Flush memory transactions */ - dsb - - /* Cache DDR_PHY_STATUS_REG translation */ - ldr r0, [DDR_PHY_STATUS_REG] - - /* power down request */ - ldr r0, =PM_S2_COMMAND - ldr r1, =0 - str r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] - ldr r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] - str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] - ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] - - /* Wait for interrupt */ - wfi - nop - - /* Bring MEMC back up */ -1: ldr r0, [DDR_PHY_STATUS_REG] - ands r0, #1 - beq 1b - - /* Power-up handshake */ - ldr r0, =1 - str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS] - ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS] - - ldr r0, =0 - str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] - ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL] - - /* Return to caller */ - ldr r0, =0 - ldmfd sp!, {r4-r11, pc} - - ENDPROC(brcmstb_pm_do_s2) - - /* Place literal pool here */ - .ltorg - -ENTRY(brcmstb_pm_do_s2_sz) - .word . - brcmstb_pm_do_s2 From 5cca02449490e767289bda38db1577e2c375c084 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 28 Feb 2023 15:43:58 +0100 Subject: [PATCH 0233/1040] arm64: dts: broadcom: bcmbca: bcm4908: fix NAND interrupt name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dtb: nand-controller@1800: interrupt-names:0: 'nand_ctlrdy' was expected From schema: Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dtb: nand-controller@1800: Unevaluated properties are not allowed ('interrupt-names' was unexpected) From schema: Documentation/devicetree/bindings/mtd/brcm,brcmnand.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/all/20230228144400.21689-1-zajec5@gmail.com/ Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index fc96ee7ab39d..1240fc5fb08c 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -556,7 +556,7 @@ reg = <0x1800 0x600>, <0x2000 0x10>; reg-names = "nand", "nand-int-base"; interrupts = ; - interrupt-names = "nand"; + interrupt-names = "nand_ctlrdy"; status = "okay"; nandcs: nand@0 { From 23be9f68f933adee8163b8efc9c6bff71410cc7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 28 Feb 2023 15:43:59 +0100 Subject: [PATCH 0234/1040] arm64: dts: broadcom: bcmbca: bcm4908: fix LED nodenames MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dtb: leds@800: 'led-lan@19', 'led-power@11', 'led-wan-red@12', 'led-wan-white@15', 'led-wps@14' do not match any of the regexes: '^led@[a-f0-9]+$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/leds/leds-bcm63138.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/all/20230228144400.21689-2-zajec5@gmail.com/ Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts index 839ca33178b0..d94a53d68320 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts @@ -120,7 +120,7 @@ }; &leds { - led-power@11 { + led@11 { reg = <0x11>; function = LED_FUNCTION_POWER; color = ; @@ -130,7 +130,7 @@ pinctrl-0 = <&pins_led_17_a>; }; - led-wan-red@12 { + led@12 { reg = <0x12>; function = LED_FUNCTION_WAN; color = ; @@ -139,7 +139,7 @@ pinctrl-0 = <&pins_led_18_a>; }; - led-wps@14 { + led@14 { reg = <0x14>; function = LED_FUNCTION_WPS; color = ; @@ -148,7 +148,7 @@ pinctrl-0 = <&pins_led_20_a>; }; - led-wan-white@15 { + led@15 { reg = <0x15>; function = LED_FUNCTION_WAN; color = ; @@ -157,7 +157,7 @@ pinctrl-0 = <&pins_led_21_a>; }; - led-lan@19 { + led@19 { reg = <0x19>; function = LED_FUNCTION_LAN; color = ; From f16a8294dd7a02c7ad042cd2e3acc5ea06698dc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 28 Feb 2023 15:44:00 +0100 Subject: [PATCH 0235/1040] arm64: dts: broadcom: bcmbca: bcm4908: fix procmon nodename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes: arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dtb: syscon@280000: $nodename:0: 'syscon@280000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: schemas/simple-bus.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/all/20230228144400.21689-3-zajec5@gmail.com/ Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index 1240fc5fb08c..f4cf0f835db7 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -260,7 +260,7 @@ }; }; - procmon: syscon@280000 { + procmon: bus@280000 { compatible = "simple-bus"; reg = <0x280000 0x1000>; ranges; From 477cad715de1dfc256a20da3ed83b62f3cb2944d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 28 Feb 2023 15:45:18 +0100 Subject: [PATCH 0236/1040] arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often have LEDs indicating state of selected USB ports. Describe those SoC USB ports to allow using them as LED trigger sources. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/ Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index f4cf0f835db7..457805efb385 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -148,6 +148,19 @@ interrupts = ; phys = <&usb_phy PHY_TYPE_USB2>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; }; ohci: usb@c400 { @@ -156,6 +169,19 @@ interrupts = ; phys = <&usb_phy PHY_TYPE_USB2>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ohci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + ohci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; }; xhci: usb@d000 { @@ -164,6 +190,19 @@ interrupts = ; phys = <&usb_phy PHY_TYPE_USB3>; status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + xhci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + xhci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; }; bus@80000 { From 889e53ccccc29ff4bf8d4c89cca34e8768845747 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 28 Feb 2023 15:45:19 +0100 Subject: [PATCH 0237/1040] arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB LED triggers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This device has 2 USB LEDs meant to be triggered by devices in relevant USB ports. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/all/20230228144520.21816-2-zajec5@gmail.com/ Signed-off-by: Florian Fainelli --- .../arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts index d8b60575eb4f..78204d71ecd2 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts @@ -58,12 +58,16 @@ function = "usb2"; color = ; gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; }; led-usb3 { function = "usb3"; color = ; gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>; + linux,default-trigger = "usbport"; }; led-wifi { From e6d356b146b75f1f77621aab7950a1eb550859f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Tue, 28 Feb 2023 15:45:20 +0100 Subject: [PATCH 0238/1040] arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB LED triggers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This device has 2 USB LEDs meant to be triggered by devices in relevant USB ports. While at it fix typo in USB LED name. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/all/20230228144520.21816-3-zajec5@gmail.com/ Signed-off-by: Florian Fainelli --- .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts index 296393d4aaab..fcf092c81b59 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts @@ -64,12 +64,16 @@ function = "usb2"; color = ; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port1>, <&ehci_port1>; + linux,default-trigger = "usbport"; }; led-usb3 { - function = "usbd3"; + function = "usb3"; color = ; gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>; + linux,default-trigger = "usbport"; }; led-brightness { From 32734bbd1802efbd60ea4f0c3c1d5500bd0b20fe Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 20:00:20 +0200 Subject: [PATCH 0239/1040] arm64: dts: qcom: sm8550: Fix PCIe PHYs and controllers nodes First, move the pinctrl related propeties out from SoC dtsi and into the board dts and add blank lines before status properties in the PHY nodes to be consistent with the rest of the nodes. Then drop the pipe clock from the controller nodes. Rename the aggre0 and aggre1 clocks to more generic noc_aggr, and then the cnoc_pcie_sf_axi to cnoc_sf_axi. Add the cpu-pcie interconnects to both controller nodes. Rename the pcie1 second reset to link_down and drop the unnecessary enable-gpios. Switch the aux clock to GCC_PCIE_1_PHY_AUX_CLK for the pcie1 PHY and drop the aux_phy from clock-names. Also rename the nocsr reset to phy_nocsr. With this changes we are now in line with the SC8280XP bindings. Fixes: 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Signed-off-by: Abel Vesa Reviewed-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208180020.2761766-12-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 10 +++++ arch/arm64/boot/dts/qcom/sm8550.dtsi | 52 +++++++++---------------- 2 files changed, 28 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5db6e789e6b8..44eab9308ff2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -414,18 +414,27 @@ &pcie0 { wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + status = "okay"; }; &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; }; &pcie1 { wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + status = "okay"; }; @@ -433,6 +442,7 @@ vdda-phy-supply = <&vreg_l3c_0p91>; vdda-pll-supply = <&vreg_l3e_1p2>; vdda-qref-supply = <&vreg_l1e_0p88>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ff4d342c0725..8992d6580bf3 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1672,25 +1672,24 @@ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_AXI_CLK>, <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>; - clock-names = "pipe", - "aux", + clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", - "aggre0"; + "noc_aggr"; - interconnect-names = "pcie-mem"; - interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; iommus = <&apps_smmu 0x1400 0x7f>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, @@ -1704,12 +1703,6 @@ phys = <&pcie0_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - status = "disabled"; }; @@ -1771,8 +1764,7 @@ <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, <&gcc GCC_PCIE_1_SLV_AXI_CLK>, @@ -1780,21 +1772,21 @@ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; - clock-names = "pipe", - "aux", + clock-names = "aux", "cfg", "bus_master", "bus_slave", "slave_q2a", "ddrss_sf_tbu", - "aggre1", - "cnoc_pcie_sf_axi"; + "noc_aggr", + "cnoc_sf_axi"; assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - interconnect-names = "pcie-mem"; - interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; iommus = <&apps_smmu 0x1480 0x7f>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, @@ -1802,20 +1794,13 @@ resets = <&gcc GCC_PCIE_1_BCR>, <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; - reset-names = "pci", - "pcie_1_link_down_reset"; + reset-names = "pci", "link_down"; power-domains = <&gcc PCIE_1_GDSC>; phys = <&pcie1_phy>; phy-names = "pciephy"; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - status = "disabled"; }; @@ -1823,18 +1808,17 @@ compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy"; reg = <0x0 0x01c0e000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&tcsr TCSR_PCIE_1_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + <&gcc GCC_PCIE_1_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", - "pipe", "aux_phy"; + "pipe"; resets = <&gcc GCC_PCIE_1_PHY_BCR>, <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; - reset-names = "phy", "nocsr"; + reset-names = "phy", "phy_nocsr"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; From fdaa922585f4474c88fbfaa129f8114f38200660 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 8 Feb 2023 21:01:59 +0200 Subject: [PATCH 0240/1040] arm64: dts: qcom: pm8550b: Add eUSB2 repeater node Add nodes for the eUSB2 repeater found on the pm8550b SPMI PMIC. Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208190200.2966723-7-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/pm8550b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550b.dtsi b/arch/arm64/boot/dts/qcom/pm8550b.dtsi index 16bcfb64d735..72609f31c890 100644 --- a/arch/arm64/boot/dts/qcom/pm8550b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550b.dtsi @@ -55,5 +55,11 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pm8550b_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; }; }; From 749078e38e1ee28357e8fdcd4eac382a465bd1e7 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 8 Feb 2023 21:02:00 +0200 Subject: [PATCH 0241/1040] arm64: dts: qcom: sm8550-mtp: Add eUSB2 repeater node Add the PMIC eUSB2 repeater node and add the usb-repeater property to the eUSB2 PHY to allow it to be controlled by the PHY driver. Signed-off-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230208190200.2966723-8-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 44eab9308ff2..9d4ddb883a70 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -457,6 +457,11 @@ }; }; +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + &qupv3_id_0 { status = "okay"; }; @@ -563,6 +568,8 @@ vdd-supply = <&vreg_l1e_0p88>; vdda12-supply = <&vreg_l3e_1p2>; + phys = <&pm8550b_eusb2_repeater>; + status = "okay"; }; From d228efe884692742e3a614c2386ee006aeb6551d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Feb 2023 17:38:44 +0100 Subject: [PATCH 0242/1040] arm64: dts: qcom: sm8550-qrd: add QRD8550 Add a minimal DTS for the new QRD8550 board - a mobile-like development board with SM8550. Serial, UFS and USB should be working. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210163844.765074-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 439 ++++++++++++++++++++++++ 2 files changed, 440 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8550-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 31aa54f0428c..e55da38ea498 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -200,3 +200,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts new file mode 100644 index 000000000000..d5a645ee2a61 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8550.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8550 QRD"; + compatible = "qcom,sm8550-qrd", "qcom,sm8550"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s4g_1p25>; + vdd-l12-supply = <&vreg_s6g_1p86>; + vdd-l15-supply = <&vreg_s6g_1p86>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + /* ldo2 supplies SM8550 VDD_LPI_MX */ + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s4e_0p95: smps4 { + regulator-name = "vreg_s4e_0p95"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <984000>; + regulator-initial-mode = ; + }; + + vreg_s5e_1p08: smps5 { + regulator-name = "vreg_s5e_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l1e_0p88: ldo1 { + regulator-name = "vreg_l1e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2e_0p9: ldo2 { + regulator-name = "vreg_l2e_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s4e_0p95>; + vdd-l2-supply = <&vreg_s4e_0p95>; + vdd-l3-supply = <&vreg_s4e_0p95>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4f_0p5: smps4 { + regulator-name = "vreg_s4f_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <700000>; + regulator-initial-mode = ; + }; + + vreg_l1f_0p9: ldo1 { + regulator-name = "vreg_l1f_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2f_0p88: ldo2 { + regulator-name = "vreg_l2f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3f_0p88: ldo3 { + regulator-name = "vreg_l3f_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + qcom,pmic-id = "g"; + + vdd-l1-supply = <&vreg_s4g_1p25>; + vdd-l2-supply = <&vreg_s4g_1p25>; + vdd-l3-supply = <&vreg_s4g_1p25>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vreg_s1g_1p25: smps1 { + regulator-name = "vreg_s1g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s2g_0p85: smps2 { + regulator-name = "vreg_s2g_0p85"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s3g_0p8: smps3 { + regulator-name = "vreg_s3g_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s4g_1p25: smps4 { + regulator-name = "vreg_s4g_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s5g_0p85: smps5 { + regulator-name = "vreg_s5g_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = ; + }; + + vreg_s6g_1p86: smps6 { + regulator-name = "vreg_s6g_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/sm8550/adsp.mbn", + "qcom/sm8550/adsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8550/cdsp.mbn", + "qcom/sm8550/cdsp_dtb.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8550/modem.mbn", + "qcom/sm8550/modem_dtb.mbn"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1g_1p2>; + vccq-max-microamp = <1200000>; + vccq2-supply = <&vreg_l3g_1p2>; + vccq2-max-microamp = <100>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1e_0p88>; + vdda12-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3f_0p88>; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; From 5a0c6d4349a7da252c9fa5fbc3d42b4e5ee1f334 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Feb 2023 18:59:28 +0100 Subject: [PATCH 0243/1040] arm64: dts: qcom: sm6375: Add RMTFS Add a node for RMTFS on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213175928.1979637-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 31b88c738510..87b4c83588df 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -424,6 +425,15 @@ no-map; }; + rmtfs_mem: rmtfs@f3900000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf3900000 0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + debug_mem: debug@ffb00000 { reg = <0 0xffb00000 0 0xc0000>; no-map; From b5d08f08377218b1d2ab4026e427a7788b271c8e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Feb 2023 22:03:31 +0100 Subject: [PATCH 0244/1040] arm64: dts: qcom: msm8998: Fix stm-stimulus-base reg name The name stm-data-base comes from ancient (msm-3.10 or older) downstream kernels. Upstream uses stm-stimulus-base instead. Fix it. Fixes: 783abfa2249a ("arm64: dts: qcom: msm8998: Add Coresight support") Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213210331.2106877-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 8bc1c59127e5..adf7258b3269 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1524,7 +1524,7 @@ compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x06002000 0x1000>, <0x16280000 0x180000>; - reg-names = "stm-base", "stm-data-base"; + reg-names = "stm-base", "stm-stimulus-base"; status = "disabled"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; From 0d589dc92fca4679186a949194fc7c452d37c575 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 14 Feb 2023 10:08:49 +0100 Subject: [PATCH 0245/1040] arm64: dts: qcom: pm8998: Add a specific compatible for coincell chg Add a PM8998-specific compatible to the coincell charger and keep the PM8941 one as fallback. Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214090849.2186370-3-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index adbba9f4089a..340033ac3186 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -72,7 +72,7 @@ }; pm8998_coincell: charger@2800 { - compatible = "qcom,pm8941-coincell"; + compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell"; reg = <0x2800>; status = "disabled"; From 603f96d4c9d0cb42f934fb0b99440bb9e8ba4385 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 14 Feb 2023 10:27:13 +0100 Subject: [PATCH 0246/1040] arm64: dts: qcom: add initial support for qcom sa8775p-ride This adds basic support for the Qualcomm sa8775p platform and the reference board: sa8775p-ride. The dt files describe the basics of the SoC and enable booting to shell. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214092713.211054-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++ 3 files changed, 853 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e55da38ea498..89e23a74bc7f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts new file mode 100644 index 000000000000..3adf7349f4e5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sa8775p.dtsi" + +/ { + model = "Qualcomm SA8775P Ride"; + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; + + aliases { + serial0 = &uart10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + qup_uart10_default: qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi new file mode 100644 index 000000000000..565c1376073e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -0,0 +1,805 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10000>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + L3_1: l3-cache { + compatible = "cache"; + }; + + }; + }; + + CPU5: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10100>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + CPU6: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10200>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + CPU7: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10300>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sa8775p", "qcom,scm"; + }; + }; + + aggre1_noc: interconnect-aggre1-noc { + compatible = "qcom,sa8775p-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible = "qcom,sa8775p-aggre2-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sa8775p-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible = "qcom,sa8775p-config-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible = "qcom,sa8775p-dc-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible = "qcom,sa8775p-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect-gpdsp-anoc { + compatible = "qcom,sa8775p-gpdsp-anoc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect-lpass-ag-noc { + compatible = "qcom,sa8775p-lpass-ag-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sa8775p-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible = "qcom,sa8775p-mmss-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible = "qcom,sa8775p-nspa-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible = "qcom,sa8775p-nspb-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect-pcie-anoc { + compatible = "qcom,sa8775p-pcie-anoc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible = "qcom,sa8775p-system-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + /* Will be updated by the bootloader. */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sail_ss_mem: sail-ss@80000000 { + reg = <0x0 0x80000000 0x0 0x10000000>; + no-map; + }; + + hyp_mem: hyp@90000000 { + reg = <0x0 0x90000000 0x0 0x600000>; + no-map; + }; + + xbl_boot_mem: xbl-boot@90600000 { + reg = <0x0 0x90600000 0x0 0x200000>; + no-map; + }; + + aop_image_mem: aop-image@90800000 { + reg = <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@90860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + uefi_log: uefi-log@908b0000 { + reg = <0x0 0x908b0000 0x0 0x10000>; + no-map; + }; + + reserved_mem: reserved@908f0000 { + reg = <0x0 0x908f0000 0x0 0xf000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908ff000 { + reg = <0x0 0x908ff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible = "qcom,smem"; + reg = <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: cpucp-fw@90b00000 { + reg = <0x0 0x90b00000 0x0 0x100000>; + no-map; + }; + + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { + reg = <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { + reg = <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg = <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg = <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg = <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg = <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg = <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg = <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg = <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg = <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg = <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg = <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + tz_stat_mem: tz-stat@d0000000 { + reg = <0x0 0xd0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg = <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg = <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1800000 { + reg = <0x0 0xd1800000 0x0 0x3900000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,sa8775p-gcc"; + reg = <0x0 0x100000 0x0 0xc7018>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SA8775P_CX>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x408000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; + + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa8c000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sa8775p-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sa8775p-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = ; + }; + }; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sa8775p-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 149>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From 2af2ef08c0ba052aefca20609572d67e0633b1ef Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:49 +0530 Subject: [PATCH 0247/1040] arm64: dts: qcom: sdm845: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-2-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..1d5e6ade8ae7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -92,6 +92,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -118,6 +119,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -140,6 +142,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -162,6 +165,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; dynamic-power-coefficient = <290>; @@ -184,6 +188,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -206,6 +211,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -228,6 +234,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -250,6 +257,7 @@ device_type = "cpu"; compatible = "qcom,kryo385"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <442>; @@ -5232,6 +5240,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; wifi: wifi@18800000 { From 667d8a2039608c4c848179cb45282204eadeb157 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:50 +0530 Subject: [PATCH 0248/1040] arm64: dts: qcom: sc7280: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-3-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bdcb74925313..d9b6e028cdac 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -168,6 +168,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -193,6 +194,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -214,6 +216,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -235,6 +238,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -256,6 +260,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -277,6 +282,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -298,6 +304,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -319,6 +326,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -5337,6 +5345,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; From afa34380d973491e87ab01d13c387528e2e1c476 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:51 +0530 Subject: [PATCH 0249/1040] arm64: dts: qcom: sm6350: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-4-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 1e1d366c92c1..c46bb6dab6a1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -46,6 +46,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -71,6 +72,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -92,6 +94,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -113,6 +116,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -134,6 +138,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -155,6 +160,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; @@ -177,6 +183,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; @@ -198,6 +205,7 @@ device_type = "cpu"; compatible = "qcom,kryo560"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; @@ -2002,6 +2010,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; From 1b0911fe3edb0895c43db4c19729b3c300028189 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:52 +0530 Subject: [PATCH 0250/1040] arm64: dts: qcom: sm8550: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-5-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 8992d6580bf3..71051fb4172b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -68,6 +68,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; @@ -91,6 +92,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; @@ -110,6 +112,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; @@ -129,6 +132,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x300>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; @@ -148,6 +152,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; @@ -167,6 +172,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; @@ -186,6 +192,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; @@ -205,6 +212,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; @@ -3323,6 +3331,7 @@ ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; pmu@24091000 { From d78cb07dbc1d384a8665b08918d188ee670ec45b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:53 +0530 Subject: [PATCH 0251/1040] arm64: dts: qcom: sm8250: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-6-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2f0e460acccd..44c8851178eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -97,6 +97,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -127,6 +128,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -151,6 +153,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -175,6 +178,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; @@ -199,6 +203,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; @@ -223,6 +228,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; @@ -248,6 +254,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; @@ -272,6 +279,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <444>; @@ -5481,6 +5489,7 @@ ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; From fcca74d893f3511a1e95869b1b3db3abb69bfb3b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:54 +0530 Subject: [PATCH 0252/1040] arm64: dts: qcom: qdu1000: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-7-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index f234159d2060..98a859ad5229 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -27,6 +27,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -45,6 +46,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -60,6 +62,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -75,6 +78,7 @@ device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -1312,6 +1316,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; gem_noc: interconnect@19100000 { From 7b39c98ff7e80f7e2bdf3c73829480e6ac123fb5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:55 +0530 Subject: [PATCH 0253/1040] arm64: dts: qcom: sc7180: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-8-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ebfa21e9ed8a..53f0076f20f6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -76,6 +76,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -103,6 +104,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -126,6 +128,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -149,6 +152,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -172,6 +176,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -195,6 +200,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 @@ -218,6 +224,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -241,6 +248,7 @@ device_type = "cpu"; compatible = "qcom,kryo468"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 @@ -3578,6 +3586,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; wifi: wifi@18800000 { From fc7258948c4a9e5dd2670adfcc80b13c621fbcd1 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:56 +0530 Subject: [PATCH 0254/1040] arm64: dts: qcom: sm8150: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-9-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index bfa19414c4be..c7e0cc18c21f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -48,6 +48,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -74,6 +75,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -97,6 +99,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -119,6 +122,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <488>; dynamic-power-coefficient = <232>; @@ -141,6 +145,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; @@ -163,6 +168,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; @@ -185,6 +191,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <369>; @@ -207,6 +214,7 @@ device_type = "cpu"; compatible = "qcom,kryo485"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <421>; @@ -4294,6 +4302,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; lmh_cluster1: lmh@18350800 { From c2a18730f0aaa2088a259f123e5fedf05f8a7041 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:57 +0530 Subject: [PATCH 0255/1040] arm64: dts: qcom: sm8350: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-10-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 1c97e28da6ad..e52deb2ccfb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -49,6 +49,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -70,6 +71,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -87,6 +89,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -104,6 +107,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -121,6 +125,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -138,6 +143,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -156,6 +162,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -173,6 +180,7 @@ device_type = "cpu"; compatible = "qcom,kryo685"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 2>; enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 2>; @@ -3240,6 +3248,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; cdsp: remoteproc@98900000 { From 2051f735b37d8e49f84914df11eb7b4a3a16349f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:58 +0530 Subject: [PATCH 0256/1040] arm64: dts: qcom: sc8280xp: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-11-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..213767a377ff 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -45,6 +45,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_0>; @@ -69,6 +70,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_100>; @@ -89,6 +91,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_200>; @@ -109,6 +112,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <602>; next-level-cache = <&L2_300>; @@ -129,6 +133,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_400>; @@ -149,6 +154,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_500>; @@ -169,6 +175,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_600>; @@ -189,6 +196,7 @@ device_type = "cpu"; compatible = "qcom,kryo"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; next-level-cache = <&L2_700>; @@ -4040,6 +4048,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; remoteproc_nsp0: remoteproc@1b300000 { From d9ab57eec39db8bf72951e00cde5ab117bcad6d8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:33:59 +0530 Subject: [PATCH 0257/1040] arm64: dts: qcom: sm6375: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-12-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 87b4c83588df..6252a547d916 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -40,6 +40,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -59,6 +60,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -75,6 +77,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x200>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -91,6 +94,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x300>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -107,6 +111,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x400>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -123,6 +128,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x500>; + clocks = <&cpufreq_hw 0>; enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -140,6 +146,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x600>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -156,6 +163,7 @@ device_type = "cpu"; compatible = "qcom,kryo660"; reg = <0x0 0x700>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; @@ -1393,6 +1401,7 @@ ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; From 0e6538e2d973bdfdf4d65a7d4b8baf1b7cdf75f0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 15 Feb 2023 12:34:00 +0530 Subject: [PATCH 0258/1040] arm64: dts: qcom: sm6115: Supply clock from cpufreq node to CPUs Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230215070400.5901-13-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index e463dd3b0f11..a9d2ff40935f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -39,6 +39,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -54,6 +55,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x1>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -65,6 +67,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x2>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -76,6 +79,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x3>; + clocks = <&cpufreq_hw 0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; enable-method = "psci"; @@ -87,6 +91,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x100>; + clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; @@ -102,6 +107,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x101>; + clocks = <&cpufreq_hw 1>; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; enable-method = "psci"; @@ -113,6 +119,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x102>; + clocks = <&cpufreq_hw 1>; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; enable-method = "psci"; @@ -124,6 +131,7 @@ device_type = "cpu"; compatible = "qcom,kryo260"; reg = <0x0 0x103>; + clocks = <&cpufreq_hw 1>; capacity-dmips-mhz = <1638>; dynamic-power-coefficient = <282>; enable-method = "psci"; @@ -2307,6 +2315,7 @@ clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; From c564b69984a78ce7811f22437794c9bb2afc11fd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:43 +0100 Subject: [PATCH 0259/1040] arm64: dts: qcom: sc7280: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-2-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d9b6e028cdac..46723418385b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2685,7 +2685,8 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; #iommu-cells = <2>; #global-interrupts = <2>; From 3e5c00256881f35b8664e1cf0b9fbf42cd9f24a1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:44 +0100 Subject: [PATCH 0260/1040] arm64: dts: qcom: sm8150: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-3-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c7e0cc18c21f..55aea7c05ed8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2271,7 +2271,8 @@ }; adreno_smmu: iommu@2ca0000 { - compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x02ca0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <1>; From 8347b12e905b99f445067d09326e4a1cc490f9cc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:45 +0100 Subject: [PATCH 0261/1040] arm64: dts: qcom: sm8250: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-4-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 44c8851178eb..0ee376b7ff86 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2664,7 +2664,8 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x10000>; #iommu-cells = <2>; #global-interrupts = <2>; From 78c61b6b2c33041940f2b22b47b058e83684b3f5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Feb 2023 15:56:46 +0100 Subject: [PATCH 0262/1040] arm64: dts: qcom: sm8350: Add qcom,smmu-500 to Adreno SMMU Add the fallback Qualcomm SMMU500 compatible to the Adreno SMMU. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216145646.4095336-5-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e52deb2ccfb5..e31043dd48a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1915,7 +1915,8 @@ }; adreno_smmu: iommu@3da0000 { - compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; reg = <0 0x03da0000 0 0x20000>; #iommu-cells = <2>; #global-interrupts = <2>; From 5a1816cc2d8caa054aa8b254efea9739aa8a68c6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 20 Feb 2023 10:43:38 +0100 Subject: [PATCH 0263/1040] arm64: dts: qcom: msm8996: move WCD9335 audio codec to boards The WCD9335 audio codec on Slimbus is a property of a board, not SoC, thus it should not be present in MSM8996 DTSI. Keep it in specific boards, so it won't appear incomplete in the boards not having it. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230220094339.47370-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 56 +++++++++++++---- .../boot/dts/qcom/msm8996-oneplus-common.dtsi | 56 +++++++++++++---- .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 60 ++++++++++++++----- arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 +--------- 4 files changed, 135 insertions(+), 67 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index fe6c415e8229..ce189dea2760 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -974,6 +974,50 @@ }; }; +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + &sound { compatible = "qcom,apq8096-sndcard"; model = "DB820c"; @@ -1101,15 +1145,3 @@ &venus { status = "okay"; }; - -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 2994337c6046..104deaee74e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -504,6 +504,50 @@ }; }; +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&div1_mclk>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + &slpi_pil { status = "okay"; }; @@ -772,15 +816,3 @@ &venus { status = "okay"; }; - -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&div1_mclk>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 2acfed28e3cb..446b1d23dec0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -337,6 +337,52 @@ }; }; +&slim_msm { + status = "okay"; + + slim@1 { + reg = <1>; + #address-cells = <2>; + #size-cells = <0>; + + tasha_ifd: tas-ifd@0,0 { + compatible = "slim217,1a0"; + reg = <0 0>; + }; + + wcd9335: codec@1,0 { + compatible = "slim217,1a0"; + reg = <1 0>; + + clock-names = "mclk", "slimbus"; + clocks = <&divclk1_cdc>, + <&rpmcc RPM_SMD_BB_CLK1>; + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, + <53 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr1", "intr2"; + interrupt-controller; + #interrupt-cells = <1>; + + pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + slim-ifc-dev = <&tasha_ifd>; + + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-vbat-supply = <&vph_pwr>; + vdd-micbias-supply = <&vph_pwr_bbyp>; + vdd-io-supply = <&vreg_s4a_1p8>; + }; + }; +}; + &slpi_pil { status = "okay"; @@ -395,20 +441,6 @@ status = "okay"; }; -&wcd9335 { - clock-names = "mclk", "slimbus"; - clocks = <&divclk1_cdc>, - <&rpmcc RPM_SMD_BB_CLK1>; - - vdd-buck-supply = <&vreg_s4a_1p8>; - vdd-buck-sido-supply = <&vreg_s4a_1p8>; - vdd-rx-supply = <&vreg_s4a_1p8>; - vdd-tx-supply = <&vreg_s4a_1p8>; - vdd-vbat-supply = <&vph_pwr>; - vdd-micbias-supply = <&vph_pwr_bbyp>; - vdd-io-supply = <&vreg_s4a_1p8>; -}; - &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8994-regulators"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 905678e7175d..293ed2e60691 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3383,36 +3383,8 @@ dma-names = "rx", "tx"; #address-cells = <1>; #size-cells = <0>; - slim@1 { - reg = <1>; - #address-cells = <2>; - #size-cells = <0>; - tasha_ifd: tas-ifd@0,0 { - compatible = "slim217,1a0"; - reg = <0 0>; - }; - - wcd9335: codec@1,0 { - pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; - pinctrl-names = "default"; - - compatible = "slim217,1a0"; - reg = <1 0>; - - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, - <53 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "intr1", "intr2"; - interrupt-controller; - #interrupt-cells = <1>; - reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; - - slim-ifc-dev = <&tasha_ifd>; - - #sound-dai-cells = <1>; - }; - }; + status = "disabled"; }; adsp_pil: remoteproc@9300000 { From aec576821e6fd233ae895f4aa57ff1b511a71e8e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 20 Feb 2023 10:43:39 +0100 Subject: [PATCH 0264/1040] arm64: dts: qcom: apq8096-db820c: fix indentation Correct indentation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230220094339.47370-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index ce189dea2760..eb18811b2676 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -1070,7 +1070,7 @@ platform { sound-dai = <&q6routing>; - }; + }; codec { sound-dai = <&wcd9335 AIF4_PB>; From 5d793ff40692c9b3f88df1820a79ac8ae7d9c80b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 21 Feb 2023 16:05:43 +0100 Subject: [PATCH 0265/1040] arm64: dts: qcom: sa8775p: add cpufreq node Add a node for the cpufreq engine and specify the frequency domains for all CPUs. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230221150543.283487-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 565c1376073e..dc21e8450058 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -37,6 +37,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "cache"; @@ -52,6 +53,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "cache"; @@ -64,6 +66,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "cache"; @@ -76,6 +79,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "cache"; @@ -88,6 +92,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10000>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "cache"; @@ -104,6 +109,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "cache"; @@ -116,6 +122,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "cache"; @@ -128,6 +135,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x10300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "cache"; @@ -645,6 +653,19 @@ #hwlock-cells = <1>; }; + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8775p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0xf000000 0x0 0x1000000>; From d39469f5ce81b2cabf07b1cad3deddeafb7b8a8d Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 22 Feb 2023 21:00:45 +0530 Subject: [PATCH 0266/1040] arm64: dts: qcom: sm8450: Add IMEM and PIL info region Add a simple-mfd representing IMEM on SM8450 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteprocs. Signed-off-by: Mukesh Ojha Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1677079845-17650-1-git-send-email-quic_mojha@quicinc.com --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1a744a33bcf4..7671f15d639b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3689,6 +3689,20 @@ }; }; + sram@146aa000 { + compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; + reg = <0 0x146aa000 0 0x1000>; + ranges = <0 0 0x146aa000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; From d0af0537e28f6eace02deed63b585396de939213 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 2 Mar 2023 02:18:49 +0100 Subject: [PATCH 0267/1040] arm64: dts: qcom: msm8996: Add missing DWC3 quirks Add missing dwc3 quirks from msm-3.18. Unfortunately, none of them make `dwc3-qcom 6af8800.usb: HS-PHY not in L2` go away. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302011849.1873056-1-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 293ed2e60691..a1e14e3540e6 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3006,8 +3006,11 @@ interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; phys = <&hsusb_phy1>, <&ssusb_phy_0>; phy-names = "usb2-phy", "usb3-phy"; + snps,hird-threshold = /bits/ 8 <0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; + snps,is-utmi-l1-suspend; + tx-fifo-resize; }; }; From 5a6d76761225bfa31d114f434b990fa2ed9b04c5 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 15 Mar 2023 11:34:40 +0800 Subject: [PATCH 0268/1040] dt-bindings: arm: rockchip: Add Khadas Edge2 board Edge2 is an ultraslim, credit-card sized ARM PC designed by Khadas. It has quite a few rich peripherals. Specification: - Rockchip RK3588s - 8/16GB LPDDR4 - 32/64GB eMMC 5.1 - AP6275P WiFi6 LAN - HDMI2.1 Type-A - MIPI-CSI x3 - MIPI-DSI x2 - usb3.1; usb2.0 - RTC clock - PWM fan - SPI Flash - Pads expansion board (UART, USB) Signed-off-by: Yixun Lan Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230315033441.32719-2-dlan@gentoo.org Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 35f74eda30ae..ff663797291c 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -533,6 +533,11 @@ properties: - khadas,edge-v - const: rockchip,rk3399 + - description: Khadas Edge2 series boards + items: + - const: khadas,edge2 + - const: rockchip,rk3588s + - description: Kobol Helios64 items: - const: kobol,helios64 From 04d5529935229a709d6facb8a80168cc0976c89a Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Wed, 15 Mar 2023 11:34:41 +0800 Subject: [PATCH 0269/1040] arm64: dts: rockchip: Add Khadas edge2 board Edge2 is an ultraslim, credit-card sized ARM PC designed by Khadas. In this patch, we will add basic device tree support for this board, Only eMMC, UART are enabled, so it's capable of booting into a basic linux system from eMMC via serial console. Signed-off-by: Yixun Lan Link: https://lore.kernel.org/r/20230315033441.32719-3-dlan@gentoo.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588s-khadas-edge2.dts | 37 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 99a44c400d6a..1743e9e14426 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -90,4 +90,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts new file mode 100644 index 000000000000..93b4a0c4ed0f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3588s.dtsi" + +/ { + model = "Khadas Edge2"; + compatible = "khadas,edge2", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; From fd7370159c36b925c842ae1c2400d4729451ec82 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 7 Mar 2023 22:32:39 -0800 Subject: [PATCH 0270/1040] dt-bindings: Add doc for FriendlyARM NanoPi R5S Add devicetree binding documentation for the FriendlyARM NanoPi R5S. Signed-off-by: Vasily Khoruzhick Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230308063240.107178-1-anarsoul@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ff663797291c..5474cb4a13d1 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -201,6 +201,11 @@ properties: - friendlyarm,nanopi-r4s-enterprise - const: rockchip,rk3399 + - description: FriendlyElec NanoPi R5S board + items: + - const: friendlyarm,nanopi-r5s + - const: rockchip,rk3568 + - description: GeekBuying GeekBox items: - const: geekbuying,geekbox From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Tue, 7 Mar 2023 22:32:40 -0800 Subject: [PATCH 0271/1040] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device. Board Specifications - Rockchip RK3568 - 2 or 4GB LPDDR4X - 8GB or 16GB eMMC, SD card slot - GbE LAN (Native) - 2x 2.5G LAN (PCIe) - M.2 Connector - HDMI 2.0, MIPI DSI/CSI - 2xUSB 3.0 Host - USB Type C PD, 5V/9V/12V - GPIO: 12-pin 0.5mm FPC connector Based on Tianling Shen's work. Signed-off-by: Vasily Khoruzhick Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++ 2 files changed, 714 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1743e9e14426..ade66d846a20 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts new file mode 100644 index 000000000000..25edc82eaa3f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -0,0 +1,713 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "FriendlyElec NanoPi R5S"; + compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>; + + led-lan1 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + led-lan2 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { + color = ; + function = LED_FUNCTION_POWER; + linux,default-trigger = "heartbeat"; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + }; + + vdd_usbc: vdd-usbc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + num-ib-windows = <8>; + num-ob-windows = <8>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gpio-leds { + lan1_led_pin: lan1-led-pin { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 56af59fc0be3fda8d8a32ed996dfb84758d4f431 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 7 Mar 2023 10:55:16 +0100 Subject: [PATCH 0272/1040] ARM: dts: rockchip: Add mmc aliases for rk3288-veyron devices All of them have an internal emmc that becomes mmc0 and devices including the sdmmc snippet get mmc1 for the external sd slot on suitable devices. Reviewed-by: Douglas Anderson Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20230307095516.4116827-1-heiko@sntech.de --- arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi | 6 ++++++ arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi index 27fb06ce907e..8b58773e592e 100644 --- a/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi @@ -5,6 +5,12 @@ * Copyright 2015 Google, Inc */ +/ { + aliases { + mmc1 = &sdmmc; + }; +}; + &io_domains { sdcard-supply = <&vccio_sd>; }; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index e406c8c7c7e5..d838bf0d5d9a 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -10,6 +10,10 @@ #include "rk3288.dtsi" / { + aliases { + mmc0 = &emmc; + }; + chosen { stdout-path = "serial2:115200n8"; }; From 49f965b6fbca63904d7397ce96066fa992f401a3 Mon Sep 17 00:00:00 2001 From: Jesse Taube Date: Tue, 14 Mar 2023 17:10:30 -0400 Subject: [PATCH 0273/1040] soc: canaan: Make K210_SYSCTL depend on CLK_K210 CLK_K210 is no longer a dependency of SOC_CANAAN, but K210_SYSCTL depends on CLK_K210. This patch makes K210_SYSCTL depend on CLK_K210. Also fix whitespace errors. Reported-by: Randy Dunlap Link: https://lore.kernel.org/all/42446784-a88b-df09-41e9-5f685b4df6ee@infradead.org Fixes: 3af577f9826f ("RISC-V: stop directly selecting drivers for SOC_CANAAN") Signed-off-by: Jesse Taube Reviewed-by: Damien Le Moal Signed-off-by: Conor Dooley --- drivers/soc/canaan/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/canaan/Kconfig b/drivers/soc/canaan/Kconfig index 2527cf5757ec..43ced2bf8444 100644 --- a/drivers/soc/canaan/Kconfig +++ b/drivers/soc/canaan/Kconfig @@ -3,8 +3,9 @@ config SOC_K210_SYSCTL bool "Canaan Kendryte K210 SoC system controller" depends on RISCV && SOC_CANAAN && OF + depends on COMMON_CLK_K210 default SOC_CANAAN - select PM - select MFD_SYSCON + select PM + select MFD_SYSCON help Canaan Kendryte K210 SoC system controller driver. From e77da13b8e3626fc6d01287fba7c1eee4ebfe018 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 21:10:54 +0000 Subject: [PATCH 0274/1040] riscv: dts: microchip: fix the mpfs' mailbox regs The mailbox on PolarFire SoC should really have three reg properties, not two. Without splitting into three sections, the system controller's QSPI cannot be accessed as it sits inside the current first range. The driver & binding have been adapted to account for both two & three ranges, so fix the dts too. Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 23b7b05ee291..104504352e99 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -501,7 +501,8 @@ mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; interrupts = <96>; #mbox-cells = <1>; From f26e18bda9e3b069fbb07a2827597952a6d0afe0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:17:26 +0100 Subject: [PATCH 0275/1040] dt-bindings: arm: qcom,ids: Add IDs for QCM2290/QRB2210 Add the missing IDs for scuba and its QRB variant. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-scuba_socinfo-v2-1-44fa1256aa6d@linaro.org --- include/dt-bindings/arm/qcom,ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index c3c078a8c0da..197873ed3a17 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -213,6 +213,7 @@ #define QCOM_ID_QCM2150 436 #define QCOM_ID_SDA429W 437 #define QCOM_ID_SM8350 439 +#define QCOM_ID_QCM2290 441 #define QCOM_ID_SM6115 444 #define QCOM_ID_SC8280XP 449 #define QCOM_ID_IPQ6005 453 @@ -229,6 +230,7 @@ #define QCOM_ID_SC7180P 495 #define QCOM_ID_SM6375 507 #define QCOM_ID_SM8550 519 +#define QCOM_ID_QRB2210 524 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 From 18290c2eec4be239318cb4e01cafe12217e36de8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:17:27 +0100 Subject: [PATCH 0276/1040] soc: qcom: socinfo: Add IDs for QCM2290/QRB2210 Add the missing IDs for scuba and its QRB variant. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-scuba_socinfo-v2-2-44fa1256aa6d@linaro.org --- drivers/soc/qcom/socinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 89081ec34dba..f352cd58630d 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -431,6 +431,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QCM2150) }, { qcom_board_id(SDA429W) }, { qcom_board_id(SM8350) }, + { qcom_board_id(QCM2290) }, { qcom_board_id(SM6115) }, { qcom_board_id(SC8280XP) }, { qcom_board_id(IPQ6005) }, @@ -447,6 +448,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SC7180P) }, { qcom_board_id(SM6375) }, { qcom_board_id(SM8550) }, + { qcom_board_id(QRB2210) }, { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, From 94b1d58f887a147d9a0e8bccc7fffd067c5b9588 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:30 +0530 Subject: [PATCH 0277/1040] dt-bindings: arm: msm: Update the maintainers for LLCC Both Rishabh and Sai have left Qualcomm, and there is no evidence of them maintaining with a new identity. So their entry needs to be removed. Listed Bjorn as the interim maintainer until someone volunteers to maintain this binding. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-2-manivannan.sadhasivam@linaro.org --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..6570b808fd0d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Bjorn Andersson description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From 43aa006e074c4dcaf7493895fb2bd4af16d7c0ab Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:31 +0530 Subject: [PATCH 0278/1040] dt-bindings: arm: msm: Fix register regions used for LLCC banks Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-3-manivannan.sadhasivam@linaro.org --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 6570b808fd0d..93b977428a14 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; From ee13b5008707948d3052c1b5aab485c6cd53658e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:41 +0530 Subject: [PATCH 0279/1040] qcom: llcc/edac: Fix the base address used for accessing LLCC banks The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, there is no need to rely on reg-names property and the base addresses can be obtained using the index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those need to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-13-manivannan.sadhasivam@linaro.org --- drivers/edac/qcom_edac.c | 14 ++---- drivers/soc/qcom/llcc-qcom.c | 78 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 51 insertions(+), 47 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 3256254c3722..1d3cc1930a74 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pdev) return 0; } -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config = { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, .fast_io = true, }; - base = devm_platform_ioremap_resource_byname(pdev, name); + base = devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); - goto err; - } - - drv_data->bcast_regmap = - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); - if (IS_ERR(drv_data->bcast_regmap)) { - ret = PTR_ERR(drv_data->bcast_regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); goto err; } cfg = of_device_get_match_data(&pdev->dev); + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret = -ENOMEM; + goto err; + } + + drv_data->regmaps[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret = PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); + if (IS_ERR(drv_data->bcast_regmap)) { + ret = PTR_ERR(drv_data->bcast_regmap); + goto err; + } + /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; From 721d3e91bfc93975c5e1a76c7d588dd8df5d82da Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:42 +0530 Subject: [PATCH 0280/1040] qcom: llcc/edac: Support polling mode for ECC handling Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-14-manivannan.sadhasivam@linaro.org --- drivers/edac/qcom_edac.c | 52 +++++++++++++++++++++--------------- drivers/soc/qcom/llcc-qcom.c | 13 +++++---- 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 1d3cc1930a74..265e0fb39bc7 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE = 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) return ret; } -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; @@ -355,30 +361,32 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq = llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); + if (!rc) { + edac_op_state = EDAC_OPSTATE_INT; + goto irq_done; + } + } + + /* Fall back to polling mode otherwise */ + edev_ctl->poll_msec = ECC_POLL_MSEC; + edev_ctl->edac_check = llcc_ecc_check; + edac_op_state = EDAC_OPSTATE_POLL; + +irq_done: rc = edac_device_add_device(edev_ctl); - if (rc) - goto out_mem; + if (rc) { + edac_device_free_ctl_info(edev_ctl); + return rc; + } platform_set_drvdata(pdev, edev_ctl); - /* Request for ecc irq */ - ecc_irq = llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc = -ENODEV; - goto out_dev; - } - rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, - IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; - - return rc; - -out_dev: - edac_device_del_device(edev_ctl->dev); -out_mem: - edac_device_free_ctl_info(edev_ctl); - return rc; } diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >= 0) { - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); return 0; err: From cca94f1dd6d0a4c7e5c8190672f5747e3c00ddde Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:43 +0530 Subject: [PATCH 0281/1040] soc: qcom: llcc: Do not create EDAC platform device on SDM845 The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. While at it, also sort the members of `struct qcom_llcc_config` to avoid any holes in-between. Cc: # 5.10 Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-15-manivannan.sadhasivam@linaro.org --- drivers/soc/qcom/llcc-qcom.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 7b7c5a38bac6..a5140f19f200 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -120,10 +120,11 @@ struct llcc_slice_config { struct qcom_llcc_config { const struct llcc_slice_config *sct_data; - int size; - bool need_llcc_cfg; const u32 *reg_offset; const struct llcc_edac_reg_offset *edac_reg_offset; + int size; + bool need_llcc_cfg; + bool no_edac; }; enum llcc_reg_offset { @@ -452,6 +453,7 @@ static const struct qcom_llcc_config sdm845_cfg = { .need_llcc_cfg = false, .reg_offset = llcc_v1_reg_offset, .edac_reg_offset = &llcc_v1_edac_reg_offset, + .no_edac = true, }; static const struct qcom_llcc_config sm6350_cfg = { @@ -1012,11 +1014,19 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); + /* + * On some platforms, the access to EDAC registers will be locked by + * the bootloader. So probing the EDAC driver will result in a crash. + * Hence, disable the creation of EDAC platform device for the + * problematic platforms. + */ + if (!cfg->no_edac) { + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); + } return 0; err: From bfe088bde391824040c39cbf277d7fe782042936 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:32 +0530 Subject: [PATCH 0282/1040] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-4-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1d5e6ade8ae7..79da7eb954f3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2200,8 +2200,11 @@ llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From 116a932bbc7bc740b068fbfe320a465811ca62f8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:33 +0530 Subject: [PATCH 0283/1040] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-5-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 53f0076f20f6..fb84aa480d91 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2768,7 +2768,7 @@ system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; }; From 62e5ee9db98ed67eb50205072135544055cba9c4 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:34 +0530 Subject: [PATCH 0284/1040] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-6-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 46723418385b..5b0b10ee0a5c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3591,8 +3591,9 @@ system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; From 0fe0955a79b994b8dcabe79f3a7192251fb256ea Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:35 +0530 Subject: [PATCH 0285/1040] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-7-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 213767a377ff..667595381ab8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2991,8 +2991,14 @@ system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = ; }; From c5ccf8d33f11f57ef46d12db1dda4afcc4d5150b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:36 +0530 Subject: [PATCH 0286/1040] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-8-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 55aea7c05ed8..d3e7df92998c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1794,8 +1794,11 @@ system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From 42c9b1578233eeb3044656a446486bd2efc87312 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:37 +0530 Subject: [PATCH 0287/1040] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-9-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 0ee376b7ff86..73c5504c1d44 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3568,8 +3568,11 @@ system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_2: usb@a8f8800 { From 7ae317cba6be783cfd6155bceec91d0918f78fb8 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:38 +0530 Subject: [PATCH 0288/1040] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-10-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e31043dd48a6..2a9248baa204 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2213,8 +2213,11 @@ system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; compute_noc: interconnect@a0c0000 { From 413c8ecd48f1df8034c7b13881ded33b3d10171f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:39 +0530 Subject: [PATCH 0289/1040] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-11-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7671f15d639b..f6514c012926 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3995,8 +3995,11 @@ system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From 65d9975e5dae4601e8902765d08f55c246fd2022 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 14 Mar 2023 13:34:40 +0530 Subject: [PATCH 0290/1040] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314080443.64635-12-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c46bb6dab6a1..318fefc8f4fa 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1356,7 +1356,7 @@ system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { From fd972da1b228974f788c115d37abe209828ca5a9 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 14 Mar 2023 11:43:33 +0530 Subject: [PATCH 0291/1040] dt-bindings: arm: qcom,ids: Add IDs for IPQ9574 and its variants Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by: Varadarajan Narayanan Acked-by: Krzysztof Kozlowski Reviewed-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1678774414-14414-2-git-send-email-quic_varada@quicinc.com --- include/dt-bindings/arm/qcom,ids.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 197873ed3a17..c3cc440dec33 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -229,7 +229,13 @@ #define QCOM_ID_SC7280 487 #define QCOM_ID_SC7180P 495 #define QCOM_ID_SM6375 507 +#define QCOM_ID_IPQ9514 510 +#define QCOM_ID_IPQ9550 511 +#define QCOM_ID_IPQ9554 512 +#define QCOM_ID_IPQ9570 513 +#define QCOM_ID_IPQ9574 514 #define QCOM_ID_SM8550 519 +#define QCOM_ID_IPQ9510 521 #define QCOM_ID_QRB2210 524 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 From c6653d8f24f4bcc255e3ffb28c629ff5d0e0ba13 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 14 Mar 2023 11:43:34 +0530 Subject: [PATCH 0292/1040] soc: qcom: socinfo: Add IDs for IPQ9574 and its variants Add SOC ID for Qualcomm IPQ9574, IPQ9570, IPQ9554, IPQ9550, IPQ9514 and IPQ9510 Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski Reviewed-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1678774414-14414-3-git-send-email-quic_varada@quicinc.com --- drivers/soc/qcom/socinfo.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index f352cd58630d..cc1204ae2198 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -447,7 +447,13 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SC7280) }, { qcom_board_id(SC7180P) }, { qcom_board_id(SM6375) }, + { qcom_board_id(IPQ9514) }, + { qcom_board_id(IPQ9550) }, + { qcom_board_id(IPQ9554) }, + { qcom_board_id(IPQ9570) }, + { qcom_board_id(IPQ9574) }, { qcom_board_id(SM8550) }, + { qcom_board_id(IPQ9510) }, { qcom_board_id(QRB2210) }, { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, From ee6ae544ddfabe60245d4eaee41a7330acd46d94 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 15 Mar 2023 21:31:50 +0530 Subject: [PATCH 0293/1040] dt-bindings: arm: qcom,ids: Add IDs for QRB4210 Add the ID for QRB4210 variant. Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315160151.2166861-2-bhupesh.sharma@linaro.org --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index c3cc440dec33..cd7a95756ea1 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -236,6 +236,7 @@ #define QCOM_ID_IPQ9574 514 #define QCOM_ID_SM8550 519 #define QCOM_ID_IPQ9510 521 +#define QCOM_ID_QRB4210 523 #define QCOM_ID_QRB2210 524 #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 From a11bc4a5b371e05e89c0fba5756efe5788a4d1ab Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 15 Mar 2023 21:31:51 +0530 Subject: [PATCH 0294/1040] soc: qcom: socinfo: Add IDs for QRB4210 Add the ID for QRB4210 variant. Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315160151.2166861-3-bhupesh.sharma@linaro.org --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index cc1204ae2198..cd370fe28d19 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -454,6 +454,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(IPQ9574) }, { qcom_board_id(SM8550) }, { qcom_board_id(IPQ9510) }, + { qcom_board_id(QRB4210) }, { qcom_board_id(QRB2210) }, { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, From de7aeee0d942d2e1d85b3db3652e037af38e24d7 Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sun, 5 Mar 2023 22:17:44 +0300 Subject: [PATCH 0295/1040] dt-bindings: arm: qcom,ids: Add Soc ID for SM7150 Add the ID for the Qualcomm SM7150 SoC. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305191745.386862-2-danila@jiaxyga.com --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index cd7a95756ea1..802495b20276 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -192,6 +192,7 @@ #define QCOM_ID_SA8155 362 #define QCOM_ID_SDA439 363 #define QCOM_ID_SDA429 364 +#define QCOM_ID_SM7150 365 #define QCOM_ID_IPQ8070 375 #define QCOM_ID_IPQ8071 376 #define QCOM_ID_QM215 386 From bad8cdc20690fa830c49783b68c6403dd44bc0bd Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sun, 5 Mar 2023 22:17:45 +0300 Subject: [PATCH 0296/1040] soc: qcom: socinfo: Add Soc ID for SM7150 Add Soc ID table entries for Qualcomm SM7150. Signed-off-by: David Wronek Signed-off-by: Danila Tikhonov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305191745.386862-3-danila@jiaxyga.com --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index cd370fe28d19..c2e4a57dd666 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -410,6 +410,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SA8155) }, { qcom_board_id(SDA439) }, { qcom_board_id(SDA429) }, + { qcom_board_id(SM7150) }, { qcom_board_id(IPQ8070) }, { qcom_board_id(IPQ8071) }, { qcom_board_id(QM215) }, From 9ebaa4a8cdf11831090a7a7e8d5e82e12b4ff7a8 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 15 Mar 2023 21:27:51 +0100 Subject: [PATCH 0297/1040] arm64: dts: qcom: sm8150: fix the uart9 label There's a typo in the @
part of the uart9 label. Fix it. Fixes: 10d900a834da ("arm64: dts: sm8150: add the QUPv3 high-speed UART node") Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315202751.1518543-1-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index d3e7df92998c..3e2b3597281e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1342,7 +1342,7 @@ status = "disabled"; }; - uart9: serial@a8c000 { + uart9: serial@a84000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a84000 0x0 0x4000>; reg-names = "se"; From f1eb5e6fc18c5e6f4ee7fd2985743f2fe7978951 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 20:59:59 +0100 Subject: [PATCH 0298/1040] soc: qcom: rpmpd: Remove SoC names from RPMPD definitions Replace the SoC names with type+id_key (or type+id+..name..+key for fixed-key definitions) and remove duplicate entries. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-1-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 360 ++++++++++++++++++--------------------- 1 file changed, 164 insertions(+), 196 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 337b1ad1cd3b..d99a56509e33 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -40,51 +40,50 @@ #define MAX_CORNER_RPMPD_STATE 6 -#define DEFINE_RPMPD_PAIR(_platform, _name, _active, r_type, r_key, \ - r_id) \ - static struct rpmpd _platform##_##_active; \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_PAIR(_name, _active, r_type, r_key, r_id) \ + static struct rpmpd r_type##r_id##_##r_key##_##_active; \ + static struct rpmpd r_type##r_id##_##r_key##_##_name = { \ .pd = { .name = #_name, }, \ - .peer = &_platform##_##_active, \ + .peer = &r_type##r_id##_##r_key##_##_active, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_##r_key, \ }; \ - static struct rpmpd _platform##_##_active = { \ + static struct rpmpd r_type##r_id##_##r_key##_##_active = { \ .pd = { .name = #_active, }, \ - .peer = &_platform##_##_name, \ + .peer = &r_type##r_id##_##r_key##_##_name, \ .active_only = true, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_##r_key, \ } -#define DEFINE_RPMPD_CORNER(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_CORNER(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name##_corner = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_CORNER, \ } -#define DEFINE_RPMPD_LEVEL(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_LEVEL(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name##_lvl = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_LEVEL, \ } -#define DEFINE_RPMPD_VFC(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_VFC(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ .key = KEY_FLOOR_CORNER, \ } -#define DEFINE_RPMPD_VFL(_platform, _name, r_type, r_id) \ - static struct rpmpd _platform##_##_name = { \ +#define DEFINE_RPMPD_VFL(_name, r_type, r_id) \ + static struct rpmpd r_type##r_id##_##_name = { \ .pd = { .name = #_name, }, \ .res_type = RPMPD_##r_type, \ .res_id = r_id, \ @@ -119,18 +118,18 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); /* mdm9607 RPM Power Domains */ -DEFINE_RPMPD_PAIR(mdm9607, vddcx, vddcx_ao, SMPA, LEVEL, 3); -DEFINE_RPMPD_VFL(mdm9607, vddcx_vfl, SMPA, 3); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 3); -DEFINE_RPMPD_PAIR(mdm9607, vddmx, vddmx_ao, LDOA, LEVEL, 12); -DEFINE_RPMPD_VFL(mdm9607, vddmx_vfl, LDOA, 12); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_VFL(vddmx_vfl, LDOA, 12); static struct rpmpd *mdm9607_rpmpds[] = { - [MDM9607_VDDCX] = &mdm9607_vddcx, - [MDM9607_VDDCX_AO] = &mdm9607_vddcx_ao, - [MDM9607_VDDCX_VFL] = &mdm9607_vddcx_vfl, - [MDM9607_VDDMX] = &mdm9607_vddmx, - [MDM9607_VDDMX_AO] = &mdm9607_vddmx_ao, - [MDM9607_VDDMX_VFL] = &mdm9607_vddmx_vfl, + [MDM9607_VDDCX] = &SMPA3_LEVEL_vddcx, + [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_vddcx_ao, + [MDM9607_VDDCX_VFL] = &SMPA3_vddcx_vfl, + [MDM9607_VDDMX] = &LDOA12_LEVEL_vddmx, + [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_vddmx_ao, + [MDM9607_VDDMX_VFL] = &LDOA12_vddmx_vfl, }; static const struct rpmpd_desc mdm9607_desc = { @@ -140,13 +139,13 @@ static const struct rpmpd_desc mdm9607_desc = { }; /* msm8226 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8226, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(msm8226, vddcx_vfc, SMPA, 1); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); static struct rpmpd *msm8226_rpmpds[] = { - [MSM8226_VDDCX] = &msm8226_vddcx, - [MSM8226_VDDCX_AO] = &msm8226_vddcx_ao, - [MSM8226_VDDCX_VFC] = &msm8226_vddcx_vfc, + [MSM8226_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8226_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8226_VDDCX_VFC] = &SMPA1_vddcx_vfc, }; static const struct rpmpd_desc msm8226_desc = { @@ -156,23 +155,23 @@ static const struct rpmpd_desc msm8226_desc = { }; /* msm8939 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8939, vddmd, vddmd_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(msm8939, vddmd_vfc, SMPA, 1); +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); -DEFINE_RPMPD_PAIR(msm8939, vddcx, vddcx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_VFC(msm8939, vddcx_vfc, SMPA, 2); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); -DEFINE_RPMPD_PAIR(msm8939, vddmx, vddmx_ao, LDOA, CORNER, 3); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); static struct rpmpd *msm8939_rpmpds[] = { - [MSM8939_VDDMDCX] = &msm8939_vddmd, - [MSM8939_VDDMDCX_AO] = &msm8939_vddmd_ao, - [MSM8939_VDDMDCX_VFC] = &msm8939_vddmd_vfc, - [MSM8939_VDDCX] = &msm8939_vddcx, - [MSM8939_VDDCX_AO] = &msm8939_vddcx_ao, - [MSM8939_VDDCX_VFC] = &msm8939_vddcx_vfc, - [MSM8939_VDDMX] = &msm8939_vddmx, - [MSM8939_VDDMX_AO] = &msm8939_vddmx_ao, + [MSM8939_VDDMDCX] = &SMPA1_CORNER_vddmd, + [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_vddmd_ao, + [MSM8939_VDDMDCX_VFC] = &SMPA1_vddmd_vfc, + [MSM8939_VDDCX] = &SMPA2_CORNER_vddcx, + [MSM8939_VDDCX_AO] = &SMPA2_CORNER_vddcx_ao, + [MSM8939_VDDCX_VFC] = &SMPA2_vddcx_vfc, + [MSM8939_VDDMX] = &LDOA3_CORNER_vddmx, + [MSM8939_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, }; static const struct rpmpd_desc msm8939_desc = { @@ -182,17 +181,12 @@ static const struct rpmpd_desc msm8939_desc = { }; /* msm8916 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8916, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(msm8916, vddmx, vddmx_ao, LDOA, CORNER, 3); - -DEFINE_RPMPD_VFC(msm8916, vddcx_vfc, SMPA, 1); - static struct rpmpd *msm8916_rpmpds[] = { - [MSM8916_VDDCX] = &msm8916_vddcx, - [MSM8916_VDDCX_AO] = &msm8916_vddcx_ao, - [MSM8916_VDDCX_VFC] = &msm8916_vddcx_vfc, - [MSM8916_VDDMX] = &msm8916_vddmx, - [MSM8916_VDDMX_AO] = &msm8916_vddmx_ao, + [MSM8916_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8916_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8916_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8916_VDDMX] = &LDOA3_CORNER_vddmx, + [MSM8916_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, }; static const struct rpmpd_desc msm8916_desc = { @@ -202,20 +196,20 @@ static const struct rpmpd_desc msm8916_desc = { }; /* msm8953 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8953, vddmd, vddmd_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_PAIR(msm8953, vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(msm8953, vddmx, vddmx_ao, SMPA, LEVEL, 7); +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); -DEFINE_RPMPD_VFL(msm8953, vddcx_vfl, SMPA, 2); +DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); static struct rpmpd *msm8953_rpmpds[] = { - [MSM8953_VDDMD] = &msm8953_vddmd, - [MSM8953_VDDMD_AO] = &msm8953_vddmd_ao, - [MSM8953_VDDCX] = &msm8953_vddcx, - [MSM8953_VDDCX_AO] = &msm8953_vddcx_ao, - [MSM8953_VDDCX_VFL] = &msm8953_vddcx_vfl, - [MSM8953_VDDMX] = &msm8953_vddmx, - [MSM8953_VDDMX_AO] = &msm8953_vddmx_ao, + [MSM8953_VDDMD] = &SMPA1_LEVEL_vddmd, + [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_vddmd_ao, + [MSM8953_VDDCX] = &SMPA2_LEVEL_vddcx, + [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, + [MSM8953_VDDCX_VFL] = &SMPA2_vddcx_vfl, + [MSM8953_VDDMX] = &SMPA7_LEVEL_vddmx, + [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_vddmx_ao, }; static const struct rpmpd_desc msm8953_desc = { @@ -225,19 +219,18 @@ static const struct rpmpd_desc msm8953_desc = { }; /* msm8976 RPM Power Domains */ -DEFINE_RPMPD_PAIR(msm8976, vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(msm8976, vddmx, vddmx_ao, SMPA, LEVEL, 6); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); -DEFINE_RPMPD_VFL(msm8976, vddcx_vfl, RWSC, 2); -DEFINE_RPMPD_VFL(msm8976, vddmx_vfl, RWSM, 6); +DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); +DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); static struct rpmpd *msm8976_rpmpds[] = { - [MSM8976_VDDCX] = &msm8976_vddcx, - [MSM8976_VDDCX_AO] = &msm8976_vddcx_ao, - [MSM8976_VDDCX_VFL] = &msm8976_vddcx_vfl, - [MSM8976_VDDMX] = &msm8976_vddmx, - [MSM8976_VDDMX_AO] = &msm8976_vddmx_ao, - [MSM8976_VDDMX_VFL] = &msm8976_vddmx_vfl, + [MSM8976_VDDCX] = &SMPA2_LEVEL_vddcx, + [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, + [MSM8976_VDDCX_VFL] = &RWSC2_vddcx_vfl, + [MSM8976_VDDMX] = &SMPA6_LEVEL_vddmx, + [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_vddmx_ao, + [MSM8976_VDDMX_VFL] = &RWSM6_vddmx_vfl, }; static const struct rpmpd_desc msm8976_desc = { @@ -247,22 +240,20 @@ static const struct rpmpd_desc msm8976_desc = { }; /* msm8994 RPM Power domains */ -DEFINE_RPMPD_PAIR(msm8994, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(msm8994, vddmx, vddmx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ -DEFINE_RPMPD_CORNER(msm8994, vddgfx, SMPB, 2); +DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); -DEFINE_RPMPD_VFC(msm8994, vddcx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(msm8994, vddgfx_vfc, SMPB, 2); +DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); static struct rpmpd *msm8994_rpmpds[] = { - [MSM8994_VDDCX] = &msm8994_vddcx, - [MSM8994_VDDCX_AO] = &msm8994_vddcx_ao, - [MSM8994_VDDCX_VFC] = &msm8994_vddcx_vfc, - [MSM8994_VDDMX] = &msm8994_vddmx, - [MSM8994_VDDMX_AO] = &msm8994_vddmx_ao, - [MSM8994_VDDGFX] = &msm8994_vddgfx, - [MSM8994_VDDGFX_VFC] = &msm8994_vddgfx_vfc, + [MSM8994_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8994_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8994_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8994_VDDMX] = &SMPA2_CORNER_vddmx, + [MSM8994_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + [MSM8994_VDDGFX] = &SMPB2_vddgfx_corner, + [MSM8994_VDDGFX_VFC] = &SMPB2_vddgfx_vfc, }; static const struct rpmpd_desc msm8994_desc = { @@ -272,21 +263,18 @@ static const struct rpmpd_desc msm8994_desc = { }; /* msm8996 RPM Power domains */ -DEFINE_RPMPD_PAIR(msm8996, vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(msm8996, vddmx, vddmx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_CORNER(msm8996, vddsscx, LDOA, 26); +DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); -DEFINE_RPMPD_VFC(msm8996, vddcx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(msm8996, vddsscx_vfc, LDOA, 26); +DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); static struct rpmpd *msm8996_rpmpds[] = { - [MSM8996_VDDCX] = &msm8996_vddcx, - [MSM8996_VDDCX_AO] = &msm8996_vddcx_ao, - [MSM8996_VDDCX_VFC] = &msm8996_vddcx_vfc, - [MSM8996_VDDMX] = &msm8996_vddmx, - [MSM8996_VDDMX_AO] = &msm8996_vddmx_ao, - [MSM8996_VDDSSCX] = &msm8996_vddsscx, - [MSM8996_VDDSSCX_VFC] = &msm8996_vddsscx_vfc, + [MSM8996_VDDCX] = &SMPA1_CORNER_vddcx, + [MSM8996_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, + [MSM8996_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8996_VDDMX] = &SMPA2_CORNER_vddmx, + [MSM8996_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + [MSM8996_VDDSSCX] = &LDOA26_vddsscx_corner, + [MSM8996_VDDSSCX_VFC] = &LDOA26_vddsscx_vfc, }; static const struct rpmpd_desc msm8996_desc = { @@ -296,29 +284,29 @@ static const struct rpmpd_desc msm8996_desc = { }; /* msm8998 RPM Power domains */ -DEFINE_RPMPD_PAIR(msm8998, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(msm8998, vddcx_vfl, RWCX, 0); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); -DEFINE_RPMPD_PAIR(msm8998, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(msm8998, vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); -DEFINE_RPMPD_LEVEL(msm8998, vdd_ssccx, RWSC, 0); -DEFINE_RPMPD_VFL(msm8998, vdd_ssccx_vfl, RWSC, 0); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); -DEFINE_RPMPD_LEVEL(msm8998, vdd_sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(msm8998, vdd_sscmx_vfl, RWSM, 0); +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &msm8998_vddcx, - [MSM8998_VDDCX_AO] = &msm8998_vddcx_ao, - [MSM8998_VDDCX_VFL] = &msm8998_vddcx_vfl, - [MSM8998_VDDMX] = &msm8998_vddmx, - [MSM8998_VDDMX_AO] = &msm8998_vddmx_ao, - [MSM8998_VDDMX_VFL] = &msm8998_vddmx_vfl, - [MSM8998_SSCCX] = &msm8998_vdd_ssccx, - [MSM8998_SSCCX_VFL] = &msm8998_vdd_ssccx_vfl, - [MSM8998_SSCMX] = &msm8998_vdd_sscmx, - [MSM8998_SSCMX_VFL] = &msm8998_vdd_sscmx_vfl, + [MSM8998_VDDCX] = &RWCX0_LEVEL_vddcx, + [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [MSM8998_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [MSM8998_VDDMX] = &RWMX0_LEVEL_vddmx, + [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [MSM8998_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [MSM8998_SSCCX] = &RWSC0_vdd_ssccx_lvl, + [MSM8998_SSCCX_VFL] = &RWSC0_vdd_ssccx_vfl, + [MSM8998_SSCMX] = &RWSM0_vdd_sscmx_lvl, + [MSM8998_SSCMX_VFL] = &RWSM0_vdd_sscmx_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -328,23 +316,20 @@ static const struct rpmpd_desc msm8998_desc = { }; /* qcs404 RPM Power domains */ -DEFINE_RPMPD_PAIR(qcs404, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(qcs404, vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); -DEFINE_RPMPD_LEVEL(qcs404, vdd_lpicx, RWLC, 0); -DEFINE_RPMPD_VFL(qcs404, vdd_lpicx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(qcs404, vdd_lpimx, RWLM, 0); -DEFINE_RPMPD_VFL(qcs404, vdd_lpimx_vfl, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &qcs404_vddmx, - [QCS404_VDDMX_AO] = &qcs404_vddmx_ao, - [QCS404_VDDMX_VFL] = &qcs404_vddmx_vfl, - [QCS404_LPICX] = &qcs404_vdd_lpicx, - [QCS404_LPICX_VFL] = &qcs404_vdd_lpicx_vfl, - [QCS404_LPIMX] = &qcs404_vdd_lpimx, - [QCS404_LPIMX_VFL] = &qcs404_vdd_lpimx_vfl, + [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, + [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [QCS404_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [QCS404_LPICX] = &RWLC0_vdd_lpicx_lvl, + [QCS404_LPICX_VFL] = &RWLC0_vdd_lpicx_vfl, + [QCS404_LPIMX] = &RWLM0_vdd_lpimx_lvl, + [QCS404_LPIMX_VFL] = &RWLM0_vdd_lpimx_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -354,29 +339,24 @@ static const struct rpmpd_desc qcs404_desc = { }; /* sdm660 RPM Power domains */ -DEFINE_RPMPD_PAIR(sdm660, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(sdm660, vddcx_vfl, RWCX, 0); -DEFINE_RPMPD_PAIR(sdm660, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(sdm660, vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); -DEFINE_RPMPD_LEVEL(sdm660, vdd_ssccx, RWLC, 0); -DEFINE_RPMPD_VFL(sdm660, vdd_ssccx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(sdm660, vdd_sscmx, RWLM, 0); -DEFINE_RPMPD_VFL(sdm660, vdd_sscmx_vfl, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &sdm660_vddcx, - [SDM660_VDDCX_AO] = &sdm660_vddcx_ao, - [SDM660_VDDCX_VFL] = &sdm660_vddcx_vfl, - [SDM660_VDDMX] = &sdm660_vddmx, - [SDM660_VDDMX_AO] = &sdm660_vddmx_ao, - [SDM660_VDDMX_VFL] = &sdm660_vddmx_vfl, - [SDM660_SSCCX] = &sdm660_vdd_ssccx, - [SDM660_SSCCX_VFL] = &sdm660_vdd_ssccx_vfl, - [SDM660_SSCMX] = &sdm660_vdd_sscmx, - [SDM660_SSCMX_VFL] = &sdm660_vdd_sscmx_vfl, + [SDM660_VDDCX] = &RWCX0_LEVEL_vddcx, + [SDM660_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SDM660_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SDM660_VDDMX] = &RWMX0_LEVEL_vddmx, + [SDM660_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SDM660_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SDM660_SSCCX] = &RWLC0_vdd_ssccx_lvl, + [SDM660_SSCCX_VFL] = &RWLC0_vdd_ssccx_vfl, + [SDM660_SSCMX] = &RWLM0_vdd_sscmx_lvl, + [SDM660_SSCMX_VFL] = &RWLM0_vdd_sscmx_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -386,24 +366,18 @@ static const struct rpmpd_desc sdm660_desc = { }; /* sm4250/6115 RPM Power domains */ -DEFINE_RPMPD_PAIR(sm6115, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6115, vddcx_vfl, RWCX, 0); - -DEFINE_RPMPD_PAIR(sm6115, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6115, vddmx_vfl, RWMX, 0); - -DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_mx, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); +DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &sm6115_vddcx, - [SM6115_VDDCX_AO] = &sm6115_vddcx_ao, - [SM6115_VDDCX_VFL] = &sm6115_vddcx_vfl, - [SM6115_VDDMX] = &sm6115_vddmx, - [SM6115_VDDMX_AO] = &sm6115_vddmx_ao, - [SM6115_VDDMX_VFL] = &sm6115_vddmx_vfl, - [SM6115_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, - [SM6115_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, + [SM6115_VDDCX] = &RWCX0_LEVEL_vddcx, + [SM6115_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SM6115_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SM6115_VDDMX] = &RWMX0_LEVEL_vddmx, + [SM6115_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SM6115_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SM6115_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, + [SM6115_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -413,19 +387,13 @@ static const struct rpmpd_desc sm6115_desc = { }; /* sm6125 RPM Power domains */ -DEFINE_RPMPD_PAIR(sm6125, vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6125, vddcx_vfl, RWCX, 0); - -DEFINE_RPMPD_PAIR(sm6125, vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(sm6125, vddmx_vfl, RWMX, 0); - static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &sm6125_vddcx, - [SM6125_VDDCX_AO] = &sm6125_vddcx_ao, - [SM6125_VDDCX_VFL] = &sm6125_vddcx_vfl, - [SM6125_VDDMX] = &sm6125_vddmx, - [SM6125_VDDMX_AO] = &sm6125_vddmx_ao, - [SM6125_VDDMX_VFL] = &sm6125_vddmx_vfl, + [SM6125_VDDCX] = &RWCX0_LEVEL_vddcx, + [SM6125_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SM6125_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SM6125_VDDMX] = &RWMX0_LEVEL_vddmx, + [SM6125_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SM6125_VDDMX_VFL] = &RWMX0_vddmx_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -434,18 +402,18 @@ static const struct rpmpd_desc sm6125_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -DEFINE_RPMPD_PAIR(sm6375, vddgx, vddgx_ao, RWGX, LEVEL, 0); +DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &sm6125_vddcx, - [SM6375_VDDCX_AO] = &sm6125_vddcx_ao, - [SM6375_VDDCX_VFL] = &sm6125_vddcx_vfl, - [SM6375_VDDMX] = &sm6125_vddmx, - [SM6375_VDDMX_AO] = &sm6125_vddmx_ao, - [SM6375_VDDMX_VFL] = &sm6125_vddmx_vfl, - [SM6375_VDDGX] = &sm6375_vddgx, - [SM6375_VDDGX_AO] = &sm6375_vddgx_ao, - [SM6375_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, - [SM6375_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, + [SM6375_VDDCX] = &RWCX0_LEVEL_vddcx, + [SM6375_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [SM6375_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [SM6375_VDDMX] = &RWMX0_LEVEL_vddmx, + [SM6375_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [SM6375_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SM6375_VDDGX] = &RWGX0_LEVEL_vddgx, + [SM6375_VDDGX_AO] = &RWGX0_LEVEL_vddgx_ao, + [SM6375_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, + [SM6375_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -455,14 +423,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &sm6115_vddcx, - [QCM2290_VDDCX_AO] = &sm6115_vddcx_ao, - [QCM2290_VDDCX_VFL] = &sm6115_vddcx_vfl, - [QCM2290_VDDMX] = &sm6115_vddmx, - [QCM2290_VDDMX_AO] = &sm6115_vddmx_ao, - [QCM2290_VDDMX_VFL] = &sm6115_vddmx_vfl, - [QCM2290_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, - [QCM2290_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, + [QCM2290_VDDCX] = &RWCX0_LEVEL_vddcx, + [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, + [QCM2290_VDDCX_VFL] = &RWCX0_vddcx_vfl, + [QCM2290_VDDMX] = &RWMX0_LEVEL_vddmx, + [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, + [QCM2290_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [QCM2290_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, + [QCM2290_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From a5d0e2819fd013e3629d3fedcae877777214ed34 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:00 +0100 Subject: [PATCH 0299/1040] soc: qcom: rpmpd: Bring all definitions to the top Keep all definitions in one place in preparation for a cleanup to make things tidier. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-2-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 111 +++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 62 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index d99a56509e33..7d9e762232ea 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -117,12 +117,58 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); -/* mdm9607 RPM Power Domains */ +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); +DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); +DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); +DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 3); +DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); +DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); + +DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); + +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); +DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); DEFINE_RPMPD_VFL(vddmx_vfl, LDOA, 12); +DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); +DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); + +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); +DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); + +DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); +DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); + +DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); + +DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); +DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); +DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); +DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); + +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); +DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); +DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); + +/* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { [MDM9607_VDDCX] = &SMPA3_LEVEL_vddcx, [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_vddcx_ao, @@ -139,9 +185,6 @@ static const struct rpmpd_desc mdm9607_desc = { }; /* msm8226 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); - static struct rpmpd *msm8226_rpmpds[] = { [MSM8226_VDDCX] = &SMPA1_CORNER_vddcx, [MSM8226_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, @@ -155,14 +198,6 @@ static const struct rpmpd_desc msm8226_desc = { }; /* msm8939 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); - -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); - -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); - static struct rpmpd *msm8939_rpmpds[] = { [MSM8939_VDDMDCX] = &SMPA1_CORNER_vddmd, [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_vddmd_ao, @@ -196,12 +231,6 @@ static const struct rpmpd_desc msm8916_desc = { }; /* msm8953 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); - -DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); - static struct rpmpd *msm8953_rpmpds[] = { [MSM8953_VDDMD] = &SMPA1_LEVEL_vddmd, [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_vddmd_ao, @@ -219,11 +248,6 @@ static const struct rpmpd_desc msm8953_desc = { }; /* msm8976 RPM Power Domains */ -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); - -DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); -DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); - static struct rpmpd *msm8976_rpmpds[] = { [MSM8976_VDDCX] = &SMPA2_LEVEL_vddcx, [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, @@ -240,18 +264,14 @@ static const struct rpmpd_desc msm8976_desc = { }; /* msm8994 RPM Power domains */ -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); -/* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ -DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); - -DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); - static struct rpmpd *msm8994_rpmpds[] = { [MSM8994_VDDCX] = &SMPA1_CORNER_vddcx, [MSM8994_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, [MSM8994_VDDCX_VFC] = &SMPA1_vddcx_vfc, [MSM8994_VDDMX] = &SMPA2_CORNER_vddmx, [MSM8994_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + + /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ [MSM8994_VDDGFX] = &SMPB2_vddgfx_corner, [MSM8994_VDDGFX_VFC] = &SMPB2_vddgfx_vfc, }; @@ -263,10 +283,6 @@ static const struct rpmpd_desc msm8994_desc = { }; /* msm8996 RPM Power domains */ -DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); - -DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); - static struct rpmpd *msm8996_rpmpds[] = { [MSM8996_VDDCX] = &SMPA1_CORNER_vddcx, [MSM8996_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, @@ -284,18 +300,6 @@ static const struct rpmpd_desc msm8996_desc = { }; /* msm8998 RPM Power domains */ -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); - -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); - -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); - -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); - static struct rpmpd *msm8998_rpmpds[] = { [MSM8998_VDDCX] = &RWCX0_LEVEL_vddcx, [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, @@ -316,12 +320,6 @@ static const struct rpmpd_desc msm8998_desc = { }; /* qcs404 RPM Power domains */ -DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); - static struct rpmpd *qcs404_rpmpds[] = { [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, @@ -339,13 +337,6 @@ static const struct rpmpd_desc qcs404_desc = { }; /* sdm660 RPM Power domains */ - -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); - -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); - static struct rpmpd *sdm660_rpmpds[] = { [SDM660_VDDCX] = &RWCX0_LEVEL_vddcx, [SDM660_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, @@ -366,9 +357,6 @@ static const struct rpmpd_desc sdm660_desc = { }; /* sm4250/6115 RPM Power domains */ -DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); - static struct rpmpd *sm6115_rpmpds[] = { [SM6115_VDDCX] = &RWCX0_LEVEL_vddcx, [SM6115_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, @@ -402,7 +390,6 @@ static const struct rpmpd_desc sm6125_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); static struct rpmpd *sm6375_rpmpds[] = { [SM6375_VDDCX] = &RWCX0_LEVEL_vddcx, [SM6375_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, From d280f3d66d9a79b1bd50258ccb3fbb413216c1be Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:01 +0100 Subject: [PATCH 0300/1040] soc: qcom: rpmpd: Unify Low Power Island definitions Up until now, we had 2 separate entries for VDD_LPI[CM]X and VDD_LPI_[CM]X which both pointed to the same RPM resource. Fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-3-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 7d9e762232ea..8ba025c4eca3 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -149,11 +149,9 @@ DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_lpicx, RWLC, 0); DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); -DEFINE_RPMPD_LEVEL(vdd_lpimx, RWLM, 0); DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); @@ -324,9 +322,9 @@ static struct rpmpd *qcs404_rpmpds[] = { [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, [QCS404_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [QCS404_LPICX] = &RWLC0_vdd_lpicx_lvl, + [QCS404_LPICX] = &RWLC0_vdd_lpi_cx_lvl, [QCS404_LPICX_VFL] = &RWLC0_vdd_lpicx_vfl, - [QCS404_LPIMX] = &RWLM0_vdd_lpimx_lvl, + [QCS404_LPIMX] = &RWLM0_vdd_lpi_mx_lvl, [QCS404_LPIMX_VFL] = &RWLM0_vdd_lpimx_vfl, }; From 1c940cc42aba5b27a259634f4aedb71e5f46dac1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:02 +0100 Subject: [PATCH 0301/1040] soc: qcom: rpmpd: Remove vdd* from struct names It's rather obvious by the characteristic of these resources that they correspond to some voltage lines governed by RPM. Remove the "vdd" unnecessary prefix from them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-4-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 296 +++++++++++++++++++-------------------- 1 file changed, 148 insertions(+), 148 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 8ba025c4eca3..8f145663af9a 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -117,63 +117,63 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(vddcx, vddcx_ao, SMPA, LEVEL, 3); -DEFINE_RPMPD_VFL(vddcx_vfl, RWCX, 0); -DEFINE_RPMPD_VFL(vddcx_vfl, RWSC, 2); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(vddcx_vfc, SMPA, 2); -DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 2); -DEFINE_RPMPD_VFL(vddcx_vfl, SMPA, 3); +DEFINE_RPMPD_PAIR(cx, cx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 2); +DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(cx_vfl, RWCX, 0); +DEFINE_RPMPD_VFL(cx_vfl, RWSC, 2); +DEFINE_RPMPD_VFC(cx_vfc, SMPA, 1); +DEFINE_RPMPD_VFC(cx_vfc, SMPA, 2); +DEFINE_RPMPD_VFL(cx_vfl, SMPA, 2); +DEFINE_RPMPD_VFL(cx_vfl, SMPA, 3); -DEFINE_RPMPD_CORNER(vddgfx, SMPB, 2); -DEFINE_RPMPD_VFC(vddgfx_vfc, SMPB, 2); +DEFINE_RPMPD_CORNER(gfx, SMPB, 2); +DEFINE_RPMPD_VFC(gfx_vfc, SMPB, 2); -DEFINE_RPMPD_PAIR(vddgx, vddgx_ao, RWGX, LEVEL, 0); +DEFINE_RPMPD_PAIR(gx, gx_ao, RWGX, LEVEL, 0); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, CORNER, 3); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, LDOA, LEVEL, 12); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 6); -DEFINE_RPMPD_PAIR(vddmx, vddmx_ao, SMPA, LEVEL, 7); -DEFINE_RPMPD_VFL(vddmx_vfl, LDOA, 12); -DEFINE_RPMPD_VFL(vddmx_vfl, RWMX, 0); -DEFINE_RPMPD_VFL(vddmx_vfl, RWSM, 6); +DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, CORNER, 3); +DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_PAIR(mx, mx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 6); +DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 7); +DEFINE_RPMPD_VFL(mx_vfl, LDOA, 12); +DEFINE_RPMPD_VFL(mx_vfl, RWMX, 0); +DEFINE_RPMPD_VFL(mx_vfl, RWSM, 6); -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(vddmd, vddmd_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_VFC(vddmd_vfc, SMPA, 1); +DEFINE_RPMPD_PAIR(md, md_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(md, md_ao, SMPA, LEVEL, 1); +DEFINE_RPMPD_VFC(md_vfc, SMPA, 1); -DEFINE_RPMPD_LEVEL(vdd_lpi_cx, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_lpicx_vfl, RWLC, 0); +DEFINE_RPMPD_LEVEL(lpi_cx, RWLC, 0); +DEFINE_RPMPD_VFL(lpicx_vfl, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_lpi_mx, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_lpimx_vfl, RWLM, 0); +DEFINE_RPMPD_LEVEL(lpi_mx, RWLM, 0); +DEFINE_RPMPD_VFL(lpimx_vfl, RWLM, 0); -DEFINE_RPMPD_CORNER(vddsscx, LDOA, 26); -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWLC, 0); -DEFINE_RPMPD_LEVEL(vdd_ssccx, RWSC, 0); -DEFINE_RPMPD_VFC(vddsscx_vfc, LDOA, 26); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWLC, 0); -DEFINE_RPMPD_VFL(vdd_ssccx_vfl, RWSC, 0); +DEFINE_RPMPD_CORNER(sscx, LDOA, 26); +DEFINE_RPMPD_LEVEL(ssccx, RWLC, 0); +DEFINE_RPMPD_LEVEL(ssccx, RWSC, 0); +DEFINE_RPMPD_VFC(sscx_vfc, LDOA, 26); +DEFINE_RPMPD_VFL(ssccx_vfl, RWLC, 0); +DEFINE_RPMPD_VFL(ssccx_vfl, RWSC, 0); -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWLM, 0); -DEFINE_RPMPD_LEVEL(vdd_sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWLM, 0); -DEFINE_RPMPD_VFL(vdd_sscmx_vfl, RWSM, 0); +DEFINE_RPMPD_LEVEL(sscmx, RWLM, 0); +DEFINE_RPMPD_LEVEL(sscmx, RWSM, 0); +DEFINE_RPMPD_VFL(sscmx_vfl, RWLM, 0); +DEFINE_RPMPD_VFL(sscmx_vfl, RWSM, 0); /* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { - [MDM9607_VDDCX] = &SMPA3_LEVEL_vddcx, - [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_vddcx_ao, - [MDM9607_VDDCX_VFL] = &SMPA3_vddcx_vfl, - [MDM9607_VDDMX] = &LDOA12_LEVEL_vddmx, - [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_vddmx_ao, - [MDM9607_VDDMX_VFL] = &LDOA12_vddmx_vfl, + [MDM9607_VDDCX] = &SMPA3_LEVEL_cx, + [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_cx_ao, + [MDM9607_VDDCX_VFL] = &SMPA3_cx_vfl, + [MDM9607_VDDMX] = &LDOA12_LEVEL_mx, + [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_mx_ao, + [MDM9607_VDDMX_VFL] = &LDOA12_mx_vfl, }; static const struct rpmpd_desc mdm9607_desc = { @@ -184,9 +184,9 @@ static const struct rpmpd_desc mdm9607_desc = { /* msm8226 RPM Power Domains */ static struct rpmpd *msm8226_rpmpds[] = { - [MSM8226_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8226_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8226_VDDCX_VFC] = &SMPA1_vddcx_vfc, + [MSM8226_VDDCX] = &SMPA1_CORNER_cx, + [MSM8226_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8226_VDDCX_VFC] = &SMPA1_cx_vfc, }; static const struct rpmpd_desc msm8226_desc = { @@ -197,14 +197,14 @@ static const struct rpmpd_desc msm8226_desc = { /* msm8939 RPM Power Domains */ static struct rpmpd *msm8939_rpmpds[] = { - [MSM8939_VDDMDCX] = &SMPA1_CORNER_vddmd, - [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_vddmd_ao, - [MSM8939_VDDMDCX_VFC] = &SMPA1_vddmd_vfc, - [MSM8939_VDDCX] = &SMPA2_CORNER_vddcx, - [MSM8939_VDDCX_AO] = &SMPA2_CORNER_vddcx_ao, - [MSM8939_VDDCX_VFC] = &SMPA2_vddcx_vfc, - [MSM8939_VDDMX] = &LDOA3_CORNER_vddmx, - [MSM8939_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, + [MSM8939_VDDMDCX] = &SMPA1_CORNER_md, + [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_md_ao, + [MSM8939_VDDMDCX_VFC] = &SMPA1_md_vfc, + [MSM8939_VDDCX] = &SMPA2_CORNER_cx, + [MSM8939_VDDCX_AO] = &SMPA2_CORNER_cx_ao, + [MSM8939_VDDCX_VFC] = &SMPA2_cx_vfc, + [MSM8939_VDDMX] = &LDOA3_CORNER_mx, + [MSM8939_VDDMX_AO] = &LDOA3_CORNER_mx_ao, }; static const struct rpmpd_desc msm8939_desc = { @@ -215,11 +215,11 @@ static const struct rpmpd_desc msm8939_desc = { /* msm8916 RPM Power Domains */ static struct rpmpd *msm8916_rpmpds[] = { - [MSM8916_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8916_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8916_VDDCX_VFC] = &SMPA1_vddcx_vfc, - [MSM8916_VDDMX] = &LDOA3_CORNER_vddmx, - [MSM8916_VDDMX_AO] = &LDOA3_CORNER_vddmx_ao, + [MSM8916_VDDCX] = &SMPA1_CORNER_cx, + [MSM8916_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8916_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8916_VDDMX] = &LDOA3_CORNER_mx, + [MSM8916_VDDMX_AO] = &LDOA3_CORNER_mx_ao, }; static const struct rpmpd_desc msm8916_desc = { @@ -230,13 +230,13 @@ static const struct rpmpd_desc msm8916_desc = { /* msm8953 RPM Power Domains */ static struct rpmpd *msm8953_rpmpds[] = { - [MSM8953_VDDMD] = &SMPA1_LEVEL_vddmd, - [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_vddmd_ao, - [MSM8953_VDDCX] = &SMPA2_LEVEL_vddcx, - [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, - [MSM8953_VDDCX_VFL] = &SMPA2_vddcx_vfl, - [MSM8953_VDDMX] = &SMPA7_LEVEL_vddmx, - [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_vddmx_ao, + [MSM8953_VDDMD] = &SMPA1_LEVEL_md, + [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_md_ao, + [MSM8953_VDDCX] = &SMPA2_LEVEL_cx, + [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, + [MSM8953_VDDCX_VFL] = &SMPA2_cx_vfl, + [MSM8953_VDDMX] = &SMPA7_LEVEL_mx, + [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_mx_ao, }; static const struct rpmpd_desc msm8953_desc = { @@ -247,12 +247,12 @@ static const struct rpmpd_desc msm8953_desc = { /* msm8976 RPM Power Domains */ static struct rpmpd *msm8976_rpmpds[] = { - [MSM8976_VDDCX] = &SMPA2_LEVEL_vddcx, - [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_vddcx_ao, - [MSM8976_VDDCX_VFL] = &RWSC2_vddcx_vfl, - [MSM8976_VDDMX] = &SMPA6_LEVEL_vddmx, - [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_vddmx_ao, - [MSM8976_VDDMX_VFL] = &RWSM6_vddmx_vfl, + [MSM8976_VDDCX] = &SMPA2_LEVEL_cx, + [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, + [MSM8976_VDDCX_VFL] = &RWSC2_cx_vfl, + [MSM8976_VDDMX] = &SMPA6_LEVEL_mx, + [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_mx_ao, + [MSM8976_VDDMX_VFL] = &RWSM6_mx_vfl, }; static const struct rpmpd_desc msm8976_desc = { @@ -263,15 +263,15 @@ static const struct rpmpd_desc msm8976_desc = { /* msm8994 RPM Power domains */ static struct rpmpd *msm8994_rpmpds[] = { - [MSM8994_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8994_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8994_VDDCX_VFC] = &SMPA1_vddcx_vfc, - [MSM8994_VDDMX] = &SMPA2_CORNER_vddmx, - [MSM8994_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, + [MSM8994_VDDCX] = &SMPA1_CORNER_cx, + [MSM8994_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8994_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8994_VDDMX] = &SMPA2_CORNER_mx, + [MSM8994_VDDMX_AO] = &SMPA2_CORNER_mx_ao, /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ - [MSM8994_VDDGFX] = &SMPB2_vddgfx_corner, - [MSM8994_VDDGFX_VFC] = &SMPB2_vddgfx_vfc, + [MSM8994_VDDGFX] = &SMPB2_gfx_corner, + [MSM8994_VDDGFX_VFC] = &SMPB2_gfx_vfc, }; static const struct rpmpd_desc msm8994_desc = { @@ -282,13 +282,13 @@ static const struct rpmpd_desc msm8994_desc = { /* msm8996 RPM Power domains */ static struct rpmpd *msm8996_rpmpds[] = { - [MSM8996_VDDCX] = &SMPA1_CORNER_vddcx, - [MSM8996_VDDCX_AO] = &SMPA1_CORNER_vddcx_ao, - [MSM8996_VDDCX_VFC] = &SMPA1_vddcx_vfc, - [MSM8996_VDDMX] = &SMPA2_CORNER_vddmx, - [MSM8996_VDDMX_AO] = &SMPA2_CORNER_vddmx_ao, - [MSM8996_VDDSSCX] = &LDOA26_vddsscx_corner, - [MSM8996_VDDSSCX_VFC] = &LDOA26_vddsscx_vfc, + [MSM8996_VDDCX] = &SMPA1_CORNER_cx, + [MSM8996_VDDCX_AO] = &SMPA1_CORNER_cx_ao, + [MSM8996_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8996_VDDMX] = &SMPA2_CORNER_mx, + [MSM8996_VDDMX_AO] = &SMPA2_CORNER_mx_ao, + [MSM8996_VDDSSCX] = &LDOA26_sscx_corner, + [MSM8996_VDDSSCX_VFC] = &LDOA26_sscx_vfc, }; static const struct rpmpd_desc msm8996_desc = { @@ -299,16 +299,16 @@ static const struct rpmpd_desc msm8996_desc = { /* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &RWCX0_LEVEL_vddcx, - [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [MSM8998_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [MSM8998_VDDMX] = &RWMX0_LEVEL_vddmx, - [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [MSM8998_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [MSM8998_SSCCX] = &RWSC0_vdd_ssccx_lvl, - [MSM8998_SSCCX_VFL] = &RWSC0_vdd_ssccx_vfl, - [MSM8998_SSCMX] = &RWSM0_vdd_sscmx_lvl, - [MSM8998_SSCMX_VFL] = &RWSM0_vdd_sscmx_vfl, + [MSM8998_VDDCX] = &RWCX0_LEVEL_cx, + [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [MSM8998_VDDCX_VFL] = &RWCX0_cx_vfl, + [MSM8998_VDDMX] = &RWMX0_LEVEL_mx, + [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [MSM8998_VDDMX_VFL] = &RWMX0_mx_vfl, + [MSM8998_SSCCX] = &RWSC0_ssccx_lvl, + [MSM8998_SSCCX_VFL] = &RWSC0_ssccx_vfl, + [MSM8998_SSCMX] = &RWSM0_sscmx_lvl, + [MSM8998_SSCMX_VFL] = &RWSM0_sscmx_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -319,13 +319,13 @@ static const struct rpmpd_desc msm8998_desc = { /* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &RWMX0_LEVEL_vddmx, - [QCS404_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [QCS404_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [QCS404_LPICX] = &RWLC0_vdd_lpi_cx_lvl, - [QCS404_LPICX_VFL] = &RWLC0_vdd_lpicx_vfl, - [QCS404_LPIMX] = &RWLM0_vdd_lpi_mx_lvl, - [QCS404_LPIMX_VFL] = &RWLM0_vdd_lpimx_vfl, + [QCS404_VDDMX] = &RWMX0_LEVEL_mx, + [QCS404_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [QCS404_VDDMX_VFL] = &RWMX0_mx_vfl, + [QCS404_LPICX] = &RWLC0_lpi_cx_lvl, + [QCS404_LPICX_VFL] = &RWLC0_lpicx_vfl, + [QCS404_LPIMX] = &RWLM0_lpi_mx_lvl, + [QCS404_LPIMX_VFL] = &RWLM0_lpimx_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -336,16 +336,16 @@ static const struct rpmpd_desc qcs404_desc = { /* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &RWCX0_LEVEL_vddcx, - [SDM660_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SDM660_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SDM660_VDDMX] = &RWMX0_LEVEL_vddmx, - [SDM660_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SDM660_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [SDM660_SSCCX] = &RWLC0_vdd_ssccx_lvl, - [SDM660_SSCCX_VFL] = &RWLC0_vdd_ssccx_vfl, - [SDM660_SSCMX] = &RWLM0_vdd_sscmx_lvl, - [SDM660_SSCMX_VFL] = &RWLM0_vdd_sscmx_vfl, + [SDM660_VDDCX] = &RWCX0_LEVEL_cx, + [SDM660_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SDM660_VDDCX_VFL] = &RWCX0_cx_vfl, + [SDM660_VDDMX] = &RWMX0_LEVEL_mx, + [SDM660_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SDM660_VDDMX_VFL] = &RWMX0_mx_vfl, + [SDM660_SSCCX] = &RWLC0_ssccx_lvl, + [SDM660_SSCCX_VFL] = &RWLC0_ssccx_vfl, + [SDM660_SSCMX] = &RWLM0_sscmx_lvl, + [SDM660_SSCMX_VFL] = &RWLM0_sscmx_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -356,14 +356,14 @@ static const struct rpmpd_desc sdm660_desc = { /* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &RWCX0_LEVEL_vddcx, - [SM6115_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SM6115_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SM6115_VDDMX] = &RWMX0_LEVEL_vddmx, - [SM6115_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SM6115_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [SM6115_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, - [SM6115_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, + [SM6115_VDDCX] = &RWCX0_LEVEL_cx, + [SM6115_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SM6115_VDDCX_VFL] = &RWCX0_cx_vfl, + [SM6115_VDDMX] = &RWMX0_LEVEL_mx, + [SM6115_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SM6115_VDDMX_VFL] = &RWMX0_mx_vfl, + [SM6115_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, + [SM6115_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -374,12 +374,12 @@ static const struct rpmpd_desc sm6115_desc = { /* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &RWCX0_LEVEL_vddcx, - [SM6125_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SM6125_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SM6125_VDDMX] = &RWMX0_LEVEL_vddmx, - [SM6125_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SM6125_VDDMX_VFL] = &RWMX0_vddmx_vfl, + [SM6125_VDDCX] = &RWCX0_LEVEL_cx, + [SM6125_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SM6125_VDDCX_VFL] = &RWCX0_cx_vfl, + [SM6125_VDDMX] = &RWMX0_LEVEL_mx, + [SM6125_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SM6125_VDDMX_VFL] = &RWMX0_mx_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -389,16 +389,16 @@ static const struct rpmpd_desc sm6125_desc = { }; static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &RWCX0_LEVEL_vddcx, - [SM6375_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [SM6375_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [SM6375_VDDMX] = &RWMX0_LEVEL_vddmx, - [SM6375_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [SM6375_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [SM6375_VDDGX] = &RWGX0_LEVEL_vddgx, - [SM6375_VDDGX_AO] = &RWGX0_LEVEL_vddgx_ao, - [SM6375_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, - [SM6375_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, + [SM6375_VDDCX] = &RWCX0_LEVEL_cx, + [SM6375_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [SM6375_VDDCX_VFL] = &RWCX0_cx_vfl, + [SM6375_VDDMX] = &RWMX0_LEVEL_mx, + [SM6375_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [SM6375_VDDMX_VFL] = &RWMX0_mx_vfl, + [SM6375_VDDGX] = &RWGX0_LEVEL_gx, + [SM6375_VDDGX_AO] = &RWGX0_LEVEL_gx_ao, + [SM6375_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, + [SM6375_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -408,14 +408,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &RWCX0_LEVEL_vddcx, - [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_vddcx_ao, - [QCM2290_VDDCX_VFL] = &RWCX0_vddcx_vfl, - [QCM2290_VDDMX] = &RWMX0_LEVEL_vddmx, - [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_vddmx_ao, - [QCM2290_VDDMX_VFL] = &RWMX0_vddmx_vfl, - [QCM2290_VDD_LPI_CX] = &RWLC0_vdd_lpi_cx_lvl, - [QCM2290_VDD_LPI_MX] = &RWLM0_vdd_lpi_mx_lvl, + [QCM2290_VDDCX] = &RWCX0_LEVEL_cx, + [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, + [QCM2290_VDDCX_VFL] = &RWCX0_cx_vfl, + [QCM2290_VDDMX] = &RWMX0_LEVEL_mx, + [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, + [QCM2290_VDDMX_VFL] = &RWMX0_mx_vfl, + [QCM2290_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, + [QCM2290_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From 91c0bcef25f985fd974b6f1ba3d3d7383ac032d2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:03 +0100 Subject: [PATCH 0302/1040] soc: qcom: rpmpd: Expand struct definition macros Expand the struct definition macros to make things easier to see and maintain. Now that the macros are unnecessary, remove them. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-5-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 523 ++++++++++++++++++++++++++++++++------- 1 file changed, 433 insertions(+), 90 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 8f145663af9a..df4e0d8a2aa9 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -40,56 +40,6 @@ #define MAX_CORNER_RPMPD_STATE 6 -#define DEFINE_RPMPD_PAIR(_name, _active, r_type, r_key, r_id) \ - static struct rpmpd r_type##r_id##_##r_key##_##_active; \ - static struct rpmpd r_type##r_id##_##r_key##_##_name = { \ - .pd = { .name = #_name, }, \ - .peer = &r_type##r_id##_##r_key##_##_active, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_##r_key, \ - }; \ - static struct rpmpd r_type##r_id##_##r_key##_##_active = { \ - .pd = { .name = #_active, }, \ - .peer = &r_type##r_id##_##r_key##_##_name, \ - .active_only = true, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_##r_key, \ - } - -#define DEFINE_RPMPD_CORNER(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name##_corner = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_CORNER, \ - } - -#define DEFINE_RPMPD_LEVEL(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name##_lvl = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_LEVEL, \ - } - -#define DEFINE_RPMPD_VFC(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_FLOOR_CORNER, \ - } - -#define DEFINE_RPMPD_VFL(_name, r_type, r_id) \ - static struct rpmpd r_type##r_id##_##_name = { \ - .pd = { .name = #_name, }, \ - .res_type = RPMPD_##r_type, \ - .res_id = r_id, \ - .key = KEY_FLOOR_LEVEL, \ - } - struct rpmpd_req { __le32 key; __le32 nbytes; @@ -117,54 +67,447 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); -DEFINE_RPMPD_PAIR(cx, cx_ao, RWCX, LEVEL, 0); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 2); -DEFINE_RPMPD_PAIR(cx, cx_ao, SMPA, LEVEL, 3); -DEFINE_RPMPD_VFL(cx_vfl, RWCX, 0); -DEFINE_RPMPD_VFL(cx_vfl, RWSC, 2); -DEFINE_RPMPD_VFC(cx_vfc, SMPA, 1); -DEFINE_RPMPD_VFC(cx_vfc, SMPA, 2); -DEFINE_RPMPD_VFL(cx_vfl, SMPA, 2); -DEFINE_RPMPD_VFL(cx_vfl, SMPA, 3); +/* CX */ +static struct rpmpd RWCX0_LEVEL_cx_ao; +static struct rpmpd RWCX0_LEVEL_cx = { + .pd = { .name = "cx", }, + .peer = &RWCX0_LEVEL_cx_ao, + .res_type = RPMPD_RWCX, + .res_id = 0, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_CORNER(gfx, SMPB, 2); -DEFINE_RPMPD_VFC(gfx_vfc, SMPB, 2); +static struct rpmpd RWCX0_LEVEL_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &RWCX0_LEVEL_cx, + .active_only = true, + .res_type = RPMPD_RWCX, + .res_id = 0, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_PAIR(gx, gx_ao, RWGX, LEVEL, 0); +static struct rpmpd SMPA1_CORNER_cx_ao; +static struct rpmpd SMPA1_CORNER_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA1_CORNER_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, CORNER, 3); -DEFINE_RPMPD_PAIR(mx, mx_ao, LDOA, LEVEL, 12); -DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, CORNER, 2); -DEFINE_RPMPD_PAIR(mx, mx_ao, RWMX, LEVEL, 0); -DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 6); -DEFINE_RPMPD_PAIR(mx, mx_ao, SMPA, LEVEL, 7); -DEFINE_RPMPD_VFL(mx_vfl, LDOA, 12); -DEFINE_RPMPD_VFL(mx_vfl, RWMX, 0); -DEFINE_RPMPD_VFL(mx_vfl, RWSM, 6); +static struct rpmpd SMPA1_CORNER_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA1_CORNER_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_PAIR(md, md_ao, SMPA, CORNER, 1); -DEFINE_RPMPD_PAIR(md, md_ao, SMPA, LEVEL, 1); -DEFINE_RPMPD_VFC(md_vfc, SMPA, 1); +static struct rpmpd SMPA2_CORNER_cx_ao; +static struct rpmpd SMPA2_CORNER_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA2_CORNER_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_LEVEL(lpi_cx, RWLC, 0); -DEFINE_RPMPD_VFL(lpicx_vfl, RWLC, 0); +static struct rpmpd SMPA2_CORNER_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA2_CORNER_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; -DEFINE_RPMPD_LEVEL(lpi_mx, RWLM, 0); -DEFINE_RPMPD_VFL(lpimx_vfl, RWLM, 0); +static struct rpmpd SMPA2_LEVEL_cx_ao; +static struct rpmpd SMPA2_LEVEL_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA2_LEVEL_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_CORNER(sscx, LDOA, 26); -DEFINE_RPMPD_LEVEL(ssccx, RWLC, 0); -DEFINE_RPMPD_LEVEL(ssccx, RWSC, 0); -DEFINE_RPMPD_VFC(sscx_vfc, LDOA, 26); -DEFINE_RPMPD_VFL(ssccx_vfl, RWLC, 0); -DEFINE_RPMPD_VFL(ssccx_vfl, RWSC, 0); +static struct rpmpd SMPA2_LEVEL_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA2_LEVEL_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_LEVEL, +}; -DEFINE_RPMPD_LEVEL(sscmx, RWLM, 0); -DEFINE_RPMPD_LEVEL(sscmx, RWSM, 0); -DEFINE_RPMPD_VFL(sscmx_vfl, RWLM, 0); -DEFINE_RPMPD_VFL(sscmx_vfl, RWSM, 0); +static struct rpmpd SMPA3_LEVEL_cx_ao; +static struct rpmpd SMPA3_LEVEL_cx = { + .pd = { .name = "cx", }, + .peer = &SMPA3_LEVEL_cx_ao, + .res_type = RPMPD_SMPA, + .res_id = 3, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA3_LEVEL_cx_ao = { + .pd = { .name = "cx_ao", }, + .peer = &SMPA3_LEVEL_cx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 3, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWCX0_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_RWCX, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSC2_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_RWSC, + .res_id = 2, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd SMPA1_cx_vfc = { + .pd = { .name = "cx_vfc", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd SMPA2_cx_vfc = { + .pd = { .name = "cx_vfc", }, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd SMPA2_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd SMPA3_cx_vfl = { + .pd = { .name = "cx_vfl", }, + .res_type = RPMPD_SMPA, + .res_id = 3, + .key = KEY_FLOOR_LEVEL, +}; + +/* G(F)X */ +static struct rpmpd SMPB2_gfx_corner = { + .pd = { .name = "gfx", }, + .res_type = RPMPD_SMPB, + .res_id = 2, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPB2_gfx_vfc = { + .pd = { .name = "gfx_vfc", }, + .res_type = RPMPD_SMPB, + .res_id = 2, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd RWGX0_LEVEL_gx_ao; +static struct rpmpd RWGX0_LEVEL_gx = { + .pd = { .name = "gx", }, + .peer = &RWGX0_LEVEL_gx_ao, + .res_type = RPMPD_RWGX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWGX0_LEVEL_gx_ao = { + .pd = { .name = "gx_ao", }, + .peer = &RWGX0_LEVEL_gx, + .active_only = true, + .res_type = RPMPD_RWGX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +/* MX */ +static struct rpmpd LDOA3_CORNER_mx_ao; +static struct rpmpd LDOA3_CORNER_mx = { + .pd = { .name = "mx", }, + .peer = &LDOA3_CORNER_mx_ao, + .res_type = RPMPD_LDOA, + .res_id = 3, + .key = KEY_CORNER, +}; + +static struct rpmpd LDOA3_CORNER_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &LDOA3_CORNER_mx, + .active_only = true, + .res_type = RPMPD_LDOA, + .res_id = 3, + .key = KEY_CORNER, +}; + +static struct rpmpd LDOA12_LEVEL_mx_ao; +static struct rpmpd LDOA12_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &LDOA12_LEVEL_mx_ao, + .res_type = RPMPD_LDOA, + .res_id = 12, + .key = KEY_LEVEL, +}; + +static struct rpmpd LDOA12_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &LDOA12_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_LDOA, + .res_id = 12, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA2_CORNER_mx_ao; +static struct rpmpd SMPA2_CORNER_mx = { + .pd = { .name = "mx", }, + .peer = &SMPA2_CORNER_mx_ao, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPA2_CORNER_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &SMPA2_CORNER_mx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 2, + .key = KEY_CORNER, +}; + +static struct rpmpd RWMX0_LEVEL_mx_ao; +static struct rpmpd RWMX0_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &RWMX0_LEVEL_mx_ao, + .res_type = RPMPD_RWMX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWMX0_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &RWMX0_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_RWMX, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA6_LEVEL_mx_ao; +static struct rpmpd SMPA6_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &SMPA6_LEVEL_mx_ao, + .res_type = RPMPD_SMPA, + .res_id = 6, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA6_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &SMPA6_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 6, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA7_LEVEL_mx_ao; +static struct rpmpd SMPA7_LEVEL_mx = { + .pd = { .name = "mx", }, + .peer = &SMPA7_LEVEL_mx_ao, + .res_type = RPMPD_SMPA, + .res_id = 7, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA7_LEVEL_mx_ao = { + .pd = { .name = "mx_ao", }, + .peer = &SMPA7_LEVEL_mx, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 7, + .key = KEY_LEVEL, +}; + +static struct rpmpd LDOA12_mx_vfl = { + .pd = { .name = "mx_vfl", }, + .res_type = RPMPD_LDOA, + .res_id = 12, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWMX0_mx_vfl = { + .pd = { .name = "mx_vfl", }, + .res_type = RPMPD_RWMX, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSM6_mx_vfl = { + .pd = { .name = "mx_vfl", }, + .res_type = RPMPD_RWSM, + .res_id = 6, + .key = KEY_FLOOR_LEVEL, +}; + +/* MD */ +static struct rpmpd SMPA1_CORNER_md_ao; +static struct rpmpd SMPA1_CORNER_md = { + .pd = { .name = "md", }, + .peer = &SMPA1_CORNER_md_ao, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPA1_CORNER_md_ao = { + .pd = { .name = "md_ao", }, + .peer = &SMPA1_CORNER_md, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_CORNER, +}; + +static struct rpmpd SMPA1_LEVEL_md_ao; +static struct rpmpd SMPA1_LEVEL_md = { + .pd = { .name = "md", }, + .peer = &SMPA1_LEVEL_md_ao, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA1_LEVEL_md_ao = { + .pd = { .name = "md_ao", }, + .peer = &SMPA1_LEVEL_md, + .active_only = true, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_LEVEL, +}; + +static struct rpmpd SMPA1_md_vfc = { + .pd = { .name = "md_vfc", }, + .res_type = RPMPD_SMPA, + .res_id = 1, + .key = KEY_FLOOR_CORNER, +}; + +/* LPI_CX */ +static struct rpmpd RWLC0_lpi_cx_lvl = { + .pd = { .name = "lpi_cx", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWLC0_lpicx_vfl = { + .pd = { .name = "lpicx_vfl", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +/* LPI_MX */ +static struct rpmpd RWLM0_lpi_mx_lvl = { + .pd = { .name = "lpi_mx", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWLM0_lpimx_vfl = { + .pd = { .name = "lpimx_vfl", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +/* SSC_CX */ +static struct rpmpd LDOA26_sscx_corner = { + .pd = { .name = "sscx", }, + .res_type = RPMPD_LDOA, + .res_id = 26, + .key = KEY_CORNER, +}; + +static struct rpmpd RWLC0_ssccx_lvl = { + .pd = { .name = "ssccx", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWSC0_ssccx_lvl = { + .pd = { .name = "ssccx", }, + .res_type = RPMPD_RWSC, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd LDOA26_sscx_vfc = { + .pd = { .name = "sscx_vfc", }, + .res_type = RPMPD_LDOA, + .res_id = 26, + .key = KEY_FLOOR_CORNER, +}; + +static struct rpmpd RWLC0_ssccx_vfl = { + .pd = { .name = "ssccx_vfl", }, + .res_type = RPMPD_RWLC, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSC0_ssccx_vfl = { + .pd = { .name = "ssccx_vfl", }, + .res_type = RPMPD_RWSC, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +/* SSC_MX */ +static struct rpmpd RWLM0_sscmx_lvl = { + .pd = { .name = "sscmx", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWSM0_sscmx_lvl = { + .pd = { .name = "sscmx", }, + .res_type = RPMPD_RWSM, + .res_id = 0, + .key = KEY_LEVEL, +}; + +static struct rpmpd RWLM0_sscmx_vfl = { + .pd = { .name = "sscmx_vfl", }, + .res_type = RPMPD_RWLM, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; + +static struct rpmpd RWSM0_sscmx_vfl = { + .pd = { .name = "sscmx_vfl", }, + .res_type = RPMPD_RWSM, + .res_id = 0, + .key = KEY_FLOOR_LEVEL, +}; /* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { From 07df05025eb4cb65c1549d392f988aa5eeb9e758 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:04 +0100 Subject: [PATCH 0303/1040] soc: qcom: rpmpd: Improve the naming Now that we aren't bound by the preprocessor macros, improve the naming to be a bit less preprocessor-y and touch up some rpmpd.pd.name fields while at it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-6-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 432 +++++++++++++++++++-------------------- 1 file changed, 216 insertions(+), 216 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index df4e0d8a2aa9..695b2fc56f40 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -68,132 +68,132 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); /* CX */ -static struct rpmpd RWCX0_LEVEL_cx_ao; -static struct rpmpd RWCX0_LEVEL_cx = { +static struct rpmpd cx_rwcx0_lvl_ao; +static struct rpmpd cx_rwcx0_lvl = { .pd = { .name = "cx", }, - .peer = &RWCX0_LEVEL_cx_ao, + .peer = &cx_rwcx0_lvl_ao, .res_type = RPMPD_RWCX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWCX0_LEVEL_cx_ao = { +static struct rpmpd cx_rwcx0_lvl_ao = { .pd = { .name = "cx_ao", }, - .peer = &RWCX0_LEVEL_cx, + .peer = &cx_rwcx0_lvl, .active_only = true, .res_type = RPMPD_RWCX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd SMPA1_CORNER_cx_ao; -static struct rpmpd SMPA1_CORNER_cx = { +static struct rpmpd cx_s1a_corner_ao; +static struct rpmpd cx_s1a_corner = { .pd = { .name = "cx", }, - .peer = &SMPA1_CORNER_cx_ao, + .peer = &cx_s1a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA1_CORNER_cx_ao = { +static struct rpmpd cx_s1a_corner_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA1_CORNER_cx, + .peer = &cx_s1a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_CORNER_cx_ao; -static struct rpmpd SMPA2_CORNER_cx = { +static struct rpmpd cx_s2a_corner_ao; +static struct rpmpd cx_s2a_corner = { .pd = { .name = "cx", }, - .peer = &SMPA2_CORNER_cx_ao, + .peer = &cx_s2a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_CORNER_cx_ao = { +static struct rpmpd cx_s2a_corner_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA2_CORNER_cx, + .peer = &cx_s2a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_LEVEL_cx_ao; -static struct rpmpd SMPA2_LEVEL_cx = { +static struct rpmpd cx_s2a_lvl_ao; +static struct rpmpd cx_s2a_lvl = { .pd = { .name = "cx", }, - .peer = &SMPA2_LEVEL_cx_ao, + .peer = &cx_s2a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_LEVEL, }; -static struct rpmpd SMPA2_LEVEL_cx_ao = { +static struct rpmpd cx_s2a_lvl_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA2_LEVEL_cx, + .peer = &cx_s2a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_LEVEL, }; -static struct rpmpd SMPA3_LEVEL_cx_ao; -static struct rpmpd SMPA3_LEVEL_cx = { +static struct rpmpd cx_s3a_lvl_ao; +static struct rpmpd cx_s3a_lvl = { .pd = { .name = "cx", }, - .peer = &SMPA3_LEVEL_cx_ao, + .peer = &cx_s3a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 3, .key = KEY_LEVEL, }; -static struct rpmpd SMPA3_LEVEL_cx_ao = { +static struct rpmpd cx_s3a_lvl_ao = { .pd = { .name = "cx_ao", }, - .peer = &SMPA3_LEVEL_cx, + .peer = &cx_s3a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 3, .key = KEY_LEVEL, }; -static struct rpmpd RWCX0_cx_vfl = { +static struct rpmpd cx_rwcx0_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_RWCX, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSC2_cx_vfl = { +static struct rpmpd cx_rwsc2_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_RWSC, .res_id = 2, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd SMPA1_cx_vfc = { +static struct rpmpd cx_s1a_vfc = { .pd = { .name = "cx_vfc", }, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd SMPA2_cx_vfc = { +static struct rpmpd cx_s2a_vfc = { .pd = { .name = "cx_vfc", }, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd SMPA2_cx_vfl = { +static struct rpmpd cx_s2a_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd SMPA3_cx_vfl = { +static struct rpmpd cx_s3a_vfl = { .pd = { .name = "cx_vfl", }, .res_type = RPMPD_SMPA, .res_id = 3, @@ -201,32 +201,32 @@ static struct rpmpd SMPA3_cx_vfl = { }; /* G(F)X */ -static struct rpmpd SMPB2_gfx_corner = { +static struct rpmpd gfx_s2b_corner = { .pd = { .name = "gfx", }, .res_type = RPMPD_SMPB, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPB2_gfx_vfc = { +static struct rpmpd gfx_s2b_vfc = { .pd = { .name = "gfx_vfc", }, .res_type = RPMPD_SMPB, .res_id = 2, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd RWGX0_LEVEL_gx_ao; -static struct rpmpd RWGX0_LEVEL_gx = { +static struct rpmpd gx_rwgx0_lvl_ao; +static struct rpmpd gx_rwgx0_lvl = { .pd = { .name = "gx", }, - .peer = &RWGX0_LEVEL_gx_ao, + .peer = &gx_rwgx0_lvl_ao, .res_type = RPMPD_RWGX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWGX0_LEVEL_gx_ao = { +static struct rpmpd gx_rwgx0_lvl_ao = { .pd = { .name = "gx_ao", }, - .peer = &RWGX0_LEVEL_gx, + .peer = &gx_rwgx0_lvl, .active_only = true, .res_type = RPMPD_RWGX, .res_id = 0, @@ -234,129 +234,129 @@ static struct rpmpd RWGX0_LEVEL_gx_ao = { }; /* MX */ -static struct rpmpd LDOA3_CORNER_mx_ao; -static struct rpmpd LDOA3_CORNER_mx = { +static struct rpmpd mx_l3a_corner_ao; +static struct rpmpd mx_l3a_corner = { .pd = { .name = "mx", }, - .peer = &LDOA3_CORNER_mx_ao, + .peer = &mx_l3a_corner_ao, .res_type = RPMPD_LDOA, .res_id = 3, .key = KEY_CORNER, }; -static struct rpmpd LDOA3_CORNER_mx_ao = { +static struct rpmpd mx_l3a_corner_ao = { .pd = { .name = "mx_ao", }, - .peer = &LDOA3_CORNER_mx, + .peer = &mx_l3a_corner, .active_only = true, .res_type = RPMPD_LDOA, .res_id = 3, .key = KEY_CORNER, }; -static struct rpmpd LDOA12_LEVEL_mx_ao; -static struct rpmpd LDOA12_LEVEL_mx = { +static struct rpmpd mx_l12a_lvl_ao; +static struct rpmpd mx_l12a_lvl = { .pd = { .name = "mx", }, - .peer = &LDOA12_LEVEL_mx_ao, + .peer = &mx_l12a_lvl_ao, .res_type = RPMPD_LDOA, .res_id = 12, .key = KEY_LEVEL, }; -static struct rpmpd LDOA12_LEVEL_mx_ao = { +static struct rpmpd mx_l12a_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &LDOA12_LEVEL_mx, + .peer = &mx_l12a_lvl, .active_only = true, .res_type = RPMPD_LDOA, .res_id = 12, .key = KEY_LEVEL, }; -static struct rpmpd SMPA2_CORNER_mx_ao; -static struct rpmpd SMPA2_CORNER_mx = { +static struct rpmpd mx_s2a_corner_ao; +static struct rpmpd mx_s2a_corner = { .pd = { .name = "mx", }, - .peer = &SMPA2_CORNER_mx_ao, + .peer = &mx_s2a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd SMPA2_CORNER_mx_ao = { +static struct rpmpd mx_s2a_corner_ao = { .pd = { .name = "mx_ao", }, - .peer = &SMPA2_CORNER_mx, + .peer = &mx_s2a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 2, .key = KEY_CORNER, }; -static struct rpmpd RWMX0_LEVEL_mx_ao; -static struct rpmpd RWMX0_LEVEL_mx = { +static struct rpmpd mx_rwmx0_lvl_ao; +static struct rpmpd mx_rwmx0_lvl = { .pd = { .name = "mx", }, - .peer = &RWMX0_LEVEL_mx_ao, + .peer = &mx_rwmx0_lvl_ao, .res_type = RPMPD_RWMX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWMX0_LEVEL_mx_ao = { +static struct rpmpd mx_rwmx0_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &RWMX0_LEVEL_mx, + .peer = &mx_rwmx0_lvl, .active_only = true, .res_type = RPMPD_RWMX, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd SMPA6_LEVEL_mx_ao; -static struct rpmpd SMPA6_LEVEL_mx = { +static struct rpmpd mx_s6a_lvl_ao; +static struct rpmpd mx_s6a_lvl = { .pd = { .name = "mx", }, - .peer = &SMPA6_LEVEL_mx_ao, + .peer = &mx_s6a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 6, .key = KEY_LEVEL, }; -static struct rpmpd SMPA6_LEVEL_mx_ao = { +static struct rpmpd mx_s6a_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &SMPA6_LEVEL_mx, + .peer = &mx_s6a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 6, .key = KEY_LEVEL, }; -static struct rpmpd SMPA7_LEVEL_mx_ao; -static struct rpmpd SMPA7_LEVEL_mx = { +static struct rpmpd mx_s7a_lvl_ao; +static struct rpmpd mx_s7a_lvl = { .pd = { .name = "mx", }, - .peer = &SMPA7_LEVEL_mx_ao, + .peer = &mx_s7a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 7, .key = KEY_LEVEL, }; -static struct rpmpd SMPA7_LEVEL_mx_ao = { +static struct rpmpd mx_s7a_lvl_ao = { .pd = { .name = "mx_ao", }, - .peer = &SMPA7_LEVEL_mx, + .peer = &mx_s7a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 7, .key = KEY_LEVEL, }; -static struct rpmpd LDOA12_mx_vfl = { +static struct rpmpd mx_l12a_vfl = { .pd = { .name = "mx_vfl", }, .res_type = RPMPD_LDOA, .res_id = 12, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWMX0_mx_vfl = { +static struct rpmpd mx_rwmx0_vfl = { .pd = { .name = "mx_vfl", }, .res_type = RPMPD_RWMX, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSM6_mx_vfl = { +static struct rpmpd mx_rwsm6_vfl = { .pd = { .name = "mx_vfl", }, .res_type = RPMPD_RWSM, .res_id = 6, @@ -364,43 +364,43 @@ static struct rpmpd RWSM6_mx_vfl = { }; /* MD */ -static struct rpmpd SMPA1_CORNER_md_ao; -static struct rpmpd SMPA1_CORNER_md = { +static struct rpmpd md_s1a_corner_ao; +static struct rpmpd md_s1a_corner = { .pd = { .name = "md", }, - .peer = &SMPA1_CORNER_md_ao, + .peer = &md_s1a_corner_ao, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA1_CORNER_md_ao = { +static struct rpmpd md_s1a_corner_ao = { .pd = { .name = "md_ao", }, - .peer = &SMPA1_CORNER_md, + .peer = &md_s1a_corner, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_CORNER, }; -static struct rpmpd SMPA1_LEVEL_md_ao; -static struct rpmpd SMPA1_LEVEL_md = { +static struct rpmpd md_s1a_lvl_ao; +static struct rpmpd md_s1a_lvl = { .pd = { .name = "md", }, - .peer = &SMPA1_LEVEL_md_ao, + .peer = &md_s1a_lvl_ao, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_LEVEL, }; -static struct rpmpd SMPA1_LEVEL_md_ao = { +static struct rpmpd md_s1a_lvl_ao = { .pd = { .name = "md_ao", }, - .peer = &SMPA1_LEVEL_md, + .peer = &md_s1a_lvl, .active_only = true, .res_type = RPMPD_SMPA, .res_id = 1, .key = KEY_LEVEL, }; -static struct rpmpd SMPA1_md_vfc = { +static struct rpmpd md_s1a_vfc = { .pd = { .name = "md_vfc", }, .res_type = RPMPD_SMPA, .res_id = 1, @@ -408,102 +408,102 @@ static struct rpmpd SMPA1_md_vfc = { }; /* LPI_CX */ -static struct rpmpd RWLC0_lpi_cx_lvl = { +static struct rpmpd lpi_cx_rwlc0_lvl = { .pd = { .name = "lpi_cx", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWLC0_lpicx_vfl = { - .pd = { .name = "lpicx_vfl", }, +static struct rpmpd lpi_cx_rwlc0_vfl = { + .pd = { .name = "lpi_cx_vfl", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; /* LPI_MX */ -static struct rpmpd RWLM0_lpi_mx_lvl = { +static struct rpmpd lpi_mx_rwlm0_lvl = { .pd = { .name = "lpi_mx", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWLM0_lpimx_vfl = { - .pd = { .name = "lpimx_vfl", }, +static struct rpmpd lpi_mx_rwlm0_vfl = { + .pd = { .name = "lpi_mx_vfl", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; /* SSC_CX */ -static struct rpmpd LDOA26_sscx_corner = { - .pd = { .name = "sscx", }, +static struct rpmpd ssc_cx_l26a_corner = { + .pd = { .name = "ssc_cx", }, .res_type = RPMPD_LDOA, .res_id = 26, .key = KEY_CORNER, }; -static struct rpmpd RWLC0_ssccx_lvl = { - .pd = { .name = "ssccx", }, +static struct rpmpd ssc_cx_rwlc0_lvl = { + .pd = { .name = "ssc_cx", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWSC0_ssccx_lvl = { - .pd = { .name = "ssccx", }, +static struct rpmpd ssc_cx_rwsc0_lvl = { + .pd = { .name = "ssc_cx", }, .res_type = RPMPD_RWSC, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd LDOA26_sscx_vfc = { - .pd = { .name = "sscx_vfc", }, +static struct rpmpd ssc_cx_l26a_vfc = { + .pd = { .name = "ssc_cx_vfc", }, .res_type = RPMPD_LDOA, .res_id = 26, .key = KEY_FLOOR_CORNER, }; -static struct rpmpd RWLC0_ssccx_vfl = { - .pd = { .name = "ssccx_vfl", }, +static struct rpmpd ssc_cx_rwlc0_vfl = { + .pd = { .name = "ssc_cx_vfl", }, .res_type = RPMPD_RWLC, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSC0_ssccx_vfl = { - .pd = { .name = "ssccx_vfl", }, +static struct rpmpd ssc_cx_rwsc0_vfl = { + .pd = { .name = "ssc_cx_vfl", }, .res_type = RPMPD_RWSC, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; /* SSC_MX */ -static struct rpmpd RWLM0_sscmx_lvl = { - .pd = { .name = "sscmx", }, +static struct rpmpd ssc_mx_rwlm0_lvl = { + .pd = { .name = "ssc_mx", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWSM0_sscmx_lvl = { - .pd = { .name = "sscmx", }, +static struct rpmpd ssc_mx_rwsm0_lvl = { + .pd = { .name = "ssc_mx", }, .res_type = RPMPD_RWSM, .res_id = 0, .key = KEY_LEVEL, }; -static struct rpmpd RWLM0_sscmx_vfl = { - .pd = { .name = "sscmx_vfl", }, +static struct rpmpd ssc_mx_rwlm0_vfl = { + .pd = { .name = "ssc_mx_vfl", }, .res_type = RPMPD_RWLM, .res_id = 0, .key = KEY_FLOOR_LEVEL, }; -static struct rpmpd RWSM0_sscmx_vfl = { - .pd = { .name = "sscmx_vfl", }, +static struct rpmpd ssc_mx_rwsm0_vfl = { + .pd = { .name = "ssc_mx_vfl", }, .res_type = RPMPD_RWSM, .res_id = 0, .key = KEY_FLOOR_LEVEL, @@ -511,12 +511,12 @@ static struct rpmpd RWSM0_sscmx_vfl = { /* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { - [MDM9607_VDDCX] = &SMPA3_LEVEL_cx, - [MDM9607_VDDCX_AO] = &SMPA3_LEVEL_cx_ao, - [MDM9607_VDDCX_VFL] = &SMPA3_cx_vfl, - [MDM9607_VDDMX] = &LDOA12_LEVEL_mx, - [MDM9607_VDDMX_AO] = &LDOA12_LEVEL_mx_ao, - [MDM9607_VDDMX_VFL] = &LDOA12_mx_vfl, + [MDM9607_VDDCX] = &cx_s3a_lvl, + [MDM9607_VDDCX_AO] = &cx_s3a_lvl_ao, + [MDM9607_VDDCX_VFL] = &cx_s3a_vfl, + [MDM9607_VDDMX] = &mx_l12a_lvl, + [MDM9607_VDDMX_AO] = &mx_l12a_lvl_ao, + [MDM9607_VDDMX_VFL] = &mx_l12a_vfl, }; static const struct rpmpd_desc mdm9607_desc = { @@ -527,9 +527,9 @@ static const struct rpmpd_desc mdm9607_desc = { /* msm8226 RPM Power Domains */ static struct rpmpd *msm8226_rpmpds[] = { - [MSM8226_VDDCX] = &SMPA1_CORNER_cx, - [MSM8226_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8226_VDDCX_VFC] = &SMPA1_cx_vfc, + [MSM8226_VDDCX] = &cx_s1a_corner, + [MSM8226_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8226_VDDCX_VFC] = &cx_s1a_vfc, }; static const struct rpmpd_desc msm8226_desc = { @@ -540,14 +540,14 @@ static const struct rpmpd_desc msm8226_desc = { /* msm8939 RPM Power Domains */ static struct rpmpd *msm8939_rpmpds[] = { - [MSM8939_VDDMDCX] = &SMPA1_CORNER_md, - [MSM8939_VDDMDCX_AO] = &SMPA1_CORNER_md_ao, - [MSM8939_VDDMDCX_VFC] = &SMPA1_md_vfc, - [MSM8939_VDDCX] = &SMPA2_CORNER_cx, - [MSM8939_VDDCX_AO] = &SMPA2_CORNER_cx_ao, - [MSM8939_VDDCX_VFC] = &SMPA2_cx_vfc, - [MSM8939_VDDMX] = &LDOA3_CORNER_mx, - [MSM8939_VDDMX_AO] = &LDOA3_CORNER_mx_ao, + [MSM8939_VDDMDCX] = &md_s1a_corner, + [MSM8939_VDDMDCX_AO] = &md_s1a_corner_ao, + [MSM8939_VDDMDCX_VFC] = &md_s1a_vfc, + [MSM8939_VDDCX] = &cx_s2a_corner, + [MSM8939_VDDCX_AO] = &cx_s2a_corner_ao, + [MSM8939_VDDCX_VFC] = &cx_s2a_vfc, + [MSM8939_VDDMX] = &mx_l3a_corner, + [MSM8939_VDDMX_AO] = &mx_l3a_corner_ao, }; static const struct rpmpd_desc msm8939_desc = { @@ -558,11 +558,11 @@ static const struct rpmpd_desc msm8939_desc = { /* msm8916 RPM Power Domains */ static struct rpmpd *msm8916_rpmpds[] = { - [MSM8916_VDDCX] = &SMPA1_CORNER_cx, - [MSM8916_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8916_VDDCX_VFC] = &SMPA1_cx_vfc, - [MSM8916_VDDMX] = &LDOA3_CORNER_mx, - [MSM8916_VDDMX_AO] = &LDOA3_CORNER_mx_ao, + [MSM8916_VDDCX] = &cx_s1a_corner, + [MSM8916_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8916_VDDCX_VFC] = &cx_s1a_vfc, + [MSM8916_VDDMX] = &mx_l3a_corner, + [MSM8916_VDDMX_AO] = &mx_l3a_corner_ao, }; static const struct rpmpd_desc msm8916_desc = { @@ -573,13 +573,13 @@ static const struct rpmpd_desc msm8916_desc = { /* msm8953 RPM Power Domains */ static struct rpmpd *msm8953_rpmpds[] = { - [MSM8953_VDDMD] = &SMPA1_LEVEL_md, - [MSM8953_VDDMD_AO] = &SMPA1_LEVEL_md_ao, - [MSM8953_VDDCX] = &SMPA2_LEVEL_cx, - [MSM8953_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, - [MSM8953_VDDCX_VFL] = &SMPA2_cx_vfl, - [MSM8953_VDDMX] = &SMPA7_LEVEL_mx, - [MSM8953_VDDMX_AO] = &SMPA7_LEVEL_mx_ao, + [MSM8953_VDDMD] = &md_s1a_lvl, + [MSM8953_VDDMD_AO] = &md_s1a_lvl_ao, + [MSM8953_VDDCX] = &cx_s2a_lvl, + [MSM8953_VDDCX_AO] = &cx_s2a_lvl_ao, + [MSM8953_VDDCX_VFL] = &cx_s2a_vfl, + [MSM8953_VDDMX] = &mx_s7a_lvl, + [MSM8953_VDDMX_AO] = &mx_s7a_lvl_ao, }; static const struct rpmpd_desc msm8953_desc = { @@ -590,12 +590,12 @@ static const struct rpmpd_desc msm8953_desc = { /* msm8976 RPM Power Domains */ static struct rpmpd *msm8976_rpmpds[] = { - [MSM8976_VDDCX] = &SMPA2_LEVEL_cx, - [MSM8976_VDDCX_AO] = &SMPA2_LEVEL_cx_ao, - [MSM8976_VDDCX_VFL] = &RWSC2_cx_vfl, - [MSM8976_VDDMX] = &SMPA6_LEVEL_mx, - [MSM8976_VDDMX_AO] = &SMPA6_LEVEL_mx_ao, - [MSM8976_VDDMX_VFL] = &RWSM6_mx_vfl, + [MSM8976_VDDCX] = &cx_s2a_lvl, + [MSM8976_VDDCX_AO] = &cx_s2a_lvl_ao, + [MSM8976_VDDCX_VFL] = &cx_rwsc2_vfl, + [MSM8976_VDDMX] = &mx_s6a_lvl, + [MSM8976_VDDMX_AO] = &mx_s6a_lvl_ao, + [MSM8976_VDDMX_VFL] = &mx_rwsm6_vfl, }; static const struct rpmpd_desc msm8976_desc = { @@ -606,15 +606,15 @@ static const struct rpmpd_desc msm8976_desc = { /* msm8994 RPM Power domains */ static struct rpmpd *msm8994_rpmpds[] = { - [MSM8994_VDDCX] = &SMPA1_CORNER_cx, - [MSM8994_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8994_VDDCX_VFC] = &SMPA1_cx_vfc, - [MSM8994_VDDMX] = &SMPA2_CORNER_mx, - [MSM8994_VDDMX_AO] = &SMPA2_CORNER_mx_ao, + [MSM8994_VDDCX] = &cx_s1a_corner, + [MSM8994_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8994_VDDCX_VFC] = &cx_s1a_vfc, + [MSM8994_VDDMX] = &mx_s2a_corner, + [MSM8994_VDDMX_AO] = &mx_s2a_corner_ao, /* Attention! *Some* 8994 boards with pm8004 may use SMPC here! */ - [MSM8994_VDDGFX] = &SMPB2_gfx_corner, - [MSM8994_VDDGFX_VFC] = &SMPB2_gfx_vfc, + [MSM8994_VDDGFX] = &gfx_s2b_corner, + [MSM8994_VDDGFX_VFC] = &gfx_s2b_vfc, }; static const struct rpmpd_desc msm8994_desc = { @@ -625,13 +625,13 @@ static const struct rpmpd_desc msm8994_desc = { /* msm8996 RPM Power domains */ static struct rpmpd *msm8996_rpmpds[] = { - [MSM8996_VDDCX] = &SMPA1_CORNER_cx, - [MSM8996_VDDCX_AO] = &SMPA1_CORNER_cx_ao, - [MSM8996_VDDCX_VFC] = &SMPA1_cx_vfc, - [MSM8996_VDDMX] = &SMPA2_CORNER_mx, - [MSM8996_VDDMX_AO] = &SMPA2_CORNER_mx_ao, - [MSM8996_VDDSSCX] = &LDOA26_sscx_corner, - [MSM8996_VDDSSCX_VFC] = &LDOA26_sscx_vfc, + [MSM8996_VDDCX] = &cx_s1a_corner, + [MSM8996_VDDCX_AO] = &cx_s1a_corner_ao, + [MSM8996_VDDCX_VFC] = &cx_s1a_vfc, + [MSM8996_VDDMX] = &mx_s2a_corner, + [MSM8996_VDDMX_AO] = &mx_s2a_corner_ao, + [MSM8996_VDDSSCX] = &ssc_cx_l26a_corner, + [MSM8996_VDDSSCX_VFC] = &ssc_cx_l26a_vfc, }; static const struct rpmpd_desc msm8996_desc = { @@ -642,16 +642,16 @@ static const struct rpmpd_desc msm8996_desc = { /* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &RWCX0_LEVEL_cx, - [MSM8998_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [MSM8998_VDDCX_VFL] = &RWCX0_cx_vfl, - [MSM8998_VDDMX] = &RWMX0_LEVEL_mx, - [MSM8998_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [MSM8998_VDDMX_VFL] = &RWMX0_mx_vfl, - [MSM8998_SSCCX] = &RWSC0_ssccx_lvl, - [MSM8998_SSCCX_VFL] = &RWSC0_ssccx_vfl, - [MSM8998_SSCMX] = &RWSM0_sscmx_lvl, - [MSM8998_SSCMX_VFL] = &RWSM0_sscmx_vfl, + [MSM8998_VDDCX] = &cx_rwcx0_lvl, + [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [MSM8998_VDDCX_VFL] = &cx_rwcx0_vfl, + [MSM8998_VDDMX] = &mx_rwmx0_lvl, + [MSM8998_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [MSM8998_VDDMX_VFL] = &mx_rwmx0_vfl, + [MSM8998_SSCCX] = &ssc_cx_rwsc0_lvl, + [MSM8998_SSCCX_VFL] = &ssc_cx_rwsc0_vfl, + [MSM8998_SSCMX] = &ssc_mx_rwsm0_lvl, + [MSM8998_SSCMX_VFL] = &ssc_mx_rwsm0_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -662,13 +662,13 @@ static const struct rpmpd_desc msm8998_desc = { /* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &RWMX0_LEVEL_mx, - [QCS404_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [QCS404_VDDMX_VFL] = &RWMX0_mx_vfl, - [QCS404_LPICX] = &RWLC0_lpi_cx_lvl, - [QCS404_LPICX_VFL] = &RWLC0_lpicx_vfl, - [QCS404_LPIMX] = &RWLM0_lpi_mx_lvl, - [QCS404_LPIMX_VFL] = &RWLM0_lpimx_vfl, + [QCS404_VDDMX] = &mx_rwmx0_lvl, + [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCS404_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCS404_LPICX] = &lpi_cx_rwlc0_lvl, + [QCS404_LPICX_VFL] = &lpi_cx_rwlc0_vfl, + [QCS404_LPIMX] = &lpi_mx_rwlm0_lvl, + [QCS404_LPIMX_VFL] = &lpi_mx_rwlm0_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -679,16 +679,16 @@ static const struct rpmpd_desc qcs404_desc = { /* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &RWCX0_LEVEL_cx, - [SDM660_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SDM660_VDDCX_VFL] = &RWCX0_cx_vfl, - [SDM660_VDDMX] = &RWMX0_LEVEL_mx, - [SDM660_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SDM660_VDDMX_VFL] = &RWMX0_mx_vfl, - [SDM660_SSCCX] = &RWLC0_ssccx_lvl, - [SDM660_SSCCX_VFL] = &RWLC0_ssccx_vfl, - [SDM660_SSCMX] = &RWLM0_sscmx_lvl, - [SDM660_SSCMX_VFL] = &RWLM0_sscmx_vfl, + [SDM660_VDDCX] = &cx_rwcx0_lvl, + [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SDM660_VDDCX_VFL] = &cx_rwcx0_vfl, + [SDM660_VDDMX] = &mx_rwmx0_lvl, + [SDM660_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SDM660_VDDMX_VFL] = &mx_rwmx0_vfl, + [SDM660_SSCCX] = &ssc_cx_rwlc0_lvl, + [SDM660_SSCCX_VFL] = &ssc_cx_rwlc0_vfl, + [SDM660_SSCMX] = &ssc_mx_rwlm0_lvl, + [SDM660_SSCMX_VFL] = &ssc_mx_rwlm0_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -699,14 +699,14 @@ static const struct rpmpd_desc sdm660_desc = { /* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &RWCX0_LEVEL_cx, - [SM6115_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SM6115_VDDCX_VFL] = &RWCX0_cx_vfl, - [SM6115_VDDMX] = &RWMX0_LEVEL_mx, - [SM6115_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SM6115_VDDMX_VFL] = &RWMX0_mx_vfl, - [SM6115_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, - [SM6115_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, + [SM6115_VDDCX] = &cx_rwcx0_lvl, + [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6115_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6115_VDDMX] = &mx_rwmx0_lvl, + [SM6115_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6115_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6115_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6115_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -717,12 +717,12 @@ static const struct rpmpd_desc sm6115_desc = { /* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &RWCX0_LEVEL_cx, - [SM6125_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SM6125_VDDCX_VFL] = &RWCX0_cx_vfl, - [SM6125_VDDMX] = &RWMX0_LEVEL_mx, - [SM6125_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SM6125_VDDMX_VFL] = &RWMX0_mx_vfl, + [SM6125_VDDCX] = &cx_rwcx0_lvl, + [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6125_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6125_VDDMX] = &mx_rwmx0_lvl, + [SM6125_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6125_VDDMX_VFL] = &mx_rwmx0_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -732,16 +732,16 @@ static const struct rpmpd_desc sm6125_desc = { }; static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &RWCX0_LEVEL_cx, - [SM6375_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [SM6375_VDDCX_VFL] = &RWCX0_cx_vfl, - [SM6375_VDDMX] = &RWMX0_LEVEL_mx, - [SM6375_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [SM6375_VDDMX_VFL] = &RWMX0_mx_vfl, - [SM6375_VDDGX] = &RWGX0_LEVEL_gx, - [SM6375_VDDGX_AO] = &RWGX0_LEVEL_gx_ao, - [SM6375_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, - [SM6375_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, + [SM6375_VDDCX] = &cx_rwcx0_lvl, + [SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6375_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6375_VDDMX] = &mx_rwmx0_lvl, + [SM6375_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6375_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6375_VDDGX] = &gx_rwgx0_lvl, + [SM6375_VDDGX_AO] = &gx_rwgx0_lvl_ao, + [SM6375_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6375_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -751,14 +751,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &RWCX0_LEVEL_cx, - [QCM2290_VDDCX_AO] = &RWCX0_LEVEL_cx_ao, - [QCM2290_VDDCX_VFL] = &RWCX0_cx_vfl, - [QCM2290_VDDMX] = &RWMX0_LEVEL_mx, - [QCM2290_VDDMX_AO] = &RWMX0_LEVEL_mx_ao, - [QCM2290_VDDMX_VFL] = &RWMX0_mx_vfl, - [QCM2290_VDD_LPI_CX] = &RWLC0_lpi_cx_lvl, - [QCM2290_VDD_LPI_MX] = &RWLM0_lpi_mx_lvl, + [QCM2290_VDDCX] = &cx_rwcx0_lvl, + [QCM2290_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [QCM2290_VDDCX_VFL] = &cx_rwcx0_vfl, + [QCM2290_VDDMX] = &mx_rwmx0_lvl, + [QCM2290_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCM2290_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCM2290_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [QCM2290_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From d338fe40cf37c3f326b5cb743c6436369d452094 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:05 +0100 Subject: [PATCH 0304/1040] soc: qcom: rpmpd: Make bindings assignments consistent Currently the whitespace between [DT_BINDING] = &struct is all over the place.. some SoC structs have a space, others have a tab, others have N tabs.. Make that a single tab for everybody to keep things coherent. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-7-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 118 +++++++++++++++++++-------------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 695b2fc56f40..946630d82b3d 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -642,16 +642,16 @@ static const struct rpmpd_desc msm8996_desc = { /* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { - [MSM8998_VDDCX] = &cx_rwcx0_lvl, - [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [MSM8998_VDDCX_VFL] = &cx_rwcx0_vfl, - [MSM8998_VDDMX] = &mx_rwmx0_lvl, - [MSM8998_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [MSM8998_VDDMX_VFL] = &mx_rwmx0_vfl, - [MSM8998_SSCCX] = &ssc_cx_rwsc0_lvl, - [MSM8998_SSCCX_VFL] = &ssc_cx_rwsc0_vfl, - [MSM8998_SSCMX] = &ssc_mx_rwsm0_lvl, - [MSM8998_SSCMX_VFL] = &ssc_mx_rwsm0_vfl, + [MSM8998_VDDCX] = &cx_rwcx0_lvl, + [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [MSM8998_VDDCX_VFL] = &cx_rwcx0_vfl, + [MSM8998_VDDMX] = &mx_rwmx0_lvl, + [MSM8998_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [MSM8998_VDDMX_VFL] = &mx_rwmx0_vfl, + [MSM8998_SSCCX] = &ssc_cx_rwsc0_lvl, + [MSM8998_SSCCX_VFL] = &ssc_cx_rwsc0_vfl, + [MSM8998_SSCMX] = &ssc_mx_rwsm0_lvl, + [MSM8998_SSCMX_VFL] = &ssc_mx_rwsm0_vfl, }; static const struct rpmpd_desc msm8998_desc = { @@ -662,13 +662,13 @@ static const struct rpmpd_desc msm8998_desc = { /* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { - [QCS404_VDDMX] = &mx_rwmx0_lvl, - [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [QCS404_VDDMX_VFL] = &mx_rwmx0_vfl, - [QCS404_LPICX] = &lpi_cx_rwlc0_lvl, - [QCS404_LPICX_VFL] = &lpi_cx_rwlc0_vfl, - [QCS404_LPIMX] = &lpi_mx_rwlm0_lvl, - [QCS404_LPIMX_VFL] = &lpi_mx_rwlm0_vfl, + [QCS404_VDDMX] = &mx_rwmx0_lvl, + [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCS404_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCS404_LPICX] = &lpi_cx_rwlc0_lvl, + [QCS404_LPICX_VFL] = &lpi_cx_rwlc0_vfl, + [QCS404_LPIMX] = &lpi_mx_rwlm0_lvl, + [QCS404_LPIMX_VFL] = &lpi_mx_rwlm0_vfl, }; static const struct rpmpd_desc qcs404_desc = { @@ -679,16 +679,16 @@ static const struct rpmpd_desc qcs404_desc = { /* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { - [SDM660_VDDCX] = &cx_rwcx0_lvl, - [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SDM660_VDDCX_VFL] = &cx_rwcx0_vfl, - [SDM660_VDDMX] = &mx_rwmx0_lvl, - [SDM660_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SDM660_VDDMX_VFL] = &mx_rwmx0_vfl, - [SDM660_SSCCX] = &ssc_cx_rwlc0_lvl, - [SDM660_SSCCX_VFL] = &ssc_cx_rwlc0_vfl, - [SDM660_SSCMX] = &ssc_mx_rwlm0_lvl, - [SDM660_SSCMX_VFL] = &ssc_mx_rwlm0_vfl, + [SDM660_VDDCX] = &cx_rwcx0_lvl, + [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SDM660_VDDCX_VFL] = &cx_rwcx0_vfl, + [SDM660_VDDMX] = &mx_rwmx0_lvl, + [SDM660_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SDM660_VDDMX_VFL] = &mx_rwmx0_vfl, + [SDM660_SSCCX] = &ssc_cx_rwlc0_lvl, + [SDM660_SSCCX_VFL] = &ssc_cx_rwlc0_vfl, + [SDM660_SSCMX] = &ssc_mx_rwlm0_lvl, + [SDM660_SSCMX_VFL] = &ssc_mx_rwlm0_vfl, }; static const struct rpmpd_desc sdm660_desc = { @@ -699,14 +699,14 @@ static const struct rpmpd_desc sdm660_desc = { /* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { - [SM6115_VDDCX] = &cx_rwcx0_lvl, - [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SM6115_VDDCX_VFL] = &cx_rwcx0_vfl, - [SM6115_VDDMX] = &mx_rwmx0_lvl, - [SM6115_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SM6115_VDDMX_VFL] = &mx_rwmx0_vfl, - [SM6115_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, - [SM6115_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, + [SM6115_VDDCX] = &cx_rwcx0_lvl, + [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6115_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6115_VDDMX] = &mx_rwmx0_lvl, + [SM6115_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6115_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6115_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6115_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6115_desc = { @@ -717,12 +717,12 @@ static const struct rpmpd_desc sm6115_desc = { /* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { - [SM6125_VDDCX] = &cx_rwcx0_lvl, - [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SM6125_VDDCX_VFL] = &cx_rwcx0_vfl, - [SM6125_VDDMX] = &mx_rwmx0_lvl, - [SM6125_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SM6125_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6125_VDDCX] = &cx_rwcx0_lvl, + [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6125_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6125_VDDMX] = &mx_rwmx0_lvl, + [SM6125_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6125_VDDMX_VFL] = &mx_rwmx0_vfl, }; static const struct rpmpd_desc sm6125_desc = { @@ -732,16 +732,16 @@ static const struct rpmpd_desc sm6125_desc = { }; static struct rpmpd *sm6375_rpmpds[] = { - [SM6375_VDDCX] = &cx_rwcx0_lvl, - [SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [SM6375_VDDCX_VFL] = &cx_rwcx0_vfl, - [SM6375_VDDMX] = &mx_rwmx0_lvl, - [SM6375_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [SM6375_VDDMX_VFL] = &mx_rwmx0_vfl, - [SM6375_VDDGX] = &gx_rwgx0_lvl, - [SM6375_VDDGX_AO] = &gx_rwgx0_lvl_ao, - [SM6375_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, - [SM6375_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, + [SM6375_VDDCX] = &cx_rwcx0_lvl, + [SM6375_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [SM6375_VDDCX_VFL] = &cx_rwcx0_vfl, + [SM6375_VDDMX] = &mx_rwmx0_lvl, + [SM6375_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [SM6375_VDDMX_VFL] = &mx_rwmx0_vfl, + [SM6375_VDDGX] = &gx_rwgx0_lvl, + [SM6375_VDDGX_AO] = &gx_rwgx0_lvl_ao, + [SM6375_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [SM6375_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc sm6375_desc = { @@ -751,14 +751,14 @@ static const struct rpmpd_desc sm6375_desc = { }; static struct rpmpd *qcm2290_rpmpds[] = { - [QCM2290_VDDCX] = &cx_rwcx0_lvl, - [QCM2290_VDDCX_AO] = &cx_rwcx0_lvl_ao, - [QCM2290_VDDCX_VFL] = &cx_rwcx0_vfl, - [QCM2290_VDDMX] = &mx_rwmx0_lvl, - [QCM2290_VDDMX_AO] = &mx_rwmx0_lvl_ao, - [QCM2290_VDDMX_VFL] = &mx_rwmx0_vfl, - [QCM2290_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, - [QCM2290_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, + [QCM2290_VDDCX] = &cx_rwcx0_lvl, + [QCM2290_VDDCX_AO] = &cx_rwcx0_lvl_ao, + [QCM2290_VDDCX_VFL] = &cx_rwcx0_vfl, + [QCM2290_VDDMX] = &mx_rwmx0_lvl, + [QCM2290_VDDMX_AO] = &mx_rwmx0_lvl_ao, + [QCM2290_VDDMX_VFL] = &mx_rwmx0_vfl, + [QCM2290_VDD_LPI_CX] = &lpi_cx_rwlc0_lvl, + [QCM2290_VDD_LPI_MX] = &lpi_mx_rwlm0_lvl, }; static const struct rpmpd_desc qcm2290_desc = { From decd6e77e02eff517efe11dfc181ce1b5bef3405 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:06 +0100 Subject: [PATCH 0305/1040] soc: qcom: rpmpd: Add parent PD support In some cases (like with the GPU core clock on GMU-less SoCs) it's required that we scale more than one voltage domain. This can be achieved by linking them in a parent-child relationship. Add support for specifying a parent PD, similarly to what has been done in the RPMhPD driver. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-8-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 946630d82b3d..2027c820caa7 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -48,6 +48,7 @@ struct rpmpd_req { struct rpmpd { struct generic_pm_domain pd; + struct generic_pm_domain *parent; struct rpmpd *peer; const bool active_only; unsigned int corner; @@ -969,6 +970,15 @@ static int rpmpd_probe(struct platform_device *pdev) data->domains[i] = &rpmpds[i]->pd; } + /* Add subdomains */ + for (i = 0; i < num; i++) { + if (!rpmpds[i]) + continue; + + if (rpmpds[i]->parent) + pm_genpd_add_subdomain(rpmpds[i]->parent, &rpmpds[i]->pd); + } + return of_genpd_add_provider_onecell(pdev->dev.of_node, data); } From ec90637c9946cc8e37afa4c1feb33fdb1fa15b68 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:07 +0100 Subject: [PATCH 0306/1040] soc: qcom: rpmpd: Hook up VDDMX as parent of SM6375 VDDGX The GPU core clock requires that both VDDGX and VDDMX domains are scaled at the same rate at the same time (well, MX just before GX but you get the idea). Set MX as parent of GX to take care of that. Suggested-by: Bjorn Andersson Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-9-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 2027c820caa7..84283719853c 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -216,18 +216,22 @@ static struct rpmpd gfx_s2b_vfc = { .key = KEY_FLOOR_CORNER, }; +static struct rpmpd mx_rwmx0_lvl; static struct rpmpd gx_rwgx0_lvl_ao; static struct rpmpd gx_rwgx0_lvl = { .pd = { .name = "gx", }, .peer = &gx_rwgx0_lvl_ao, .res_type = RPMPD_RWGX, + .parent = &mx_rwmx0_lvl.pd, .res_id = 0, .key = KEY_LEVEL, }; +static struct rpmpd mx_rwmx0_lvl_ao; static struct rpmpd gx_rwgx0_lvl_ao = { .pd = { .name = "gx_ao", }, .peer = &gx_rwgx0_lvl, + .parent = &mx_rwmx0_lvl_ao.pd, .active_only = true, .res_type = RPMPD_RWGX, .res_id = 0, From e556c94e8c20bcfb6c910e93a0cfd2d0cce5adc8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 13 Mar 2023 21:00:08 +0100 Subject: [PATCH 0307/1040] soc: qcom: rpmpd: Remove useless comments It goes without saying that socname_rpmpds[] is the array of the RPM power domains associated with socname. Remove these comments. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-rpmpd-v3-10-06a4f448ff90@linaro.org --- drivers/soc/qcom/rpmpd.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 84283719853c..f8397dcb146c 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -514,7 +514,6 @@ static struct rpmpd ssc_mx_rwsm0_vfl = { .key = KEY_FLOOR_LEVEL, }; -/* mdm9607 RPM Power Domains */ static struct rpmpd *mdm9607_rpmpds[] = { [MDM9607_VDDCX] = &cx_s3a_lvl, [MDM9607_VDDCX_AO] = &cx_s3a_lvl_ao, @@ -530,7 +529,6 @@ static const struct rpmpd_desc mdm9607_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; -/* msm8226 RPM Power Domains */ static struct rpmpd *msm8226_rpmpds[] = { [MSM8226_VDDCX] = &cx_s1a_corner, [MSM8226_VDDCX_AO] = &cx_s1a_corner_ao, @@ -543,7 +541,6 @@ static const struct rpmpd_desc msm8226_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8939 RPM Power Domains */ static struct rpmpd *msm8939_rpmpds[] = { [MSM8939_VDDMDCX] = &md_s1a_corner, [MSM8939_VDDMDCX_AO] = &md_s1a_corner_ao, @@ -561,7 +558,6 @@ static const struct rpmpd_desc msm8939_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8916 RPM Power Domains */ static struct rpmpd *msm8916_rpmpds[] = { [MSM8916_VDDCX] = &cx_s1a_corner, [MSM8916_VDDCX_AO] = &cx_s1a_corner_ao, @@ -576,7 +572,6 @@ static const struct rpmpd_desc msm8916_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8953 RPM Power Domains */ static struct rpmpd *msm8953_rpmpds[] = { [MSM8953_VDDMD] = &md_s1a_lvl, [MSM8953_VDDMD_AO] = &md_s1a_lvl_ao, @@ -593,7 +588,6 @@ static const struct rpmpd_desc msm8953_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; -/* msm8976 RPM Power Domains */ static struct rpmpd *msm8976_rpmpds[] = { [MSM8976_VDDCX] = &cx_s2a_lvl, [MSM8976_VDDCX_AO] = &cx_s2a_lvl_ao, @@ -609,7 +603,6 @@ static const struct rpmpd_desc msm8976_desc = { .max_state = RPM_SMD_LEVEL_TURBO_HIGH, }; -/* msm8994 RPM Power domains */ static struct rpmpd *msm8994_rpmpds[] = { [MSM8994_VDDCX] = &cx_s1a_corner, [MSM8994_VDDCX_AO] = &cx_s1a_corner_ao, @@ -628,7 +621,6 @@ static const struct rpmpd_desc msm8994_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8996 RPM Power domains */ static struct rpmpd *msm8996_rpmpds[] = { [MSM8996_VDDCX] = &cx_s1a_corner, [MSM8996_VDDCX_AO] = &cx_s1a_corner_ao, @@ -645,7 +637,6 @@ static const struct rpmpd_desc msm8996_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; -/* msm8998 RPM Power domains */ static struct rpmpd *msm8998_rpmpds[] = { [MSM8998_VDDCX] = &cx_rwcx0_lvl, [MSM8998_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -665,7 +656,6 @@ static const struct rpmpd_desc msm8998_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -/* qcs404 RPM Power domains */ static struct rpmpd *qcs404_rpmpds[] = { [QCS404_VDDMX] = &mx_rwmx0_lvl, [QCS404_VDDMX_AO] = &mx_rwmx0_lvl_ao, @@ -682,7 +672,6 @@ static const struct rpmpd_desc qcs404_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; -/* sdm660 RPM Power domains */ static struct rpmpd *sdm660_rpmpds[] = { [SDM660_VDDCX] = &cx_rwcx0_lvl, [SDM660_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -702,7 +691,6 @@ static const struct rpmpd_desc sdm660_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; -/* sm4250/6115 RPM Power domains */ static struct rpmpd *sm6115_rpmpds[] = { [SM6115_VDDCX] = &cx_rwcx0_lvl, [SM6115_VDDCX_AO] = &cx_rwcx0_lvl_ao, @@ -720,7 +708,6 @@ static const struct rpmpd_desc sm6115_desc = { .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, }; -/* sm6125 RPM Power domains */ static struct rpmpd *sm6125_rpmpds[] = { [SM6125_VDDCX] = &cx_rwcx0_lvl, [SM6125_VDDCX_AO] = &cx_rwcx0_lvl_ao, From d882778eb430d430d5f72b92d49cb3f4f50be01c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:56 +0100 Subject: [PATCH 0308/1040] arm64: dts: qcom: drop incorrect cell-index from SPMI The SPMI controller (PMIC Arbiter)) does not use nor allow 'cell-index' property: sm8150-microsoft-surface-duo.dtb: spmi@c440000: Unevaluated properties are not allowed ('cell-index' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8976.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8998.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 - arch/arm64/boot/dts/qcom/sm6125.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 - 8 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 62d05d740646..f769e63c955c 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -397,7 +397,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sdhc_1: mmc@7824900 { diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 2d360d05aa5e..712f80fc865c 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -809,7 +809,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sdhc_1: mmc@7824000 { diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index adf7258b3269..d450fe69fe33 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1993,7 +1993,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; usb3: usb@a8f8800 { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index fb84aa480d91..604c2aa0c276 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3288,7 +3288,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sram@146aa000 { diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 5827cda270a0..72d9a12b5e9c 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1189,7 +1189,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; usb3: usb@a8f8800 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 79da7eb954f3..99edd2ba85e2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4935,7 +4935,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; sram@146bf000 { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 65033227718a..fd577eb705f8 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1134,7 +1134,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; apps_smmu: iommu@c600000 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 3e2b3597281e..46072ba37390 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3968,7 +3968,6 @@ #size-cells = <0>; interrupt-controller; #interrupt-cells = <4>; - cell-index = <0>; }; apps_smmu: iommu@15000000 { From d24539a6a98c19c81deb4004ec5023b3ee6e7bb8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:57 +0100 Subject: [PATCH 0309/1040] arm64: dts: qcom: sm8250: drop incorrect Coresight funnel properties There is only one output port, thus out-ports should not have 'address/size-cells' and unit addresses. 'reg-names' are also not allowed by bindings. qrb5165-rb5.dtb: funnel@6042000: out-ports: '#address-cells', '#size-cells', 'port@0' do not match any of the regexes: 'pinctrl-[0-9]+' qrb5165-rb5.dtb: funnel@6b04000: Unevaluated properties are not allowed ('reg-names' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 73c5504c1d44..9c8a48c28a88 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2808,11 +2808,7 @@ clock-names = "apb_pclk"; out-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + port { funnel_in1_out_funnel_merg: endpoint { remote-endpoint = <&funnel_merg_in_funnel_in1>; }; @@ -2913,7 +2909,6 @@ arm,primecell-periphid = <0x000bb908>; reg = <0 0x06b04000 0 0x1000>; - reg-names = "funnel-base"; clocks = <&aoss_qmp>; clock-names = "apb_pclk"; @@ -3229,9 +3224,6 @@ clock-names = "apb_pclk"; out-ports { - #address-cells = <1>; - #size-cells = <0>; - port { funnel_apss_merg_out_funnel_in1: endpoint { remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; From 9b8bfc443349c0c220438c6ac8839774210c9ba2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:58 +0100 Subject: [PATCH 0310/1040] arm64: dts: qcom: qdu1000: drop incorrect serial properties The serial node does not use/allow address/size cells: qdu1000-idp.dtb: geniqup@9c0000: serial@99c000: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) Fixes: 6bd20c54b589 ("arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 98a859ad5229..99d784085fb3 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -416,8 +416,6 @@ pinctrl-0 = <&qup_uart0_default>; pinctrl-names = "default"; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -585,8 +583,6 @@ pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; }; From 9135ab4a53f7e967456b792ec6fc21ecaf06032b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:58:59 +0100 Subject: [PATCH 0311/1040] arm64: dts: qcom: sdm845-db845c: drop SPI label The SPI controller nodes do not use/allow label property: sdm845-db845c.dtb: spi@888000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index d4866feef2c4..acd4f9ca6c09 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -819,7 +819,6 @@ &spi2 { /* On Low speed expansion */ - label = "LS-SPI0"; status = "okay"; }; From 9b0ff841f0724fb4bf0218e33afba46a097b258c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:00 +0100 Subject: [PATCH 0312/1040] arm64: dts: qcom: apq8096-db820c: drop SPI label The SPI controller nodes do not use/allow label property: apq8096-db820c.dtb: spi@7575000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index eb18811b2676..842836ed680a 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -146,7 +146,6 @@ &blsp1_spi1 { /* On Low speed expansion */ - label = "LS-SPI0"; status = "okay"; }; @@ -183,7 +182,6 @@ &blsp2_spi6 { /* On High speed expansion */ - label = "HS-SPI1"; status = "okay"; }; From afa8eb675fc6dd606783ed2350de90927d6fb9d3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:01 +0100 Subject: [PATCH 0313/1040] arm64: dts: qcom: ipq6018-cp01-c1: drop SPI cs-select The SPI controller nodes do not use/allow cs-select property: ipq6018-cp01-c1.dtb: spi@78b5000: Unevaluated properties are not allowed ('cs-select' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 2aee8594b280..f5f4827c0e17 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -35,7 +35,6 @@ }; &blsp1_spi1 { - cs-select = <0>; pinctrl-0 = <&spi_0_pins>; pinctrl-names = "default"; status = "okay"; From 35343312a4399074e7a20ab086d29273bb5f1ad2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:02 +0100 Subject: [PATCH 0314/1040] arm64: dts: qcom: msm8953: correct RPMCC node name The bindings expect RPM clock controller subnode to be named 'clock-controller': msm8953-motorola-potter.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 610f3e3fc0c2..4e362b9012bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -269,7 +269,7 @@ compatible = "qcom,rpm-msm8953"; qcom,smd-channels = "rpm_requests"; - rpmcc: rpmcc { + rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; clocks = <&xo_board>; clock-names = "xo"; From 9bc3dc3c9dc1b9e594a6d56210b857f9ffca5853 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:03 +0100 Subject: [PATCH 0315/1040] arm64: dts: qcom: msm8953: drop clocks from RPMPD The RPM power domain controller does not take XO clock as input (according to bindings and Linux driver): msm8953-xiaomi-vince.dtb: rpm-requests: power-controller: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 4e362b9012bd..da00c2f04cda 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -281,9 +281,6 @@ #power-domain-cells = <1>; operating-points-v2 = <&rpmpd_opp_table>; - clocks = <&xo_board>; - clock-names = "ref"; - rpmpd_opp_table: opp-table { compatible = "operating-points-v2"; From e96d20585c84aca49771609b6bca3a7c30f7d397 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:04 +0100 Subject: [PATCH 0316/1040] arm64: dts: qcom: msm8994: correct RPMCC node name The bindings expect RPM clock controller subnode to be named 'clock-controller': apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests: 'rpmcc' does not match any of the regexes: '^regulators(-[01])?$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 9ff9d35496d2..768fe2326933 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -242,7 +242,7 @@ compatible = "qcom,rpm-msm8994"; qcom,smd-channels = "rpm_requests"; - rpmcc: rpmcc { + rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; #clock-cells = <1>; }; From a369c74243ca4ad60b9de0ac5c2207fb4c4117b8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:05 +0100 Subject: [PATCH 0317/1040] arm64: dts: qcom: sc7280: fix EUD port properties Nodes with unit addresses must have also 'reg' property: sc7280-herobrine-crd.dtb: eud@88e0000: ports:port@0: 'reg' is a required property Fixes: 0b059979090d ("arm64: dts: qcom: sc7280: Add EUD dt node and dwc3 connector") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Souradeep Chowdhury Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5b0b10ee0a5c..9e20243cce44 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3603,12 +3603,17 @@ <0 0x088e2000 0 0x1000>; interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; eud_ep: endpoint { remote-endpoint = <&usb2_role_switch>; }; }; port@1 { + reg = <1>; eud_con: endpoint { remote-endpoint = <&con_eud>; }; @@ -3619,7 +3624,11 @@ eud_typec: connector { compatible = "usb-c-connector"; ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; con_eud: endpoint { remote-endpoint = <&eud_con>; }; From 5ff9e238a17733669d6dd1992cae19e1684fe5ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 13:59:06 +0100 Subject: [PATCH 0318/1040] arm64: dts: qcom: msm8996-oneplus: do not enable incomplete nodes status=okay should appear in final place where all required properties are provided, because that makes the code the easiest to read. Move the status from common OnePlus DTSI to board DTS. No functional changes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308125906.236885-11-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom/msm8996-oneplus-common.dtsi | 17 ----------------- arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts | 6 ++++++ arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts | 6 ++++++ 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index 104deaee74e5..2adadc1e5b7c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -85,10 +85,6 @@ }; }; -&adsp_pil { - status = "okay"; -}; - &blsp1_i2c3 { status = "okay"; @@ -183,10 +179,6 @@ status = "okay"; }; -&gpu { - status = "okay"; -}; - &hsusb_phy1 { vdd-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; @@ -215,7 +207,6 @@ &mss_pil { pll-supply = <&vreg_l12a_1p8>; - status = "okay"; }; &pcie0 { @@ -548,10 +539,6 @@ }; }; -&slpi_pil { - status = "okay"; -}; - &sound { compatible = "qcom,apq8096-sndcard"; model = "OnePlus3"; @@ -812,7 +799,3 @@ maximum-speed = "high-speed"; }; - -&venus { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts index 1bdc1b134305..dfe75119b8d2 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts @@ -17,6 +17,7 @@ &adsp_pil { firmware-name = "qcom/msm8996/oneplus3/adsp.mbn"; + status = "okay"; }; &battery { @@ -25,6 +26,8 @@ }; &gpu { + status = "okay"; + zap-shader { firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn"; }; @@ -33,12 +36,15 @@ &mss_pil { firmware-name = "qcom/msm8996/oneplus3/mba.mbn", "qcom/msm8996/oneplus3/modem.mbn"; + status = "okay"; }; &slpi_pil { firmware-name = "qcom/msm8996/oneplus3/slpi.mbn"; + status = "okay"; }; &venus { firmware-name = "qcom/msm8996/oneplus3/venus.mbn"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts index 34f837dd0c12..51fce65e89f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts @@ -18,6 +18,7 @@ &adsp_pil { firmware-name = "qcom/msm8996/oneplus3t/adsp.mbn"; + status = "okay"; }; &battery { @@ -26,6 +27,8 @@ }; &gpu { + status = "okay"; + zap-shader { firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn"; }; @@ -34,12 +37,15 @@ &mss_pil { firmware-name = "qcom/msm8996/oneplus3t/mba.mbn", "qcom/msm8996/oneplus3t/modem.mbn"; + status = "okay"; }; &slpi_pil { firmware-name = "qcom/msm8996/oneplus3t/slpi.mbn"; + status = "okay"; }; &venus { firmware-name = "qcom/msm8996/oneplus3t/venus.mbn"; + status = "okay"; }; From 81ac39144bf65c5f8ee00e61308fe1f3399b347c Mon Sep 17 00:00:00 2001 From: Poovendhan Selvaraj Date: Thu, 16 Feb 2023 17:30:08 +0530 Subject: [PATCH 0319/1040] dt-bindings: scm: Add compatible for IPQ9574 Add the scm compatible string for IPQ9574 SoC Acked-by: Krzysztof Kozlowski Signed-off-by: Poovendhan Selvaraj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230216120012.28357-2-quic_poovendh@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index a66e99812b1f..868fc7e555a6 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -27,6 +27,7 @@ properties: - qcom,scm-ipq6018 - qcom,scm-ipq806x - qcom,scm-ipq8074 + - qcom,scm-ipq9574 - qcom,scm-mdm9607 - qcom,scm-msm8226 - qcom,scm-msm8660 From f99cdbd858df8457bcffc3e90fa6939d517193c5 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:26 +0530 Subject: [PATCH 0320/1040] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Add binding for the Qualcomm IPQ5332 Global Clock Controller. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-4-quic_kathirav@quicinc.com --- .../bindings/clock/qcom,ipq5332-gcc.yaml | 53 +++ include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++ 2 files changed, 409 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml new file mode 100644 index 000000000000..718fe0625424 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5332 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5332. + + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-gcc + + clocks: + items: + - description: Board XO clock source + - description: Sleep clock source + - description: PCIE 2lane PHY pipe clock source + - description: PCIE 2lane x1 PHY pipe clock source (For second lane) + - description: USB PCIE wrapper pipe clock source + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_2lane_phy_pipe_clk>, + <&pcie_2lane_phy_pipe_clk_x1>, + <&usb_pcie_wrapper_pipe_clk>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h new file mode 100644 index 000000000000..8a405a0a96d0 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -0,0 +1,356 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H +#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define GCC_ADSS_PWM_CLK 6 +#define GCC_ADSS_PWM_CLK_SRC 7 +#define GCC_AHB_CLK 8 +#define GCC_APSS_AXI_CLK_SRC 9 +#define GCC_BLSP1_AHB_CLK 10 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 15 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 17 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 18 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19 +#define GCC_BLSP1_SLEEP_CLK 20 +#define GCC_BLSP1_UART1_APPS_CLK 21 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 22 +#define GCC_BLSP1_UART2_APPS_CLK 23 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 24 +#define GCC_BLSP1_UART3_APPS_CLK 25 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 26 +#define GCC_CE_AHB_CLK 27 +#define GCC_CE_AXI_CLK 28 +#define GCC_CE_PCNOC_AHB_CLK 29 +#define GCC_CMN_12GPLL_AHB_CLK 30 +#define GCC_CMN_12GPLL_APU_CLK 31 +#define GCC_CMN_12GPLL_SYS_CLK 32 +#define GCC_GP1_CLK 33 +#define GCC_GP1_CLK_SRC 34 +#define GCC_GP2_CLK 35 +#define GCC_GP2_CLK_SRC 36 +#define GCC_LPASS_CORE_AXIM_CLK 37 +#define GCC_LPASS_SWAY_CLK 38 +#define GCC_LPASS_SWAY_CLK_SRC 39 +#define GCC_MDIO_AHB_CLK 40 +#define GCC_MDIO_SLAVE_AHB_CLK 41 +#define GCC_MEM_NOC_Q6_AXI_CLK 42 +#define GCC_MEM_NOC_TS_CLK 43 +#define GCC_NSS_TS_CLK 44 +#define GCC_NSS_TS_CLK_SRC 45 +#define GCC_NSSCC_CLK 46 +#define GCC_NSSCFG_CLK 47 +#define GCC_NSSNOC_ATB_CLK 48 +#define GCC_NSSNOC_NSSCC_CLK 49 +#define GCC_NSSNOC_QOSGEN_REF_CLK 50 +#define GCC_NSSNOC_SNOC_1_CLK 51 +#define GCC_NSSNOC_SNOC_CLK 52 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 53 +#define GCC_NSSNOC_XO_DCD_CLK 54 +#define GCC_PCIE3X1_0_AHB_CLK 55 +#define GCC_PCIE3X1_0_AUX_CLK 56 +#define GCC_PCIE3X1_0_AXI_CLK_SRC 57 +#define GCC_PCIE3X1_0_AXI_M_CLK 58 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE3X1_0_AXI_S_CLK 60 +#define GCC_PCIE3X1_0_PIPE_CLK 61 +#define GCC_PCIE3X1_0_RCHG_CLK 62 +#define GCC_PCIE3X1_0_RCHG_CLK_SRC 63 +#define GCC_PCIE3X1_1_AHB_CLK 64 +#define GCC_PCIE3X1_1_AUX_CLK 65 +#define GCC_PCIE3X1_1_AXI_CLK_SRC 66 +#define GCC_PCIE3X1_1_AXI_M_CLK 67 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68 +#define GCC_PCIE3X1_1_AXI_S_CLK 69 +#define GCC_PCIE3X1_1_PIPE_CLK 70 +#define GCC_PCIE3X1_1_RCHG_CLK 71 +#define GCC_PCIE3X1_1_RCHG_CLK_SRC 72 +#define GCC_PCIE3X1_PHY_AHB_CLK 73 +#define GCC_PCIE3X2_AHB_CLK 74 +#define GCC_PCIE3X2_AUX_CLK 75 +#define GCC_PCIE3X2_AXI_M_CLK 76 +#define GCC_PCIE3X2_AXI_M_CLK_SRC 77 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78 +#define GCC_PCIE3X2_AXI_S_CLK 79 +#define GCC_PCIE3X2_AXI_S_CLK_SRC 80 +#define GCC_PCIE3X2_PHY_AHB_CLK 81 +#define GCC_PCIE3X2_PIPE_CLK 82 +#define GCC_PCIE3X2_RCHG_CLK 83 +#define GCC_PCIE3X2_RCHG_CLK_SRC 84 +#define GCC_PCIE_AUX_CLK_SRC 85 +#define GCC_PCNOC_AT_CLK 86 +#define GCC_PCNOC_BFDCD_CLK_SRC 87 +#define GCC_PCNOC_LPASS_CLK 88 +#define GCC_PRNG_AHB_CLK 89 +#define GCC_Q6_AHB_CLK 90 +#define GCC_Q6_AHB_S_CLK 91 +#define GCC_Q6_AXIM_CLK 92 +#define GCC_Q6_AXIM_CLK_SRC 93 +#define GCC_Q6_AXIS_CLK 94 +#define GCC_Q6_TSCTR_1TO2_CLK 95 +#define GCC_Q6SS_ATBM_CLK 96 +#define GCC_Q6SS_PCLKDBG_CLK 97 +#define GCC_Q6SS_TRIG_CLK 98 +#define GCC_QDSS_AT_CLK 99 +#define GCC_QDSS_AT_CLK_SRC 100 +#define GCC_QDSS_CFG_AHB_CLK 101 +#define GCC_QDSS_DAP_AHB_CLK 102 +#define GCC_QDSS_DAP_CLK 103 +#define GCC_QDSS_DAP_DIV_CLK_SRC 104 +#define GCC_QDSS_ETR_USB_CLK 105 +#define GCC_QDSS_EUD_AT_CLK 106 +#define GCC_QDSS_TSCTR_CLK_SRC 107 +#define GCC_QPIC_AHB_CLK 108 +#define GCC_QPIC_CLK 109 +#define GCC_QPIC_IO_MACRO_CLK 110 +#define GCC_QPIC_IO_MACRO_CLK_SRC 111 +#define GCC_QPIC_SLEEP_CLK 112 +#define GCC_SDCC1_AHB_CLK 113 +#define GCC_SDCC1_APPS_CLK 114 +#define GCC_SDCC1_APPS_CLK_SRC 115 +#define GCC_SLEEP_CLK_SRC 116 +#define GCC_SNOC_LPASS_CFG_CLK 117 +#define GCC_SNOC_NSSNOC_1_CLK 118 +#define GCC_SNOC_NSSNOC_CLK 119 +#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120 +#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121 +#define GCC_SNOC_PCIE3_1LANE_M_CLK 122 +#define GCC_SNOC_PCIE3_1LANE_S_CLK 123 +#define GCC_SNOC_PCIE3_2LANE_M_CLK 124 +#define GCC_SNOC_PCIE3_2LANE_S_CLK 125 +#define GCC_SNOC_USB_CLK 126 +#define GCC_SYS_NOC_AT_CLK 127 +#define GCC_SYS_NOC_WCSS_AHB_CLK 128 +#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129 +#define GCC_UNIPHY0_AHB_CLK 130 +#define GCC_UNIPHY0_SYS_CLK 131 +#define GCC_UNIPHY1_AHB_CLK 132 +#define GCC_UNIPHY1_SYS_CLK 133 +#define GCC_UNIPHY_SYS_CLK_SRC 134 +#define GCC_USB0_AUX_CLK 135 +#define GCC_USB0_AUX_CLK_SRC 136 +#define GCC_USB0_EUD_AT_CLK 137 +#define GCC_USB0_LFPS_CLK 138 +#define GCC_USB0_LFPS_CLK_SRC 139 +#define GCC_USB0_MASTER_CLK 140 +#define GCC_USB0_MASTER_CLK_SRC 141 +#define GCC_USB0_MOCK_UTMI_CLK 142 +#define GCC_USB0_MOCK_UTMI_CLK_SRC 143 +#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144 +#define GCC_USB0_PHY_CFG_AHB_CLK 145 +#define GCC_USB0_PIPE_CLK 146 +#define GCC_USB0_SLEEP_CLK 147 +#define GCC_WCSS_AHB_CLK_SRC 148 +#define GCC_WCSS_AXIM_CLK 149 +#define GCC_WCSS_AXIS_CLK 150 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151 +#define GCC_WCSS_DBG_IFC_APB_CLK 152 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153 +#define GCC_WCSS_DBG_IFC_ATB_CLK 154 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155 +#define GCC_WCSS_DBG_IFC_NTS_CLK 156 +#define GCC_WCSS_ECAHB_CLK 157 +#define GCC_WCSS_MST_ASYNC_BDG_CLK 158 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159 +#define GCC_XO_CLK 160 +#define GCC_XO_CLK_SRC 161 +#define GCC_XO_DIV4_CLK 162 +#define GCC_IM_SLEEP_CLK 163 +#define GCC_NSSNOC_PCNOC_1_CLK 164 +#define GCC_MEM_NOC_AHB_CLK 165 +#define GCC_MEM_NOC_APSS_AXI_CLK 166 +#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167 +#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168 +#define GCC_PCIE3X2_PIPE_CLK_SRC 169 +#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 +#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 +#define GCC_USB0_PIPE_CLK_SRC 172 + +#define GCC_ADSS_BCR 0 +#define GCC_ADSS_PWM_CLK_ARES 1 +#define GCC_AHB_CLK_ARES 2 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4 +#define GCC_APSS_AHB_CLK_ARES 5 +#define GCC_APSS_AXI_CLK_ARES 6 +#define GCC_BLSP1_AHB_CLK_ARES 7 +#define GCC_BLSP1_BCR 8 +#define GCC_BLSP1_QUP1_BCR 9 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11 +#define GCC_BLSP1_QUP2_BCR 12 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14 +#define GCC_BLSP1_QUP3_BCR 15 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17 +#define GCC_BLSP1_SLEEP_CLK_ARES 18 +#define GCC_BLSP1_UART1_APPS_CLK_ARES 19 +#define GCC_BLSP1_UART1_BCR 20 +#define GCC_BLSP1_UART2_APPS_CLK_ARES 21 +#define GCC_BLSP1_UART2_BCR 22 +#define GCC_BLSP1_UART3_APPS_CLK_ARES 23 +#define GCC_BLSP1_UART3_BCR 24 +#define GCC_CE_BCR 25 +#define GCC_CMN_BLK_BCR 26 +#define GCC_CMN_LDO0_BCR 27 +#define GCC_CMN_LDO1_BCR 28 +#define GCC_DCC_BCR 29 +#define GCC_GP1_CLK_ARES 30 +#define GCC_GP2_CLK_ARES 31 +#define GCC_LPASS_BCR 32 +#define GCC_LPASS_CORE_AXIM_CLK_ARES 33 +#define GCC_LPASS_SWAY_CLK_ARES 34 +#define GCC_MDIOM_BCR 35 +#define GCC_MDIOS_BCR 36 +#define GCC_NSS_BCR 37 +#define GCC_NSS_TS_CLK_ARES 38 +#define GCC_NSSCC_CLK_ARES 39 +#define GCC_NSSCFG_CLK_ARES 40 +#define GCC_NSSNOC_ATB_CLK_ARES 41 +#define GCC_NSSNOC_NSSCC_CLK_ARES 42 +#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43 +#define GCC_NSSNOC_SNOC_1_CLK_ARES 44 +#define GCC_NSSNOC_SNOC_CLK_ARES 45 +#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46 +#define GCC_NSSNOC_XO_DCD_CLK_ARES 47 +#define GCC_PCIE3X1_0_AHB_CLK_ARES 48 +#define GCC_PCIE3X1_0_AUX_CLK_ARES 49 +#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50 +#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51 +#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52 +#define GCC_PCIE3X1_0_BCR 53 +#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54 +#define GCC_PCIE3X1_0_PHY_BCR 55 +#define GCC_PCIE3X1_0_PHY_PHY_BCR 56 +#define GCC_PCIE3X1_1_AHB_CLK_ARES 57 +#define GCC_PCIE3X1_1_AUX_CLK_ARES 58 +#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59 +#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60 +#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61 +#define GCC_PCIE3X1_1_BCR 62 +#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63 +#define GCC_PCIE3X1_1_PHY_BCR 64 +#define GCC_PCIE3X1_1_PHY_PHY_BCR 65 +#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66 +#define GCC_PCIE3X2_AHB_CLK_ARES 67 +#define GCC_PCIE3X2_AUX_CLK_ARES 68 +#define GCC_PCIE3X2_AXI_M_CLK_ARES 69 +#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70 +#define GCC_PCIE3X2_AXI_S_CLK_ARES 71 +#define GCC_PCIE3X2_BCR 72 +#define GCC_PCIE3X2_LINK_DOWN_BCR 73 +#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74 +#define GCC_PCIE3X2_PHY_BCR 75 +#define GCC_PCIE3X2PHY_PHY_BCR 76 +#define GCC_PCNOC_BCR 77 +#define GCC_PCNOC_LPASS_CLK_ARES 78 +#define GCC_PRNG_AHB_CLK_ARES 79 +#define GCC_PRNG_BCR 80 +#define GCC_Q6_AHB_CLK_ARES 81 +#define GCC_Q6_AHB_S_CLK_ARES 82 +#define GCC_Q6_AXIM_CLK_ARES 83 +#define GCC_Q6_AXIS_CLK_ARES 84 +#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85 +#define GCC_Q6SS_ATBM_CLK_ARES 86 +#define GCC_Q6SS_PCLKDBG_CLK_ARES 87 +#define GCC_Q6SS_TRIG_CLK_ARES 88 +#define GCC_QDSS_APB2JTAG_CLK_ARES 89 +#define GCC_QDSS_AT_CLK_ARES 90 +#define GCC_QDSS_BCR 91 +#define GCC_QDSS_CFG_AHB_CLK_ARES 92 +#define GCC_QDSS_DAP_AHB_CLK_ARES 93 +#define GCC_QDSS_DAP_CLK_ARES 94 +#define GCC_QDSS_ETR_USB_CLK_ARES 95 +#define GCC_QDSS_EUD_AT_CLK_ARES 96 +#define GCC_QDSS_STM_CLK_ARES 97 +#define GCC_QDSS_TRACECLKIN_CLK_ARES 98 +#define GCC_QDSS_TS_CLK_ARES 99 +#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100 +#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101 +#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102 +#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103 +#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104 +#define GCC_QPIC_AHB_CLK_ARES 105 +#define GCC_QPIC_CLK_ARES 106 +#define GCC_QPIC_BCR 107 +#define GCC_QPIC_IO_MACRO_CLK_ARES 108 +#define GCC_QPIC_SLEEP_CLK_ARES 109 +#define GCC_QUSB2_0_PHY_BCR 110 +#define GCC_SDCC1_AHB_CLK_ARES 111 +#define GCC_SDCC1_APPS_CLK_ARES 112 +#define GCC_SDCC_BCR 113 +#define GCC_SNOC_BCR 114 +#define GCC_SNOC_LPASS_CFG_CLK_ARES 115 +#define GCC_SNOC_NSSNOC_1_CLK_ARES 116 +#define GCC_SNOC_NSSNOC_CLK_ARES 117 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118 +#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119 +#define GCC_UNIPHY0_AHB_CLK_ARES 120 +#define GCC_UNIPHY0_BCR 121 +#define GCC_UNIPHY0_SYS_CLK_ARES 122 +#define GCC_UNIPHY1_AHB_CLK_ARES 123 +#define GCC_UNIPHY1_BCR 124 +#define GCC_UNIPHY1_SYS_CLK_ARES 125 +#define GCC_USB0_AUX_CLK_ARES 126 +#define GCC_USB0_EUD_AT_CLK_ARES 127 +#define GCC_USB0_LFPS_CLK_ARES 128 +#define GCC_USB0_MASTER_CLK_ARES 129 +#define GCC_USB0_MOCK_UTMI_CLK_ARES 130 +#define GCC_USB0_PHY_BCR 131 +#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132 +#define GCC_USB0_SLEEP_CLK_ARES 133 +#define GCC_USB3PHY_0_PHY_BCR 134 +#define GCC_USB_BCR 135 +#define GCC_WCSS_AXIM_CLK_ARES 136 +#define GCC_WCSS_AXIS_CLK_ARES 137 +#define GCC_WCSS_BCR 138 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139 +#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141 +#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143 +#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144 +#define GCC_WCSS_ECAHB_CLK_ARES 145 +#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146 +#define GCC_WCSS_Q6_BCR 147 +#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148 +#define GCC_XO_CLK_ARES 149 +#define GCC_XO_DIV4_CLK_ARES 150 +#define GCC_Q6SS_DBG_ARES 151 +#define GCC_WCSS_DBG_BDG_ARES 152 +#define GCC_WCSS_DBG_ARES 153 +#define GCC_WCSS_AXI_S_ARES 154 +#define GCC_WCSS_AXI_M_ARES 155 +#define GCC_WCSSAON_ARES 156 +#define GCC_PCIE3X2_PIPE_ARES 157 +#define GCC_PCIE3X2_CORE_STICKY_ARES 158 +#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159 +#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160 +#define GCC_PCIE3X1_0_PIPE_ARES 161 +#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162 +#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163 +#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164 +#define GCC_PCIE3X1_1_PIPE_ARES 165 +#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166 +#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167 +#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168 +#define GCC_IM_SLEEP_CLK_ARES 169 +#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170 +#define GCC_UNIPHY0_XPCS_ARES 171 +#define GCC_UNIPHY1_XPCS_ARES 172 +#endif From 5d092236e0b0e154ca5f4f65d33eea504cc18578 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:29 +0530 Subject: [PATCH 0321/1040] dt-bindings: qcom: add ipq5332 boards Document the new ipq5332 SoC/board device tree bindings Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-7-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 23c9c9ba5d52..014ed8d5ba18 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -30,6 +30,7 @@ description: | apq8084 apq8096 ipq4018 + ipq5332 ipq6018 ipq8074 mdm9615 @@ -80,6 +81,7 @@ description: | The 'board' element must be one of the following strings: adp + ap-mi01.2 cdp cp01-c1 dragonboard @@ -320,6 +322,11 @@ properties: - qcom,ipq4019-dk04.1-c1 - const: qcom,ipq4019 + - items: + - enum: + - qcom,ipq5332-ap-mi01.2 + - const: qcom,ipq5332 + - items: - enum: - mikrotik,rb3011 From 9e4a7652d7028d40b2dd6636d400ca6266d641ef Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:30 +0530 Subject: [PATCH 0322/1040] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Document the compatible for IPQ5332 SCM. Acked-by: Krzysztof Kozlowski Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-8-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 868fc7e555a6..ddda28bddde5 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -24,6 +24,7 @@ properties: - qcom,scm-apq8064 - qcom,scm-apq8084 - qcom,scm-ipq4019 + - qcom,scm-ipq5332 - qcom,scm-ipq6018 - qcom,scm-ipq806x - qcom,scm-ipq8074 From 0360f0ea8c0f67ec8a25c5ec89f044dbc66b5c5f Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:31 +0530 Subject: [PATCH 0323/1040] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Add initial device tree support for the Qualcomm IPQ5332 SoC and MI01.2 board. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-9-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 ++++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 263 ++++++++++++++++++++ 3 files changed, 339 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 89e23a74bc7f..3ba8a11bb81d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts new file mode 100644 index 000000000000..702013b867d7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 AP-MI01.2 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; + compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi new file mode 100644 index 000000000000..a2ed54264d5c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5332", "qcom,scm"; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_mem: tz@4a600000 { + reg = <0x0 0x4a600000 0x0 0x200000>; + no-map; + }; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupt-controller; + #interrupt-cells = <2>; + + serial_0_pins: serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq5332-gcc"; + reg = <0x01800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>; + }; + + sdhc: mmc@7804000 { + compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + status = "disabled"; + }; + + blsp1_uart0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x1000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x1000>; /* GICV */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00002000 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From 48adb3be7d617ecc7d9656032e7253406b8040f5 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 7 Mar 2023 11:52:32 +0530 Subject: [PATCH 0324/1040] arm64: defconfig: Enable IPQ5332 SoC base configs Enable the clock and pinctrl configs for Qualcomm IPQ5332 SoC Reviewed-by: Dmitry Baryshkov Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307062232.4889-10-quic_kathirav@quicinc.com --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..4a8b3f5e07be 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX8ULP=y CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ8074=y +CONFIG_PINCTRL_IPQ5332=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8953=y @@ -1122,6 +1123,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_APCC_MSM8996=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y +CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_MSM_GCC_8916=y From ed32155302fc3e5b8d30c51b95666e844f1449e1 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 10 Feb 2023 11:34:00 +0530 Subject: [PATCH 0325/1040] arm64: dts: qcom: ipq5332: enable the download mode support Enable the support for download mode to collect the RAM dumps if system crashes, to perform the post mortem analysis. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210060401.24383-2-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index a2ed54264d5c..46ce6985e580 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -70,6 +70,7 @@ firmware { scm { compatible = "qcom,scm-ipq5332", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x6100>; }; }; @@ -137,6 +138,11 @@ <0>; }; + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-ipq5332", "syscon"; + reg = <0x01937000 0x21000>; + }; + sdhc: mmc@7804000 { compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; reg = <0x07804000 0x1000>, <0x07805000 0x1000>; From d56dd7f935e125244bc15f5a0a9e68cdb0ec87ca Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 10 Feb 2023 11:34:01 +0530 Subject: [PATCH 0326/1040] arm64: dts: qcom: ipq5332: add SMEM support Add SMEM support by adding required nodes. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230210060401.24383-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 46ce6985e580..76d739b216dd 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -99,6 +99,14 @@ reg = <0x0 0x4a600000 0x0 0x200000>; no-map; }; + + smem@4a800000 { + compatible = "qcom,smem"; + reg = <0x0 0x4a800000 0x0 0x00100000>; + no-map; + + hwlocks = <&tcsr_mutex 0>; + }; }; soc@0 { @@ -138,6 +146,12 @@ <0>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + tcsr: syscon@1937000 { compatible = "qcom,tcsr-ipq5332", "syscon"; reg = <0x01937000 0x21000>; From 44750f153699b6e4f851a399287e5c8df208d696 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 6 Jan 2023 17:46:18 +0100 Subject: [PATCH 0327/1040] arm64: dts: qcom: sdm845: correct dynamic power coefficients While stressing EAS on my dragonboard RB3, I have noticed that LITTLE cores where never selected as the most energy efficient CPU whatever the utilization level of waking task. energy model framework uses its cost field to estimate the energy with the formula: nrg = cost of the selected OPP * utilization / CPU's max capacity which ends up selecting the CPU with lowest cost / max capacity ration as long as the utilization fits in the OPP's capacity. If we compare the cost of a little OPP with similar capacity of a big OPP like : OPP(kHz) OPP capacity cost max capacity cost/max capacity LITTLE 1766400 407 351114 407 863 big 1056000 408 520267 1024 508 This can be interpreted as the LITTLE core consumes 70% more than big core for the same compute capacity. According to [1], LITTLE consumes 10% less than big core for Coremark benchmark at those OPPs. If we consider that everything else stays unchanged, the dynamic-power-coefficient of LITTLE core should be only 53% of the current value: 290 * 53% = 154 Set the dynamic-power-coefficient of CPU0-3 to 154 to fix the energy model. [1] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main Fixes: 0e0a8e35d725 ("arm64: dts: qcom: sdm845: correct dynamic power coefficients") Signed-off-by: Vincent Guittot Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230106164618.1845281-1-vincent.guittot@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 99edd2ba85e2..6c7acaab6e13 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -95,7 +95,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -122,7 +122,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -145,7 +145,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -168,7 +168,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <611>; - dynamic-power-coefficient = <290>; + dynamic-power-coefficient = <154>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, From b74ca4a0e3043af06819905306e05189f337466a Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:48 +0100 Subject: [PATCH 0328/1040] ARM: dts: qcom: add per SoC compatible for qcom,kpss-gcc nodes Add per Soc compatible for qcom,kpss-gcc nodes. While currently not used by the kpss driver they can serve further customization and they are required to be defined per Documentation schema. Signed-off-by: Christian Marangi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-5-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-mdm9615.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8660.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 3aeac0cabb28..6ebf33e2e699 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -879,7 +879,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 52d77e105957..6e49b54f53d7 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -569,7 +569,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 8e9ea61a1e48..b40c52ddf9b4 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -116,7 +116,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 86f76d0feff4..f601b40ebcf4 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -473,7 +473,7 @@ }; l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon"; reg = <0x02082000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index a0369b38fe07..4fdbb867532c 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -182,7 +182,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; + compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; From a9e6d16ad493529da4a48d7ae474ecdc399ee884 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:49 +0100 Subject: [PATCH 0329/1040] ARM: dts: qcom: add and fix clock configuration for kpss-gcc nodes Add missing clock configuration by adding clocks, clock-names and #clock-cells bindings for each kpss-acc-v1 clock-controller node for apq8064 and msm8960 to reflect Documentation schema. Add missing #clock-cells binding and remove useless clock-output-names for ipq806x dtsi. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-6-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8960.dtsi | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 6ebf33e2e699..70d6ed1ac62c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -881,6 +881,9 @@ l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 6e49b54f53d7..e45da8f01ba0 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -573,7 +573,7 @@ reg = <0x02011000 0x1000>; clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; - clock-output-names = "acpu_l2_aux"; + #clock-cells = <0>; }; acc0: clock-controller@2088000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 4fdbb867532c..026480efe8ec 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -184,6 +184,9 @@ l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + #clock-cells = <0>; }; rpm: rpm@108000 { From 6b20edd72930d83e9c2c2017df883b3c5c1502fd Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:50 +0100 Subject: [PATCH 0330/1040] ARM: dts: qcom: add missing clock configuration for kpss-acc-v1 Add missing clock configuration by adding clocks, clock-names, clock-output-names and #clock-cells bindings for each kpss-acc-v1 clock-controller to reflect Documentation schema. Reviewed-by: Dmitry Baryshkov Signed-off-by: Christian Marangi Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-7-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++++++ arch/arm/boot/dts/qcom-msm8960.dtsi | 8 ++++++++ 3 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 70d6ed1ac62c..920d318da266 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -388,21 +388,37 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; acc2: clock-controller@20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu2_aux"; + #clock-cells = <0>; }; acc3: clock-controller@20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu3_aux"; + #clock-cells = <0>; }; saw0: power-controller@2089000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index e45da8f01ba0..5a464f6de0b6 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -579,6 +579,10 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { @@ -590,6 +594,10 @@ acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw1: regulator@2099000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 026480efe8ec..2a668cd535cc 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -207,11 +207,19 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu0_aux"; + #clock-cells = <0>; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names = "pll8_vote", "pxo"; + clock-output-names = "acpu1_aux"; + #clock-cells = <0>; }; saw0: regulator@2089000 { From 158ce4b3e1dfcf3e38c0dbfd626aee0f1bbfa3d1 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Mon, 16 Jan 2023 21:47:51 +0100 Subject: [PATCH 0331/1040] ARM: dts: qcom: rename kpss-acc-v2 nodes to power-manager nodes Change kpss-acc-v2 nodes naming to power-manager to reflect Documentation schema. Signed-off-by: Christian Marangi Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230116204751.23045-8-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-apq8084.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-ipq4019.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-msm8974.dtsi | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fabd7455eb8f..b653ea40c441 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -654,25 +654,25 @@ regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-manager@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - acc1: clock-controller@f9098000 { + acc1: power-manager@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - acc2: clock-controller@f90a8000 { + acc2: power-manager@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - acc3: clock-controller@f90b8000 { + acc3: power-manager@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 44beeb90c306..9595229c4f0d 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -326,22 +326,22 @@ status = "disabled"; }; - acc0: clock-controller@b088000 { + acc0: power-manager@b088000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; }; - acc1: clock-controller@b098000 { + acc1: power-manager@b098000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; }; - acc2: clock-controller@b0a8000 { + acc2: power-manager@b0a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; }; - acc3: clock-controller@b0b8000 { + acc3: power-manager@b0b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 834ad95515b1..23104193f63a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -418,22 +418,22 @@ regulator; }; - acc0: clock-controller@f9088000 { + acc0: power-manager@f9088000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; }; - acc1: clock-controller@f9098000 { + acc1: power-manager@f9098000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; }; - acc2: clock-controller@f90a8000 { + acc2: power-manager@f90a8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; }; - acc3: clock-controller@f90b8000 { + acc3: power-manager@f90b8000 { compatible = "qcom,kpss-acc-v2"; reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; From fb1fe1542a12e4694e05fe14d4003f828515700c Mon Sep 17 00:00:00 2001 From: Mao Jinlong Date: Tue, 17 Jan 2023 06:57:08 -0800 Subject: [PATCH 0332/1040] arm64: dts: qcom: sm8250: Add tpdm mm/prng Add tpdm mm and tpdm prng for sm8250. +---------------+ +-------------+ | tpdm@6c08000 | |tpdm@684C000 | +-------|-------+ +------|------+ | | +-------|-------+ | | funnel@6c0b000| | +-------|-------+ | | | +-------|-------+ | |funnel@6c2d000 | | +-------|-------+ | | | | +---------------+ | +----- tpda@6004000 -----------+ +-------|-------+ | +-------|-------+ |funnel@6005000 | +---------------+ Acked-by: Suzuki K Poulose Signed-off-by: Mao Jinlong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230117145708.16739-10-quic_jinlmao@quicinc.com --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 164 +++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 9c8a48c28a88..9916186c633d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2772,6 +2772,73 @@ }; }; + tpda@6004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0 0x06004000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + tpda_out_funnel_qatb: endpoint { + remote-endpoint = <&funnel_qatb_in_tpda>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@9 { + reg = <9>; + tpda_9_in_tpdm_mm: endpoint { + remote-endpoint = <&tpdm_mm_out_tpda9>; + }; + }; + + port@17 { + reg = <23>; + tpda_23_in_tpdm_prng: endpoint { + remote-endpoint = <&tpdm_prng_out_tpda_23>; + }; + }; + }; + }; + + funnel@6005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06005000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_qatb_out_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_in_funnel_qatb>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_qatb_in_tpda: endpoint { + remote-endpoint = <&tpda_out_funnel_qatb>; + }; + }; + }; + }; + funnel@6041000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x06041000 0 0x1000>; @@ -2791,6 +2858,13 @@ #address-cells = <1>; #size-cells = <0>; + port@6 { + reg = <6>; + funnel_in0_in_funnel_qatb: endpoint { + remote-endpoint = <&funnel_qatb_out_funnel_in0>; + }; + }; + port@7 { reg = <7>; funnel0_in7: endpoint { @@ -2904,6 +2978,22 @@ }; }; + tpdm@684c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0 0x0684c000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_prng_out_tpda_23: endpoint { + remote-endpoint = <&tpda_23_in_tpdm_prng>; + }; + }; + }; + }; + funnel@6b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; arm,primecell-periphid = <0x000bb908>; @@ -2987,6 +3077,80 @@ }; }; + tpdm@6c08000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0 0x06c08000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + tpdm_mm_out_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; + }; + }; + }; + }; + + funnel@6c0b000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06c0b000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_dl_mm_out_funnel_dl_center: endpoint { + remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + funnel_dl_mm_in_tpdm_mm: endpoint { + remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; + }; + }; + }; + }; + + funnel@6c2d000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x06c2d000 0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + port { + tpdm_mm_out_tpda9: endpoint { + remote-endpoint = <&tpda_9_in_tpdm_mm>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@2 { + reg = <2>; + funnel_dl_center_in_funnel_dl_mm: endpoint { + remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; + }; + }; + }; + }; + etm@7040000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0 0x07040000 0 0x1000>; From d4b2c596fe5cb62560ce5a1442d8f64ec1ee716e Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Sat, 21 Jan 2023 19:25:39 +0000 Subject: [PATCH 0333/1040] ARM: dts: qcom: msm8226: add clocks and clock-names to GCC node Add the XO and Sleep Clock sources to the GCC node on MSM8226. Signed-off-by: Rayyan Ansari Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230121192540.9177-3-rayyan@ansari.sh --- arch/arm/boot/dts/qcom-msm8226.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index c373081bc21b..42acb9ddb8cc 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -377,6 +378,11 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>; + clock-names = "xo", + "sleep_clk"; }; mmcc: clock-controller@fd8c0000 { From 17c5ee1914dc8c4f42cab7a5beb2dc91aef0f873 Mon Sep 17 00:00:00 2001 From: Rayyan Ansari Date: Sat, 21 Jan 2023 19:25:40 +0000 Subject: [PATCH 0334/1040] ARM: dts: qcom: msm8974: add correct XO clock source to GCC node Change the XO clock in MSM8974's GCC node to point to RPMCC. Signed-off-by: Rayyan Ansari Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230121192540.9177-4-rayyan@ansari.sh --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 23104193f63a..8208012684d4 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1057,7 +1057,7 @@ #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; - clocks = <&xo_board>, + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; clock-names = "xo", "sleep_clk"; From 968a26a07f75377afbd4f7bb18ef587a1443c244 Mon Sep 17 00:00:00 2001 From: Elliot Berman Date: Mon, 13 Feb 2023 10:18:29 -0800 Subject: [PATCH 0335/1040] firmware: qcom_scm: Use fixed width src vm bitmap The maximum VMID for assign_mem is 63. Use a u64 to represent this bitmap instead of architecture-dependent "unsigned int" which varies in size on 32-bit and 64-bit platforms. Acked-by: Kalle Valo (ath10k) Tested-by: Gokul krishna Krishnakumar Signed-off-by: Elliot Berman Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230213181832.3489174-1-quic_eberman@quicinc.com --- drivers/firmware/qcom_scm.c | 12 +++++++----- drivers/misc/fastrpc.c | 2 +- drivers/net/wireless/ath/ath10k/qmi.c | 4 ++-- drivers/remoteproc/qcom_q6v5_mss.c | 8 ++++---- drivers/remoteproc/qcom_q6v5_pas.c | 2 +- drivers/soc/qcom/rmtfs_mem.c | 2 +- include/linux/firmware/qcom/qcom_scm.h | 2 +- 7 files changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 468d4d5ab550..b95616b35bff 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -905,7 +905,7 @@ static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, * Return negative errno on failure or 0 on success with @srcvm updated. */ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, - unsigned int *srcvm, + u64 *srcvm, const struct qcom_scm_vmperm *newvm, unsigned int dest_cnt) { @@ -922,9 +922,9 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, __le32 *src; void *ptr; int ret, i, b; - unsigned long srcvm_bits = *srcvm; + u64 srcvm_bits = *srcvm; - src_sz = hweight_long(srcvm_bits) * sizeof(*src); + src_sz = hweight64(srcvm_bits) * sizeof(*src); mem_to_map_sz = sizeof(*mem_to_map); dest_sz = dest_cnt * sizeof(*destvm); ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) + @@ -937,8 +937,10 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, /* Fill source vmid detail */ src = ptr; i = 0; - for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG) - src[i++] = cpu_to_le32(b); + for (b = 0; b < BITS_PER_TYPE(u64); b++) { + if (srcvm_bits & BIT(b)) + src[i++] = cpu_to_le32(b); + } /* Fill details of mem buff to map */ mem_to_map = ptr + ALIGN(src_sz, SZ_64); diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c index a701132638cf..f48466960f1b 100644 --- a/drivers/misc/fastrpc.c +++ b/drivers/misc/fastrpc.c @@ -262,7 +262,7 @@ struct fastrpc_channel_ctx { int domain_id; int sesscount; int vmcount; - u32 perms; + u64 perms; struct qcom_scm_vmperm vmperms[FASTRPC_MAX_VMIDS]; struct rpmsg_device *rpdev; struct fastrpc_session_ctx session[FASTRPC_MAX_SESSIONS]; diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c index 90f457b8e1fe..038c5903c0dc 100644 --- a/drivers/net/wireless/ath/ath10k/qmi.c +++ b/drivers/net/wireless/ath/ath10k/qmi.c @@ -33,7 +33,7 @@ static int ath10k_qmi_map_msa_permission(struct ath10k_qmi *qmi, { struct qcom_scm_vmperm dst_perms[3]; struct ath10k *ar = qmi->ar; - unsigned int src_perms; + u64 src_perms; u32 perm_count; int ret; @@ -65,7 +65,7 @@ static int ath10k_qmi_unmap_msa_permission(struct ath10k_qmi *qmi, { struct qcom_scm_vmperm dst_perms; struct ath10k *ar = qmi->ar; - unsigned int src_perms; + u64 src_perms; int ret; src_perms = BIT(QCOM_SCM_VMID_MSS_MSA) | BIT(QCOM_SCM_VMID_WLAN); diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index ab053084f7a2..1ba711bc0100 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -235,8 +235,8 @@ struct q6v5 { bool has_qaccept_regs; bool has_ext_cntl_regs; bool has_vq6; - int mpss_perm; - int mba_perm; + u64 mpss_perm; + u64 mba_perm; const char *hexagon_mdt_image; int version; }; @@ -414,7 +414,7 @@ static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds, } } -static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, +static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, u64 *current_perm, bool local, bool remote, phys_addr_t addr, size_t size) { @@ -967,7 +967,7 @@ static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw, unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; dma_addr_t phys; void *metadata; - int mdata_perm; + u64 mdata_perm; int xferop_ret; size_t size; void *ptr; diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 0871108fb4dc..c99a20542685 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -94,7 +94,7 @@ struct qcom_adsp { size_t region_assign_size; int region_assign_idx; - int region_assign_perms; + u64 region_assign_perms; struct qcom_rproc_glink glink_subdev; struct qcom_rproc_subdev smd_subdev; diff --git a/drivers/soc/qcom/rmtfs_mem.c b/drivers/soc/qcom/rmtfs_mem.c index 2d3ee22b9249..2657c6105bb7 100644 --- a/drivers/soc/qcom/rmtfs_mem.c +++ b/drivers/soc/qcom/rmtfs_mem.c @@ -31,7 +31,7 @@ struct qcom_rmtfs_mem { unsigned int client_id; - unsigned int perms; + u64 perms; }; static ssize_t qcom_rmtfs_mem_show(struct device *dev, diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 1e449a5d7f5c..250ea4efb7cb 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -94,7 +94,7 @@ extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, u32 cp_nonpixel_start, u32 cp_nonpixel_size); extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, - unsigned int *src, + u64 *src, const struct qcom_scm_vmperm *newvm, unsigned int dest_cnt); From 64d5c8a46890010e7cf5a72c0616d1141f84494f Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Tue, 14 Feb 2023 22:01:14 +0530 Subject: [PATCH 0336/1040] dt-bindings: arm: qcom: Add ipq9574 compatible Document the new ipq9574 SoC/board device tree bindings Acked-by: Krzysztof Kozlowski Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214163116.9924-6-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 014ed8d5ba18..05badce5fedc 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -33,6 +33,7 @@ description: | ipq5332 ipq6018 ipq8074 + ipq9574 mdm9615 msm8226 msm8916 @@ -81,6 +82,7 @@ description: | The 'board' element must be one of the following strings: adp + ap-al02-c7 ap-mi01.2 cdp cp01-c1 @@ -340,6 +342,11 @@ properties: - qcom,ipq8074-hk10-c2 - const: qcom,ipq8074 + - items: + - enum: + - qcom,ipq9574-ap-al02-c7 + - const: qcom,ipq9574 + - description: Sierra Wireless MangOH Green with WP8548 Module items: - const: swir,mangoh-green-wp8548 From 56d2156e7c298ecad5a113a81e5550631bcf7fd5 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Fri, 17 Feb 2023 19:50:25 +0530 Subject: [PATCH 0337/1040] dt-bindings: soc: qcom: smd-rpm: Add IPQ9574 compatible Document the compatible for RPM communication over SMD for IPQ9574 SoC Signed-off-by: Devi Priya Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217142030.16012-2-quic_devipriy@quicinc.com --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 16fd67c0bd1f..2a5791ebc8dd 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -33,6 +33,7 @@ properties: enum: - qcom,rpm-apq8084 - qcom,rpm-ipq6018 + - qcom,rpm-ipq9574 - qcom,rpm-msm8226 - qcom,rpm-msm8909 - qcom,rpm-msm8916 From c2819cab9d2edddcb8395bb74367ba61e581a2c5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 24 Feb 2023 14:07:58 +0100 Subject: [PATCH 0338/1040] arm64: dts: qcom: sc8280xp: Use correct CPU compatibles Cores 0-3 are CA78C r0p0, cores 4-7 are CX1C r0p0. Use the correct compatibles instead of the placeholder qcom,kryo. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230224130759.45579-2-konrad.dybcio@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 667595381ab8..ae06ed488b8a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -43,7 +43,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -68,7 +68,7 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -89,7 +89,7 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -110,7 +110,7 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-a78c"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -131,7 +131,7 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -152,7 +152,7 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -173,7 +173,7 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -194,7 +194,7 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "qcom,kryo"; + compatible = "arm,cortex-x1c"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; From 67aa109eee654c76dcc100554e637fa64d5aa099 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:37 +0530 Subject: [PATCH 0339/1040] arm64: dts: qcom: sdm845: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 42ad231338c1 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller") Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-2-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6c7acaab6e13..0fdd59a9feed 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2303,8 +2303,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>; interrupts = ; interrupt-names = "msi"; @@ -2408,7 +2408,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; From c30a27dcfe4545edbda1578b3a63ed6147519cdd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:38 +0530 Subject: [PATCH 0340/1040] arm64: dts: qcom: msm8998: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x1b200000) specified in the ranges property for I/O region. Fixes: b84dfd175c09 ("arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-3-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d450fe69fe33..09b222f363c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -922,7 +922,7 @@ phy-names = "pciephy"; status = "disabled"; - ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; #interrupt-cells = <1>; From 1d4743d6312582978966d38908b69085621b7693 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:39 +0530 Subject: [PATCH 0341/1040] arm64: dts: qcom: sc7280: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-4-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 9e20243cce44..e35f1d5325da 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2085,7 +2085,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; From 565c633940312b4eea7785a0a58e1944258c47e9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:40 +0530 Subject: [PATCH 0342/1040] arm64: dts: qcom: sm8550: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 7d1158c984d3 ("arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-5-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 71051fb4172b..a07bbb8e9fb5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1661,8 +1661,8 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; bus-range = <0x00 0xff>; dma-coherent; @@ -1753,8 +1753,8 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; bus-range = <0x00 0xff>; dma-coherent; From e49eafefe5ab325e38dd074f2005076ffc271e54 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:41 +0530 Subject: [PATCH 0343/1040] arm64: dts: qcom: ipq8074: Fix the PCI I/O port range For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses (0x10200000, 0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses and align them in a single line. Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-6-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index f769e63c955c..fe37dcdc52c8 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -779,10 +779,8 @@ phys = <&pcie_phy1>; phy-names = "pciephy"; - ranges = <0x81000000 0 0x10200000 0x10200000 - 0 0x10000>, /* downstream I/O */ - <0x82000000 0 0x10220000 0x10220000 - 0 0xfde0000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ interrupts = ; interrupt-names = "msi"; @@ -843,10 +841,8 @@ phys = <&pcie_phy0>; phy-names = "pciephy"; - ranges = <0x81000000 0 0x20200000 0x20200000 - 0 0x10000>, /* downstream I/O */ - <0x82000000 0 0x20220000 0x20220000 - 0 0xfde0000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ + <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ interrupts = ; interrupt-names = "msi"; From 75a6e1fdb351189f55097741e8460ca3f9b2883f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:42 +0530 Subject: [PATCH 0344/1040] arm64: dts: qcom: ipq6018: Fix the PCI I/O port range For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI address (0x20200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 095bbdd9a5c3 ("arm64: dts: qcom: ipq6018: Add pcie support") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-7-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index bbd94025ff5d..9ff4e9d45065 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -738,8 +738,8 @@ phys = <&pcie_phy0>; phy-names = "pciephy"; - ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>, - <0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>; + ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, + <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; interrupts = ; interrupt-names = "msi"; From cf0ac10feb17661987d0018eb9475dc03e2a2253 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:43 +0530 Subject: [PATCH 0345/1040] arm64: dts: qcom: msm8996: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x0c200000, 0x0d200000, 0x0e200000) specified in the ranges property for I/O region. While at it, let's also align the entries. Fixes: ed965ef89227 ("arm64: dts: qcom: msm8996: add support to pcie") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-8-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index a1e14e3540e6..55104630a7f0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1851,8 +1851,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, - <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, + <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; device_type = "pci"; @@ -1905,8 +1905,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, - <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, + <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; device_type = "pci"; @@ -1956,8 +1956,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, - <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, + <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; device_type = "pci"; From e115a4495db687898b8d91d4f16c2cf55bbf167c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:44 +0530 Subject: [PATCH 0346/1040] arm64: dts: qcom: sm8250: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000, 0x64200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-9-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 9916186c633d..7ccec48255f0 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1842,8 +1842,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; interrupts = , , @@ -1951,7 +1951,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; @@ -2059,7 +2059,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; interrupts = ; From cb3d6ab7fb72f89c92884a6236911da28ddf9b47 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:45 +0530 Subject: [PATCH 0347/1040] arm64: dts: qcom: qcs404: Use 0x prefix for the PCI I/O and MEM ranges To maintain the uniformity, let's use the 0x prefix for the values of ranges property. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-10-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index bc2ed73afb74..42fc33ab8b2e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1469,8 +1469,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */ - <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */ + ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ + <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ interrupts = ; interrupt-names = "msi"; From 89fe81c01715f81c3a7d371e9e5f7d7ae5bc557c Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:46 +0530 Subject: [PATCH 0348/1040] arm64: dts: qcom: sc8280xp: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x30200000, 0x32200000, 0x34200000, 0x38200000, 0x3c200000) specified in the ranges property for I/O region. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-11-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ae06ed488b8a..64d351aa3b0f 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1665,7 +1665,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -1764,7 +1764,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -1861,7 +1861,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -1961,7 +1961,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; @@ -2058,7 +2058,7 @@ reg-names = "parf", "dbi", "elbi", "atu", "config"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; From 422b110b9b0af0afd4a4b19e8fc3ceab9e71d842 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:47 +0530 Subject: [PATCH 0349/1040] arm64: dts: qcom: sm8150: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: a1c86c680533 ("arm64: dts: qcom: sm8150: Add PCIe nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-12-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 46072ba37390..95e573890983 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1824,8 +1824,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; interrupts = ; interrupt-names = "msi"; @@ -1920,7 +1920,7 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; From f57903c8f4c77938eb71fc67e4652264a9fa14f9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:48 +0530 Subject: [PATCH 0350/1040] arm64: dts: qcom: sm8450: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: bc6588bc25fb ("arm64: dts: qcom: sm8450: add PCIe1 root device") Fixes: 7b09b1b47335 ("arm64: dts: qcom: sm8450: add PCIe0 RC device") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-13-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f6514c012926..f1f2ce33a1e0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1746,8 +1746,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; /* * MSIs for BDF (1:0.0) only works with Device ID 0x5980. @@ -1862,8 +1862,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; /* * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. From cf4e716e9a38b32a922a88ac3c5b701137a663dd Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:49 +0530 Subject: [PATCH 0351/1040] arm64: dts: qcom: sm8350: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI addresses (0x60200000, 0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 6daee40678a0 ("arm64: dts: qcom: sm8350: add PCIe devices") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-14-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 2a9248baa204..2f27b9da96af 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1495,8 +1495,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; interrupts = , , @@ -1589,8 +1589,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; interrupts = ; interrupt-names = "msi"; From 84160da56dd0ce48dd8eed56237cc8be45bd55dc Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:50 +0530 Subject: [PATCH 0352/1040] ARM: dts: qcom: apq8064: Use 0x prefix for the PCI I/O and MEM ranges To maintain the uniformity, let's use the 0x prefix for the values of ranges property. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-15-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 920d318da266..672b246afbba 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1513,8 +1513,8 @@ num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */ - <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */ + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */ + <0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */ interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; From 2540279e9a9e74fc880d1e4c83754ecfcbe290a0 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:51 +0530 Subject: [PATCH 0353/1040] ARM: dts: qcom: ipq4019: Fix the PCI I/O port range For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 187519403273 ("ARM: dts: ipq4019: Add a few peripheral nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-16-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 9595229c4f0d..dfcfb3339c23 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -427,8 +427,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, - <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; + ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, + <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; interrupts = ; interrupt-names = "msi"; From 0b16b34e491629016109e56747ad64588074194b Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:52 +0530 Subject: [PATCH 0354/1040] ARM: dts: qcom: ipq8064: Fix the PCI I/O port range For 64KiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x10000. Hence, fix the bogus PCI addresses (0x0fe00000, 0x31e00000, 0x35e00000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 93241840b664 ("ARM: dts: qcom: Add pcie nodes for ipq8064") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-17-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 5a464f6de0b6..af6764770fd1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1089,8 +1089,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* MEM */ interrupts = ; interrupt-names = "msi"; @@ -1140,8 +1140,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x31e00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x2e000000 0x2e000000 0x0 0x03e00000>; /* MEM */ interrupts = ; interrupt-names = "msi"; @@ -1191,8 +1191,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x35e00000 0x0 0x00010000 /* I/O */ + 0x82000000 0x0 0x32000000 0x32000000 0x0 0x03e00000>; /* MEM */ interrupts = ; interrupt-names = "msi"; From 4a2c9b9e1215c557c17a48e3fabe9b1674c1d608 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Thu, 2 Mar 2023 13:30:49 +0100 Subject: [PATCH 0355/1040] arm64: dts: qcom: msm8976: Add and provide xo clk to rpmcc In order for consumers of RPMCC XO clock to probe successfully their parent needs to be feed with reference clock to obtain proper rate, add fixed xo-board clock and supply it to rpmcc to make consumers happy. Frequency setting is left per board basis just like on other recent trees. Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Fixes: ff7f6d34ca07 ("arm64: dts: qcom: Add support for SONY Xperia X/X Compact") Signed-off-by: Adam Skladowski Reviewed-by: Dmitry Baryshkov [bjorn: Squashed the two patches] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302123051.12440-1-a39.skl@gmail.com Link: https://lore.kernel.org/r/20230302123051.12440-2-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/msm8976.dtsi | 9 +++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi index 67baced639c9..085d79542e1b 100644 --- a/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi @@ -280,3 +280,7 @@ vdda3p3-supply = <&pm8950_l13>; status = "okay"; }; + +&xo_board { + clock-frequency = <19200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 712f80fc865c..05929d7a1d23 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -20,6 +20,13 @@ chosen { }; + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -351,6 +358,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; #clock-cells = <1>; }; From 62d882e62fe91ebdf4acbb8444bb3cf78a958aef Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:04 -0800 Subject: [PATCH 0356/1040] arm64: dts: qcom: sc7180: Delete wormdingler-rev0 The earliest wormdingler I could find in my pile of hardware is -rev1. I believe that -rev0 boards were just distributed as a pile of components with no case. At this point I can't imagine anyone needing to make wormdingler-rev0 work, so let's delete support for it. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.1.Id0cd5120469eb200118c0c7b8ee8209f877767b4@changeid --- arch/arm64/boot/dts/qcom/Makefile | 2 -- .../sc7180-trogdor-wormdingler-rev0-boe.dts | 22 ------------ .../sc7180-trogdor-wormdingler-rev0-inx.dts | 22 ------------ .../qcom/sc7180-trogdor-wormdingler-rev0.dtsi | 36 ------------------- 4 files changed, 82 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3ba8a11bb81d..ea16e19de4dc 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -120,8 +120,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts deleted file mode 100644 index d6ed7d0afe4a..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Wormdingler board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x10 => 16 - * - bits 7..4: Panel ID: 0x1 (BOE) - */ - -/dts-v1/; - -#include "sc7180-trogdor-wormdingler-rev0.dtsi" - -/ { - model = "Google Wormdingler rev0 BOE panel board"; - compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180"; -}; - -&panel { - compatible = "boe,tv110c9m-ll3"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts deleted file mode 100644 index c03525ea64ca..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Wormdingler board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x0 => 0 - * - bits 7..4: Panel ID: 0x0 (INX) - */ - -/dts-v1/; - -#include "sc7180-trogdor-wormdingler-rev0.dtsi" - -/ { - model = "Google Wormdingler rev0 INX panel board"; - compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180"; -}; - -&panel { - compatible = "innolux,hj110iz-01a"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi deleted file mode 100644 index 7f272c6e95f6..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Wormdingler board device tree source - * - * Copyright 2021 Google LLC. - * - */ - -/dts-v1/; - -#include "sc7180-trogdor-wormdingler.dtsi" - -&avdd_lcd { - gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; -}; - -&panel { - enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; -}; - -&v1p8_mipi { - gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; -}; - -/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */ -&avdd_lcd_en { - pins = "gpio80"; -}; - -&mipi_1800_en { - pins = "gpio81"; -}; - -&vdd_reset_1800 { - pins = "gpio76"; -}; From 5fe8b1c88d7b3a227d96f277cd0d36a76aff0273 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:05 -0800 Subject: [PATCH 0357/1040] arm64: dts: qcom: sc7180: Delete kingoftown-rev0 The earliest kingoftown that I could find in my pile of boards was -rev2 and even that revision looks pretty rough (plastics on the case are very unfinished). Though I don't actually have details about how many -rev0 devices were produced, I can't imagine anyone still using one. Let's delete support. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.2.I68cbe5d5d45074428469da8c52f1d6a78bdc62fc@changeid --- arch/arm64/boot/dts/qcom/Makefile | 3 +- .../dts/qcom/sc7180-trogdor-kingoftown-r0.dts | 38 ------------------- .../dts/qcom/sc7180-trogdor-kingoftown-r1.dts | 17 --------- ...own.dtsi => sc7180-trogdor-kingoftown.dts} | 10 ++++- 4 files changed, 10 insertions(+), 58 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts rename arch/arm64/boot/dts/qcom/{sc7180-trogdor-kingoftown.dtsi => sc7180-trogdor-kingoftown.dts} (95%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ea16e19de4dc..f3e7c8c04c58 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -85,8 +85,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts deleted file mode 100644 index 3abd6222fe46..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Kingoftown board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" -#include "sc7180-trogdor-kingoftown.dtsi" - -/ { - model = "Google Kingoftown (rev0)"; - compatible = "google,kingoftown-rev0", "qcom,sc7180"; -}; - -/* - * In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a - * power rail instead, since kingoftown does not have FP. - */ -&pp3300_fp_tp { - gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; -}; - -&tlmm { - en_fp_rails: en-fp-rails-state { - pins = "gpio74"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts deleted file mode 100644 index e0752ba7df11..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Kingoftown board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-parade-ps8640.dtsi" -#include "sc7180-trogdor-kingoftown.dtsi" - -/ { - model = "Google Kingoftown (rev1+)"; - compatible = "google,kingoftown", "qcom,sc7180"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts similarity index 95% rename from arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi rename to arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts index 315ac5eb5f78..36326ef972dc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts @@ -5,10 +5,18 @@ * Copyright 2021 Google LLC. */ -/* This file must be included after sc7180-trogdor.dtsi */ +/dts-v1/; + +#include "sc7180-trogdor.dtsi" +#include "sc7180-trogdor-parade-ps8640.dtsi" #include #include "sc7180-trogdor-lte-sku.dtsi" +/ { + model = "Google Kingoftown"; + compatible = "google,kingoftown", "qcom,sc7180"; +}; + &alc5682 { compatible = "realtek,rt5682s"; /delete-property/ VBAT-supply; From c0d1296512102a216f9ce10238a9f79c0ac22ccf Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:06 -0800 Subject: [PATCH 0358/1040] arm64: dts: qcom: sc7180: Delete lazor-rev0 lazor-rev0 was a pile of parts. While I kept the pile of parts for lazor running on my desk for longer than I usually do, those days are still long past. Let's finally delete support for lazor-rev0. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.3.I30128a6f4b60b096770186430036afb40ede6f70@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 - .../boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 34 ------------------- 2 files changed, 35 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f3e7c8c04c58..477783764bf8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -86,7 +86,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts deleted file mode 100644 index d49de65aa960..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Lazor board device tree source - * - * Copyright 2020 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" -#include "sc7180-trogdor-ti-sn65dsi86.dtsi" -#include "sc7180-trogdor-lazor.dtsi" - -/ { - model = "Google Lazor (rev0)"; - compatible = "google,lazor-rev0", "qcom,sc7180"; -}; - -&sn65dsi86_out { - /* - * Lane 0 was incorrectly mapped on the cable, but we've now decided - * that the cable is canon and in -rev1+ we'll make a board change - * that means we no longer need the swizzle. - */ - lane-polarities = <1 0>; -}; - -&usb_hub_2_x { - vdd-supply = <&pp3300_l7c>; -}; - -&usb_hub_3_x { - vdd-supply = <&pp3300_l7c>; -}; From b82c362b4d27f439f9ba753e74e0e7a364263f3a Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Mar 2023 13:11:07 -0800 Subject: [PATCH 0359/1040] arm64: dts: qcom: sc7180: Delete mrbland The mrbland board was never actually produced and there has been no activity around the board for quite some time. It seems highly unlikely to magically get revived. There should be nobody in need of these device trees, so let's delete them. If somehow the project resurrects itself then we can re-add support, perhaps just for -rev1+. Signed-off-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230302131031.v2.4.I79eee3b8e9eb3086ae02760e97a2e12ffa8eb4f0@changeid --- arch/arm64/boot/dts/qcom/Makefile | 4 - .../qcom/sc7180-trogdor-mrbland-rev0-auo.dts | 22 -- .../qcom/sc7180-trogdor-mrbland-rev0-boe.dts | 22 -- .../dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi | 36 -- .../qcom/sc7180-trogdor-mrbland-rev1-auo.dts | 22 -- .../qcom/sc7180-trogdor-mrbland-rev1-boe.dts | 24 -- .../boot/dts/qcom/sc7180-trogdor-mrbland.dtsi | 320 ------------------ 7 files changed, 450 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 477783764bf8..1a29403400b7 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -100,10 +100,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts deleted file mode 100644 index 2767817fb053..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x0 => 0 - * - bits 7..4: Panel ID: 0x0 (AUO) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland-rev0.dtsi" - -/ { - model = "Google Mrbland rev0 AUO panel board"; - compatible = "google,mrbland-rev0-sku0", "qcom,sc7180"; -}; - -&panel { - compatible = "auo,b101uan08.3"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts deleted file mode 100644 index 711485574a03..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x10 => 16 - * - bits 7..4: Panel ID: 0x1 (BOE) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland-rev0.dtsi" - -/ { - model = "Google Mrbland rev0 BOE panel board"; - compatible = "google,mrbland-rev0-sku16", "qcom,sc7180"; -}; - -&panel { - compatible = "boe,tv101wum-n53"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi deleted file mode 100644 index f4c1f3813664..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi +++ /dev/null @@ -1,36 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland.dtsi" - -&avdd_lcd { - gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; -}; - -&panel { - enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>; -}; - -&v1p8_mipi { - gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; -}; - -/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */ -&avdd_lcd_en { - pins = "gpio80"; -}; - -&mipi_1800_en { - pins = "gpio81"; -}; - -&vdd_reset_1800 { - pins = "gpio76"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts deleted file mode 100644 index 275313ef7554..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x600 => 1536 - * - bits 11..8: Panel ID: 0x6 (AUO) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland.dtsi" - -/ { - model = "Google Mrbland rev1+ AUO panel board"; - compatible = "google,mrbland-sku1536", "qcom,sc7180"; -}; - -&panel { - compatible = "auo,b101uan08.3"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts deleted file mode 100644 index 87c6b6c30b5e..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - * - * SKU: 0x300 => 768 - * - bits 11..8: Panel ID: 0x3 (BOE) - */ - -/dts-v1/; - -#include "sc7180-trogdor-mrbland.dtsi" - -/ { - model = "Google Mrbland (rev1 - 2) BOE panel board"; - /* Uses ID 768 on rev1 and 1024 on rev2+ */ - compatible = "google,mrbland-sku1024", "google,mrbland-sku768", - "qcom,sc7180"; -}; - -&panel { - compatible = "boe,tv101wum-n53"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi deleted file mode 100644 index ed12ee35f06b..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi +++ /dev/null @@ -1,320 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Mrbland board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include "sc7180-trogdor.dtsi" - -/* This board only has 1 USB Type-C port. */ -/delete-node/ &usb_c1; - -/ { - avdd_lcd: avdd-lcd-regulator { - compatible = "regulator-fixed"; - regulator-name = "avdd_lcd"; - - gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&avdd_lcd_en>; - - vin-supply = <&pp5000_a>; - }; - - avee_lcd: avee-lcd-regulator { - compatible = "regulator-fixed"; - regulator-name = "avee_lcd"; - - gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&avee_lcd_en>; - - vin-supply = <&pp5000_a>; - }; - - v1p8_mipi: v1p8-mipi-regulator { - compatible = "regulator-fixed"; - regulator-name = "v1p8_mipi"; - - gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&mipi_1800_en>; - - vin-supply = <&pp3300_a>; - }; -}; - -&backlight { - pwms = <&cros_ec_pwm 0>; -}; - -&camcc { - status = "okay"; -}; - -&cros_ec { - keyboard-controller { - compatible = "google,cros-ec-keyb-switches"; - }; -}; - -&dsi0 { - - panel: panel@0 { - /* Compatible will be filled in per-board */ - reg = <0>; - enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vdd_reset_1800>; - avdd-supply = <&avdd_lcd>; - avee-supply = <&avee_lcd>; - pp1800-supply = <&v1p8_mipi>; - pp3300-supply = <&pp3300_dx_edp>; - backlight = <&backlight>; - rotation = <270>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - ports { - port@1 { - endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; -}; - -&gpio_keys { - status = "okay"; -}; - -&i2c4 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@5d { - compatible = "goodix,gt7375p"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - - reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; - - vdd-supply = <&pp3300_ts>; - }; -}; - -&pp1800_uf_cam { - status = "okay"; -}; - -&pp1800_wf_cam { - status = "okay"; -}; - -&pp2800_uf_cam { - status = "okay"; -}; - -&pp2800_wf_cam { - status = "okay"; -}; - -&wifi { - qcom,ath10k-calibration-variant = "GO_MRBLAND"; -}; - -/* - * No eDP on this board but it's logically the same signal so just give it - * a new name and assign the proper GPIO. - */ -pp3300_disp_on: &pp3300_dx_edp { - gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>; -}; - -/* PINCTRL - modifications to sc7180-trogdor.dtsi */ - -/* - * No eDP on this board but it's logically the same signal so just give it - * a new name and assign the proper GPIO. - */ - -tp_en: &en_pp3300_dx_edp { - pins = "gpio85"; -}; - -/* PINCTRL - board-specific pinctrl */ - -&tlmm { - gpio-line-names = "HUB_RST_L", - "AP_RAM_ID0", - "AP_SKU_ID2", - "AP_RAM_ID1", - "", - "AP_RAM_ID2", - "UF_CAM_EN", - "WF_CAM_EN", - "TS_RESET_L", - "TS_INT_L", - "", - "", - "AP_EDP_BKLTEN", - "UF_CAM_MCLK", - "WF_CAM_CLK", - "", - "", - "UF_CAM_SDA", - "UF_CAM_SCL", - "WF_CAM_SDA", - "WF_CAM_SCL", - "AVEE_LCD_EN", - "", - "AMP_EN", - "", - "", - "", - "", - "HP_IRQ", - "WF_CAM_RST_L", - "UF_CAM_RST_L", - "AP_BRD_ID2", - "", - "AP_BRD_ID0", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - "AP_H1_SPI_CLK", - "AP_H1_SPI_CS_L", - "BT_UART_CTS", - "BT_UART_RTS", - "BT_UART_TXD", - "BT_UART_RXD", - "H1_AP_INT_ODL", - "", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "HP_I2C_SDA", - "HP_I2C_SCL", - "FORCED_USB_BOOT", - "AMP_BCLK", - "AMP_LRCLK", - "AMP_DIN", - "PEN_DET_ODL", - "HP_BCLK", - "HP_LRCLK", - "HP_DOUT", - "HP_DIN", - "HP_MCLK", - "AP_SKU_ID0", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "AP_SPI_CLK", - "AP_SPI_MOSI", - "AP_SPI_MISO", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "", - "AP_SPI_CS0_L", - "", - "", - "", - "", - "WLAN_SW_CTRL", - "", - "REPORT_E", - "", - "ID0", - "", - "ID1", - "", - "", - "", - "CODEC_PWR_EN", - "HUB_EN", - "TP_EN", - "MIPI_1.8V_EN", - "VDD_RESET_1.8V", - "AVDD_LCD_EN", - "", - "AP_SKU_ID1", - "AP_RST_REQ", - "", - "AP_BRD_ID1", - "AP_EC_INT_L", - "SDM_GRFC_3", - "", - "", - "BOOT_CONFIG_4", - "BOOT_CONFIG_2", - "", - "", - "", - "", - "", - "", - "", - "BOOT_CONFIG_3", - "WCI2_LTE_COEX_TXD", - "WCI2_LTE_COEX_RXD", - "", - "", - "", - "", - "FORCED_USB_BOOT_POL", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "DP_HOT_PLUG_DET", - "EC_IN_RW_ODL"; - - avdd_lcd_en: avdd-lcd-en-state { - pins = "gpio88"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - avee_lcd_en: avee-lcd-en-state { - pins = "gpio21"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - mipi_1800_en: mipi-1800-en-state { - pins = "gpio86"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - vdd_reset_1800: vdd-reset-1800-state { - pins = "gpio87"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; -}; From b26d66228e9744f4ac278d4fa891fc973b00dc6b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:51 +0100 Subject: [PATCH 0360/1040] arm64: dts: qcom: sm8150-kumano: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm8150-sony-xperia-kumano-bahamut.dtb: gpio-keys: key-camera-focus: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index ff77cc3c879a..47e2430991ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -59,7 +59,7 @@ gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; key-camera-snapshot { @@ -68,7 +68,7 @@ gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; key-vol-down { @@ -77,7 +77,7 @@ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; From d7f1f0fd7944b89d45accde9017095feab2b4675 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:52 +0100 Subject: [PATCH 0361/1040] arm64: dts: qcom: msm8998-fxtec: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: msm8998-fxtec-pro1.dtb: gpio-hall-sensors: event-hall-sensor1: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 5aad9f05780a..8b71b1f8f300 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -44,7 +44,7 @@ label = "Keyboard Hall Sensor"; gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; debounce-interval = <15>; - gpio-key,wakeup; + wakeup-source; linux,input-type = ; linux,code = ; }; @@ -116,7 +116,7 @@ gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; }; From ff348b7d963a8b80502997bc266d47e31406db45 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:53 +0100 Subject: [PATCH 0362/1040] arm64: dts: qcom: msm8998-sony-xperia: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: msm8998-sony-xperia-yoshino-lilac.dtb: gpio-keys: button-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 820414758888..fa02e45f1c24 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -106,7 +106,7 @@ gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; }; @@ -138,7 +138,7 @@ gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <30>; }; }; From aa03d854ad656ae214f7ebb13e7d95e436e99da1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:54 +0100 Subject: [PATCH 0363/1040] arm64: dts: qcom: sc7280-idp: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sc7280-idp.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 8b5293e7fd2a..388770be8f13 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -70,7 +70,7 @@ gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; linux,can-disable; }; From f06c0f2779e4567e3a83986646bdd7f63edfee17 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:55 +0100 Subject: [PATCH 0364/1040] arm64: dts: qcom: sdm630-sony-xperia: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sdm630-sony-xperia-nile-voyager.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index e52580acd5c8..2ca713a3902a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -112,7 +112,7 @@ gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; - gpio-key,wakeup; + wakeup-source; debounce-interval = <15>; }; }; From d30f4d6de95ab05cec138929f54f5b92a394c68b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:56 +0100 Subject: [PATCH 0365/1040] arm64: dts: qcom: sm6115p-lenovo-j606f: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm6115p-lenovo-j606f.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 4ce2d905d70e..00b153aa1b7d 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -49,7 +49,7 @@ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; }; From 77a7e394287177b57ec14172a046819eec1a8e90 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:57 +0100 Subject: [PATCH 0366/1040] arm64: dts: qcom: sm8250-sony-xperia: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm8250-sony-xperia-edo-pdx206.dtb: gpio-keys: key-vol-down: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts | 2 +- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts index 5ecf7dafb2ec..01fe3974ee72 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -26,7 +26,7 @@ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index b9c982a059df..c96cc9c90a5f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -63,7 +63,7 @@ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; From df03c41673308006fab6ba71a8458b15a79181f6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:58 +0100 Subject: [PATCH 0367/1040] arm64: dts: qcom: sm8250-xiaomi-elish: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property: sm8250-xiaomi-elish.dtb: gpio-keys: key-vol-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304123358.34274-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts index acaa99c5ff8b..24fc29f0ee5e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts @@ -95,7 +95,7 @@ linux,code = ; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; From bbf97c274da60fcfbb8ebde70a1c3abc6102c709 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 6 Mar 2023 15:11:56 -0800 Subject: [PATCH 0368/1040] dt-bindings: firmware: qcom,scm: Update QDU1000/QRU1000 compatible Update compatible for QDU1000 and QRU1000 to include the interconnect these devices have. Signed-off-by: Melody Olvera Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306231202.12223-2-quic_molvera@quicinc.com --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index ddda28bddde5..543feb3b6c58 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -168,6 +168,7 @@ allOf: compatible: contains: enum: + - qcom,scm-qdu1000 - qcom,scm-sm8450 - qcom,scm-sm8550 then: From 9559342891be54d9ffd13061022d9e5d24b2577a Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 6 Mar 2023 15:11:57 -0800 Subject: [PATCH 0369/1040] dt-bindings: soc: qcom: aoss: Document QDU1000/QRU1000 compatible Add compatible for QDU1000 and QRU1000 aoss devices. Signed-off-by: Melody Olvera Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306231202.12223-3-quic_molvera@quicinc.com --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index ab607efbb64c..798f15588ee2 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -25,6 +25,7 @@ properties: compatible: items: - enum: + - qcom,qdu1000-aoss-qmp - qcom,sc7180-aoss-qmp - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp From 3b76b736cd9933ff88764ffec01cbd859c1475e7 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:16 +0530 Subject: [PATCH 0370/1040] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node Unit address of PCIe EP node should be 0x1c00000 as it has to match the first address specified in the reg property. This also requires sorting the node in the ascending order. Fixes: e6b69813283f ("ARM: dts: qcom: sdx55: Add support for PCIe EP") Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-6-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 78 +++++++++++++++---------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index df7303c5c843..7fa542249f1a 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -304,6 +304,45 @@ status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>; + clock-names = "aux", "cfg", "bus_master", "bus_slave", + "slave_q2a", "sleep", "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_GDSC>; + phys = <&pcie0_lane>; + phy-names = "pciephy"; + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; @@ -401,45 +440,6 @@ status = "disabled"; }; - pcie_ep: pcie-ep@40000000 { - compatible = "qcom,sdx55-pcie-ep"; - reg = <0x01c00000 0x3000>, - <0x40000000 0xf1d>, - <0x40000f20 0xc8>, - <0x40001000 0x1000>, - <0x40200000 0x100000>, - <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", - "mmio"; - - qcom,perst-regs = <&tcsr 0xb258 0xb270>; - - clocks = <&gcc GCC_PCIE_AUX_CLK>, - <&gcc GCC_PCIE_CFG_AHB_CLK>, - <&gcc GCC_PCIE_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_SLV_AXI_CLK>, - <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, - <&gcc GCC_PCIE_SLEEP_CLK>, - <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; - - interrupts = , - ; - interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; - resets = <&gcc GCC_PCIE_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; - phy-names = "pciephy"; - max-link-speed = <3>; - num-lanes = <2>; - - status = "disabled"; - }; - remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From c9f30e3dd92ba779c9cb8bb694ed7a8e2c9f0bb3 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:17 +0530 Subject: [PATCH 0371/1040] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} There is only one PCIe PHY in this SoC, so there is no need to add an index to the suffix. This also matches the naming convention of the PCIe controller. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-7-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 2 +- arch/arm/boot/dts/qcom-sdx55.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index ad74ecc2a196..81f33eba39e5 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -242,7 +242,7 @@ status = "okay"; }; -&pcie0_phy { +&pcie_phy { status = "okay"; vdda-phy-supply = <&vreg_l1e_bb_1p2>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 7fa542249f1a..bd4edceaa1f4 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -335,7 +335,7 @@ resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie_lane>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -343,7 +343,7 @@ status = "disabled"; }; - pcie0_phy: phy@1c07000 { + pcie_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; reg = <0x01c07000 0x1c4>; #address-cells = <1>; @@ -363,7 +363,7 @@ status = "disabled"; - pcie0_lane: lanes@1c06000 { + pcie_lane: lanes@1c06000 { reg = <0x01c06000 0x104>, /* tx0 */ <0x01c06200 0x328>, /* rx0 */ <0x01c07200 0x1e8>, /* pcs */ From 2b20437e67a4b74b990d19d3dbf55388e941f30f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:18 +0530 Subject: [PATCH 0372/1040] ARM: dts: qcom: sdx55: Add support for PCIe RC controller The PCIe controller in SDX55 can act as the RC controller also. Let's add support for it. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-8-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 81 +++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index bd4edceaa1f4..9dabb94eafbc 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -304,6 +304,87 @@ status = "disabled"; }; + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>, From f9364a7ced5e6e36904c359cafe23cbf03645884 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:19 +0530 Subject: [PATCH 0373/1040] ARM: dts: qcom: sdx55: List the property values vertically To align with the rest of the devicetree files and the relative properties, let's list the values of properties such as {reg/clock/interrupt}-names vertically. Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-9-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 9dabb94eafbc..286fa92da428 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -393,7 +393,11 @@ <0x40001000 0x1000>, <0x40200000 0x100000>, <0x01c03000 0x3000>; - reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", "mmio"; qcom,perst-regs = <&tcsr 0xb258 0xb270>; @@ -405,12 +409,18 @@ <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>; - clock-names = "aux", "cfg", "bus_master", "bus_slave", - "slave_q2a", "sleep", "ref"; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; interrupts = , ; - interrupt-names = "global", "doorbell"; + interrupt-names = "global", + "doorbell"; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; @@ -434,7 +444,10 @@ <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen"; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; From 046392390884c9dead1d3703fa60dff97f22857a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:20 +0530 Subject: [PATCH 0374/1040] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support Enable PCIe RC support on Thundercomm T55 board. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-10-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 42 ++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index d5343bb0daee..5edc09af8e0d 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -242,6 +242,23 @@ status = "okay"; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1e_bb_1p2>; + vdda-pll-supply = <&vreg_l4e_bb_0p875>; + + status = "okay"; +}; + +&pcie_rc { + perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &qpic_bam { status = "okay"; }; @@ -265,6 +282,31 @@ memory-region = <&mpss_adsp_mem>; }; +&tlmm { + pcie_default: pcie-default-state { + clkreq-pins { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + wake-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + &usb_hsphy { status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; From 43743bfa36daed8f31860ad889a1413f239bb2f2 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:54:21 +0530 Subject: [PATCH 0375/1040] ARM: dts: qcom: sdx55-t55: Move "status" property down To align with rest of the devicetree files, let's move the "status" property down Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308082424.140224-11-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-t55.dts | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 5edc09af8e0d..51058b065279 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -278,8 +278,8 @@ }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + status = "okay"; }; &tlmm { @@ -308,16 +308,18 @@ }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; vdda33-supply = <&vreg_l10e_3p1>; vdda18-supply = <&vreg_l5e_bb_1p7>; + + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4e_bb_0p875>; vdda-pll-supply = <&vreg_l1e_bb_1p2>; + + status = "okay"; }; &usb { From 7629c7a525d163f2a3a08e260a69ff25163ab357 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 8 Mar 2023 09:32:53 +0100 Subject: [PATCH 0376/1040] arm64: dts: qcom: sm8550: fix qup_spi0_cs node The node is incomplete and doesn't need a subnode, add the missing properties and move everything to the root of qup-spi0-cs-state node. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-2-595b02067672@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index a07bbb8e9fb5..d3a1e320306e 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2799,10 +2799,10 @@ }; qup_spi0_cs: qup-spi0-cs-state { - cs-pins { - pins = "gpio31"; - function = "qup1_se0"; - }; + pins = "gpio31"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; }; qup_spi0_data_clk: qup-spi0-data-clk-state { From f03908b23f84ecd49f12facf4acf34c3ad24f27a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 8 Mar 2023 09:32:54 +0100 Subject: [PATCH 0377/1040] arm64: dts: qcom: sm8550: misc style fixes Miscellaneous DT fixes to remove spurious blank line and enhance readability. Fixes: ffc50b2d3828 ("arm64: dts: qcom: Add base SM8550 dtsi") Fixes: d7da51db5b81 ("arm64: dts: qcom: sm8550: add display hardware devices") Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-sm8550-upstream-dt-fixups-v1-3-595b02067672@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index d3a1e320306e..8789ea42d6eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -420,7 +420,6 @@ no-map; }; - hyp_tags_reserved_mem: hyp-tags-reserved-region@811d0000 { reg = <0 0x811d0000 0 0x30000>; no-map; @@ -2202,7 +2201,8 @@ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -2294,8 +2294,10 @@ power-domains = <&rpmhpd SM8550_MMCX>; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; @@ -3163,7 +3165,7 @@ intc: interrupt-controller@17100000 { compatible = "arm,gic-v3"; - reg = <0 0x17100000 0 0x10000>, /* GICD */ + reg = <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ ranges; #interrupt-cells = <3>; From 608465f798bb3eaf6773a49b893902860858e294 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 8 Mar 2023 13:36:17 +0100 Subject: [PATCH 0378/1040] arm64: dts: qcom: msm8916: Fix tsens_mode unit address The reg address of the tsens_mode nvmem cell is correct but the unit address does not match (0xec vs 0xef). Fix it. No functional change. Fixes: 24aafd041fb2 ("arm64: dts: qcom: msm8916: specify per-sensor calibration cells") Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308123617.101211-1-stephan.gerhold@kernkonzept.com --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0733c2f4f379..0d5283805f42 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -503,7 +503,7 @@ bits = <1 7>; }; - tsens_mode: mode@ec { + tsens_mode: mode@ef { reg = <0xef 0x1>; bits = <5 3>; }; From ddb705deeefc9807a5db9ef8da47a020371bfb9c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 14:26:49 +0100 Subject: [PATCH 0379/1040] soc: renesas: mark OF related data as maybe unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver can be compile tested with !CONFIG_OF making certain data unused. With W=1: drivers/soc/renesas/renesas-soc.c:272:34: error: ‘renesas_socs’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230312132650.352796-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/renesas-soc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index a22e65916e20..ae07269f0d9c 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -269,7 +269,7 @@ static const struct renesas_soc soc_shmobile_ag5 __initconst __maybe_unused = { }; -static const struct of_device_id renesas_socs[] __initconst = { +static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R7S72100 { .compatible = "renesas,r7s72100", .data = &soc_rz_a1h }, #endif From 641a5e94dc9f61471736d6f776625348f46fb97f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 14:26:50 +0100 Subject: [PATCH 0380/1040] soc: renesas: pwc-rzv2m: drop of_match_ptr for ID table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might not be relevant here). This also fixes a !CONFIG_OF error with W=1: drivers/soc/renesas/pwc-rzv2m.c:124:34: error: ‘rzv2m_pwc_of_match’ defined but not used [-Werror=unused-const-variable=] Signed-off-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230312132650.352796-2-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/pwc-rzv2m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/renesas/pwc-rzv2m.c b/drivers/soc/renesas/pwc-rzv2m.c index c83bdbdabb64..452cee8d68be 100644 --- a/drivers/soc/renesas/pwc-rzv2m.c +++ b/drivers/soc/renesas/pwc-rzv2m.c @@ -131,7 +131,7 @@ static struct platform_driver rzv2m_pwc_driver = { .probe = rzv2m_pwc_probe, .driver = { .name = "rzv2m_pwc", - .of_match_table = of_match_ptr(rzv2m_pwc_of_match), + .of_match_table = rzv2m_pwc_of_match, }, }; module_platform_driver(rzv2m_pwc_driver); From 2653d5bf1c9d123c0d8b8c1634cf54dacfcfdb52 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 13 Mar 2023 12:02:56 +0100 Subject: [PATCH 0381/1040] soc: renesas: Use "#ifdef" for single-symbol definition checks Replace "#if defined(CONFIG_)" by "#ifdef CONFIG_" for brevity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/6026a3fe36735f0e6a0ecb037bf7c45f42aa3daf.1678705241.git.geert+renesas@glider.be --- drivers/soc/renesas/renesas-soc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index ae07269f0d9c..4ba893e45427 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -373,20 +373,20 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = { #ifdef CONFIG_ARCH_R8A779G0 { .compatible = "renesas,r8a779g0", .data = &soc_rcar_v4h }, #endif -#if defined(CONFIG_ARCH_R9A07G043) +#ifdef CONFIG_ARCH_R9A07G043 #ifdef CONFIG_RISCV { .compatible = "renesas,r9a07g043", .data = &soc_rz_five }, #else { .compatible = "renesas,r9a07g043", .data = &soc_rz_g2ul }, #endif #endif -#if defined(CONFIG_ARCH_R9A07G044) +#ifdef CONFIG_ARCH_R9A07G044 { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, #endif -#if defined(CONFIG_ARCH_R9A07G054) +#ifdef CONFIG_ARCH_R9A07G054 { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, #endif -#if defined(CONFIG_ARCH_R9A09G011) +#ifdef CONFIG_ARCH_R9A09G011 { .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m }, #endif #ifdef CONFIG_ARCH_SH73A0 From 279ac702bef0bff67a58a0ed483692932a29ce37 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 9 Mar 2023 16:30:47 +0100 Subject: [PATCH 0382/1040] ARM: dts: armadillo800eva: Add I2C EEPROM for MAC address Add a device node for the M24C01 I2C EEPROM which serves as external storage for the Ethernet MAC address. While at it, restore sort order (by unit address) of the devices on the I2C bus. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/6d402b289fd20125d9f6f6b2a4f239aa1887daa6.1678375464.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 0af63ddc4473..fa09295052c6 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -196,6 +196,19 @@ &i2c0 { status = "okay"; + + wm8978: codec@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; + + eeprom@50 { + compatible = "st,24c01", "atmel,24c01"; + reg = <0x50>; + pagesize = <16>; + }; + touchscreen@55 { compatible = "sitronix,st1232"; reg = <0x55>; @@ -205,12 +218,6 @@ pinctrl-names = "default"; gpios = <&pfc 166 GPIO_ACTIVE_LOW>; }; - - wm8978: codec@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; }; &i2c2 { From 9f92b342e1388ed1be0e0c27ef8dfc65a3abd7f3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 9 Mar 2023 16:30:48 +0100 Subject: [PATCH 0383/1040] arm64: dts: renesas: condor: Add I2C EEPROM for PMIC Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/84971f48eca0b696f592a922268af8c150d9bae3.1678375464.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 1d326552e2fa..68d1f1d53b3a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -14,3 +14,11 @@ model = "Renesas Condor board based on r8a77980"; compatible = "renesas,condor", "renesas,r8a77980"; }; + +&i2c0 { + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; From d5136914e48c7da5eab5caefd566b61a3aab4fc1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 9 Mar 2023 16:30:49 +0100 Subject: [PATCH 0384/1040] arm64: dts: renesas: ulcb: Add I2C EEPROM for PMIC Add a device node for the I2C EEPROM which serves as external storage for the PMIC setup. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b52c6c21a94aa7320ac0c900f7023a5dfca76a29.1678375464.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index d693e879b330..0be2716659e9 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -267,6 +267,12 @@ }; }; }; + + eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; }; &ohci1 { From 4db0ce4038dec3cf5cb42587a111f4415be381b6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 13 Mar 2023 12:04:21 +0100 Subject: [PATCH 0385/1040] arm64: dts: renesas: r8a779a0: Update CAN-FD to R-Car Gen4 compatible value Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible property in the CAN-FD device node to include the family-specific compatible value for R-Car Gen4. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/9823058fa57156e88a084a4a99fc8525af1686ff.1678705389.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index f04792baef80..7925341a69c8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -606,7 +606,8 @@ }; canfd: can@e6660000 { - compatible = "renesas,r8a779a0-canfd"; + compatible = "renesas,r8a779a0-canfd", + "renesas,rcar-gen4-canfd"; reg = <0 0xe6660000 0 0x8000>; interrupts = , ; From cf386126aef92256245adc8be686f2df4b837013 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 16 Mar 2023 15:12:52 +0100 Subject: [PATCH 0386/1040] arm64: dts: qcom: sc8280xp: fix external display power domain Fix the external display controller nodes which erroneously described the controllers as belonging to CX rather than MMCX. Fixes: 19d3bb90754f ("arm64: dts: qcom: sc8280xp: Add USB-C-related DP blocks") Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316141252.2436-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 64d351aa3b0f..c22ab532cdf3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3267,7 +3267,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&mdss0_dp0_opp_table>; - power-domains = <&rpmhpd SC8280XP_CX>; + power-domains = <&rpmhpd SC8280XP_MMCX>; status = "disabled"; @@ -3345,7 +3345,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&mdss0_dp1_opp_table>; - power-domains = <&rpmhpd SC8280XP_CX>; + power-domains = <&rpmhpd SC8280XP_MMCX>; status = "disabled"; From d2e5c16f6c86901040f3bb6b40d1a01ccf1a21b0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 8 Feb 2023 12:55:06 -0600 Subject: [PATCH 0387/1040] arm64: dts: cavium: Fix GICv3 ITS nodes The GICv3 ITS is an MSI controller, therefore its node name should be 'msi-controller'. The ITS node is also expected to have '#msi-cells'. Add it on Thunder as there are no users. Thunder2 uses 'msi-parent', but Robin says that should be 'msi-map' instead and I'm not sure what's correct for it. The unit-addresses of both the ITS and main GIC node on thunder2 are also wrong, so fix them while we're here. Cc: Robin Murphy Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230208185506.2305349-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 3 ++- arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index e0a71795261b..8ad31dee11a3 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -389,9 +389,10 @@ <0x8010 0x80000000 0x0 0x600000>; /* GICR */ interrupts = <1 9 0xf04>; - its: gic-its@8010,00020000 { + its: msi-controller@801000020000 { compatible = "arm,gic-v3-its"; msi-controller; + #msi-cells = <1>; reg = <0x8010 0x20000 0x0 0x200000>; }; }; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi index dfb41705a9a9..3419bd252696 100644 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi @@ -55,7 +55,7 @@ method = "smc"; }; - gic: interrupt-controller@400080000 { + gic: interrupt-controller@4000080000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; @@ -67,7 +67,7 @@ <0x04 0x01000000 0x0 0x1000000>; /* GICR */ interrupts = ; - gicits: gic-its@40010000 { + gicits: msi-controller@4000100000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ From c04d7b263d3ff036ca124494c57011c1c274dbe6 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Wed, 15 Mar 2023 22:28:13 +0100 Subject: [PATCH 0388/1040] arm64: dts: exynos: drop mshc aliases Previously, the mshc0 alias has been necessary so that MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA are set for mshc_0/mmc_0. However, these capabilities should be described in the device tree so that we do not have to rely on the alias. The property mmc-ddr-1_8v replaces MMC_CAP_1_8V_DDR, while bus_width = <8>, which is already set for all the mshc0/mmc0 nodes, replaces MMC_CAP_8_BIT_DATA. Also drop other mshc aliases as they are not needed. Signed-off-by: Henrik Grimler Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230315212814.15908-2-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 3 +-- arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index f54f30633417..868f7b98a637 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -40,8 +40,6 @@ spi2 = &spi_2; spi3 = &spi_3; spi4 = &spi_4; - mshc0 = &mshc_0; - mshc2 = &mshc_2; }; chosen { @@ -952,6 +950,7 @@ &mshc_0 { status = "okay"; + mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; cap-mmc-highspeed; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index f3f4a6ab4b49..35d949099166 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -18,8 +18,6 @@ aliases { serial0 = &serial_2; - mshc0 = &mmc_0; - mshc2 = &mmc_2; }; chosen { @@ -362,6 +360,7 @@ &mmc_0 { status = "okay"; cap-mmc-highspeed; + mmc-ddr-1_8v; mmc-hs200-1_8v; non-removable; card-detect-delay = <200>; From 5f67124757464d632f0e5288e0ba48e3ff5531a9 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Wed, 15 Mar 2023 22:28:14 +0100 Subject: [PATCH 0389/1040] arm64: dts: exynos: add mmc aliases Add aliases for eMMC and SD card where applicable, so that assigned mmc indeces are always the same. Signed-off-by: Henrik Grimler Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230315212814.15908-3-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 2 ++ arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 2 ++ arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index 868f7b98a637..e4ed788413fe 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -21,6 +21,8 @@ gsc0 = &gsc_0; gsc1 = &gsc_1; gsc2 = &gsc_2; + mmc0 = &mshc_0; + mmc2 = &mshc_2; pinctrl0 = &pinctrl_alive; pinctrl1 = &pinctrl_aud; pinctrl2 = &pinctrl_cpif; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 35d949099166..1f2eddcebdd9 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -17,6 +17,8 @@ compatible = "samsung,exynos7-espresso", "samsung,exynos7"; aliases { + mmc0 = &mmc_0; + mmc2 = &mmc_2; serial0 = &serial_2; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts index 5db9a81ac7bb..47a389d9ff7d 100644 --- a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -18,6 +18,7 @@ chassis-type = "handset"; aliases { + mmc0 = &mmc_0; serial0 = &serial_0; serial1 = &serial_1; serial2 = &serial_2; From 129469c4881d097e832a48b7b8c62750a8b323e2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 11 Mar 2023 00:14:20 +0100 Subject: [PATCH 0390/1040] ARM: dts: ixp4xx: use "okay" for status "okay" over "ok" is preferred for status property. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230127101832.93789-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230310231420.583121-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts | 2 +- arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts | 4 ++-- arch/arm/boot/dts/intel-ixp42x-ixdp425.dts | 4 ++-- arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts | 4 ++-- arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts | 6 +++--- arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts | 4 ++-- arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts | 2 +- arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts | 6 +++--- arch/arm/boot/dts/intel-ixp43x-kixrp435.dts | 4 ++-- arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi | 2 +- 17 files changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts index bd4230d7dac9..765ab36e6f0c 100644 --- a/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts +++ b/arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts @@ -56,7 +56,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from Coyote PCI boardfile. @@ -80,7 +80,7 @@ /* EthB */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -102,7 +102,7 @@ /* EthC */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts index 92b987bc3f99..6f5b4e4eb1cc 100644 --- a/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts +++ b/arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts @@ -112,7 +112,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from Vulcan PCI boardfile. @@ -137,7 +137,7 @@ /* EthB */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -159,7 +159,7 @@ /* EthC */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts index 5ab09fb10dae..b9d46eb06507 100644 --- a/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts +++ b/arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts @@ -122,7 +122,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from DSM-G600 PCI boardfile (dsmg600-pci.c) diff --git a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts index b740403b05a9..5a5e16cc7335 100644 --- a/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts +++ b/arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts @@ -159,7 +159,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Written based on the FSG-3 PCI boardfile. @@ -187,7 +187,7 @@ /* EthB */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -209,7 +209,7 @@ /* EthC */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts index b7cbc90e1c18..4d70f6afd13a 100644 --- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts +++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts @@ -53,7 +53,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from Gateway 7001 PCI boardfile (gateway7001-pci.c) @@ -74,7 +74,7 @@ }; ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -91,7 +91,7 @@ }; ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts b/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts index a5943f51e8c2..97e3f25bb210 100644 --- a/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts +++ b/arch/arm/boot/dts/intel-ixp42x-gateworks-gw2348.dts @@ -108,7 +108,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from Avila PCI boardfile. @@ -142,7 +142,7 @@ /* EthB */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -164,7 +164,7 @@ /* EthC */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts index f80388b17a9e..9ec0169bacf8 100644 --- a/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts +++ b/arch/arm/boot/dts/intel-ixp42x-goramo-multilink.dts @@ -82,7 +82,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * The device has 4 slots (IDSEL) with one dedicated IRQ per slot. @@ -148,7 +148,7 @@ /* EthB */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 32>; phy-mode = "rgmii"; @@ -170,7 +170,7 @@ /* EthC */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 33>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts b/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts index cbc87b344f6a..8da6823e1dbe 100644 --- a/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts +++ b/arch/arm/boot/dts/intel-ixp42x-iomega-nas100d.dts @@ -109,7 +109,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from NAS 100D PCI boardfile (nas100d-pci.c) @@ -129,7 +129,7 @@ }; ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts index beaadda4685f..194945748dc3 100644 --- a/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts +++ b/arch/arm/boot/dts/intel-ixp42x-ixdp425.dts @@ -40,7 +40,7 @@ /* EthB */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -62,7 +62,7 @@ /* EthC */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts index f17cab12a64b..7011fea6205b 100644 --- a/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts +++ b/arch/arm/boot/dts/intel-ixp42x-ixdpg425.dts @@ -61,7 +61,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from IXDPG425 PCI boardfile. @@ -95,7 +95,7 @@ /* EthB */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -117,7 +117,7 @@ /* EthC */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts index 0edc5928e00b..da1e93212b86 100644 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts @@ -116,7 +116,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant @@ -143,7 +143,7 @@ }; ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts index 5e7e31b74b04..4aba9e0214a0 100644 --- a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts @@ -117,7 +117,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * We have up to 2 slots (IDSEL) with 2 swizzled IRQs. @@ -141,7 +141,7 @@ * Do we need a new binding and property for this? */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; @@ -165,7 +165,7 @@ /* EthC - connected to KS8995 switch port 5 */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts index df2ca6d95ee5..19d56e9aec9d 100644 --- a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts +++ b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts @@ -54,7 +54,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) @@ -77,7 +77,7 @@ }; ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts index b444003c10e1..c550c421b659 100644 --- a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts +++ b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts @@ -79,7 +79,7 @@ /* LAN port */ ethernet@c8009000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts index cf4010d60187..1db849515f9e 100644 --- a/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts +++ b/arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts @@ -121,7 +121,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * In the boardfile for the Cambria from OpenWRT the interrupts @@ -167,7 +167,7 @@ }; ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; @@ -188,7 +188,7 @@ }; ethernet@c800c000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 2>; queue-txready = <&qmgr 19>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts b/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts index 3d7cfa1a5ed4..4703a8b24765 100644 --- a/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts +++ b/arch/arm/boot/dts/intel-ixp43x-kixrp435.dts @@ -36,7 +36,7 @@ /* CHECKME: ethernet set-up taken from Gateworks Cambria */ ethernet@c800a000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 4>; queue-txready = <&qmgr 21>; phy-mode = "rgmii"; @@ -57,7 +57,7 @@ }; ethernet@c800c000 { - status = "ok"; + status = "okay"; queue-rx = <&qmgr 2>; queue-txready = <&qmgr 19>; phy-mode = "rgmii"; diff --git a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi index 146352ba848b..31c0a69771c4 100644 --- a/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi +++ b/arch/arm/boot/dts/intel-ixp4xx-reference-design.dtsi @@ -99,7 +99,7 @@ }; pci@c0000000 { - status = "ok"; + status = "okay"; /* * Taken from IXDP425 PCI boardfile. From 2b4881839a392bf66312685cf1c65cd3487e6ec8 Mon Sep 17 00:00:00 2001 From: Chunyan Zhang Date: Mon, 6 Mar 2023 16:57:17 +0800 Subject: [PATCH 0391/1040] arm64: dts: sprd: Add support for Unisoc's UMS512 Add basic support for Unisoc's UMS512, with this patch, the board ums512-1h10 can run into console. Signed-off-by: Chunyan Zhang Link: https://lore.kernel.org/r/20230306085717.420353-1-chunyan.zhang@unisoc.com Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/sprd/Makefile | 3 +- arch/arm64/boot/dts/sprd/ums512-1h10.dts | 61 ++ arch/arm64/boot/dts/sprd/ums512.dtsi | 911 +++++++++++++++++++++++ 3 files changed, 974 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/sprd/ums512-1h10.dts create mode 100644 arch/arm64/boot/dts/sprd/ums512.dtsi diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile index f4f1f5148cc2..97522fb0bf66 100644 --- a/arch/arm64/boot/dts/sprd/Makefile +++ b/arch/arm64/boot/dts/sprd/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ sp9860g-1h10.dtb \ - sp9863a-1h10.dtb + sp9863a-1h10.dtb \ + ums512-1h10.dtb diff --git a/arch/arm64/boot/dts/sprd/ums512-1h10.dts b/arch/arm64/boot/dts/sprd/ums512-1h10.dts new file mode 100644 index 000000000000..46890f6d140d --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums512-1h10.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS512-1h10 boards DTS file + * + * Copyright (C) 2021, Unisoc Inc. + */ + +/dts-v1/; + +#include "ums512.dtsi" + +/ { + model = "Unisoc UMS512-1H10 Board"; + + compatible = "sprd,ums512-1h10", "sprd,ums512"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* SD card */ +&sdio0 { + bus-width = <4>; + no-sdio; + no-mmc; + sprd,phy-delay-sd-uhs-sdr104 = <0x7f 0x73 0x72 0x72>; + sprd,phy-delay-sd-uhs-sdr50 = <0x6e 0x7f 0x01 0x01>; + sprd,phy-delay-sd-highspeed = <0x7f 0x1a 0x9a 0x9a>; + sprd,phy-delay-legacy = <0x7f 0x1a 0x9a 0x9a>; + sd-uhs-sdr104; + sd-uhs-sdr50; +}; + +/* EMMC storage */ +&sdio3 { + status = "okay"; + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + cap-mmc-hw-reset; +}; diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi new file mode 100644 index 000000000000..024be594c47d --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -0,0 +1,911 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS512 SoC DTS file + * + * Copyright (C) 2021, Unisoc Inc. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&CORE_PD>; + }; + }; + + idle-states { + entry-method = "psci"; + CORE_PD: core-pd { + compatible = "arm,idle-state"; + entry-latency-us = <4000>; + exit-latency-us = <4000>; + min-residency-us = <10000>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure PPI */ + , /* Physical Non-Secure PPI */ + , /* Virtual PPI */ + ; /* Hipervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@12000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x12000000 0 0x20000>, /* GICD */ + <0x0 0x12040000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + redistributor-stride = <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions = <1>; + interrupt-controller; + interrupts = ; + }; + + ap_ahb_regs: syscon@20100000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x20100000 0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20100000 0x4000>; + + apahb_gate: clock-controller@0 { + compatible = "sprd,ums512-apahb-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + pub_apb_regs: syscon@31050000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x31050000 0 0x9000>; + }; + + top_dvfs_apb_regs: syscon@322a0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x322a0000 0 0x8000>; + }; + + ap_intc0_regs: syscon@32310000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32310000 0 0x1000>; + }; + + ap_intc1_regs: syscon@32320000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32320000 0 0x1000>; + }; + + ap_intc2_regs: syscon@32330000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32330000 0 0x1000>; + }; + + ap_intc3_regs: syscon@32340000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32340000 0 0x1000>; + }; + + ap_intc4_regs: syscon@32350000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32350000 0 0x1000>; + }; + + ap_intc5_regs: syscon@32360000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32360000 0 0x1000>; + }; + + anlg_phy_g0_regs: syscon@32390000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x32390000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x32390000 0x3000>; + + dpll0: clock-controller@0 { + compatible = "sprd,ums512-g0-pll"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g2_regs: syscon@323b0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323b0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323b0000 0x3000>; + + mpll1: clock-controller@0 { + compatible = "sprd,ums512-g2-pll"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + anlg_phy_g3_regs: syscon@323c0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323c0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323c0000 0x3000>; + + pll1: clock-controller@0 { + compatible = "sprd,ums512-g3-pll"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_gc_regs: syscon@323e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323e0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x323e0000 0x3000>; + + pll2: clock-controller@0 { + compatible = "sprd,ums512-gc-pll"; + reg = <0x0 0x100>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + anlg_phy_g10_regs: syscon@323f0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x323f0000 0 0x3000>; + }; + + aon_apb_regs: syscon@327d0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x327d0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x327d0000 0x3000>; + + aonapb_gate: clock-controller@0 { + compatible = "sprd,ums512-aon-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + pmu_apb_regs: syscon@327e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x327e0000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x327e0000 0x3000>; + + pmu_gate: clock-controller@0 { + compatible = "sprd,ums512-pmu-gate"; + reg = <0x0 0x3000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + }; + + audcp_apb_regs: syscon@3350d000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x3350d000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x3350d000 0x1000>; + + audcpapb_gate: clock-controller@0 { + compatible = "sprd,ums512-audcpapb-gate"; + reg = <0x0 0x300>; + #clock-cells = <1>; + }; + }; + + audcp_ahb_regs: syscon@335e0000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x335e0000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x335e0000 0x1000>; + + audcpahb_gate: clock-controller@0 { + compatible = "sprd,ums512-audcpahb-gate"; + reg = <0x0 0x300>; + #clock-cells = <1>; + }; + }; + + gpu_apb_regs: syscon@60100000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60100000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x60100000 0x3000>; + + gpu_clk: clock-controller@0 { + compatible = "sprd,ums512-gpu-clk"; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + reg = <0x0 0x100>; + #clock-cells = <1>; + }; + }; + + gpu_dvfs_apb_regs: syscon@60110000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x60110000 0 0x3000>; + }; + + mm_ahb_regs: syscon@62200000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x62200000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x62200000 0x3000>; + + mm_gate: clock-controller@0 { + compatible = "sprd,ums512-mm-gate-clk"; + reg = <0x0 0x3000>; + #clock-cells = <1>; + }; + }; + + ap_apb_regs: syscon@71000000 { + compatible = "sprd,ums512-glbregs", "syscon", + "simple-mfd"; + reg = <0 0x71000000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x71000000 0x3000>; + + apapb_gate: clock-controller@0 { + compatible = "sprd,ums512-apapb-gate"; + reg = <0x0 0x3000>; + #clock-cells = <1>; + }; + }; + + ap_clk: clock-controller@20200000 { + compatible = "sprd,ums512-ap-clk"; + reg = <0 0x20200000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + + aon_clk: clock-controller@32080000 { + compatible = "sprd,ums512-aonapb-clk"; + reg = <0 0x32080000 0 0x1000>; + clocks = <&ext_26m>, <&ext_32k>, + <&ext_4m>, <&rco_100m>; + clock-names = "ext-26m", "ext-32k", + "ext-4m", "rco-100m"; + #clock-cells = <1>; + }; + + mm_clk: clock-controller@62100000 { + compatible = "sprd,ums512-mm-clk"; + reg = <0 0x62100000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "ext-26m"; + #clock-cells = <1>; + }; + + /* SoC Funnel */ + funnel@3c002000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3c002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_soc_out_port: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + funnel_soc_in_port: endpoint { + remote-endpoint = + <&funnel_corinth_out_port>; + }; + }; + }; + }; + + /* SoC ETF */ + soc_etb: etb@3c003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3c003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + in-ports { + port { + etb_in: endpoint { + remote-endpoint = + <&funnel_soc_out_port>; + }; + }; + }; + }; + + /* AP-CPU Funnel for core3/4/5/7 */ + funnel@3e001000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e001000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_lit_out_port: endpoint { + remote-endpoint = + <&corinth_etf_lit_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_core_in_port3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_core_in_port4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_core_in_port5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_core_in_port7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + /* AP-CPU ETF for little cores */ + etf@3e002000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3e002000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + corinth_etf_lit_out: endpoint { + remote-endpoint = + <&funnel_corinth_from_lit_in_port>; + }; + }; + }; + + in-ports { + port { + corinth_etf_lit_in: endpoint { + remote-endpoint = + <&funnel_corinth_lit_out_port>; + }; + }; + }; + }; + + /* AP-CPU ETF for big cores */ + etf@3e003000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0x3e003000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + corinth_etf_big_out: endpoint { + remote-endpoint = + <&funnel_corinth_from_big_in_port>; + }; + }; + }; + + in-ports { + port { + corinth_etf_big_in: endpoint { + remote-endpoint = + <&funnel_corinth_big_out_port>; + }; + }; + }; + }; + + /* Funnel to SoC */ + funnel@3e004000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e004000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_out_port: endpoint { + remote-endpoint = + <&funnel_soc_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_corinth_from_lit_in_port: endpoint { + remote-endpoint = <&corinth_etf_lit_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_corinth_from_big_in_port: endpoint { + remote-endpoint = <&corinth_etf_big_out>; + }; + }; + }; + }; + + /* AP-CPU Funnel for core0/1/2/6 */ + funnel@3e005000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0 0x3e005000 0 0x1000>; + clocks = <&ext_26m>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel_corinth_big_out_port: endpoint { + remote-endpoint = <&corinth_etf_big_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_core_in_port0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_core_in_port1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_core_in_port2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_core_in_port6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + }; + }; + + etm0: etm@3f040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f040000 0 0x1000>; + cpu = <&CPU0>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&funnel_core_in_port0>; + }; + }; + }; + }; + + etm1: etm@3f140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f140000 0 0x1000>; + cpu = <&CPU1>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&funnel_core_in_port1>; + }; + }; + }; + }; + + etm2: etm@3f240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f240000 0 0x1000>; + cpu = <&CPU2>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&funnel_core_in_port2>; + }; + }; + }; + }; + + etm3: etm@3f340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f340000 0 0x1000>; + cpu = <&CPU3>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&funnel_core_in_port3>; + }; + }; + }; + }; + + etm4: etm@3f440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f440000 0 0x1000>; + cpu = <&CPU4>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&funnel_core_in_port4>; + }; + }; + }; + }; + + etm5: etm@3f540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f540000 0 0x1000>; + cpu = <&CPU5>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&funnel_core_in_port5>; + }; + }; + }; + }; + + etm6: etm@3f640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f640000 0 0x1000>; + cpu = <&CPU6>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&funnel_core_in_port6>; + }; + }; + }; + }; + + etm7: etm@3f740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0x3f740000 0 0x1000>; + cpu = <&CPU7>; + clocks = <&ext_26m>, <&aon_clk CLK_CSSYS>, <&pll2 CLK_TWPLL_512M>; + clock-names = "apb_pclk", "clk_cs", "cs_src"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&funnel_core_in_port7>; + }; + }; + }; + }; + + apb@70000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x70000000 0x10000000>; + + uart0: serial@0 { + compatible = "sprd,ums512-uart", + "sprd,sc9836-uart"; + reg = <0x0 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart1: serial@100000 { + compatible = "sprd,ums512-uart", + "sprd,sc9836-uart"; + reg = <0x100000 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + sdio0: mmc@1100000 { + compatible = "sprd,sdhci-r11"; + reg = <0x1100000 0x1000>; + interrupts = ; + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_SDIO0_2X>, + <&apapb_gate CLK_SDIO0_EB>; + assigned-clocks = <&ap_clk CLK_SDIO0_2X>; + assigned-clock-parents = <&pll1 CLK_RPLL>; + status = "disabled"; + }; + + sdio3: mmc@1400000 { + compatible = "sprd,sdhci-r11"; + reg = <0x1400000 0x1000>; + interrupts = ; + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apapb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&pll1 CLK_RPLL>; + status = "disabled"; + }; + }; + + aon: bus@32000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x32000000 0x1000000>; + + adi_bus: spi@100000 { + compatible = "sprd,ums512-adi"; + reg = <0x100000 0x100000>; + #address-cells = <1>; + #size-cells = <0>; + sprd,hw-channels = <2 0x18cc>, <3 0x18cc>, <13 0x1854>, <15 0x1874>, + <17 0x1844>,<19 0x1844>, <21 0x1864>, <30 0x1820>, + <35 0x19b8>, <39 0x19ac>; + }; + }; + }; + + ext_26m: clk-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_32k: clk-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + ext_4m: clk-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + rco_100m: clk-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; +}; From 7bf891434919ae1492bb583dba349e895c818255 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Mon, 6 Mar 2023 15:34:21 +0000 Subject: [PATCH 0392/1040] arm64: virtconfig: Further shrink the config After disabling platform support there's still some more pruning we can do to the virtconfig size, there are a number of drivers and subsystems which are not likely to be useful on mach-virt and so can be disabled in order to further improve build times. Let's do so, noting that having PCI device assignment means that PCI devices might potentially appear. This is just an initial manual passthrough, there will be further savings available especially if we take a much more focused approach. Signed-off-by: Mark Brown Link: https://lore.kernel.org/r/20230221-arm64-virtconfig-slim-v1-1-604b64be7ec3@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm64/configs/virt.config | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/configs/virt.config b/arch/arm64/configs/virt.config index 6ef0a739717f..6865d54e68f8 100644 --- a/arch/arm64/configs/virt.config +++ b/arch/arm64/configs/virt.config @@ -1,3 +1,7 @@ +# +# Base options for platforms +# + # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set @@ -37,3 +41,20 @@ # CONFIG_ARCH_VISCONTI is not set # CONFIG_ARCH_XGENE is not set # CONFIG_ARCH_ZYNQMP is not set + +# +# Subsystems which can't be used in mach-virt +# +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_EXTCON is not set +# CONFIG_IIO is not set +# CONFIG_MTD is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_PWM is not set +# CONFIG_REGULATOR is not set +# CONFIG_SLIMBUS is not set +# CONFIG_SND_SOC is not set +# CONFIG_SOUNDWIRE is not set +# CONFIG_SPI is not set +# CONFIG_SURFACE_PLATFORMS is not set +# CONFIG_THERMAL is not set From 781d32d1c9709fd25655c4e3e3e15370ae4ae4db Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 16 Mar 2023 20:44:26 +0530 Subject: [PATCH 0393/1040] firmware: qcom_scm: Clear download bit during reboot During normal restart of a system download bit should be cleared irrespective of whether download mode is set or not. Fixes: 8c1b7dc9ba22 ("firmware: qcom: scm: Expose download-mode control") Signed-off-by: Mukesh Ojha Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1678979666-551-1-git-send-email-quic_mojha@quicinc.com --- drivers/firmware/qcom_scm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index b95616b35bff..ce76f5263aa3 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1508,8 +1508,7 @@ static int qcom_scm_probe(struct platform_device *pdev) static void qcom_scm_shutdown(struct platform_device *pdev) { /* Clean shutdown, disable download mode to allow normal restart */ - if (download_mode) - qcom_scm_set_download_mode(false); + qcom_scm_set_download_mode(false); } static const struct of_device_id qcom_scm_dt_match[] = { From 0ea0edc04a04e3e36fa7d0b3c8463b0440764cf1 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 14 Mar 2023 14:06:32 +0530 Subject: [PATCH 0394/1040] arm64: dts: qcom: sm6115: Cleanup USB node's label There is only one USB controller present on SM6115 / SM4250 Qualcomm SoC, so drop the numbering used with USB node's label names in the dtsi and the related sm4250-oneplus-billie2.dts. Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314083633.1882214-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index a3f1c7c41fd7..fa57f4bf5825 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -225,11 +225,11 @@ status = "okay"; }; -&usb_1 { +&usb { status = "okay"; }; -&usb_1_hsphy { +&usb_hsphy { vdd-supply = <&vreg_l4a>; vdda-pll-supply = <&vreg_l12a>; vdda-phy-dpdm-supply = <&vreg_l15a>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index a9d2ff40935f..86d26a782654 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -650,7 +650,7 @@ #power-domain-cells = <1>; }; - usb_1_hsphy: phy@1613000 { + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x0 0x01613000 0x0 0x180>; #phy-cells = <0>; @@ -1089,7 +1089,7 @@ }; }; - usb_1: usb@4ef8800 { + usb: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; reg = <0x0 0x04ef8800 0x0 0x400>; #address-cells = <2>; @@ -1117,11 +1117,11 @@ qcom,select-utmi-as-pipe-clk; status = "disabled"; - usb_1_dwc3: usb@4e00000 { + usb_dwc3: usb@4e00000 { compatible = "snps,dwc3"; reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = ; - phys = <&usb_1_hsphy>; + phys = <&usb_hsphy>; phy-names = "usb2-phy"; iommus = <&apps_smmu 0x120 0x0>; snps,dis_u2_susphy_quirk; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 00b153aa1b7d..20a51e164d2a 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -273,11 +273,11 @@ status = "okay"; }; -&usb_1 { +&usb { status = "okay"; }; -&usb_1_hsphy { +&usb_hsphy { vdd-supply = <&pm6125_l4>; vdda-pll-supply = <&pm6125_l12>; vdda-phy-dpdm-supply = <&pm6125_l15>; From 1f1e512288edf0ef99d9ceb9af29e2e004341ced Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 14 Mar 2023 14:06:33 +0530 Subject: [PATCH 0395/1040] arm64: dts: qcom: sm6115: Move USB node's 'maximum-speed' and 'dr_mode' properties to dts Normally the 'maximum-speed' and 'dr_mode' properties of a USB controller + port is dependent on the type of the ports, regulators and mode change interrupt routing available on the board(s). So, move the same from the sm6115 dtsi file to respective board file(s). Reviewed-by: Konrad Dybcio Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314083633.1882214-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts | 5 +++++ arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 5 +++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index fa57f4bf5825..3f39f25e0721 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -229,6 +229,11 @@ status = "okay"; }; +&usb_dwc3 { + maximum-speed = "high-speed"; + dr_mode = "peripheral"; +}; + &usb_hsphy { vdd-supply = <&vreg_l4a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 86d26a782654..fdad0f13e064 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1129,8 +1129,6 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; - maximum-speed = "high-speed"; - dr_mode = "peripheral"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 20a51e164d2a..10c9d338446c 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -277,6 +277,11 @@ status = "okay"; }; +&usb_dwc3 { + maximum-speed = "high-speed"; + dr_mode = "peripheral"; +}; + &usb_hsphy { vdd-supply = <&pm6125_l4>; vdda-pll-supply = <&pm6125_l12>; From 27ad7815cb70cbfdcbee4368f41033e83731479f Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 14 Mar 2023 13:10:01 +0530 Subject: [PATCH 0396/1040] arm64: dts: qcom: sm6115: Move SDHC node(s)'s 'pinctrl' properties to dts Normally the 'pinctrl' properties of a SDHC controller and the chip detect pin settings are dependent on the type of the slots (for e.g uSD card slot), regulators and GPIO(s) available on the board(s). So, move the same from the sm6115 dtsi file to the respective board file(s). Reviewed-by: Marijn Suijten Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314074001.1873781-1-bhupesh.sharma@linaro.org --- .../boot/dts/qcom/sm4250-oneplus-billie2.dts | 10 +++++++++ arch/arm64/boot/dts/qcom/sm6115.dtsi | 22 ------------------- 2 files changed, 10 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts index 3f39f25e0721..a1f0622db5a0 100644 --- a/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts +++ b/arch/arm64/boot/dts/qcom/sm4250-oneplus-billie2.dts @@ -202,12 +202,22 @@ vqmmc-supply = <&vreg_l5a>; cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_state_off &sdc2_card_det_n>; status = "okay"; }; &tlmm { gpio-reserved-ranges = <14 4>; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index fdad0f13e064..840a453f1f14 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -603,13 +603,6 @@ bias-pull-up; drive-strength = <10>; }; - - sd-cd-pins { - pins = "gpio88"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; }; sdc2_state_off: sdc2-off-state { @@ -630,13 +623,6 @@ bias-pull-up; drive-strength = <2>; }; - - sd-cd-pins { - pins = "gpio88"; - function = "gpio"; - bias-disable; - drive-strength = <2>; - }; }; }; @@ -739,10 +725,6 @@ <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "iface", "core", "xo", "ice"; - pinctrl-0 = <&sdc1_state_on>; - pinctrl-1 = <&sdc1_state_off>; - pinctrl-names = "default", "sleep"; - bus-width = <8>; status = "disabled"; }; @@ -761,10 +743,6 @@ <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; - pinctrl-0 = <&sdc2_state_on>; - pinctrl-1 = <&sdc2_state_off>; - pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd SM6115_VDDCX>; operating-points-v2 = <&sdhc2_opp_table>; iommus = <&apps_smmu 0x00a0 0x0>; From 19f969c0c7388a729ec209ff74590c65a1957aab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Leonard=20G=C3=B6hrs?= Date: Fri, 10 Mar 2023 10:26:50 +0100 Subject: [PATCH 0397/1040] ARM: dts: stm32: Add coprocessor detach mbox on stm32mp15xx-osd32 SoM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To support the detach feature, add a new mailbox channel to inform the remote processor on a detach. This signal allows the remote processor firmware to stop IPC communication and to reinitialize the resources for a re-attach. See 6257dfc1c412dcdbd76ca5fa92c8444222dbe5b0 for a patch that does the same for stm32mp15x-dkx boards. Signed-off-by: Leonard Göhrs Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 935b7084b5a2..a43965c86fe8 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -210,8 +210,8 @@ &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; From 6974371cab1c488a53960945cb139b20ebb5f16b Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 20 Mar 2023 10:19:34 +0530 Subject: [PATCH 0398/1040] arm64: dts: ti: k3-am625: Correct L2 cache size to 512KB Per AM62x SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am625 Page 1. Fixes: f1d17330a5be ("arm64: dts: ti: Introduce base support for AM62x SoC") Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index acc7f8ab6426..4193c2b3eed6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -148,7 +148,7 @@ compatible = "cache"; cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; }; From 438b8dc949bf45979c32553e96086ff1c6e2504e Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 20 Mar 2023 10:19:35 +0530 Subject: [PATCH 0399/1040] arm64: dts: ti: k3-am62a7: Correct L2 cache size to 512KB Per AM62Ax SoC datasheet[0] L2 cache is 512KB. [0] https://www.ti.com/lit/gpn/am62a7 Page 1. Fixes: 5fc6b1b62639 ("arm64: dts: ti: Introduce AM62A7 family of SoCs") Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230320044935.2512288-2-vigneshr@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index 9734549851c0..58f1c43edcf8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -97,7 +97,7 @@ compatible = "cache"; cache-unified; cache-level = <2>; - cache-size = <0x40000>; + cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; }; From 22733814631983a8bed09658648f8ffc20b99f69 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 7 Mar 2023 12:09:42 -0600 Subject: [PATCH 0400/1040] arm64: dts: ti: k3-j721e-sk: Remove firmware-name override for R5F The firmware name for this core should stay as the default name "j7-main-r5f0_0-fw". This is expected to by a symlink to the actual firmware file. If one wants to use a different firmware they should change where the symlink points. This is usually achieved with an update-alternative or other distro specific selection mechanisms. The actual selection is policy and does not belong in DT. Remove this name override. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230307180942.2719-1-afd@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 4640d280c85c..f650a7fd66b4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -687,10 +687,6 @@ status = "disabled"; }; -&main_r5fss0_core0{ - firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f"; -}; - &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; From c680fa2a09a9550284546d2deeb31640ec3b56c8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 15 Mar 2023 10:52:26 -0500 Subject: [PATCH 0401/1040] dt-bindings: net: ti: k3-am654-cpsw-nuss: Drop pinmux header Drop the pinmux header reference as it is not used. Examples should just show the node definition. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230315155228.1566883-2-nm@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml index 900063411a20..837d6db299c4 100644 --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml @@ -222,7 +222,6 @@ additionalProperties: false examples: - | - #include #include #include #include From fe49f2d776f7994dc60dd04712a437fd0bdc67a0 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 15 Mar 2023 10:52:27 -0500 Subject: [PATCH 0402/1040] arm64: dts: ti: Use local header for pinctrl register values The DTS uses hardware register values directly in pin controller pin configuration and not an abstraction of any form. These definitions were previously put in the bindings header to avoid code duplication and to provide some context meaning (name), but they do not fit the purpose of bindings. Store the constants in a header next to DTS and use them instead of bindings. Suggested-by: Krzysztof Kozlowski Suggested-by: Linus Walleij Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Link: https://lore.kernel.org/all/c4d53e9c-dac0-8ccc-dc86-faada324beba@linaro.org/ Link: https://lore.kernel.org/r/20230315155228.1566883-3-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-am62a.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-am64.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-am65.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 3 +- arch/arm64/boot/dts/ti/k3-pinctrl.h | 53 +++++++++++++++++++++++++++ 9 files changed, 69 insertions(+), 8 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-pinctrl.h diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index 37fcbe7a3c33..a401f5225243 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM625 SoC"; compatible = "ti,am625"; diff --git a/arch/arm64/boot/dts/ti/k3-am62a.dtsi b/arch/arm64/boot/dts/ti/k3-am62a.dtsi index 6eb87c3f9f3c..fe60c9ce21e3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM62A SoC"; compatible = "ti,am62a7"; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index c858725133af..60fe95b48312 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM642 SoC"; compatible = "ti,am642"; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index c538a0bf3cdd..3093ef6b9b23 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -8,9 +8,10 @@ #include #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 AM654 SoC"; compatible = "ti,am654"; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index d74f86b0f622..bbe380c72a7e 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -7,9 +7,10 @@ #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J7200 SoC"; compatible = "ti,j7200"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 6975cae644d9..4c7d5f9d61a8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -7,9 +7,10 @@ #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J721E SoC"; compatible = "ti,j721e"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index 78295ee0fee5..376924726f1f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -10,9 +10,10 @@ #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J721S2 SoC"; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 3eb0d0568959..2e03d84da7d2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -10,9 +10,10 @@ #include #include -#include #include +#include "k3-pinctrl.h" + / { model = "Texas Instruments K3 J784S4 SoC"; compatible = "ti,j784s4"; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h new file mode 100644 index 000000000000..c97548a3f42d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for pinctrl bindings for TI's K3 SoC + * family. + * + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ +#ifndef DTS_ARM64_TI_K3_PINCTRL_H +#define DTS_ARM64_TI_K3_PINCTRL_H + +#define PULLUDEN_SHIFT (16) +#define PULLTYPESEL_SHIFT (17) +#define RXACTIVE_SHIFT (18) + +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) + +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) + +#define INPUT_EN (1 << RXACTIVE_SHIFT) +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) + +/* Only these macros are expected be used directly in device tree files */ +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) + +#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + +#endif From f2de003e1426ccbefa281a066040da7699f6d461 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 15 Mar 2023 10:52:28 -0500 Subject: [PATCH 0403/1040] dt-bindings: pinctrl: k3: Deprecate header with register constants For convenience (less code duplication), the pin controller pin configuration register values were defined in the bindings header. These are not some IDs or other abstraction layer but raw numbers used in the registers. These constants do not fit the purpose of bindings. They do not provide any abstraction, any hardware and driver independent ID. In fact, the Linux pinctrl-single driver actually do not use the bindings header at all. All of the constants were moved already to headers local to DTS (residing in DTS directory), so remove any references to the bindings header and add a warning that it is deprecated. Suggested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Acked-by: Linus Walleij Link: https://lore.kernel.org/linux-arm-kernel/71c7feff-4189-f12f-7353-bce41a61119d@linaro.org/ Link: https://lore.kernel.org/r/20230315155228.1566883-4-nm@ti.com Signed-off-by: Nishanth Menon --- include/dt-bindings/pinctrl/k3.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index 6bb9df1a264d..b5aca149664e 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -8,6 +8,13 @@ #ifndef _DT_BINDINGS_PINCTRL_TI_K3_H #define _DT_BINDINGS_PINCTRL_TI_K3_H +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure register values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead, use the header in the DTS source directory." + #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) From 00e34c94987e4fe866f12ad8eac17268c936880c Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Tue, 14 Mar 2023 14:25:00 +0530 Subject: [PATCH 0404/1040] soc: ti: k3-socinfo: Add entry for J784S4 SOC J784S4 SoC's JTAG ID is 0xBB80. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20230314085500.10597-1-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/k3-socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index d15764e19d96..ad97e08a25f6 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -43,6 +43,7 @@ static const struct k3_soc_id { { 0xBB38, "AM64X" }, { 0xBB75, "J721S2"}, { 0xBB7E, "AM62X" }, + { 0xBB80, "J784S4" }, { 0xBB8D, "AM62AX" }, }; From a43f0ac3851833302174567dadd60f58e24d0f30 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 14 Mar 2023 20:56:11 +0530 Subject: [PATCH 0405/1040] arm64: dts: ti: k3-j784s4-main: Enable crypto accelerator Add the node for SA2UL to support hardware crypto algorithms, including SHA-1/256/512, AES, 3DES and AEAD suites. Add rng node for hardware random number generator. Signed-off-by: Jayesh Choudhary Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230314152611.140969-3-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 80a1b08c51a8..8c1474a7bd0f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -72,6 +72,25 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_crypto: crypto@4e00000 { + compatible = "ti,j721e-sa2ul"; + reg = <0x00 0x4e00000 0x00 0x1200>; + power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; + + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, + <&main_udmap 0x4a41>; + dma-names = "tx", "rx1", "rx2"; + + rng: rng@4e10000 { + compatible = "inside-secure,safexcel-eip76"; + reg = <0x00 0x4e10000 0x00 0x7d>; + interrupts = ; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; From 4beba5cf9ecc099d59e6fe8a03254cd995b80123 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Thu, 16 Mar 2023 15:21:45 +0530 Subject: [PATCH 0406/1040] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support for ADC nodes J721s2 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by: Bhavya Kapoor Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230316095146.498999-2-b-kapoor@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 0af242aa9816..5da5f0cf7009 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -306,4 +306,44 @@ ti,cpts-periodic-outputs = <2>; }; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40210000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; }; From 0c51ceeebf04c388c06e29a2bb69855cd97f7c91 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 20 Mar 2023 11:51:22 -0500 Subject: [PATCH 0407/1040] arm64: dts: ti: k3-am62-wakeup: Introduce RTC node Introduce digital RTC node in wakeup domain. Even though this has no specific battery backup supply, this on-chip RTC is used in cost-optimized board designs as a wakeup source. Reviewed-by: Dhruva Gole Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230320165123.80561-2-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 38dced6b4fef..fec81546fbbd 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -40,4 +40,14 @@ clock-names = "fck"; status = "disabled"; }; + + wkup_rtc0: rtc@2b1f0000 { + compatible = "ti,am62-rtc"; + reg = <0x00 0x2b1f0000 0x00 0x100>; + interrupts = ; + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; + clock-names = "vbus", "osc32k"; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + wakeup-source; + }; }; From 4eec5d77d330638dc8e79e25992420a78f2a3019 Mon Sep 17 00:00:00 2001 From: Julien Panis Date: Mon, 20 Mar 2023 11:51:23 -0500 Subject: [PATCH 0408/1040] arm64: dts: ti: k3-am62: Add watchdog nodes Add nodes for watchdogs : - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Julien Panis Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230320165123.80561-3-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 45 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 11 ++++++ arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 11 ++++++ 3 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index a143ea5e78a5..16e14863d7df 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -758,6 +758,51 @@ status = "disabled"; }; + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti15: watchdog@e0f0000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e0f0000 0x00 0x100>; + clocks = <&k3_clks 130 0>; + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 130 0>; + assigned-clock-parents = <&k3_clks 130 2>; + }; + epwm0: pwm@23000000 { compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index a427231527c3..076601a41e84 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -130,4 +130,15 @@ clocks = <&k3_clks 79 0>; clock-names = "gpio"; }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index fec81546fbbd..7726ebae2539 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -50,4 +50,15 @@ power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; wakeup-source; }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; }; From cf2aacfe5f48b8c91d148dd7a3d3814b8ae04463 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Thu, 16 Mar 2023 15:21:46 +0530 Subject: [PATCH 0409/1040] arm64: dts: ti: k3-j721s2-common-proc-board: Add pinmux information for ADC J721s2 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by: Bhavya Kapoor Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230316095146.498999-3-b-kapoor@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j721s2-common-proc-board.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a7aa6cf08acd..b4b9edfe2d12 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -197,6 +197,32 @@ J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ + J721S2_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ + J721S2_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ + J721S2_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ + J721S2_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ + J721S2_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ + J721S2_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ + J721S2_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ + J721S2_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ + J721S2_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ + J721S2_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ + J721S2_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ + J721S2_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ + J721S2_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ + J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ + >; + }; }; &main_gpio2 { @@ -309,3 +335,21 @@ pinctrl-0 = <&mcu_mcan1_pins_default>; phys = <&transceiver2>; }; + +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; From 6cd4b7cfbcca4a45f06a8031f299c4019221a4ce Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 15 Mar 2023 09:55:48 +0530 Subject: [PATCH 0410/1040] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G Add device tree support to enable MCU CPSW with J784S4 EVM. Signed-off-by: Siddharth Vadapalli Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230315042548.1500528-1-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 8cd4a7ecc121..476ad8915c5b 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -140,6 +140,32 @@ }; }; +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; @@ -194,3 +220,27 @@ &main_gpio0 { status = "okay"; }; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +}; From a2ff7f1108f6eeaa73a60378ed891b634a3bba61 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 15 Mar 2023 11:53:04 +0530 Subject: [PATCH 0411/1040] arm64: dts: ti: k3-j721e: Add CPSW9G nodes TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230315062307.1612220-2-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 116 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + 2 files changed, 117 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index bfa296dce3a3..42eb6ed4b195 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -61,6 +61,13 @@ , ; }; + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports = <2>, <2>; + reg = <0x4044 0x20>; + #phy-cells = <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -404,6 +411,115 @@ }; }; + cpsw0: ethernet@c000000 { + compatible = "ti,j721e-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x0 0xc000000 0x0 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; + clocks = <&k3_clks 19 89>; + clock-names = "fck"; + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + cpsw0_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + status = "disabled"; + }; + + cpsw0_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + status = "disabled"; + }; + + cpsw0_port3: port@3 { + reg = <3>; + ti,mac-only; + label = "port3"; + status = "disabled"; + }; + + cpsw0_port4: port@4 { + reg = <4>; + ti,mac-only; + label = "port4"; + status = "disabled"; + }; + + cpsw0_port5: port@5 { + reg = <5>; + ti,mac-only; + label = "port5"; + status = "disabled"; + }; + + cpsw0_port6: port@6 { + reg = <6>; + ti,mac-only; + label = "port6"; + status = "disabled"; + }; + + cpsw0_port7: port@7 { + reg = <7>; + ti,mac-only; + label = "port7"; + status = "disabled"; + }; + + cpsw0_port8: port@8 { + reg = <8>; + ti,mac-only; + label = "port8"; + status = "disabled"; + }; + }; + + cpsw9g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x0 0xf00 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 19 89>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x0 0x3d000 0x0 0x400>; + clocks = <&k3_clks 19 16>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x0 0x4e00000 0x0 0x1200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 4c7d5f9d61a8..b912143b6a11 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -136,6 +136,7 @@ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ + <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ From 86e7de8bf908a03ac8fba4afeef25c54a1c2ef4a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 15 Mar 2023 11:53:05 +0530 Subject: [PATCH 0412/1040] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230315062307.1612220-3-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 3 +- .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 133 ++++++++++++++++++ 2 files changed, 135 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 6acd12409d59..7ded6dacd3f2 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -31,8 +31,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb # Boards with J721e SoC +k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb -dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb # Boards with J721s2 SoC diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso new file mode 100644 index 000000000000..6ff7b6ad33ed --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J721E board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw9g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw9g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw9g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@17 { + reg = <17>; + }; + cpsw9g_phy1: ethernet-phy@16 { + reg = <16>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "qsgmii-pwrdn-line"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz0 { + status = "okay"; +}; + +&serdes0 { + status = "okay"; + + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>; + assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>; + #address-cells = <1>; + #size-cells = <0>; + + serdes0_qsgmii_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 2>; + }; +}; From d3bac98015da55866891054a2aeb42af7904fca8 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 15 Mar 2023 11:53:06 +0530 Subject: [PATCH 0413/1040] arm64: dts: ti: j7200-main: Add CPSW5G nodes TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external ports and 1 host port, referred to as CPSW5G. Add device-tree nodes for CPSW5G and disable it by default. Device-tree overlays will be used to enable it. Signed-off-by: Siddharth Vadapalli Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230315062307.1612220-4-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 +++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 138381f43ce4..abad0cb441ad 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -39,6 +39,13 @@ <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ }; + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; + ti,qsgmii-main-ports = <1>; + reg = <0x4044 0x10>; + #phy-cells = <1>; + }; + usb_serdes_mux: mux-controller@4000 { compatible = "mmio-mux"; #mux-control-cells = <1>; @@ -304,6 +311,87 @@ }; }; + cpsw0: ethernet@c000000 { + compatible = "ti,j7200-cpswxg-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0xc000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + cpsw0_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + status = "disabled"; + }; + + cpsw0_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + status = "disabled"; + }; + + cpsw0_port3: port@3 { + reg = <3>; + ti,mac-only; + label = "port3"; + status = "disabled"; + }; + + cpsw0_port4: port@4 { + reg = <4>; + ti,mac-only; + label = "port4"; + status = "disabled"; + }; + }; + + cpsw5g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 19 33>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 19 16>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ From 496cdc82e05f5683cdca5ab157938091e7744c95 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 15 Mar 2023 11:53:07 +0530 Subject: [PATCH 0414/1040] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230315062307.1612220-5-s-vadapalli@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 3 +- .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 101 ++++++++++++++++++ 2 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 7ded6dacd3f2..5312e4adc4e3 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -28,7 +28,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb # Boards with J7200 SoC -dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb +k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb # Boards with J721e SoC k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso new file mode 100644 index 000000000000..31b932eebc0a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J7200 board. + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw5g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw5g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw5g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw5g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw5g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw5g_phy0: ethernet-phy@16 { + reg = <16>; + }; + cpsw5g_phy1: ethernet-phy@17 { + reg = <17>; + }; + cpsw5g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw5g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "qsgmii-pwrdn-line"; + }; +}; + +&main_pmx0 { + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ + J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ + >; + }; +}; From 3cd557272ef0b1bbad3c5450f09629e451e101f3 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Thu, 16 Mar 2023 10:21:41 -0500 Subject: [PATCH 0415/1040] dt-bindings: arm: ti: Add BeaglePlay This board is based on ti,am625 https://beagleplay.org/ https://git.beagleboard.org/beagleplay/beagleplay Signed-off-by: Robert Nelson Reviewed-by: Dhruva Gole Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230316152143.2438928-2-nm@ti.com Co-developed-by: Nishanth Menon Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index a60a4065caa8..b4703ac88f04 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -28,6 +28,7 @@ properties: - description: K3 AM625 SoC items: - enum: + - beagle,am625-beagleplay - ti,am625-sk - const: ti,am625 From 1c894486fc638b1aafabe78cd38441518e7cdb00 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 20 Mar 2023 17:17:07 +0200 Subject: [PATCH 0416/1040] arm64: defconfig: Enable QCOM eUSB2 SNPS PHY and repeater In order to have USB 2.0 working on Qualcomm SM8550, both the eUSB2 PHY and the eUSB2 repeater need to be built as modules. So select them accordingly. Signed-off-by: Abel Vesa Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230320151707.1842171-1-abel.vesa@linaro.org --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4a8b3f5e07be..d3a23b30776c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1305,9 +1305,11 @@ CONFIG_PHY_HISI_INNO_USB2=y CONFIG_PHY_MVEBU_CP110_COMPHY=y CONFIG_PHY_MTK_TPHY=y CONFIG_PHY_QCOM_EDP=m +CONFIG_PHY_QCOM_EUSB2_REPEATER=m CONFIG_PHY_QCOM_PCIE2=m CONFIG_PHY_QCOM_QMP=m CONFIG_PHY_QCOM_QUSB2=m +CONFIG_PHY_QCOM_SNPS_EUSB2=m CONFIG_PHY_QCOM_USB_HS=m CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=m CONFIG_PHY_QCOM_USB_HS_28NM=m From 8f680c287445c467c927e875103ad2bfd7d356e1 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Fri, 17 Feb 2023 19:42:38 +0100 Subject: [PATCH 0417/1040] arm64: defconfig: Switch msm8996 clk drivers to module Switch to module, because there is a support for probe defer on the power-domains. This should be working since 2b28a1a84a0e ("driver core: Extend deferred probe timeout on driver registration") Suggested-by: Bjorn Andersson Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217184239.21450-2-pvorel@suse.cz --- arch/arm64/configs/defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d3a23b30776c..d6d432c12228 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1128,7 +1128,7 @@ CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y -CONFIG_MSM_MMCC_8996=y +CONFIG_MSM_MMCC_8996=m CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y CONFIG_SA_GCC_8775P=y From 4705d0137af61823dca83bb6302073181d83945d Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Fri, 17 Feb 2023 19:42:39 +0100 Subject: [PATCH 0418/1040] arm64: defconfig: Enable qcom msm899{4,8} clk drivers Enable the rest of qcom clk drivers on arm64, enabling as module, because there is a support for probe defer on the power-domains. Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217184239.21450-3-pvorel@suse.cz --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d6d432c12228..d25538b591d6 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1128,7 +1128,9 @@ CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y +CONFIG_MSM_MMCC_8994=m CONFIG_MSM_MMCC_8996=m +CONFIG_MSM_MMCC_8998=m CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y CONFIG_SA_GCC_8775P=y From c9ab590f54c75c6c6b6016bdfe9ffb3ac40a7ad2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 Mar 2023 16:57:33 +0100 Subject: [PATCH 0419/1040] arm64: defconfig: enable Qualcomm pin controller drivers Enable pin controller drivers for several Qualcomm SoCs, as they are necessary for basic system functionality: - main Top Level Mode Multiplexer as built-in for QDU1000, SDM660, SDM670, SM6125, SM6350 and SM6375. - Low Power Audio (LPASS) TLMM as module for SC7280, SC8280XP, SM8450 and SM8550. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309155733.662043-1-krzysztof.kozlowski@linaro.org --- arch/arm64/configs/defconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d25538b591d6..bf5962ca67ea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -557,19 +557,29 @@ CONFIG_PINCTRL_QCM2290=y CONFIG_PINCTRL_QCS404=y CONFIG_PINCTRL_QDF2XXX=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_QDU1000=y CONFIG_PINCTRL_SA8775P=y CONFIG_PINCTRL_SC7180=y CONFIG_PINCTRL_SC7280=y +CONFIG_PINCTRL_SC7280_LPASS_LPI=m CONFIG_PINCTRL_SC8180X=y CONFIG_PINCTRL_SC8280XP=y +CONFIG_PINCTRL_SDM660=y +CONFIG_PINCTRL_SDM670=y CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM6115=y +CONFIG_PINCTRL_SM6125=y +CONFIG_PINCTRL_SM6350=y +CONFIG_PINCTRL_SM6375=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SM8250=y CONFIG_PINCTRL_SM8250_LPASS_LPI=m CONFIG_PINCTRL_SM8350=y CONFIG_PINCTRL_SM8450=y +CONFIG_PINCTRL_SM8450_LPASS_LPI=m +CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m CONFIG_PINCTRL_SM8550=y +CONFIG_PINCTRL_SM8550_LPASS_LPI=m CONFIG_PINCTRL_LPASS_LPI=m CONFIG_GPIO_ALTERA=m CONFIG_GPIO_DAVINCI=y From 14bc45c4e72da1a80311cd82815867f36599f698 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:42 +0100 Subject: [PATCH 0420/1040] dt-bindings: soc: qcom: qcom,pmic-glink: document SM8450 compatible Document the SM8450 compatible used to describe the pmic glink on this platform. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-2-552f3b721f9e@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index cf863683c21a..a85bc14de065 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -25,6 +25,7 @@ properties: - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink + - qcom,sm8450-pmic-glink - const: qcom,pmic-glink '#address-cells': From 84a334131f091d83239f54cc40627d9b28324b45 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:43 +0100 Subject: [PATCH 0421/1040] dt-bindings: soc: qcom: qcom,pmic-glink: document SM8550 compatible Document the SM8550 compatible used to describe the pmic glink on this platform. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-3-552f3b721f9e@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index a85bc14de065..6440dc801387 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -26,6 +26,7 @@ properties: - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink - qcom,sm8450-pmic-glink + - qcom,sm8550-pmic-glink - const: qcom,pmic-glink '#address-cells': From ff642773b6b5b801f2f3bbdabe22c3d02656981e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:44 +0100 Subject: [PATCH 0422/1040] soc: qcom: pmic_glink: register ucsi aux device Only register UCSI on know working devices, like on the SM8450 or SM8550 which requires UCSI to get USB mode switch events. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-4-552f3b721f9e@linaro.org --- drivers/soc/qcom/pmic_glink.c | 65 +++++++++++++++++++++++++++++------ 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index bb3fb57abcc6..8bf95df0a56a 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -4,6 +4,7 @@ * Copyright (c) 2022, Linaro Ltd */ #include +#include #include #include #include @@ -11,12 +12,23 @@ #include #include +enum { + PMIC_GLINK_CLIENT_BATT = 0, + PMIC_GLINK_CLIENT_ALTMODE, + PMIC_GLINK_CLIENT_UCSI, +}; + +#define PMIC_GLINK_CLIENT_DEFAULT (BIT(PMIC_GLINK_CLIENT_BATT) | \ + BIT(PMIC_GLINK_CLIENT_ALTMODE)) + struct pmic_glink { struct device *dev; struct pdr_handle *pdr; struct rpmsg_endpoint *ept; + unsigned long client_mask; + struct auxiliary_device altmode_aux; struct auxiliary_device ps_aux; struct auxiliary_device ucsi_aux; @@ -233,6 +245,7 @@ static struct rpmsg_driver pmic_glink_rpmsg_driver = { static int pmic_glink_probe(struct platform_device *pdev) { + const unsigned long *match_data; struct pdr_service *service; struct pmic_glink *pg; int ret; @@ -249,12 +262,27 @@ static int pmic_glink_probe(struct platform_device *pdev) mutex_init(&pg->client_lock); mutex_init(&pg->state_lock); - ret = pmic_glink_add_aux_device(pg, &pg->altmode_aux, "altmode"); - if (ret) - return ret; - ret = pmic_glink_add_aux_device(pg, &pg->ps_aux, "power-supply"); - if (ret) - goto out_release_altmode_aux; + match_data = (unsigned long *)of_device_get_match_data(&pdev->dev); + if (match_data) + pg->client_mask = *match_data; + else + pg->client_mask = PMIC_GLINK_CLIENT_DEFAULT; + + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) { + ret = pmic_glink_add_aux_device(pg, &pg->ucsi_aux, "ucsi"); + if (ret) + return ret; + } + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) { + ret = pmic_glink_add_aux_device(pg, &pg->altmode_aux, "altmode"); + if (ret) + goto out_release_ucsi_aux; + } + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) { + ret = pmic_glink_add_aux_device(pg, &pg->ps_aux, "power-supply"); + if (ret) + goto out_release_altmode_aux; + } pg->pdr = pdr_handle_alloc(pmic_glink_pdr_callback, pg); if (IS_ERR(pg->pdr)) { @@ -278,9 +306,14 @@ static int pmic_glink_probe(struct platform_device *pdev) out_release_pdr_handle: pdr_handle_release(pg->pdr); out_release_aux_devices: - pmic_glink_del_aux_device(pg, &pg->ps_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) + pmic_glink_del_aux_device(pg, &pg->ps_aux); out_release_altmode_aux: - pmic_glink_del_aux_device(pg, &pg->altmode_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) + pmic_glink_del_aux_device(pg, &pg->altmode_aux); +out_release_ucsi_aux: + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) + pmic_glink_del_aux_device(pg, &pg->ucsi_aux); return ret; } @@ -291,8 +324,12 @@ static int pmic_glink_remove(struct platform_device *pdev) pdr_handle_release(pg->pdr); - pmic_glink_del_aux_device(pg, &pg->ps_aux); - pmic_glink_del_aux_device(pg, &pg->altmode_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_BATT)) + pmic_glink_del_aux_device(pg, &pg->ps_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_ALTMODE)) + pmic_glink_del_aux_device(pg, &pg->altmode_aux); + if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI)) + pmic_glink_del_aux_device(pg, &pg->ucsi_aux); mutex_lock(&__pmic_glink_lock); __pmic_glink = NULL; @@ -301,8 +338,14 @@ static int pmic_glink_remove(struct platform_device *pdev) return 0; } +/* Do not handle altmode for now on those platforms */ +static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | + BIT(PMIC_GLINK_CLIENT_UCSI); + static const struct of_device_id pmic_glink_of_match[] = { - { .compatible = "qcom,pmic-glink", }, + { .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, + { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, + { .compatible = "qcom,pmic-glink" }, {} }; MODULE_DEVICE_TABLE(of, pmic_glink_of_match); From 75b81e5a49f897ef1a2f95182216850a53664aa3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:46 +0100 Subject: [PATCH 0423/1040] arm64: dts: qcom: sm8350: add port subnodes in dwc3 node Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-6-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 2f27b9da96af..77c2fdeaab4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2272,6 +2272,25 @@ snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; From f28d912671c87ffa30e223fc32c9145a8b5135cd Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:47 +0100 Subject: [PATCH 0424/1040] arm64: dts: qcom: sm8450: add port subnodes in dwc3 node Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-7-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f1f2ce33a1e0..d67e72cdd897 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4172,6 +4172,25 @@ snps,dis_enblslpm_quirk; phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; From 34e7e432f17ce1df90a044c815ec753bc70f7c6c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:48 +0100 Subject: [PATCH 0425/1040] arm64: dts: qcom: sm8550: add port subnodes in dwc3 node Add ports subnodes in dwc3 node to avoid repeating the same description in each board DT. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-8-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 8789ea42d6eb..9c135417cd54 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2461,6 +2461,25 @@ phys = <&usb_1_hsphy>, <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; }; }; From a891ec9e4f3adf62068695a48b769b30b22591e2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:49 +0100 Subject: [PATCH 0426/1040] arm64: dts: qcom: sm8350-hdk: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-9-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 46 +++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 09baf6959c71..a10bf7c8764f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -31,6 +31,40 @@ }; }; + pmic-glink { + compatible = "qcom,sm8350-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -674,8 +708,16 @@ }; &usb_1_dwc3 { - /* TODO: Define USB-C connector properly */ - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { From 2ca9703147ca7e347e300fb23f699f1065302b0b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:50 +0100 Subject: [PATCH 0427/1040] arm64: dts: qcom: sm8450-hdk: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-10-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 45 ++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index feef3837e4cd..1755ee3aa04c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -87,6 +87,40 @@ enable-active-high; }; + pmic-glink { + compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -724,7 +758,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { From 0dbb756c9120eb46aa1ec4fa47b6da0f6d21374f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:51 +0100 Subject: [PATCH 0428/1040] arm64: dts: qcom: sm8550-mtp: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-11-552f3b721f9e@linaro.org --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 45 ++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 9d4ddb883a70..e2b9bb6b1e27 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -27,6 +27,40 @@ stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -561,7 +595,16 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { From 4ffd0b0019560a52b46b9ebd8127be3fdc157f16 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 21 Mar 2023 14:21:52 +0100 Subject: [PATCH 0429/1040] arm64: defconfig: add PMIC GLINK modules Enable the PMIC GLINK core, altmode, battery and UCSI aux drivers as module to enable USB Type-C management over the PMIC GLINK protocol on modern Qcom platforms. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v5-12-552f3b721f9e@linaro.org --- arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bf5962ca67ea..2d9325a2163d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -273,6 +273,10 @@ CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_NVME=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_FASTRPC=m +CONFIG_BATTERY_QCOM_BATTMGR=m +CONFIG_QCOM_PMIC_GLINK=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_PMIC_GLINK=m CONFIG_SRAM=y CONFIG_PCI_ENDPOINT_TEST=m CONFIG_EEPROM_AT24=m From b767d1b40cbca49452d712ca0f4f053dacfc5c45 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 22 Mar 2023 00:31:14 +0530 Subject: [PATCH 0430/1040] arm64: dts: qcom: sdm845: Fix the BAM DMA engine compatible string As per documentation, Qualcomm SDM845 SoC supports BAM DMA engine v1.7.4, so use the correct compatible strings. Signed-off-by: Bhupesh Sharma Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230321190118.3327360-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 0fdd59a9feed..e8e9aa4da914 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2628,7 +2628,7 @@ }; cryptobam: dma-controller@1dc4000 { - compatible = "qcom,bam-v1.7.0"; + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = ; clocks = <&rpmhcc RPMH_CE_CLK>; From 4f278f71c79f174c027d07f57837d1ca41b2df37 Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Tue, 21 Mar 2023 21:23:19 +0300 Subject: [PATCH 0431/1040] arm64: dts: qcom: pm8150l: add spmi-flash-led node Add a node describing the flash block found on pm8150l. Signed-off-by: Danila Tikhonov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230321182319.24958-1-danila@jiaxyga.com --- arch/arm64/boot/dts/qcom/pm8150l.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 135bfb8d629b..cca45fad75ac 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -116,6 +116,12 @@ #address-cells = <1>; #size-cells = <0>; + pm8150l_flash: led-controller@d300 { + compatible = "qcom,pm8150l-flash-led", "qcom,spmi-flash-led"; + reg = <0xd300>; + status = "disabled"; + }; + pm8150l_lpg: pwm { compatible = "qcom,pm8150l-lpg"; From dc3ad22112de7fe76352ef2aa2943b62eb1836a3 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:44 +0100 Subject: [PATCH 0432/1040] arm64: dts: qcom: sa8775p: add the QUPv3 #2 node Add the second instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index dc21e8450058..9fbddd980f60 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -499,6 +499,19 @@ }; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x6000>; + ranges; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0x5a3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ From 4926a8e93f321760fa265f91d78aa2a2163e222b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:45 +0100 Subject: [PATCH 0433/1040] arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2 Enable the second instance of the QUPv3 engine on the sa8775p-ride board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 3adf7349f4e5..a538bb79c04a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -24,6 +24,10 @@ status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; From a23d122572a4ad1292e60d4a87e6f0238aaa0505 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:46 +0100 Subject: [PATCH 0434/1040] arm64: dts: qcom: sa8775p: add the i2c18 node Add a disabled node for the I2C interface that's exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-4-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9fbddd980f60..3f935b37ccd1 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2023, Linaro Limited */ +#include #include #include #include @@ -510,6 +511,27 @@ #address-cells = <2>; #size-cells = <2>; status = "disabled"; + + i2c18: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; intc: interrupt-controller@17a00000 { From 12f35f74ad6da53d94fcbc1bbb2adff60b31a71f Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:47 +0100 Subject: [PATCH 0435/1040] arm64: dts: qcom: sa8775p-ride: enable i2c18 This enables the I2C interface on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-5-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index a538bb79c04a..5fdce8279537 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -13,6 +13,7 @@ aliases { serial0 = &uart10; + i2c18 = &i2c18; }; chosen { @@ -20,6 +21,13 @@ }; }; +&i2c18 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c18_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; @@ -37,6 +45,13 @@ pins = "gpio46", "gpio47"; function = "qup1_se3"; }; + + qup_i2c18_default: qup-i2c18-state { + pins = "gpio95", "gpio96"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart10 { From cfd975f588400e0942d55dc4bb84c12c6f217fb4 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:48 +0100 Subject: [PATCH 0436/1040] arm64: dts: qcom: sa8775p: add the spi16 node Add the SPI controller node for the interface exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-6-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 3f935b37ccd1..0be5a469c8ea 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -512,6 +512,27 @@ #size-cells = <2>; status = "disabled"; + spi16: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x00890000 0x0 0x4000>; From a3b31b0e0f76326bfa4bc81577f52738ad8e072b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:49 +0100 Subject: [PATCH 0437/1040] arm64: dts: qcom: sa8775p-ride: enable the SPI node Enable the SPI interface exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-7-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 5fdce8279537..d01ca3a9ee37 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart10; i2c18 = &i2c18; + spi16 = &spi16; }; chosen { @@ -40,12 +41,25 @@ clock-frequency = <32764>; }; +&spi16 { + pinctrl-0 = <&qup_spi16_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &tlmm { qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3"; }; + qup_spi16_default: qup-spi16-state { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; + qup_i2c18_default: qup-i2c18-state { pins = "gpio95", "gpio96"; function = "qup2_se4"; From 41ae5ca448c21a82a2f07e10954b043a0d45a811 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:50 +0100 Subject: [PATCH 0438/1040] arm64: dts: qcom: sa8775p: add high-speed UART nodes Add two UART nodes that are known to be used by existing development boards with this SoC. Signed-off-by: Bartosz Golaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-8-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 0be5a469c8ea..c5b73c591e0f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -498,6 +498,21 @@ operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; + + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_2: geniqup@8c0000 { @@ -533,6 +548,21 @@ status = "disabled"; }; + uart17: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x0088c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c18: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x00890000 0x0 0x4000>; From 4b6c4249069694a593f3b4c3d81c75a5053b7693 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:51 +0100 Subject: [PATCH 0439/1040] arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-9-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index d01ca3a9ee37..cba7c8116141 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -13,6 +13,7 @@ aliases { serial0 = &uart10; + serial1 = &uart12; i2c18 = &i2c18; spi16 = &spi16; }; @@ -66,6 +67,32 @@ drive-strength = <2>; bias-pull-up; }; + + qup_uart12_default: qup-uart12-state { + qup_uart12_cts: qup-uart12-cts-pins { + pins = "gpio52"; + function = "qup1_se5"; + bias-disable; + }; + + qup_uart12_rts: qup-uart12-rts-pins { + pins = "gpio53"; + function = "qup1_se5"; + bias-pull-down; + }; + + qup_uart12_tx: qup-uart12-tx-pins { + pins = "gpio54"; + function = "qup1_se5"; + bias-pull-up; + }; + + qup_uart12_rx: qup-uart12-rx-pins { + pins = "gpio55"; + function = "qup1_se5"; + bias-pull-down; + }; + }; }; &uart10 { @@ -75,6 +102,12 @@ status = "okay"; }; +&uart12 { + pinctrl-0 = <&qup_uart12_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; From e1988af7a646aafe8075b179c00fd8053ced2add Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 9 Mar 2023 11:37:52 +0100 Subject: [PATCH 0440/1040] arm64: dts: qcom: sa8775p-ride: enable the BT UART port Enable the high-speed UART port connected to the Bluetooth controller on the sa8775p-adp development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309103752.173541-10-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index cba7c8116141..1020dfd21da2 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -14,6 +14,7 @@ aliases { serial0 = &uart10; serial1 = &uart12; + serial2 = &uart17; i2c18 = &i2c18; spi16 = &spi16; }; @@ -93,6 +94,32 @@ bias-pull-down; }; }; + + qup_uart17_default: qup-uart17-state { + qup_uart17_cts: qup-uart17-cts-pins { + pins = "gpio91"; + function = "qup2_se3"; + bias-disable; + }; + + qup_uart17_rts: qup0-uart17-rts-pins { + pins = "gpio92"; + function = "qup2_se3"; + bias-pull-down; + }; + + qup_uart17_tx: qup0-uart17-tx-pins { + pins = "gpio93"; + function = "qup2_se3"; + bias-pull-up; + }; + + qup_uart17_rx: qup0-uart17-rx-pins { + pins = "gpio94"; + function = "qup2_se3"; + bias-pull-down; + }; + }; }; &uart10 { @@ -108,6 +135,12 @@ status = "okay"; }; +&uart17 { + pinctrl-0 = <&qup_uart17_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; }; From 613f14a3a9d7e12a832ff822f85a33ad0ebee952 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 14:03:14 +0100 Subject: [PATCH 0441/1040] arm64: dts: qcom: sm8250-xiaomi-elish: fix USB maximum speed property Fix typo in USB DWC3 node maximum speed property. Fixes: a41b617530bf ("arm64: dts: qcom: sm8250: Add device tree for Xiaomi Mi Pad 5 Pro") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304130315.51595-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts index 24fc29f0ee5e..6bd0dda8b6e9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts @@ -595,7 +595,7 @@ &usb_1_dwc3 { dr_mode = "peripheral"; - maximum-spped = "high-speed"; + maximum-speed = "high-speed"; /* Remove USB3 phy */ phys = <&usb_1_hsphy>; phy-names = "usb2-phy"; From 0beda02e530f8fc571877939645cb20ade113027 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 14:03:15 +0100 Subject: [PATCH 0442/1040] arm64: dts: qcom: sm8350-microsoft-surface: fix USB dual-role mode property The "dr_mode" is a property of USB DWC3 node, not the Qualcomm wrapper one: sm8350-microsoft-surface-duo2.dtb: usb@a6f8800: 'dr_mode' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+' Fixes: c16160cfa565 ("arm64: dts: qcom: add minimal DTS for Microsoft Surface Duo 2") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304130315.51595-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index b536ae36ae6d..3bd5e57cbcda 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -341,6 +341,9 @@ &usb_1 { status = "okay"; +}; + +&usb_1_dwc3 { dr_mode = "peripheral"; }; From 34d84c3b0f63978efcb5136a6fd2e7e9d889da70 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Mar 2023 13:24:28 +0100 Subject: [PATCH 0443/1040] dt-bindings: soc: qcom: smd-rpm: re-add missing qcom,rpm-msm8994 Re-add the qcom,rpm-msm8994 compatible, dropped during conversion from TXT to DT schema: apq8094-sony-xperia-kitakami-karin_windy.dtb: smd: rpm:rpm-requests:compatible:0: 'qcom,rpm-msm8994' is not one of ['qcom,rpm-apq8084' ...] Fixes: f935a752f229 ("dt-bindings: soc: qcom: smd-rpm: Convert binding to YAML schema") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Reviewed-by: Petr Vorel Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305122428.167580-1-krzysztof.kozlowski@linaro.org --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 2a5791ebc8dd..94765fbc868e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -41,6 +41,7 @@ properties: - qcom,rpm-msm8953 - qcom,rpm-msm8974 - qcom,rpm-msm8976 + - qcom,rpm-msm8994 - qcom,rpm-msm8996 - qcom,rpm-msm8998 - qcom,rpm-sdm660 @@ -85,6 +86,7 @@ if: - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8953 + - qcom,rpm-msm8994 then: properties: qcom,glink-channels: false From 6b056f38f07d6fe48e9c0ea9bbcf68f11c1a388b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 5 Mar 2023 16:43:08 +0100 Subject: [PATCH 0444/1040] arm64: dts: qcom: pm660: align thermal node names with bindings Bindings expect thermal node names to end with '-thermal', so fix pm660 and pm660l: sda660-inforce-ifc6560.dtb: thermal-zones: 'pm660', 'pm660l' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305154308.241651-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/pm660.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm660l.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index fc0eccaccdf6..4bc717917f44 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -11,7 +11,7 @@ / { thermal-zones { - pm660 { + pm660-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index f9b3864bd3b9..87b71b7205b8 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -11,7 +11,7 @@ / { thermal-zones { - pm660l { + pm660l-thermal { polling-delay-passive = <250>; polling-delay = <1000>; From 1e0952e7b978eb4a182c4a9c003f9313d30d00df Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 Mar 2023 23:26:26 +0300 Subject: [PATCH 0445/1040] dt-bindings: arm: msm: Add LLCC for SM7150 Add LLCC compatible for SM7150 SoC. Signed-off-by: Danila Tikhonov Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305202627.402386-2-danila@jiaxyga.com --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 93b977428a14..02cc6894eb13 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -26,6 +26,7 @@ properties: - qcom,sc8280xp-llcc - qcom,sdm845-llcc - qcom,sm6350-llcc + - qcom,sm7150-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc From 92b9d86252c1d76faf06f155c2a73b0c673bf59d Mon Sep 17 00:00:00 2001 From: Danila Tikhonov Date: Sun, 5 Mar 2023 23:26:27 +0300 Subject: [PATCH 0446/1040] soc: qcom: llcc: Add configuration data for SM7150 Add LLCC configuration data for SM7150 SoC. Signed-off-by: Danila Tikhonov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230305202627.402386-3-danila@jiaxyga.com --- drivers/soc/qcom/llcc-qcom.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index a5140f19f200..97c0908c689c 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -226,6 +226,14 @@ static const struct llcc_slice_config sm6350_data[] = { { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, }; +static const struct llcc_slice_config sm7150_data[] = { + { LLCC_CPUSS, 1, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 1 }, + { LLCC_MDM, 8, 128, 2, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPUHTW, 11, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPU, 12, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_NPU, 23, 512, 1, 0, 0xF, 0x0, 0, 0, 0, 1, 0 }, +}; + static const struct llcc_slice_config sm8150_data[] = { { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, @@ -464,6 +472,14 @@ static const struct qcom_llcc_config sm6350_cfg = { .edac_reg_offset = &llcc_v1_edac_reg_offset, }; +static const struct qcom_llcc_config sm7150_cfg = { + .sct_data = sm7150_data, + .size = ARRAY_SIZE(sm7150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, +}; + static const struct qcom_llcc_config sm8150_cfg = { .sct_data = sm8150_data, .size = ARRAY_SIZE(sm8150_data), @@ -1041,6 +1057,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, + { .compatible = "qcom,sm7150-llcc", .data = &sm7150_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, From 424a4e5273bfc16b6974faff50f0d24c1df0c76e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Mar 2023 08:26:18 +0100 Subject: [PATCH 0447/1040] ARM: dts: qcom: sdx55: add dedicated SDX55 TCSR compatible syscon should not be used alone as compatible. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306072618.10770-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 286fa92da428..9148a840b8a0 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -518,7 +518,7 @@ }; tcsr: syscon@1fcb000 { - compatible = "syscon"; + compatible = "qcom,sdx55-tcsr", "syscon"; reg = <0x01fc0000 0x1000>; }; From e225d56042e3a02aa3ee60c96da687ac3c690a37 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Mar 2023 09:14:29 +0100 Subject: [PATCH 0448/1040] arm64: dts: qcom: sdm845-db845c: drop empty node override Drop empty override of pm8998_gpios. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306081430.28491-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index acd4f9ca6c09..e14fe9bbb386 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1135,10 +1135,6 @@ bias-disable; }; -&pm8998_gpios { - -}; - /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi0_default { drive-strength = <6>; From e18b829549793f706c6c8a39f24ba93b3213fb33 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Mar 2023 09:14:30 +0100 Subject: [PATCH 0449/1040] arm64: dts: qcom: drop redundant line breaks Remove trailing, redundant line breaks. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306081430.28491-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 1 - arch/arm64/boot/dts/qcom/msm8916.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 -- arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts | 1 - arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts | 1 - arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 2 -- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm6375.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 1 - arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 --- 18 files changed, 29 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 842836ed680a..5ceaab5d4039 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -1137,7 +1137,6 @@ vdda-phy-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; - }; &venus { diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0d5283805f42..639b158b4fbe 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -2180,7 +2180,6 @@ }; }; }; - }; timer { diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 55104630a7f0..4661a556772e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1882,7 +1882,6 @@ "cfg", "bus_master", "bus_slave"; - }; pcie1: pcie@608000 { @@ -3471,7 +3470,6 @@ }; }; }; - }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 604c2aa0c276..7b0c25f31a41 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3027,7 +3027,6 @@ required-opps = <&rpmhpd_opp_nom>; }; }; - }; dsi0: dsi@ae94000 { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e35f1d5325da..e342dd073fd2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -943,7 +943,6 @@ opp-avg-kBps = <390000 0>; }; }; - }; gpi_dma0: dma-controller@900000 { @@ -3298,7 +3297,6 @@ opp-avg-kBps = <200000 0>; }; }; - }; usb_1_hsphy: phy@88e3000 { @@ -3767,7 +3765,6 @@ required-opps = <&rpmhpd_opp_turbo>; }; }; - }; videocc: clock-controller@aaf0000 { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index c22ab532cdf3..87774d43d8b2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2781,7 +2781,6 @@ drive-strength = <2>; slew-rate = <1>; bias-bus-hold; - }; }; @@ -4413,7 +4412,6 @@ required-opps = <&rpmhpd_opp_nom>; }; }; - }; mdss1_dp1: displayport-controller@22098000 { diff --git a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts index e3e61b9d1b9d..32a7bd59e1ec 100644 --- a/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts +++ b/arch/arm64/boot/dts/qcom/sdm670-google-sargo.dts @@ -395,7 +395,6 @@ regulator-enable-ramp-delay = <500>; }; }; - }; &gcc { diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 086d14e2de92..d82c0d4407f0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -45,7 +45,6 @@ "AMIC3", "MIC BIAS4", "AMIC4", "MIC BIAS1", "AMIC5", "MIC BIAS3"; - }; /* diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 4916d0db5b47..2a3ad478892b 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -233,7 +233,6 @@ regulator-allow-set-load; regulator-allowed-modes = ; - }; pm6150l_l7: ldo7 { @@ -255,7 +254,6 @@ regulator-allow-set-load; regulator-allowed-modes = ; - }; pm6150l_l10: ldo10 { diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 318fefc8f4fa..578238910f23 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -176,7 +176,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { @@ -888,7 +887,6 @@ interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; - }; config_noc: interconnect@1500000 { diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 6252a547d916..a84a19027cad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -139,7 +139,6 @@ compatible = "cache"; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 95e573890983..8e2820aa0f6e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -92,7 +92,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU2: cpu@200 { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7ccec48255f0..7b78761f2041 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -247,7 +247,6 @@ cache-unified; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { @@ -2428,7 +2427,6 @@ drive-strength = <2>; slew-rate = <1>; bias-bus-hold; - }; }; @@ -2447,7 +2445,6 @@ drive-strength = <2>; input-enable; bias-pull-down; - }; }; @@ -3022,7 +3019,6 @@ }; }; }; - }; etf@6b05000 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index a10bf7c8764f..2ee1b121686a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -678,7 +678,6 @@ bias-pull-up; }; }; - }; &uart2 { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 77c2fdeaab4e..86d887a1c3eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -155,7 +155,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 1755ee3aa04c..cc6bfe99d07d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -377,7 +377,6 @@ regulator-max-microvolt = <912000>; regulator-initial-mode = ; }; - }; regulators-3 { diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index f7592946c783..65a94dfaf5ae 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -282,7 +282,6 @@ regulator-max-microvolt = <912000>; regulator-initial-mode = ; }; - }; regulators-3 { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d67e72cdd897..357ef1d275c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -154,7 +154,6 @@ cache-level = <2>; next-level-cache = <&L3_0>; }; - }; CPU6: cpu@600 { @@ -2762,7 +2761,6 @@ remote-endpoint = <&mdss_dsi1_in>; }; }; - }; mdp_opp_table: opp-table { @@ -3569,7 +3567,6 @@ pins = "gpio76", "gpio77", "gpio78", "gpio79"; function = "qup20"; }; - }; lpass_tlmm: pinctrl@3440000 { From 80dc42d9facc9232072855340c2285682c0c3b19 Mon Sep 17 00:00:00 2001 From: Gergo Koteles Date: Mon, 6 Mar 2023 18:41:47 +0100 Subject: [PATCH 0450/1040] arm64: dts: qcom: sdm845-oneplus-common: add Hall sensor Enable the Hall effect sensor (flip cover) for OnePlus 6/6T. The GPIO is mapped to SW_LID events as in msm8916, msm8994, msm8998 devices. Signed-off-by: Gergo Koteles Reviewed-by: Caleb Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306174147.185239-1-soyer@irl.hu --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 64638ea94db7..b01542d79ae2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -29,6 +29,23 @@ stdout-path = "serial0:115200n8"; }; + gpio-hall-sensor { + compatible = "gpio-keys"; + label = "Hall effect sensor"; + + pinctrl-0 = <&hall_sensor_default>; + pinctrl-names = "default"; + + event-hall-sensor { + gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + label = "Hall Effect Sensor"; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + gpio-keys { compatible = "gpio-keys"; label = "Volume keys"; @@ -753,6 +770,14 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + hall_sensor_default: hall-sensor-default-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + tri_state_key_default: tri-state-key-default-state { pins = "gpio40", "gpio42", "gpio26"; function = "gpio"; From fb1eb0b5dcf6f214479e853ee466958190785ab4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 7 Mar 2023 02:22:47 +0100 Subject: [PATCH 0451/1040] firmware: qcom_scm: Add SM6375 compatible While it was introduced in bindings, requiring a core clock, and added into the DT, this compatible was apparently forgotten about on the driver side of things. Fix it. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307012247.3655547-1-konrad.dybcio@linaro.org --- drivers/firmware/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index ce76f5263aa3..280d6a4ac71a 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1543,6 +1543,7 @@ static const struct of_device_id qcom_scm_dt_match[] = { }, { .compatible = "qcom,scm-msm8994" }, { .compatible = "qcom,scm-msm8996" }, + { .compatible = "qcom,scm-sm6375", .data = (void *)SCM_HAS_CORE_CLK }, { .compatible = "qcom,scm" }, {} }; From e4c17be956fbe133211c24b9fc9ba253ffc44db6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:01 +0100 Subject: [PATCH 0452/1040] arm64: dts: qcom: sc7180: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-4-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 7b0c25f31a41..3c799b564b64 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3576,7 +3576,7 @@ }; cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; From 236e7dd568ed4b839fb8abdf3ce7c77444e610e2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:02 +0100 Subject: [PATCH 0453/1040] arm64: dts: qcom: sdm845: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-5-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e8e9aa4da914..2f32179c7d1b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -5232,7 +5232,7 @@ }; cpufreq_hw: cpufreq@17d43000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; From f33f95773e148cd0adbfc3135f2bfbf56a69f488 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:03 +0100 Subject: [PATCH 0454/1040] arm64: dts: qcom: sm6115: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-6-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 840a453f1f14..30d53b812987 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -2282,7 +2282,7 @@ }; cpufreq_hw: cpufreq@f521000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0x0 0x0f521000 0x0 0x1000>, <0x0 0x0f523000 0x0 0x1000>; From 64917707914f95fa5827f2cc5bea2d5febe3a01b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:04 +0100 Subject: [PATCH 0455/1040] arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-7-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 578238910f23..18c4616848ce 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2001,7 +2001,7 @@ }; cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; From b2e1f87070ead06fb2918edeeed4329f58d1b2ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 8 Mar 2023 02:27:05 +0100 Subject: [PATCH 0456/1040] arm64: dts: qcom: sm8150: Add SoC-specific compatible to cpufreq_hw Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308-topic-cpufreq_bindings-v1-8-3368473ec52d@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8e2820aa0f6e..573f6bba6f39 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4294,7 +4294,7 @@ }; cpufreq_hw: cpufreq@18323000 { - compatible = "qcom,cpufreq-hw"; + compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, <0 0x18327800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1", From 7c2c4c9decf6f4604fe15a1db2da7c1250b3e9e5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 15:27:12 +0100 Subject: [PATCH 0457/1040] arm64: dts: qcom: sm8450-hdk: use recommended drive strength for speaker SD_N Downstream DTS (and sc8280xp-lenovo-thinkpad-x13s with the same speakers) uses 16 mA drive strength for the WSA8835 speaker SD_N reset/shutdown pin. Use the same for HDK8450, as it is seem the recommended value. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308142712.277659-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index cc6bfe99d07d..a2ae37e4ac68 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -797,7 +797,7 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio1"; function = "gpio"; - drive-strength = <4>; + drive-strength = <16>; bias-disable; output-low; }; @@ -805,7 +805,7 @@ spkr_2_sd_n_active: spkr-2-sd-n-active-state { pins = "gpio89"; function = "gpio"; - drive-strength = <4>; + drive-strength = <16>; bias-disable; output-low; }; From f0d0966f87f9c38b74619bf7f0345f368af3a4c1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 19:33:16 +0100 Subject: [PATCH 0458/1040] arm64: dts: qcom: sm8450-hdk: use precise WCD9385 compatible The HDK8450 uses WCD9385 audio codec, so use precise compatible, even though WCD9380 and WCD9385 are both compatible. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308183317.559253-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index a2ae37e4ac68..c97e775e00b3 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -25,7 +25,7 @@ }; wcd938x: audio-codec { - compatible = "qcom,wcd9380-codec"; + compatible = "qcom,wcd9385-codec"; pinctrl-names = "default"; pinctrl-0 = <&wcd_default>; From 6b2777fff8a9942cdcee82ae3f17d7f483a1e18c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 19:33:17 +0100 Subject: [PATCH 0459/1040] arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it is more like a shutdown pin, not a reset. Use the same settings here for HDK8450 and keep the WCD9385 by default in powered off (so pin as low). Align the name of pin configuration node with other pins in the DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308183317.559253-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index c97e775e00b3..e931545a2cac 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -810,9 +810,11 @@ output-low; }; - wcd_default: wcd-default-state { + wcd_default: wcd-reset-n-active-state { pins = "gpio43"; function = "gpio"; + drive-strength = <16>; bias-disable; + output-low; }; }; From 4ca4a633205fb372882de3e6e93a0a3584298249 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 21 Mar 2023 18:12:11 +0100 Subject: [PATCH 0460/1040] ARM: dts: meson8: add the xtal_32k_out pin GPIOX_10 can generate a 32768Hz signal when enabling the "xtal_32k_out" group with the xtal function. This is typically used as LPO clock for the SDIO wifi chips. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230321171213.2808460-2-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 21eb59041a7d..4d18bb4e3c33 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -568,6 +568,14 @@ bias-disable; }; }; + + xtal_32k_out_pins: xtal-32k-out { + mux { + groups = "xtal_32k_out"; + function = "xtal"; + bias-disable; + }; + }; }; }; From ef8474d50a37ab5f2f2f60e179d749b4273470de Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 21 Mar 2023 18:12:12 +0100 Subject: [PATCH 0461/1040] ARM: dts: meson8: add the SDXC_A pins Add the pins for the SDHC MMC controller which connect to the SDIO wifi on some boards. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230321171213.2808460-3-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/meson8.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 4d18bb4e3c33..4f22ab451aae 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -506,6 +506,15 @@ }; }; + sdxc_a_pins: sdxc-a { + mux { + groups = "sdxc_d0_a", "sdxc_d13_a", + "sdxc_clk_a", "sdxc_cmd_a"; + function = "sdxc_a"; + bias-pull-up; + }; + }; + sdxc_b_pins: sdxc-b { mux { groups = "sdxc_d0_b", "sdxc_d13_b", From 8446b84c894f7441f8bf4410f9638e38dcb29c49 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 21 Mar 2023 18:12:13 +0100 Subject: [PATCH 0462/1040] ARM: dts: meson8m2: mxiii-plus: Enable Bluetooth and WiFi support The MXIII Plus uses an Ampak AP6330 Bluetooth and WiFi combo chip. Bluetooth is connected to &uart_A and requires toggling GPIOX_20. WiFi can be routed to either &sdhc or &sdio. Route WiFi to &sdhc since &sdio is already connected to the SD card. Additionally WiFi requires toggling GPIOX_11 and GPIOAO_6 as well as enabling the 32kHz clock signal. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230321171213.2808460-4-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 48 ++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts index fa6d55f1cfb9..aa4d4bf70629 100644 --- a/arch/arm/boot/dts/meson8m2-mxiii-plus.dts +++ b/arch/arm/boot/dts/meson8m2-mxiii-plus.dts @@ -19,7 +19,6 @@ ethernet0 = ðmac; i2c0 = &i2c_AO; serial0 = &uart_AO; - serial1 = &uart_A; mmc0 = &sd_card_slot; }; @@ -45,12 +44,32 @@ }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + + pinctrl-0 = <&xtal_32k_out_pins>; + pinctrl-names = "default"; + + reset-gpios = <&gpio GPIOX_11 GPIO_ACTIVE_LOW>, + <&gpio_ao GPIOAO_6 GPIO_ACTIVE_LOW>; + + clocks = <&xtal_32k_out>; + clock-names = "ext_clock"; + }; + vcc_3v3: regulator-vcc3v3 { compatible = "regulator-fixed"; regulator-name = "VCC3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + xtal_32k_out: xtal-32k-out-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xtal_32k_out"; + }; }; &cpu0 { @@ -192,6 +211,27 @@ vref-supply = <&vddio_ao1v8>; }; +/* SDIO wifi */ +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_a_pins>; + pinctrl-names = "default"; + + bus-width = <4>; + max-frequency = <50000000>; + + disable-wp; + non-removable; + cap-mmc-highspeed; + cap-sd-highspeed; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + &sdio { status = "okay"; @@ -222,6 +262,12 @@ pinctrl-0 = <&uart_a1_pins>, <&uart_a1_cts_rts_pins>; pinctrl-names = "default"; uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm20702a1"; + shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + }; }; &uart_AO { From 6ff9453765565b34cd9dfb874afd8b06902453f7 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Thu, 9 Mar 2023 22:35:01 +0100 Subject: [PATCH 0463/1040] arm64: dts: mediatek: Initial mt8365-evk support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups, add CPU cache layout, add systimer, fix GIC] Signed-off-by: Bernhard Rosenkränzer [aouledameur@baylibre.com: Fix systimer properties] Signed-off-by: Amjad Ouled-Ameur Signed-off-by: Alexandre Mergnat Tested-by: Kevin Hilman Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230309213501.794764-4-bero@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 168 +++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 377 ++++++++++++++++++++ 3 files changed, 546 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index d5cd7b3e09cf..c99c3372a4b5 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -52,4 +52,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts new file mode 100644 index 000000000000..4683704ea235 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkränzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model = "MediaTek MT8365 Open Platform EVK"; + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-volume-up { + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x20000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&pio { + gpio_keys: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + }; + }; + + usb_pins: usb-pins { + id-pins { + pinmux = ; + input-enable; + bias-pull-up; + }; + + usb0-vbus-pins { + pinmux = ; + output-high; + }; + + usb1-vbus-pins { + pinmux = ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux = , + ; + }; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi new file mode 100644 index 000000000000..351197c453c9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkränzer + */ +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8365"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + cache-unified; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = ; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8365-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible = "mediatek,mt8365-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8365-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + keypad: keypad@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt8365-mcucfg", "syscon"; + reg = <0 0x10200000 0 0x2000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x20>; + }; + + infracfg_nao: infracfg@1020e000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x1020e000 0 0x1000>; + #clock-cells = <1>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_IFR_TRNG>; + clock-names = "rng"; + }; + + apdma: dma-controller@11000280 { + compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; + reg = <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts = , + , + , + , + , + ; + dma-requests = <6>; + clocks = <&infracfg CLK_IFR_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt8365-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; + reg = <0 0x1100a000 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + ssusb: usb@11201000 { + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11200000 { + compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status = "disabled"; + }; + }; + + u3phy: t-phy@11cc0000 { + compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11cc0000 0x9000>; + + u2port0: usb-phy@0 { + reg = <0x0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1000 { + reg = <0x1000 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x100>; + interrupts = ; + clocks = <&system_clk>; + clock-names = "clk13m"; + }; +}; From ed066df385cb1a7286123a246337636f8debd18d Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:17 +0100 Subject: [PATCH 0464/1040] arm64: dts: qcom: sc8280xp-x13s: add pmic regulator supplies The s11b, s12b, s1c and bob supplies are used by several pmic regulators. Add the missing description to the devicetree. Note that there are still some consumers that are not (fully) described in the devicetree so the supplies must remain marked as always-on for now. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-6-johan+linaro@kernel.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 9b674686943d..ad90f72e116a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -363,7 +363,11 @@ compatible = "qcom,pm8350-rpmh-regulators"; qcom,pmic-id = "b"; + vdd-l1-l4-supply = <&vreg_s12b>; + vdd-l2-l7-supply = <&vreg_bob>; vdd-l3-l5-supply = <&vreg_s11b>; + vdd-l6-l9-l10-supply = <&vreg_s12b>; + vdd-l8-supply = <&vreg_s12b>; vreg_s10b: smps10 { regulator-name = "vreg_s10b"; @@ -413,7 +417,21 @@ regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; + vdd-bob-supply = <&vreg_vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1c>; + vdd-l2-l8-supply = <&vreg_s1c>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s11b>; + + vreg_s1c: smps1 { + regulator-name = "vreg_s1c"; + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + regulator-always-on; + }; vreg_l1c: ldo1 { regulator-name = "vreg_l1c"; @@ -449,6 +467,10 @@ qcom,pmic-id = "d"; vdd-l1-l4-supply = <&vreg_s11b>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_s11b>; + vdd-l6-l9-l10-supply = <&vreg_s12b>; + vdd-l8-supply = <&vreg_s12b>; vreg_l3d: ldo3 { regulator-name = "vreg_l3d"; From b01899cb18659c9911cc790cd66784623e5e5a0e Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 22 Mar 2023 12:33:18 +0100 Subject: [PATCH 0465/1040] arm64: dts: qcom: sc8280xp-x13s: add hid 1.8V supplies All the input devices use s10b as 1.8V supply. Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322113318.17908-7-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index ad90f72e116a..57180368d3e2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -592,6 +592,7 @@ hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&ts0_default>; @@ -613,6 +614,7 @@ hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&tpad_default>; @@ -629,6 +631,7 @@ hid-descr-addr = <0x20>; interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&tpad_default>; @@ -643,6 +646,7 @@ hid-descr-addr = <0x1>; interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; vdd-supply = <&vreg_misc_3p3>; + vddl-supply = <&vreg_s10b>; pinctrl-names = "default"; pinctrl-0 = <&kybd_default>; From 2702f54f400ad3979632cdb76553772414f4c5e3 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 21 Mar 2023 10:40:11 +0100 Subject: [PATCH 0466/1040] arm64: dts: qcom: sc8280xp-x13s: add wifi calibration variant Describe the bus topology for PCIe domain 6 and add the ath11k calibration variant so that the board file (calibration data) can be loaded. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216246 Reviewed-by: Konrad Dybcio Tested-by: Steev Klimaszewski Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230321094011.9759-3-johan+linaro@kernel.org --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 57180368d3e2..0d1e49ddd540 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -703,6 +703,23 @@ pinctrl-0 = <&pcie4_default>; status = "okay"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + bus-range = <0x01 0xff>; + + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + qcom,ath11k-calibration-variant = "LE_X13S"; + }; + }; }; &pcie4_phy { From 2ae66ecc0825b0b4707384772b848c79b0986ef5 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Sun, 19 Mar 2023 17:13:03 +0000 Subject: [PATCH 0467/1040] memory: tegra: remove redundant variable initialization tegra210_emc_table_device_init() sets count = 0 twice, so remove the second instance. Signed-off-by: Diogo Ivo Link: https://lore.kernel.org/r/20230319171303.120777-1-diogo.ivo@tecnico.ulisboa.pt Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210-emc-table.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/memory/tegra/tegra210-emc-table.c b/drivers/memory/tegra/tegra210-emc-table.c index 3e0598363b87..34a8785d2861 100644 --- a/drivers/memory/tegra/tegra210-emc-table.c +++ b/drivers/memory/tegra/tegra210-emc-table.c @@ -22,8 +22,6 @@ static int tegra210_emc_table_device_init(struct reserved_mem *rmem, return -ENOMEM; } - count = 0; - for (i = 0; i < TEGRA_EMC_MAX_FREQS; i++) { if (timings[i].revision == 0) break; From c8ec73b05a95d9f0969ae0f28dd8799a54fcdfc7 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 18 Mar 2023 16:37:41 +0800 Subject: [PATCH 0468/1040] arm64: dts: rockchip: create common dtsi for NanoPi R5 series Create common dtsi for the FriendlyElec NanoPi R5 series. Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 575 +---------------- .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 596 ++++++++++++++++++ 2 files changed, 597 insertions(+), 574 deletions(-) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index 25edc82eaa3f..e9adf5e66529 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -7,12 +7,7 @@ */ /dts-v1/; -#include -#include -#include -#include -#include -#include "rk3568.dtsi" +#include "rk3568-nanopi-r5s.dtsi" / { model = "FriendlyElec NanoPi R5S"; @@ -20,23 +15,6 @@ aliases { ethernet0 = &gmac0; - mmc0 = &sdmmc0; - mmc1 = &sdhci; - }; - - chosen: chosen { - stdout-path = "serial2:1500000n8"; - }; - - hdmi-con { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con_in: endpoint { - remote-endpoint = <&hdmi_out_con>; - }; - }; }; gpio-leds { @@ -71,130 +49,6 @@ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; }; }; - - vdd_usbc: vdd-usbc-regulator { - compatible = "regulator-fixed"; - regulator-name = "vdd_usbc"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vcc3v3_sys: vcc3v3-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - vcc3v3_pcie: vcc3v3-pcie-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; - startup-delay-us = <200000>; - vin-supply = <&vcc5v0_sys>; - }; - - vcc5v0_usb: vcc5v0-usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_usb"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vdd_usbc>; - }; - - vcc5v0_usb_host: vcc5v0-usb-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_host_en>; - regulator-name = "vcc5v0_usb_host"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&vcc5v0_usb_otg_en>; - regulator-name = "vcc5v0_usb_otg"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; - }; - - pcie30_avdd0v9: pcie30-avdd0v9-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - - pcie30_avdd1v8: pcie30-avdd1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; -}; - -&combphy0 { - status = "okay"; -}; - -&combphy1 { - status = "okay"; -}; - -&combphy2 { - status = "okay"; -}; - -&cpu0 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu1 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu2 { - cpu-supply = <&vdd_cpu>; -}; - -&cpu3 { - cpu-supply = <&vdd_cpu>; }; &gmac0 { @@ -219,292 +73,6 @@ status = "okay"; }; -&gpu { - mali-supply = <&vdd_gpu>; - status = "okay"; -}; - -&hdmi { - avdd-0v9-supply = <&vdda0v9_image>; - avdd-1v8-supply = <&vcca1v8_image>; - status = "okay"; -}; - -&hdmi_in { - hdmi_in_vp0: endpoint { - remote-endpoint = <&vp0_out_hdmi>; - }; -}; - -&hdmi_out { - hdmi_out_con: endpoint { - remote-endpoint = <&hdmi_con_in>; - }; -}; - -&hdmi_sound { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - vdd_cpu: regulator@1c { - compatible = "tcs,tcs4525"; - reg = <0x1c>; - fcs,suspend-voltage-selector = <1>; - regulator-name = "vdd_cpu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <2300>; - vin-supply = <&vcc5v0_sys>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - rk809: pmic@20 { - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; - rockchip,system-power-controller; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - wakeup-source; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-always-on; - regulator-boot-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdd_gpu: DCDC_REG2 { - regulator-name = "vdd_gpu"; - regulator-always-on; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vdd_npu: DCDC_REG4 { - regulator-name = "vdd_npu"; - regulator-init-microvolt = <900000>; - regulator-initial-mode = <0x2>; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_1v8: DCDC_REG5 { - regulator-name = "vcc_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_image: LDO_REG1 { - regulator-name = "vdda0v9_image"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <950000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda_0v9: LDO_REG2 { - regulator-name = "vdda_0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vdda0v9_pmu: LDO_REG3 { - regulator-name = "vdda0v9_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - - vccio_acodec: LDO_REG4 { - regulator-name = "vccio_acodec"; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_pmu: LDO_REG6 { - regulator-name = "vcc3v3_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcca_1v8: LDO_REG7 { - regulator-name = "vcca_1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcca1v8_pmu: LDO_REG8 { - regulator-name = "vcca1v8_pmu"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vcca1v8_image: LDO_REG9 { - regulator-name = "vcca1v8_image"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc_3v3: SWITCH_REG1 { - regulator-name = "vcc_3v3"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - - vcc3v3_sd: SWITCH_REG2 { - regulator-name = "vcc3v3_sd"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - }; - }; - }; - - }; -}; - -&i2c5 { - status = "okay"; - - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; - interrupt-parent = <&gpio0>; - interrupts = ; - #clock-cells = <0>; - clock-output-names = "rtcic_32kout"; - pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; - wakeup-source; - }; -}; - -&i2s0_8ch { - status = "okay"; -}; - -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -568,146 +136,5 @@ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; - - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - pmic { - pmic_int: pmic-int { - rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - vcc5v0_usb_host_en: vcc5v0-usb-host-en { - rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; }; -&pmu_io_domains { - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; - status = "okay"; -}; - -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; - -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; - status = "okay"; -}; - -&sdmmc0 { - max-frequency = <150000000>; - no-sdio; - no-mmc; - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <1>; - rockchip,hw-tshut-polarity = <0>; - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host0_xhci { - extcon = <&usb2phy0>; - dr_mode = "host"; - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host1_xhci { - status = "okay"; -}; - -&usb2phy0 { - status = "okay"; -}; - -&usb2phy0_host { - phy-supply = <&vcc5v0_usb_host>; - status = "okay"; -}; - -&usb2phy0_otg { - status = "okay"; -}; - -&usb2phy1 { - status = "okay"; -}; - -&usb2phy1_host { - phy-supply = <&vcc5v0_usb_otg>; - status = "okay"; -}; - -&usb2phy1_otg { - status = "okay"; -}; - -&vop { - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; - status = "okay"; -}; - -&vop_mmu { - status = "okay"; -}; - -&vp0 { - vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { - reg = ; - remote-endpoint = <&hdmi_in_vp0>; - }; -}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi new file mode 100644 index 000000000000..dd9a7907a1c5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vdd_usbc: vdd-usbc-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_usbc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vdd_usbc>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + }; +}; + +&i2c5 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <0>; + clock-output-names = "rtcic_32kout"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From 7d4fc70351d155699fe41949d16ce696885a4ca8 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 18 Mar 2023 16:37:42 +0800 Subject: [PATCH 0469/1040] dt-bindings: Add doc for FriendlyARM NanoPi R5C Add devicetree binding documentation for the FriendlyARM NanoPi R5C. Acked-by: Krzysztof Kozlowski Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230318083745.6181-3-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 5474cb4a13d1..6f4270f2bd9e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -201,9 +201,11 @@ properties: - friendlyarm,nanopi-r4s-enterprise - const: rockchip,rk3399 - - description: FriendlyElec NanoPi R5S board + - description: FriendlyElec NanoPi R5 series boards items: - - const: friendlyarm,nanopi-r5s + - enum: + - friendlyarm,nanopi-r5c + - friendlyarm,nanopi-r5s - const: rockchip,rk3568 - description: GeekBuying GeekBox From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 18 Mar 2023 16:37:43 +0800 Subject: [PATCH 0470/1040] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device. Specification: - Rockchip RK3568 - 1/4GB LPDDR4X RAM - 8/32GB eMMC - SD card slot - M.2 Connector - 2x USB 3.0 Port - 2x 2500 Base-T (PCIe, r8125) - HDMI 2.0 - MIPI DSI/CSI - USB Type C 5V Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index ade66d846a20..a315a8117b0f 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts new file mode 100644 index 000000000000..f70ca9f0470a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3568-nanopi-r5s.dtsi" + +/ { + model = "FriendlyElec NanoPi R5C"; + compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button_pin>; + + button-reset { + debounce-interval = <50>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + label = "reset"; + linux,code = ; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>; + + led-lan { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + power_led: led-power { + color = ; + function = LED_FUNCTION_POWER; + linux,default-trigger = "heartbeat"; + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + + led-wan { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + led-wlan { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_reset_pin>; + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + power_led_pin: power-led-pin { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led_pin: wlan-led-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_reset_pin: pcie20-reset-pin { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + reset_button_pin: reset-button-pin { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 18 Mar 2023 16:37:44 +0800 Subject: [PATCH 0471/1040] arm64: dts: rockchip: fix gmac support for NanoPi R5S - Changed phy-mode to rgmii. - Fixed pull type in pinctrl for gmac0. - Removed duplicate properties in mdio node. These properties are defined in the gmac0 node already. Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts index e9adf5e66529..2a1118f15c29 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts @@ -57,7 +57,7 @@ assigned-clock-rates = <0>, <125000000>; clock_in_out = "output"; phy-handle = <&rgmii_phy0>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&gmac0_miim &gmac0_tx_bus2 @@ -79,9 +79,6 @@ reg = <1>; pinctrl-0 = <ð_phy0_reset_pin>; pinctrl-names = "default"; - reset-assert-us = <10000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; }; }; @@ -115,7 +112,7 @@ &pinctrl { gmac0 { eth_phy0_reset_pin: eth-phy0-reset-pin { - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 18 Mar 2023 16:37:45 +0800 Subject: [PATCH 0472/1040] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5 series This is for the audio output which does not exist on the boards. Also disable regulator-always-on for vccio_acodec since it's only used by the audio output. Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi index dd9a7907a1c5..58ba328ea782 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi @@ -330,7 +330,6 @@ vccio_acodec: LDO_REG4 { regulator-name = "vccio_acodec"; - regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -441,11 +440,6 @@ status = "okay"; }; -&i2s1_8ch { - rockchip,trcm-sync-tx-only; - status = "okay"; -}; - &pcie30phy { data-lanes = <1 2>; status = "okay"; From ea2d16f90629e3158307d0183cad5c40aa55c995 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:29:35 +0100 Subject: [PATCH 0473/1040] ARM: dts: rockchip: fix rk3288 dsi node Use generic node name for rk3288.dtsi dsi node. With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node is required, so add a node with label mipi_out. Also restyle. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/f3edcbff-4aef-1d24-8d65-e519c9451cda@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 2ca76b69add7..5745e9241e36 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1114,7 +1114,7 @@ status = "disabled"; }; - mipi_dsi: mipi@ff960000 { + mipi_dsi: dsi@ff960000 { compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x4000>; interrupts = ; @@ -1125,18 +1125,28 @@ status = "disabled"; ports { - mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; + mipi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_mipi>; }; + mipi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_mipi>; }; }; + + mipi_out: port@1 { + reg = <1>; + }; }; }; From 8a19e4c74d17ed8d1e6bc06b32c5b7b7c3b9fcfb Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:30:06 +0100 Subject: [PATCH 0474/1040] ARM: dts: rockchip: fix rk3288 lvds node With the conversion of rockchip,lvds.yaml a port@1 node is required, so add a node with label lvds_out. Also restyle. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/e7b78a73-0e89-d9e9-2ecc-a8a380635f64@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 5745e9241e36..8b71ca41e848 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1167,7 +1167,6 @@ lvds_in: port@0 { reg = <0>; - #address-cells = <1>; #size-cells = <0>; @@ -1175,11 +1174,16 @@ reg = <0>; remote-endpoint = <&vopb_out_lvds>; }; + lvds_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_lvds>; }; }; + + lvds_out: port@1 { + reg = <1>; + }; }; }; From 95e2ac6ae9f2330557a6aef70bf15173e1dd9714 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:30:38 +0100 Subject: [PATCH 0475/1040] ARM: dts: rockchip: fix rk3288 dp node With the conversion of rockchip,analogix-dp.yaml a port@1 node is required, so add a node with label edp_out. Also restyle. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/0a423eb4-0ab6-7ecb-d450-d93639160dbc@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 8b71ca41e848..2fa7fdc60d27 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1204,19 +1204,26 @@ ports { #address-cells = <1>; #size-cells = <0>; + edp_in: port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; + edp_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_edp>; }; + edp_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_edp>; }; }; + + edp_out: port@1 { + reg = <1>; + }; }; }; From 0d5e24918976edffffee006e07730434a36d264a Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:31:22 +0100 Subject: [PATCH 0476/1040] arm64: dts: rockchip: fix px30 lvds node With the conversion of rockchip,lvds.yaml a port@1 node is required, so add a node with label lvds_out. Also add label lvds_in to port@0. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/99895a4b-25c4-4b64-42ac-6f70940ab56e@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 4f6959eb564d..8aa80106e5c3 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -474,7 +474,7 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + lvds_in: port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -489,6 +489,10 @@ remote-endpoint = <&vopl_out_lvds>; }; }; + + lvds_out: port@1 { + reg = <1>; + }; }; }; }; From 30322f812d4e0e75e2488c1d45aba94e51dd19bb Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:31:52 +0100 Subject: [PATCH 0477/1040] arm64: dts: rockchip: fix px30 dsi node With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node is required, so add a node with label dsi_out. Also add label dsi_in to port@0. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/1ee3e676-aef4-f464-82b0-8fb39ba5c60d@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/px30.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 8aa80106e5c3..8332c8aaf49b 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -1138,7 +1138,7 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + dsi_in: port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -1153,6 +1153,10 @@ remote-endpoint = <&vopl_out_dsi>; }; }; + + dsi_out: port@1 { + reg = <1>; + }; }; }; From f82fe7ad31530b38d2f61aa6ae68bd35c33f4ad0 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:32:22 +0100 Subject: [PATCH 0478/1040] arm64: dts: rockchip: fix rk3399 dsi node Use generic node name for rk3399.dtsi dsi node. With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node is required, so add a node with label mipi_out. Also restyle. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/1e019e9e-a8da-3d57-2770-f6b81bbbf591@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 1881b4b71f91..ccf5e8679199 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1954,7 +1954,7 @@ }; }; - mipi_dsi: mipi@ff960000 { + mipi_dsi: dsi@ff960000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = ; @@ -1982,15 +1982,20 @@ reg = <0>; remote-endpoint = <&vopb_out_mipi>; }; + mipi_in_vopl: endpoint@1 { reg = <1>; remote-endpoint = <&vopl_out_mipi>; }; }; + + mipi_out: port@1 { + reg = <1>; + }; }; }; - mipi_dsi1: mipi@ff968000 { + mipi_dsi1: dsi@ff968000 { compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff968000 0x0 0x8000>; interrupts = ; @@ -2025,6 +2030,10 @@ remote-endpoint = <&vopl_out_mipi1>; }; }; + + mipi1_out: port@1 { + reg = <1>; + }; }; }; From d94024bd6342c6f3e88c5fac785a685c1974d48e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:32:52 +0100 Subject: [PATCH 0479/1040] arm64: dts: rockchip: fix rk3399 dp node Use generic node name for rk3399.dtsi dp node. With the conversion of rockchip,analogix-dp.yaml a port@1 node is required, so add a node with label edp_out. Also restyle. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/f6008819-db9b-0944-3f5b-5522b7cd8a8d@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index ccf5e8679199..74f667fbdf5b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -2037,7 +2037,7 @@ }; }; - edp: edp@ff970000 { + edp: dp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; interrupts = ; @@ -2054,6 +2054,7 @@ ports { #address-cells = <1>; #size-cells = <0>; + edp_in: port@0 { reg = <0>; #address-cells = <1>; @@ -2069,6 +2070,10 @@ remote-endpoint = <&vopl_out_edp>; }; }; + + edp_out: port@1 { + reg = <1>; + }; }; }; From fc440ea1732abb714150bb8f3d90672ccc679e2d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:33:22 +0100 Subject: [PATCH 0480/1040] arm64: dts: rockchip: rename vbus-supply to phy-supply in rk3566-box-demo.dts 'vbus-supply' does not match any of the regexes in rk3566-box-demo.dts in the usb2phy0_otg node, so rename vbus-supply to phy-supply. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/1889d8ee-e119-4a52-33a1-b990a41a137c@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts index 2671f207cfd1..410cd3e5e7bc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts @@ -495,7 +495,7 @@ }; &usb2phy0_otg { - vbus-supply = <&vcc5v0_usb2_otg>; + phy-supply = <&vcc5v0_usb2_otg>; status = "okay"; }; From cadda005961cd6a202ae6f8ff99f2bba35a31dc8 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 22 Dec 2022 15:33:49 +0100 Subject: [PATCH 0481/1040] arm64: dts: rockchip: remove hclk from dsi node on rk356x The hclk is not used in the dw-mipi-dsi binding, so remove hclk from the rk356x.dtsi dsi node. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/4df211eb-4fcd-ee20-48a1-ce7712de552c@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index eed0059a68b8..802fcc96384e 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -744,8 +744,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x00 0xfe060000 0x00 0x10000>; interrupts = ; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_0>; phy-names = "dphy"; phys = <&dsi_dphy0>; power-domains = <&power RK3568_PD_VO>; @@ -772,8 +772,8 @@ compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xfe070000 0x0 0x10000>; interrupts = ; - clock-names = "pclk", "hclk"; - clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; + clock-names = "pclk"; + clocks = <&cru PCLK_DSITX_1>; phy-names = "dphy"; phys = <&dsi_dphy1>; power-domains = <&power RK3568_PD_VO>; From e16dd29a3dff57eb6c84374ad8d824f1ec1c48bd Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 17 Feb 2023 14:03:08 +0530 Subject: [PATCH 0482/1040] arm64: dts: qcom: ipq5332: enable the CPUFreq support Add the APCS, A53 PLL, cpu-opp-table nodes to bump the CPU frequency above 800MHz. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217083308.12017-6-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 76d739b216dd..04ef80f267bf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include #include @@ -35,6 +36,8 @@ reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@1 { @@ -43,6 +46,8 @@ reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@2 { @@ -51,6 +56,8 @@ reg = <0x2>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@3 { @@ -59,6 +66,8 @@ reg = <0x3>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache { @@ -80,6 +89,16 @@ reg = <0x0 0x40000000 0x0 0x0>; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-1488000000 { + opp-hz = /bits/ 64 <1488000000>; + clock-latency-ns = <200000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -214,6 +233,24 @@ }; }; + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq5332-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg = <0x0b111000 0x1000>; + #clock-cells = <1>; + clocks = <&a53pll>, <&xo_board>; + clock-names = "pll", "xo"; + #mbox-cells = <1>; + }; + + a53pll: clock@b116000 { + compatible = "qcom,ipq5332-a53pll"; + reg = <0x0b116000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; From 45875db5cc91958af0e0ada3d8d27ad57ab7c8bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:58:36 +0100 Subject: [PATCH 0483/1040] arm64: dts: qcom: sc7180-trogdor-pazquel360: drop incorrect RT5682S VBAT-supply It seems that the RT5682S codec does not use VBAT-supply: sc7180-trogdor-pazquel360-lte.dtb: codec@1a: Unevaluated properties are not allowed ('VBAT-supply' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217155838.848403-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi index bc4f3b6c6634..273e2249f018 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi @@ -12,6 +12,7 @@ compatible = "realtek,rt5682s"; realtek,dmic1-clk-pin = <2>; realtek,dmic-clk-rate-hz = <2048000>; + /delete-property/ VBAT-supply; }; ap_ts_pen_1v8: &i2c4 { From 11c0d37d4c03ac8002d378cb814aca89118e7d35 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:58:37 +0100 Subject: [PATCH 0484/1040] arm64: dts: qcom: sc7280-herobrine-audio-rt5682: add missing supplies Bindings expect DBVDD-supply and LDO1-IN-supply: sc7280-herobrine-evoker-lte.dtb: codec@1a: 'DBVDD-supply' is a required property sc7280-herobrine-evoker-lte.dtb: codec@1a: 'LDO1-IN-supply' is a required property In sc7180-trogdor.dtsi they come from the same regulator, so let's assume intention was the same here. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217155838.848403-2-krzysztof.kozlowski@linaro.org --- .../arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi | 2 ++ arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi index 1ca11a14104d..485f9942e128 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi @@ -94,6 +94,8 @@ hp_i2c: &i2c2 { interrupts = <101 IRQ_TYPE_EDGE_BOTH>; AVDD-supply = <&pp1800_alc5682>; + DBVDD-supply = <&pp1800_alc5682>; + LDO1-IN-supply = <&pp1800_alc5682>; MICVDD-supply = <&pp3300_codec>; realtek,dmic1-data-pin = <1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi index 69e7aa7b2f6c..8b855345e5c7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi @@ -76,6 +76,8 @@ hp_i2c: &i2c2 { interrupts = <101 IRQ_TYPE_EDGE_BOTH>; AVDD-supply = <&pp1800_alc5682>; + DBVDD-supply = <&pp1800_alc5682>; + LDO1-IN-supply = <&pp1800_alc5682>; MICVDD-supply = <&pp3300_codec>; realtek,dmic1-data-pin = <1>; From a93af4677e8c3db24eeeb0498bee83b6b7e341fe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:58:38 +0100 Subject: [PATCH 0485/1040] arm64: dts: qcom: sc7280: align RPMh regulator nodes with bindings Device node names should be generic and bindings expect certain pattern for RPMh regulator nodes. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230217155838.848403-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index 1185141f348e..afae7f46b050 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -27,7 +27,7 @@ }; &apps_rsc { - pmg1110-regulators { + regulators-2 { compatible = "qcom,pmg1110-rpmh-regulators"; qcom,pmic-id = "k"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index 4e0b013e25f4..df39a64da923 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -40,7 +40,7 @@ /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ &apps_rsc { - pmg1110-regulators { + regulators-2 { compatible = "qcom,pmg1110-rpmh-regulators"; qcom,pmic-id = "k"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index ba64316b4427..15222e92e3f5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -25,7 +25,7 @@ }; &apps_rsc { - pmr735a-regulators { + regulators-2 { compatible = "qcom,pmr735a-rpmh-regulators"; qcom,pmic-id = "e"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 388770be8f13..5dc9bee28e7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -184,7 +184,7 @@ }; &apps_rsc { - pm7325-regulators { + regulators-0 { compatible = "qcom,pm7325-rpmh-regulators"; qcom,pmic-id = "b"; @@ -279,7 +279,7 @@ }; }; - pm8350c-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 88204f794ccb..cb0cc2ba2fa3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -87,7 +87,7 @@ * are left out of here since they are managed elsewhere. */ - pm7325-regulators { + regulators-0 { compatible = "qcom,pm7325-rpmh-regulators"; qcom,pmic-id = "b"; @@ -188,7 +188,7 @@ }; }; - pm8350c-regulators { + regulators-1 { compatible = "qcom,pm8350c-rpmh-regulators"; qcom,pmic-id = "c"; From 2458a305e80ef736ae03e6ca0bcae4c3f6923163 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:33 +0100 Subject: [PATCH 0486/1040] arm64: dts: qcom: sm8350: switch to combo usb3/dp phy The first QMP PHY is an USB3/DP combo phy, switch to the newly documented bindings and register the clocks to the GCC and DISPCC controllers. Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov #SM8350-HDK Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-2-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 42 ++++++++++------------------ 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 86d887a1c3eb..4907aa68e584 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -660,7 +661,7 @@ <&ufs_mem_phy_lanes 0>, <&ufs_mem_phy_lanes 1>, <&ufs_mem_phy_lanes 2>, - <0>, + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <0>; }; @@ -2133,37 +2134,24 @@ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; }; - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8350-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sm8350-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; }; usb_2_qmpphy: phy-wrapper@88eb000 { @@ -2269,7 +2257,7 @@ iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; ports { @@ -2653,8 +2641,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, - <0>; + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", From a2802008af93b70165a80624082c695d89f51eb2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:34 +0100 Subject: [PATCH 0487/1040] arm64: dts: qcom: sm8350: add dp controller Add the Display Port controller subnode to the MDSS node. Tested-by: Dmitry Baryshkov #SM8350-HDK Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-3-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 79 ++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 4907aa68e584..d9d7ee90d5d4 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2435,6 +2435,85 @@ remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp_in>; + }; + }; + }; + }; + + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0x600>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8350_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; }; }; From d3054cec1e9ea475e53280724db62b62e25669d7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:35 +0100 Subject: [PATCH 0488/1040] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy The QMP PHY is a USB3/DP combo phy, switch to the newly documented bindings and register the clocks to the GCC and DISPCC controllers. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-4-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++------------------ 1 file changed, 15 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 357ef1d275c9..c334200cd54b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -747,7 +748,7 @@ <&ufs_mem_phy_lanes 0>, <&ufs_mem_phy_lanes 1>, <&ufs_mem_phy_lanes 2>, - <0>; + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk", @@ -2033,37 +2034,24 @@ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; }; - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8450-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + usb_1_qmpphy: phy@88e8000 { + compatible = "qcom,sm8450-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; }; remoteproc_slpi: remoteproc@2400000 { @@ -2970,8 +2958,8 @@ <&mdss_dsi0_phy 1>, <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, - <0>, /* dp0 */ - <0>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <0>, /* dp1 */ <0>, <0>, /* dp2 */ @@ -4167,7 +4155,7 @@ iommus = <&apps_smmu 0x0 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; ports { From bdd2f4ce5e762d5aede6c30ae161e377536dae1c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 17 Mar 2023 16:06:36 +0100 Subject: [PATCH 0489/1040] arm64: dts: qcom: sm8450: add dp controller Add the Display Port controller subnode to the MDSS node. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206-topic-sm8450-upstream-dp-controller-v6-5-d78313cbc41d@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 79 ++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index c334200cd54b..d8f18e07383d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2749,6 +2749,13 @@ remote-endpoint = <&mdss_dsi1_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2781,6 +2788,78 @@ }; }; + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; + reg = <0 0xae90000 0 0x200>, + <0 0xae90200 0 0x200>, + <0 0xae90400 0 0xc00>, + <0 0xae91000 0 0x400>, + <0 0xae91400 0 0x400>; + interrupt-parent = <&mdss>; + interrupts = <12>; + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + #sound-dai-cells = <0>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; From 9737a63558deeec01ce202c6c06c96a0503a3128 Mon Sep 17 00:00:00 2001 From: Muhammad Usama Anjum Date: Fri, 3 Mar 2023 18:03:46 +0500 Subject: [PATCH 0490/1040] soc/tegra: cbb: remove linux/version.h make versioncheck reports the following: ./drivers/soc/tegra/cbb/tegra-cbb.c: 19 linux/version.h not needed. ./drivers/soc/tegra/cbb/tegra194-cbb.c: 26 linux/version.h not needed. ./drivers/soc/tegra/cbb/tegra234-cbb.c: 27 linux/version.h not needed. So remove linux/version.h from these files. Signed-off-by: Muhammad Usama Anjum Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/cbb/tegra-cbb.c | 1 - drivers/soc/tegra/cbb/tegra194-cbb.c | 1 - drivers/soc/tegra/cbb/tegra234-cbb.c | 1 - 3 files changed, 3 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra-cbb.c b/drivers/soc/tegra/cbb/tegra-cbb.c index a8566b9dd8de..bd96204a68ee 100644 --- a/drivers/soc/tegra/cbb/tegra-cbb.c +++ b/drivers/soc/tegra/cbb/tegra-cbb.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include diff --git a/drivers/soc/tegra/cbb/tegra194-cbb.c b/drivers/soc/tegra/cbb/tegra194-cbb.c index d4112b683f00..a05fc2caff3b 100644 --- a/drivers/soc/tegra/cbb/tegra194-cbb.c +++ b/drivers/soc/tegra/cbb/tegra194-cbb.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c index f33d094e5ea6..e23e8acfd7c7 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include From 1681ce3735483ab6897e403a20a7faf5c34c1f09 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 20 Mar 2023 14:57:09 +0100 Subject: [PATCH 0491/1040] arm64: dts: qcom: sc8280xp-pmics: fix sdam 'reg' property The SPMI PMIC register region width is fixed and should not be encoded in the devicetree. Fixes: d6dbbda37ab5 ("arm64: dts: qcom: sc8280xp-pmics: add pmk8280 sdam nvram") Signed-off-by: Johan Hovold Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230320135710.1989-3-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index 1411edd42b25..c35e7f6bd657 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -107,7 +107,7 @@ pmk8280_sdam_6: nvram@8500 { compatible = "qcom,spmi-sdam"; - reg = <0x8500 0x100>; + reg = <0x8500>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x8500 0x100>; From f23ba46e0799fc701bcd429d22767932401e9ae8 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:31 +0000 Subject: [PATCH 0492/1040] ARM: dts: suniv: add USB-related device nodes The suniv SoC has a USB OTG controller and a USB PHY like other Allwinner SoCs. Add their device tree node. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara Acked-by: Jernej Skrabec Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 9455d27e516e..111f8bbc2a80 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -133,6 +133,32 @@ #size-cells = <0>; }; + usb_otg: usb@1c13000 { + compatible = "allwinner,suniv-f1c100s-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <26>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; From bedc7c5490fce4e57b55e025b4adfbd31f25623d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:32 +0000 Subject: [PATCH 0493/1040] ARM: dts: suniv: licheepi-nano: enable USB Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected to the USB pins of the SoC and ID pin connected to PE2 GPIO. Enable the USB functionality. Signed-off-by: Icenowy Zheng Acked-by: Jernej Skrabec Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- .../arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts index 04e59b8381cb..43896723a994 100644 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "suniv-f1c100s.dtsi" +#include + / { model = "Lichee Pi Nano"; compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; @@ -50,8 +52,22 @@ }; }; +&otg_sram { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pe_pins>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */ + status = "okay"; +}; From eef696356f58a4f5c17ec5d7cb1d495f75edf62e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:33 +0000 Subject: [PATCH 0494/1040] dt-bindings: vendor-prefixes: add Source Parts and Lctech names Source Parts Inc. [1] is a company that makes a series of SBCs, SoMs, etc under a brand called Popcorn Computer [2]. Shenzen LC Technology [3] makes various boards and related products around IoT and AI technology. They used the "Cherry Pi" brand name before. Add both companies' names to the vendor prefixes list. [1] https://source.parts/ [2] https://popcorncomputer.com/ [3] http://www.chinalctech.com Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski Acked-by: Jernej Skrabec Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..fbe837c6798a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -721,6 +721,8 @@ patternProperties: description: Lantiq Semiconductor "^lattice,.*": description: Lattice Semiconductor + "^lctech,.*": + description: Shenzen LC Technology Co., Ltd. "^leadtek,.*": description: Shenzhen Leadtek Technology Co., Ltd. "^leez,.*": @@ -1243,6 +1245,8 @@ patternProperties: description: Solomon Systech Limited "^sony,.*": description: Sony Corporation + "^sourceparts,.*": + description: Source Parts Inc. "^spansion,.*": description: Spansion Inc. "^sparkfun,.*": From e89556d6350430f4d9d38e555a298281e68e130e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:34 +0000 Subject: [PATCH 0495/1040] dt-binding: arm: sunxi: add two board compatible strings The SourceParts PopStick is a F1C200s-based stick-shaped SBC. The publicly released version is actually v1.1. The Lctech Pi F1C200s is a small development board using the Allwinner F1C200s SoC. Add the compatible string lists to the bindings documentation. Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-5-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 3ad1cd50e3fe..cbdfc1c247a2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -366,6 +366,12 @@ properties: - const: lamobo,lamobo-r1 - const: allwinner,sun7i-a20 + - description: Lctech Pi F1C200s + items: + - const: lctech,pi-f1c200s + - const: allwinner,suniv-f1c200s + - const: allwinner,suniv-f1c100s + - description: Libre Computer Board ALL-H3-CC H2+ items: - const: libretech,all-h3-cc-h2-plus @@ -807,6 +813,13 @@ properties: - const: sinlinx,sina33 - const: allwinner,sun8i-a33 + - description: SourceParts PopStick v1.1 + items: + - const: sourceparts,popstick-v1.1 + - const: sourceparts,popstick + - const: allwinner,suniv-f1c200s + - const: allwinner,suniv-f1c100s + - description: SL631 Action Camera with IMX179 items: - const: allwinner,sl631-imx179 From 7452d4799c5b352d6987cff3db8b1e415466586e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:35 +0000 Subject: [PATCH 0496/1040] ARM: dts: suniv: add device tree for PopStick v1.1 PopStick is a minimal Allwinner F1C200s dongle, with its USB controller wired to a USB Type-A plug, a SD slot and a SPI NAND flash on board, and an on-board CH340 USB-UART converted connected to F1C200s's UART0. Add a device tree for it. As F1C200s is just F1C100s with a different DRAM chip co-packaged, directly use F1C100s DTSI here. This commit covers the v1.1 version of this board, which is now shipped. v1.0 is some internal sample that have not been shipped at all. Signed-off-by: Icenowy Zheng Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230319212936.26649-6-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/Makefile | 3 +- .../boot/dts/suniv-f1c200s-popstick-v1.1.dts | 81 +++++++++++++++++++ 2 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe4152e5846..3b97d7c1e3c2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1406,7 +1406,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb dtb-$(CONFIG_MACH_SUNIV) += \ - suniv-f1c100s-licheepi-nano.dtb + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-popstick-v1.1.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ tegra20-asus-tf101.dtb \ diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts new file mode 100644 index 000000000000..184c245041a6 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +#include +#include + +/ { + model = "Popcorn Computer PopStick v1.1"; + compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick", + "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */ + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pe_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From cc1858614f5d99d87d4467079c25f6bdf434add9 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 19 Mar 2023 21:29:36 +0000 Subject: [PATCH 0497/1040] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree The Lctech Pi F1C200s (also previously known under the Cherry Pi brand) is a small development board with the Allwinner F1C200s SoC. This is the same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM. Alongside the obligatory micro-SD card slot, the board features a SPI-NAND flash chip, LCD and touch connectors, and unpopulated expansion header pins. There are two USB Type-C ports on the board: One supplies the power, also connects to the USB MUSB OTG controller port. The other one is connected to an CH340 USB serial chip, which in turn is connected to UART1. Add a devicetree file, so that the board can be used easily. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230319212936.26649-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 ++ arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 76 +++++++++++++++++++ 3 files changed, 83 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3b97d7c1e3c2..a627d5593e51 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1407,6 +1407,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-cubieboard4.dtb dtb-$(CONFIG_MACH_SUNIV) += \ suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ suniv-f1c200s-popstick-v1.1.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 111f8bbc2a80..3c61d59ab5f8 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -207,6 +207,12 @@ pins = "PE0", "PE1"; function = "uart0"; }; + + /omit-if-no-ref/ + uart1_pa_pins: uart1-pa-pins { + pins = "PA2", "PA3"; + function = "uart1"; + }; }; i2c0: i2c@1c27000 { diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts new file mode 100644 index 000000000000..2d2a3f026df3 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Arm Ltd, + * based on work: + * Copyright 2022 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +#include + +/ { + model = "Lctech Pi F1C200s"; + compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s", + "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pa_pins>; + status = "okay"; +}; + +/* + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected + * to Vin, which supplies the board. Host mode works (if the board is powered + * otherwise), but peripheral is probably the intention. + */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; From 4367d763698c5c7c2c0e540f0508e48b337c7d8a Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 24 Mar 2023 10:47:44 +0100 Subject: [PATCH 0498/1040] arm64: dts: qcom: sc8280xp-x13s: enable alternate touchpad Enable both touchpad nodes in the devictree and let the HID driver determine which one is actually populated (by attempting to read from each i2c address). Ideally this would not be needed and the boot firmware should instead enable only the node for the populated touchpad, but this is unlikely to ever be realised for the X13s. Note that the pin configuration must currently be moved to the parent i2c-bus node even though only one of these nodes will ever be successfully probed on a specific device (e.g. to allow them to be probed in parallel). Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324094744.20448-1-johan+linaro@kernel.org --- .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 0d1e49ddd540..19d5ac6591fa 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -603,7 +603,7 @@ clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&i2c21_default>; + pinctrl-0 = <&i2c21_default>, <&tpad_default>; status = "okay"; @@ -616,12 +616,7 @@ vdd-supply = <&vreg_misc_3p3>; vddl-supply = <&vreg_s10b>; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; - wakeup-source; - - status = "disabled"; }; touchpad@2c { @@ -633,9 +628,6 @@ vdd-supply = <&vreg_misc_3p3>; vddl-supply = <&vreg_s10b>; - pinctrl-names = "default"; - pinctrl-0 = <&tpad_default>; - wakeup-source; }; From 74f9d27ac7591e0df05c85ca5eb538253f39919d Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Fri, 24 Mar 2023 10:18:53 +0800 Subject: [PATCH 0499/1040] soc: qcom: smsm: Use dev_err_probe() Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/202303241018532824420@zte.com.cn --- drivers/soc/qcom/smsm.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 8c137dff7dac..c58cfff64856 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -452,11 +452,10 @@ static int smsm_get_size_info(struct qcom_smsm *smsm) } *info; info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_SMSM_SIZE_INFO, &size); - if (IS_ERR(info) && PTR_ERR(info) != -ENOENT) { - if (PTR_ERR(info) != -EPROBE_DEFER) - dev_err(smsm->dev, "unable to retrieve smsm size info\n"); - return PTR_ERR(info); - } else if (IS_ERR(info) || size != sizeof(*info)) { + if (IS_ERR(info) && PTR_ERR(info) != -ENOENT) + return dev_err_probe(smsm->dev, PTR_ERR(info), + "unable to retrieve smsm size info\n"); + else if (IS_ERR(info) || size != sizeof(*info)) { dev_warn(smsm->dev, "no smsm size info, using defaults\n"); smsm->num_entries = SMSM_DEFAULT_NUM_ENTRIES; smsm->num_hosts = SMSM_DEFAULT_NUM_HOSTS; From af87ac738715d8877222b25829845589b25fe24c Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Fri, 24 Mar 2023 12:54:43 +0530 Subject: [PATCH 0500/1040] arm64: defconfig: Enable CAN PHY transceiver driver Enable CAN PHY transceiver driver to be built as a module which will add support for generic CAN transceivers used by TI K3 specific SoCs. Signed-off-by: Bhavya Kapoor Reviewed-by: Geert Uytterhoeven Reviewed-by: Bjorn Andersson Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..6e123de3a9cf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1292,6 +1292,7 @@ CONFIG_RESET_QCOM_PDC=m CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_RESET_TI_SCI=y CONFIG_PHY_XGENE=y +CONFIG_PHY_CAN_TRANSCEIVER=m CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_CADENCE_TORRENT=m CONFIG_PHY_CADENCE_SIERRA=m From c98a56395e7854f7975dd8539d0563e0ac7d060e Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 24 Mar 2023 10:28:48 +0100 Subject: [PATCH 0501/1040] arm64: dts: qcom: sm8450: remove invalid power-domain-names in pcie nodes Fixes the following DT bindings check error: pci@1c00000: Unevaluated properties are not allowed ('power-domain-names' were unexpected) Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-3-0ca1bea1a843@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d8f18e07383d..16a1fbb2b9da 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1798,7 +1798,6 @@ reset-names = "pci"; power-domains = <&gcc PCIE_0_GDSC>; - power-domain-names = "gdsc"; phys = <&pcie0_lane>; phy-names = "pciephy"; @@ -1912,7 +1911,6 @@ reset-names = "pci"; power-domains = <&gcc PCIE_1_GDSC>; - power-domain-names = "gdsc"; phys = <&pcie1_lane>; phy-names = "pciephy"; From e57430d2483506f046e39bf8c61159dde88aede2 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 24 Mar 2023 10:28:49 +0100 Subject: [PATCH 0502/1040] arm64: dts: qcom: sm8450: fix pcie1 gpios properties name Add the final "s" to the pgio properties and fix the invalid "enable" name to the correct "wake", checked against the HDK8450 schematics. Fixes: bc6588bc25fb ("arm64: dts: qcom: sm8450: add PCIe1 root device") Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-4-0ca1bea1a843@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 16a1fbb2b9da..08381fd3729d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1915,8 +1915,8 @@ phys = <&pcie1_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From 3dffd4755f41c4d603f1ae8533c7c8b04ed7f334 Mon Sep 17 00:00:00 2001 From: Ryan Roberts Date: Mon, 13 Feb 2023 10:16:33 +0000 Subject: [PATCH 0503/1040] arm64: defconfig: Enable Virtio RNG driver as built in Modern versions of FVP_Base_RevC-2xAEMvA contain a Virtio RNG device, use of which can dramatically speed up the time taken for Linux to initialize its CRNG, from 10s of seconds in some cases, to instant. This improves the debug cycle significantly. However, there are 2 barriers to getting people to use it. The first is that the defconfig doesn't have the required driver. The second is that the device is disabled in the device tree (for back-compat since older versions of the FVP don't have the device). Here we solve the first issue. Signed-off-by: Ryan Roberts Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6e123de3a9cf..0657fa46b71d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -463,6 +463,8 @@ CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=m CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y CONFIG_TCG_TPM=y CONFIG_TCG_TIS=m CONFIG_TCG_TIS_SPI=m From 704e26678c8d50d8988e30a47edddbb361e9e973 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:41 +0100 Subject: [PATCH 0504/1040] arm64: dts: qcom: apq8096-db820c: drop simple-bus from clocks 'clocks' node is not a bus, but just a placeholder for clocks: apq8096-db820c.dtb: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: dtschema/schemas/simple-bus.yaml apq8096-db820c.dtb: clocks: xo-board: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], ... From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 5ceaab5d4039..c965a8c81d9b 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -63,7 +63,6 @@ }; clocks { - compatible = "simple-bus"; divclk4: divclk4 { compatible = "fixed-clock"; #clock-cells = <0>; From 5574a5022df4cf67fdcf8c94bfbafb2cc296beee Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:42 +0100 Subject: [PATCH 0505/1040] arm64: dts: qcom: msm8994-msft-lumia: drop simple-bus from clocks 'clocks' node is not a bus, but just a placeholder for clocks: msm8992-msft-lumia-octagon-talkman.dtb: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: dtschema/schemas/simple-bus.yaml msm8992-msft-lumia-octagon-talkman.dtb: clocks: xo-board: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], ... From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 4520a7e86d5b..e9480c4208f6 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -46,8 +46,6 @@ }; clocks { - compatible = "simple-bus"; - divclk4: divclk4 { compatible = "fixed-clock"; #clock-cells = <0>; From 338958e30c6897b7978019b5ea3fa1897cd511ba Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:43 +0100 Subject: [PATCH 0506/1040] arm64: dts: qcom: msm8996-xiaomi: drop simple-bus from clocks 'clocks' node is not a bus, but just a placeholder for clocks: msm8996-xiaomi-gemini.dtb: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' From schema: dtschema/schemas/simple-bus.yaml msm8996-xiaomi-gemini.dtb: clocks: xo-board: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], ... From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 446b1d23dec0..1ce5df0a3405 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -12,8 +12,6 @@ / { clocks { - compatible = "simple-bus"; - divclk1_cdc: divclk1 { compatible = "gpio-gate-clock"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>; From a2e5260d07555834d14431399cefdd3220b917d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:44 +0100 Subject: [PATCH 0507/1040] arm64: dts: qcom: sdm630: move DSI opp-table into DSI node The soc node is supposed to have only device nodes with MMIO addresses, so move the DSI OPP into the DSI controller node to fix: sda660-inforce-ifc6560.dtb: soc: opp-table-dsi: {'compatible': ['operating-points-v2'], ... should not be valid under {'type': 'object'} From schema: dtschema/schemas/simple-bus.yaml Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 38 ++++++++++++++-------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 72d9a12b5e9c..8bdb36a63474 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1450,25 +1450,6 @@ <0>; }; - dsi_opp_table: opp-table-dsi { - compatible = "operating-points-v2"; - - opp-131250000 { - opp-hz = /bits/ 64 <131250000>; - required-opps = <&rpmpd_opp_svs>; - }; - - opp-210000000 { - opp-hz = /bits/ 64 <210000000>; - required-opps = <&rpmpd_opp_svs_plus>; - }; - - opp-262500000 { - opp-hz = /bits/ 64 <262500000>; - required-opps = <&rpmpd_opp_nom>; - }; - }; - mdss: display-subsystem@c900000 { compatible = "qcom,mdss"; reg = <0x0c900000 0x1000>, @@ -1610,6 +1591,25 @@ status = "disabled"; + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-262500000 { + opp-hz = /bits/ 64 <262500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; From 92f87bcbb24aebe07b711b96c9e50031b97d4c98 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 9 Mar 2023 21:45:55 +0100 Subject: [PATCH 0508/1040] arm64: dts: imx8mq-librem5: lower the mipi csi 1 frequencies No frames are streamed when using the default frequencies. I'm not yet sure why the fastest ones don't work here but we've been using these frequencies successfully for a long time now. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 6895bcc12165..c81cf3e6582b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1143,6 +1143,7 @@ }; &mipi_csi1 { + assigned-clock-rates = <266000000>, <200000000>, <66000000>; status = "okay"; ports { From 0a8381160244513203900f04c5f5bbd00a04ebb6 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 9 Mar 2023 21:45:56 +0100 Subject: [PATCH 0509/1040] arm64: dts: imx8mq-librem5: describe the clock for the csi sensors The CLKO2 clock is used for both camera CSI interfaces as the driving clock for the connected sensors. In order for it to be available, use this hog. We can't simply add it to 2 different sensor descriptions. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index c81cf3e6582b..fd1f6fb6d6f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -371,6 +371,16 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + /* CLKO2 for cameras on both CSI1 and CSI2 */ + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f + >; + }; + pinctrl_audiopwr: audiopwrgrp { fsl,pins = < /* AUDIO_POWER_EN_3V3 */ From 969fe9113531ee8d71796481b2ec0c01cfc9793f Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 9 Mar 2023 21:45:57 +0100 Subject: [PATCH 0510/1040] arm64: dts: imx8mq-librem5: fix audio-1v8 regulator name Fix the regulator name for the audio-1v8 regulator. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index fd1f6fb6d6f6..6c44af94ac02 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -84,7 +84,7 @@ compatible = "regulator-fixed"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audiopwr>; - regulator-name = "AUDIO_PWR_EN"; + regulator-name = "AUD_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; From 5d24b9017fe3e80f804d9a51925f2c7acf51fb72 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:45:58 +0100 Subject: [PATCH 0511/1040] arm64: dts: imx8mq-librem5: Describe MIC_2V4 regulator No functional change, but it describes the hardware better. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 6c44af94ac02..9f374da5c18a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -91,6 +91,14 @@ enable-active-high; }; + reg_mic_2v4: regulator-mic-2v4 { + compatible = "regulator-fixed"; + regulator-name = "MIC_2V4"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <2400000>; + vin-supply = <®_aud_1v8>; + }; + /* * the pinctrl for reg_csi_1v8 and reg_vcam_1v8 is added to the PMIC * since we can't have it twice in the 2 different regulator nodes. @@ -1033,7 +1041,7 @@ DBVDD-supply = <®_aud_1v8>; AVDD-supply = <®_aud_1v8>; CPVDD-supply = <®_aud_1v8>; - MICVDD-supply = <®_aud_1v8>; + MICVDD-supply = <®_mic_2v4>; PLLVDD-supply = <®_aud_1v8>; SPKVDD1-supply = <®_vsys_3v4>; SPKVDD2-supply = <®_vsys_3v4>; From 956fdfe744c9473c51b5270cbdfb087eed0c9717 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Thu, 9 Mar 2023 21:45:59 +0100 Subject: [PATCH 0512/1040] arm64: dts: imx8mq-librem5: add brightness levels to led-backlight Add brightness-levels and default-brightness-level properties to the librem5 board description that have been used for a long time. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 9f374da5c18a..f8698b699534 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -20,6 +20,8 @@ backlight_dsi: backlight-dsi { compatible = "led-backlight"; leds = <&led_backlight>; + brightness-levels = <255>; + default-brightness-level = <190>; }; pmic_osc: clock-pmic { From 41d208c4c8dd64c5cf0c8ec9879bacd97b0755d7 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:00 +0100 Subject: [PATCH 0513/1040] arm64: dts: imx8mq-librem5: Set charger parameters for each batch Correctly set regulation-voltage, termination-current and charge-current for the different librem 5 board revisions. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts | 10 ++++------ arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi | 2 -- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 +++- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts index 73bd431cbd6a..4f69eb32b1c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts @@ -12,18 +12,16 @@ compatible = "purism,librem5r2", "purism,librem5", "fsl,imx8mq"; }; -&bq25895 { - ti,battery-regulation-voltage = <4192000>; /* uV */ - ti,charge-current = <1600000>; /* uA */ - ti,termination-current = <66000>; /* uA */ -}; - &accel_gyro { mount-matrix = "1", "0", "0", "0", "-1", "0", "0", "0", "1"; }; +&bq25895 { + ti,charge-current = <1600000>; /* uA */ +}; + &proximity { proximity-near-level = <120>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi index e4f8b47cce4f..c1279e96effd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -22,9 +22,7 @@ }; &bq25895 { - ti,battery-regulation-voltage = <4200000>; /* uV */ ti,charge-current = <1500000>; /* uA */ - ti,termination-current = <144000>; /* uA */ }; &camera_front { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index f8698b699534..509776a63259 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1147,7 +1147,9 @@ interrupt-parent = <&gpio3>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; phys = <&usb3_phy0>; - ti,precharge-current = <130000>; /* uA */ + ti,battery-regulation-voltage = <4208000>; /* uV */ + ti,termination-current = <128000>; /* uA */ + ti,precharge-current = <128000>; /* uA */ ti,minimum-sys-voltage = <3700000>; /* uV */ ti,boost-voltage = <5000000>; /* uV */ ti,boost-max-current = <1500000>; /* uA */ From c24a9b698fb02cd0723fa8375abab07f94b97b10 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:01 +0100 Subject: [PATCH 0514/1040] arm64: dts: imx8mq-librem5: Set the DVS voltages lower They're still in the operating range according to i.MX 8M Quad datasheet. There's some headroom added over minimal values to account for voltage drop. Operational ranges (min - typ - max [selected]): - VDD_SOC (BUCK1): 0.81 - 0.9 - 0.99 [0.88] - VDD_ARM (BUCK2): 0.81 - 0.9 - 1.05 [0.84] (1000MHz) 0.90 - 1.0 - 1.05 [0.93] (1500MHz) - VDD_GPU (BUCK3): 0.81 - 0.9 - 1.05 [0.85] (800MHz) 0.90 - 1.0 - 1.05 [ -- ] (1000MHz) - VDD_VPU (BUCK4): 0.81 - 0.9 - 1.05 [ -- ] (550/500/588MHz) 0.90 - 1.0 - 1.05 [0.93] (660/600/800MHz) Idle power consumption doesn't appear to be influenced much, but a simple load test (`cat /dev/urandom | pigz - > /dev/null` combined with running Animatch) seems to show about 0.3W of difference. Care is advised, as there may be differences between each units in how low can they be undervolted - in my experience, reaching that point usually makes the phone fail to boot. In my case, it appears that my Birch phone can go down the most. This is a somewhat conservative set of values that I've seen working well on all my devices; I haven't tried very hard to optimize it, so more experiments are welcome. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5-r3.dts | 2 +- .../boot/dts/freescale/imx8mq-librem5.dtsi | 22 ++++++++++++++----- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts index 4533a84fb0b9..077c5cd2586f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dts @@ -7,7 +7,7 @@ &a53_opp_table { opp-1000000000 { - opp-microvolt = <1000000>; + opp-microvolt = <950000>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 509776a63259..eaf35cff2f8a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -839,8 +839,8 @@ regulator-max-microvolt = <1300000>; regulator-boot-on; regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <900000>; - rohm,dvs-idle-voltage = <850000>; + rohm,dvs-run-voltage = <880000>; + rohm,dvs-idle-voltage = <820000>; rohm,dvs-suspend-voltage = <800000>; regulator-always-on; }; @@ -851,8 +851,8 @@ regulator-max-microvolt = <1300000>; regulator-boot-on; regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; + rohm,dvs-run-voltage = <950000>; + rohm,dvs-idle-voltage = <850000>; regulator-always-on; }; @@ -861,14 +861,14 @@ regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; - rohm,dvs-run-voltage = <900000>; + rohm,dvs-run-voltage = <850000>; }; buck4_reg: BUCK4 { regulator-name = "buck4"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; - rohm,dvs-run-voltage = <1000000>; + rohm,dvs-run-voltage = <930000>; }; buck5_reg: BUCK5 { @@ -1403,3 +1403,13 @@ fsl,ext-reset-output; status = "okay"; }; + +&a53_opp_table { + opp-1000000000 { + opp-microvolt = <850000>; + }; + + opp-1500000000 { + opp-microvolt = <950000>; + }; +}; From a27f81d3d59350a196c3c7bfba4a9f45cbacc7ae Mon Sep 17 00:00:00 2001 From: Angus Ainslie Date: Thu, 9 Mar 2023 21:46:02 +0100 Subject: [PATCH 0515/1040] arm64: dts: imx8mq-librem5: add the magnetometer mount matrix Userland needs the mount matrix to know the correct orientation of the part. Signed-off-by: Angus Ainslie Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi index c1279e96effd..db81ed699de7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -38,6 +38,12 @@ }; }; +&magnetometer { + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; +}; + &proximity { proximity-near-level = <25>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index eaf35cff2f8a..7e470135b86a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -981,7 +981,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - magnetometer@1e { + magnetometer: magnetometer@1e { compatible = "st,lsm9ds1-magn"; reg = <0x1e>; pinctrl-names = "default"; From 536612ec0df77d521a359f3a186254cec3880c23 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:03 +0100 Subject: [PATCH 0516/1040] arm64: dts: imx8mq-librem5: Bump usdhc2 frequency to 100MHz RS9116 card already limits itself to 50MHz by being a high-speed card, while AP6275S can work at 100MHz just fine (technically it should work at 200MHz as well since it's a SDR104 card, but it doesn't appear to be the case in practice and further research will be needed to find out why). Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 7e470135b86a..0b4b49fa1392 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1389,7 +1389,7 @@ mmc-pwrseq = <&usdhc2_pwrseq>; post-power-on-delay-ms = <1000>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - max-frequency = <50000000>; + max-frequency = <100000000>; disable-wp; cap-sdio-irq; keep-power-in-suspend; From e0faf4c53c23b03d03ed8ad3eef76a39c587bb9e Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:04 +0100 Subject: [PATCH 0517/1040] arm64: dts: imx8mq-librem5: Adjust proximity sensor's near levels Based on tests with my left ear (which appears to require lower levels than the right one), one Birch, one Dogwood and three Evergreens. It seems that the sensor reacts very weakly to hair, so let's make the thresholds rather generous to compensate. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts index 4f69eb32b1c9..2b3d437a642a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts @@ -23,5 +23,5 @@ }; &proximity { - proximity-near-level = <120>; + proximity-near-level = <50>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi index db81ed699de7..7fd0176e4bd3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -45,5 +45,5 @@ }; &proximity { - proximity-near-level = <25>; + proximity-near-level = <10>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts index 1056b7981bdb..97577c0a7715 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts @@ -23,5 +23,5 @@ }; &proximity { - proximity-near-level = <10>; + proximity-near-level = <5>; }; From cfe9de291bd2bbce18c5cd79e1dd582cbbacdb4f Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:05 +0100 Subject: [PATCH 0518/1040] arm64: dts: imx8mq-librem5: Remove dis_u3_susphy_quirk from usb_dwc3_0 This reduces power consumption in system suspend by about 10%. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 0b4b49fa1392..f557632f574f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1322,7 +1322,6 @@ #address-cells = <1>; #size-cells = <0>; dr_mode = "otg"; - snps,dis_u3_susphy_quirk; usb-role-switch; status = "okay"; From 94b91e3ca6688fafd6a5dd70bd89fe9d3aee88da Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:06 +0100 Subject: [PATCH 0519/1040] arm64: dts: imx8mq-librem5: Bump BUCK1 suspend voltage to 0.81V 0.8V is outside of the operating voltage specified for imx8mq, see chapter 3.1.4 "Operating ranges" of the IMX8MDQLQCEC document. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index f557632f574f..7e70663cffa3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -841,7 +841,7 @@ regulator-ramp-delay = <1250>; rohm,dvs-run-voltage = <880000>; rohm,dvs-idle-voltage = <820000>; - rohm,dvs-suspend-voltage = <800000>; + rohm,dvs-suspend-voltage = <810000>; regulator-always-on; }; From ea06362f80a11a738e8e11309923fb755471a7ae Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:07 +0100 Subject: [PATCH 0520/1040] arm64: dts: imx8mq-librem5: Reduce I2C frequency to 384kHz According to imx8mq errata (ERR007805): > To meet the clock low period requirement in fast speed mode, > SCL must be configured to 384KHz or less. Note that the imx i2c driver already implements this erratum and works around it. This is only for the description to reflect reality. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 7e70663cffa3..35bde8d41e8e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -778,7 +778,7 @@ }; &i2c1 { - clock-frequency = <387000>; + clock-frequency = <384000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; @@ -976,7 +976,7 @@ }; &i2c2 { - clock-frequency = <387000>; + clock-frequency = <384000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; @@ -1025,7 +1025,7 @@ }; &i2c3 { - clock-frequency = <387000>; + clock-frequency = <384000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; @@ -1115,7 +1115,7 @@ }; &i2c4 { - clock-frequency = <387000>; + clock-frequency = <384000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; From 62669328294a337a5a3cb878e098b5d27295e098 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Thu, 9 Mar 2023 21:46:08 +0100 Subject: [PATCH 0521/1040] arm64: dts: imx8mq-librem5: Add 166MHz to DDRC OPP table This is the lowest frequency supported by older iMX8MQ SoC revisions. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 35bde8d41e8e..ceced6bc4e89 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -329,6 +329,10 @@ opp-hz = /bits/ 64 <100000000>; }; + opp-166000000 { + opp-hz = /bits/ 64 <166935483>; + }; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; }; From 816aec03a043af6d0234c3e770bead2c772ef4eb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 13 Mar 2023 08:49:03 +0800 Subject: [PATCH 0522/1040] soc: imx: imx8m-blk-ctrl: reordering the fields The clang-analyzer reports: "Excessive padding in 'struct imx8m_blk_ctrl_domain_data' (12 padding bytes, where 4 is optimal). Optimal fields order: name, clk_names, path_names, gpc_name, num_clks, num_paths, rst_mask, clk_mask, mipi_phy_rst_mask, consider reordering the fields or adding explicit padding members [clang-analyzer-optin.performance.Padding] struct imx8m_blk_ctrl_domain_data {" So reordering the fields. Reported-by: kernel test robot Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 9129c97b7a01..afbca0d48c14 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -38,10 +38,10 @@ struct imx8m_blk_ctrl { struct imx8m_blk_ctrl_domain_data { const char *name; const char * const *clk_names; - int num_clks; const char * const *path_names; - int num_paths; const char *gpc_name; + int num_clks; + int num_paths; u32 rst_mask; u32 clk_mask; From fc226f865c05a6a0e1d4f4166ba9d4ceb27e7550 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:06 +0100 Subject: [PATCH 0523/1040] dt-bindings: arm: fsl: Add colibri-imx8x carrier boards Prepare the dt-bindings for the new colibri-imx8x carrier-boards Aster and Iris. The Toradex SoM standard is called Colibri, fix the typo. Signed-off-by: Philippe Schenker Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 67a325ed5794..2285c8d65a58 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1154,10 +1154,13 @@ properties: - fsl,imx8dxl-evk # i.MX8DXL EVK Board - const: fsl,imx8dxl - - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules + - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules items: - enum: + - toradex,colibri-imx8x-aster # Colibri iMX8X Module on Aster Board - toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3 + - toradex,colibri-imx8x-iris # Colibri iMX8X Module on Iris Board + - toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2 - const: toradex,colibri-imx8x - const: fsl,imx8qxp From 2eba243813e27a8654ec4df15b208b2a321bb5b2 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:47 +0100 Subject: [PATCH 0524/1040] arm64: dts: colibri-imx8x: Prepare for qxp and dx variants Toradex sells the Colibri iMX8X module in variants with the i.MX 8QXP and i.MX8DX SoC. Prepare for this by moving majority of stuff from imx8qxp-colibri.dtsi into imx8x-colibri.dtsi. Remove DX from the model string. This commit intends no functional change. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../dts/freescale/imx8qxp-colibri-eval-v3.dts | 4 +- .../boot/dts/freescale/imx8qxp-colibri.dtsi | 590 +---------------- ...val-v3.dtsi => imx8x-colibri-eval-v3.dtsi} | 0 .../boot/dts/freescale/imx8x-colibri.dtsi | 593 ++++++++++++++++++ 4 files changed, 597 insertions(+), 590 deletions(-) rename arch/arm64/boot/dts/freescale/{imx8qxp-colibri-eval-v3.dtsi => imx8x-colibri-eval-v3.dtsi} (100%) create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts index 6b21a295c126..413a9e9d6c28 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts @@ -6,10 +6,10 @@ /dts-v1/; #include "imx8qxp-colibri.dtsi" -#include "imx8qxp-colibri-eval-v3.dtsi" +#include "imx8x-colibri-eval-v3.dtsi" / { - model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; + model = "Toradex Colibri iMX8QXP on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx8x-eval-v3", "toradex,colibri-imx8x", "fsl,imx8qxp"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi index 89d70e030433..1ffc42f4a4b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -4,595 +4,9 @@ */ #include "imx8qxp.dtsi" +#include "imx8x-colibri.dtsi" / { - model = "Toradex Colibri iMX8QXP/DX Module"; + model = "Toradex Colibri iMX8QXP Module"; compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; - - chosen { - stdout-path = &lpuart3; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -/* On-module I2C */ -&i2c0 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; - status = "okay"; - - /* Touch controller */ - touchscreen@2c { - compatible = "adi,ad7879-1"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ad7879_int>; - reg = <0x2c>; - interrupt-parent = <&lsio_gpio3>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - }; -}; - -/* Colibri I2C */ -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; -}; - -/* Colibri UART_B */ -&lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; -}; - -/* Colibri UART_C */ -&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; -}; - -/* Colibri UART_A */ -&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; -}; - -/* Colibri FastEthernet */ -&fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-1 = <&pinctrl_fec1_sleep>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <2>; - }; - }; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - non-removable; - no-sd; - no-sdio; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Colibri SD/MMC Card */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_module_3v3>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - disable-wp; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>; - - /* On-module touch pen-down interrupt */ - pinctrl_ad7879_int: ad7879intgrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 - >; - }; - - /* Colibri Analogue Inputs */ - pinctrl_adc0: adc0grp { - fsl,pins = < - IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ - IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ - IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ - IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ - >; - }; - - pinctrl_can_int: canintgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ - >; - }; - - pinctrl_csi_ctl: csictlgrp { - fsl,pins = < - IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ - IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ - >; - }; - - pinctrl_ext_io0: extio0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ - >; - }; - - /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 - >; - }; - - pinctrl_fec1_sleep: fec1slpgrp { - fsl,pins = < - IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 - IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 - IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 - IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 - IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 - IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 - IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 - IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 - IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 - IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 - >; - }; - - /* Colibri optional CAN on UART_B RTS/CTS */ - pinctrl_flexcan1: flexcan0grp { - fsl,pins = < - IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ - IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ - >; - }; - - /* Colibri optional CAN on PS2 */ - pinctrl_flexcan2: flexcan1grp { - fsl,pins = < - IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ - IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ - >; - }; - - /* Colibri optional CAN on UART_A TXD/RXD */ - pinctrl_flexcan3: flexcan2grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ - IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ - >; - }; - - /* Colibri LCD Back-Light GPIO */ - pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ - >; - }; - - pinctrl_hog0: hog0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ - IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ - IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ - IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ - IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ - IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ - IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ - IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ - IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ - IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ - IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ - IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ - IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ - IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ - IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ - IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ - IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ - IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ - IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ - IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ - IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ - IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ - IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ - IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ - IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ - >; - }; - - pinctrl_hog1: hog1grp { - fsl,pins = < - IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ - IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ - >; - }; - - /* - * This pin is used in the SCFW as a UART. Using it from - * Linux would require rewritting the SCFW board file. - */ - pinctrl_hog_scfw: hogscfwgrp { - fsl,pins = < - IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ - >; - }; - - /* On Module I2C */ - pinctrl_i2c0: i2c0grp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 - IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 - >; - }; - - /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ - pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ - IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ - >; - }; - - /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ - pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ - IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ - >; - }; - - /* Colibri I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ - IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ - >; - }; - - /* Colibri Parallel RGB LCD Interface */ - pinctrl_lcdif: lcdifgrp { - fsl,pins = < - IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ - IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ - IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ - IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ - IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ - IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ - IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ - IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ - IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ - IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ - IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ - IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ - IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ - IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ - IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ - IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ - IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ - IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ - IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ - IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ - IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ - IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ - IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ - IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ - >; - }; - - /* Colibri SPI */ - pinctrl_lpspi2: lpspi2grp { - fsl,pins = < - IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ - IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ - IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ - IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ - >; - }; - - /* Colibri UART_B */ - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ - >; - }; - - /* Colibri UART_C */ - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ - IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ - >; - }; - - /* Colibri UART_A */ - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ - >; - }; - - /* Colibri UART_A Control */ - pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ - IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ - IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ - IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ - IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ - >; - }; - - /* On module wifi module */ - pinctrl_pcieb: pciebgrp { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ - IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ - IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ - >; - }; - - /* Colibri PWM_A */ - pinctrl_pwm_a: pwmagrp { - /* both pins are connected together, reserve the unused CSI_D05 */ - fsl,pins = < - IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ - IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ - >; - }; - - /* Colibri PWM_B */ - pinctrl_pwm_b: pwmbgrp { - fsl,pins = < - IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ - >; - }; - - /* Colibri PWM_C */ - pinctrl_pwm_c: pwmcgrp { - fsl,pins = < - IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ - >; - }; - - /* Colibri PWM_D */ - pinctrl_pwm_d: pwmdgrp { - /* both pins are connected together, reserve the unused CSI_D04 */ - fsl,pins = < - IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ - IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ - >; - }; - - /* On-module I2S */ - pinctrl_sai0: sai0grp { - fsl,pins = < - IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 - IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 - IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 - IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 - >; - }; - - /* Colibri Audio Analogue Microphone GND */ - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - /* MIC GND EN */ - IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 - >; - }; - - /* On-module SGTL5000 clock */ - pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { - fsl,pins = < - IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 - >; - }; - - /* On-module USB interrupt */ - pinctrl_usb3503a: usb3503agrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 - >; - }; - - /* Colibri USB Client Cable Detect */ - pinctrl_usbc_det: usbcdetgrp { - fsl,pins = < - IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ - >; - }; - - /* USB Host Power Enable */ - pinctrl_usbh1_reg: usbh1reggrp { - fsl,pins = < - IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* Colibri SD/MMC Card Detect */ - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ - >; - }; - - /* Colibri SD/MMC Card */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_wifi: wifigrp { - fsl,pins = < - IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 - >; - }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi similarity index 100% rename from arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi rename to arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi new file mode 100644 index 000000000000..cb22bde19ea0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -0,0 +1,593 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/ { + chosen { + stdout-path = &lpuart3; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; + status = "okay"; + + /* Touch controller */ + touchscreen@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; +}; + +/* Colibri I2C */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; +}; + +/* Colibri UART_B */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Colibri UART_C */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Colibri UART_A */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; +}; + +/* Colibri FastEthernet */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Colibri SD/MMC Card */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_module_3v3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + disable-wp; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>; + + /* On-module touch pen-down interrupt */ + pinctrl_ad7879_int: ad7879intgrp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 + >; + }; + + /* Colibri Analogue Inputs */ + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ + IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ + IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ + IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ + >; + }; + + pinctrl_can_int: canintgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ + >; + }; + + pinctrl_csi_ctl: csictlgrp { + fsl,pins = < + IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ + IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ + >; + }; + + pinctrl_ext_io0: extio0grp { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ + >; + }; + + /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 + >; + }; + + pinctrl_fec1_sleep: fec1slpgrp { + fsl,pins = < + IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 + IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 + IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 + IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 + IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 + IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 + IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 + IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 + IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 + IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 + >; + }; + + /* Colibri optional CAN on UART_B RTS/CTS */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ + >; + }; + + /* Colibri optional CAN on PS2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ + >; + }; + + /* Colibri optional CAN on UART_A TXD/RXD */ + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ + >; + }; + + /* Colibri LCD Back-Light GPIO */ + pinctrl_gpio_bl_on: gpioblongrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ + IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ + IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ + IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ + IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ + IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ + IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ + IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ + IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ + IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ + IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ + IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ + IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ + IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ + IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ + IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ + IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ + IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ + IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ + IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ + IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ + IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ + IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ + IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ + IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ + IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ + IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ + >; + }; + + /* + * This pin is used in the SCFW as a UART. Using it from + * Linux would require rewritting the SCFW board file. + */ + pinctrl_hog_scfw: hogscfwgrp { + fsl,pins = < + IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ + >; + }; + + /* On Module I2C */ + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 + IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 + >; + }; + + /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ + pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ + >; + }; + + /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ + pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ + >; + }; + + /* Colibri I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ + IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ + >; + }; + + /* Colibri Parallel RGB LCD Interface */ + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ + IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ + IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ + >; + }; + + /* Colibri SPI */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ + >; + }; + + /* Colibri UART_B */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ + IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ + IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ + >; + }; + + /* Colibri UART_C */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ + >; + }; + + /* Colibri UART_A */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ + >; + }; + + /* Colibri UART_A Control */ + pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ + IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ + IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ + >; + }; + + /* On module wifi module */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ + >; + }; + + /* Colibri PWM_A */ + pinctrl_pwm_a: pwmagrp { + /* both pins are connected together, reserve the unused CSI_D05 */ + fsl,pins = < + IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ + IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ + >; + }; + + /* Colibri PWM_B */ + pinctrl_pwm_b: pwmbgrp { + fsl,pins = < + IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ + >; + }; + + /* Colibri PWM_C */ + pinctrl_pwm_c: pwmcgrp { + fsl,pins = < + IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ + >; + }; + + /* Colibri PWM_D */ + pinctrl_pwm_d: pwmdgrp { + /* both pins are connected together, reserve the unused CSI_D04 */ + fsl,pins = < + IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ + IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ + >; + }; + + /* On-module I2S */ + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + /* Colibri Audio Analogue Microphone GND */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + /* MIC GND EN */ + IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 + >; + }; + + /* On-module SGTL5000 clock */ + pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { + fsl,pins = < + IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module USB interrupt */ + pinctrl_usb3503a: usb3503agrp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 + >; + }; + + /* Colibri USB Client Cable Detect */ + pinctrl_usbc_det: usbcdetgrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ + >; + }; + + /* USB Host Power Enable */ + pinctrl_usbh1_reg: usbh1reggrp { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* Colibri SD/MMC Card Detect */ + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ + >; + }; + + /* Colibri SD/MMC Card */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; +}; From e8f7a387017da912f56317252c9da64a3188a55f Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:48 +0100 Subject: [PATCH 0525/1040] arm64: dts: colibri-imx8x: Update spdx license GPL-2.0+ is deprecated, update it to GPL-2.0-or-later. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts | 2 +- arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts index 413a9e9d6c28..fe4597a6f7e0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2019 Toradex */ diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi index 1ffc42f4a4b3..0f1aa31dd3e5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2019 Toradex */ diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi index 7c334b93db3b..dc0339b35a3c 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2019 Toradex */ diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index cb22bde19ea0..12056b77d22e 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright 2019 Toradex */ From 7efa409ed64847b72633573f9783b7b36da7e44a Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:49 +0100 Subject: [PATCH 0526/1040] arm64: dts: colibri-imx8x: Use new bracket format Use the new bracket format as described by Rob since this seems the format that we're heading in the future. https://lore.kernel.org/all/CAL_JsqKqQdRZC08-BGJqTjzJZ8aWA41LHMbv0QyyVePVm0co7A@mail.gmail.com/ Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8x-colibri.dtsi | 497 +++++++----------- 1 file changed, 202 insertions(+), 295 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 12056b77d22e..4e0d5762b76c 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -123,144 +123,116 @@ /* On-module touch pen-down interrupt */ pinctrl_ad7879_int: ad7879intgrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 - >; + fsl,pins = ; }; /* Colibri Analogue Inputs */ pinctrl_adc0: adc0grp { - fsl,pins = < - IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ - IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ - IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ - IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ - >; + fsl,pins = , /* SODIMM 8 */ + , /* SODIMM 6 */ + , /* SODIMM 4 */ + ; /* SODIMM 2 */ }; pinctrl_can_int: canintgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ - >; + fsl,pins = ; /* SODIMM 73 */ }; pinctrl_csi_ctl: csictlgrp { - fsl,pins = < - IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ - IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ - >; + fsl,pins = , /* SODIMM 77 */ + ; /* SODIMM 89 */ }; pinctrl_ext_io0: extio0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ - >; + fsl,pins = ; /* SODIMM 135 */ }; /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 - >; + fsl,pins = , + , + , + , + , + , + , + , + , + ; }; pinctrl_fec1_sleep: fec1slpgrp { - fsl,pins = < - IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 - IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 - IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 - IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 - IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 - IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 - IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 - IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 - IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 - IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 - >; + fsl,pins = , + , + , + , + , + , + , + , + , + ; }; /* Colibri optional CAN on UART_B RTS/CTS */ pinctrl_flexcan1: flexcan0grp { - fsl,pins = < - IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ - IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ - >; + fsl,pins = , /* SODIMM 32 */ + ; /* SODIMM 34 */ }; /* Colibri optional CAN on PS2 */ pinctrl_flexcan2: flexcan1grp { - fsl,pins = < - IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ - IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ - >; + fsl,pins = , /* SODIMM 55 */ + ; /* SODIMM 63 */ }; /* Colibri optional CAN on UART_A TXD/RXD */ pinctrl_flexcan3: flexcan2grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ - IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ - >; + fsl,pins = , /* SODIMM 35 */ + ; /* SODIMM 33 */ }; /* Colibri LCD Back-Light GPIO */ pinctrl_gpio_bl_on: gpioblongrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ - >; + fsl,pins = ; /* SODIMM 71 */ }; pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ - >; + fsl,pins = ; /* SODIMM 45 */ }; pinctrl_hog0: hog0grp { - fsl,pins = < - IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ - IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ - IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ - IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ - IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ - IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ - IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ - IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ - IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ - IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ - IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ - IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ - IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ - IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ - IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ - IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ - IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ - IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ - IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ - IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ - IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ - IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ - IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ - IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ - IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ - >; + fsl,pins = , /* SODIMM 65 */ + , /* SODIMM 65 */ + , /* SODIMM 69 */ + , /* SODIMM 79 */ + , /* SODIMM 79 */ + , /* SODIMM 85 */ + , /* SODIMM 85 */ + , /* SODIMM 95 */ + , /* SODIMM 97 */ + , /* SODIMM 97 */ + , /* SODIMM 99 */ + , /* SODIMM 101 */ + , /* SODIMM 101 */ + , /* SODIMM 103 */ + , /* SODIMM 103 */ + , /* SODIMM 105 */ + , /* SODIMM 107 */ + , /* SODIMM 127 */ + , /* SODIMM 131 */ + , /* SODIMM 133 */ + , /* SODIMM 96 */ + , /* SODIMM 98 */ + , /* SODIMM 100 */ + , /* SODIMM 102 */ + , /* SODIMM 104 */ + ; /* SODIMM 106 */ }; pinctrl_hog1: hog1grp { - fsl,pins = < - IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ - IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ - >; + fsl,pins = , /* SODIMM 75 */ + ; /* SODIMM 93 */ }; /* @@ -268,326 +240,261 @@ * Linux would require rewritting the SCFW board file. */ pinctrl_hog_scfw: hogscfwgrp { - fsl,pins = < - IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ - >; + fsl,pins = ; /* SODIMM 144 */ }; /* On Module I2C */ pinctrl_i2c0: i2c0grp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 - IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 - >; + fsl,pins = , + ; }; /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ - IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ - >; + fsl,pins = , /* SODIMM 140 */ + ; /* SODIMM 142 */ }; /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ - IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ - >; + fsl,pins = , /* SODIMM 186 */ + ; /* SODIMM 188 */ }; /* Colibri I2C */ pinctrl_i2c1: i2c1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ - IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ - >; + fsl,pins = , /* SODIMM 196 */ + ; /* SODIMM 194 */ }; /* Colibri Parallel RGB LCD Interface */ pinctrl_lcdif: lcdifgrp { - fsl,pins = < - IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ - IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ - IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ - IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ - IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ - IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ - IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ - IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ - IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ - IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ - IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ - IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ - IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ - IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ - IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ - IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ - IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ - IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ - IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ - IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ - IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ - IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ - IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ - IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ - >; + fsl,pins = , /* SODIMM 56 */ + , /* SODIMM 68 */ + , /* SODIMM 82 */ + , /* SODIMM 44 */ + , /* SODIMM 44 */ + , /* SODIMM 76 */ + , /* SODIMM 76 */ + , /* SODIMM 70 */ + , /* SODIMM 60 */ + , /* SODIMM 58 */ + , /* SODIMM 78 */ + , /* SODIMM 72 */ + , /* SODIMM 80 */ + , /* SODIMM 46 */ + , /* SODIMM 62 */ + , /* SODIMM 48 */ + , /* SODIMM 74 */ + , /* SODIMM 50 */ + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 66 */ + , /* SODIMM 64 */ + , /* SODIMM 57 */ + , /* SODIMM 57 */ + ; /* SODIMM 61 */ }; /* Colibri SPI */ pinctrl_lpspi2: lpspi2grp { - fsl,pins = < - IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ - IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ - IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ - IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ - >; + fsl,pins = , /* SODIMM 86 */ + , /* SODIMM 92 */ + , /* SODIMM 90 */ + ; /* SODIMM 88 */ }; /* Colibri UART_B */ pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ - >; + fsl,pins = , /* SODIMM 36 */ + , /* SODIMM 38 */ + , /* SODIMM 34 */ + ; /* SODIMM 32 */ }; /* Colibri UART_C */ pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ - IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ - >; + fsl,pins = , /* SODIMM 19 */ + ; /* SODIMM 21 */ }; /* Colibri UART_A */ pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ - >; + fsl,pins = , /* SODIMM 33 */ + ; /* SODIMM 35 */ }; /* Colibri UART_A Control */ pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ - IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ - IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ - IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ - IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ - >; + fsl,pins = , /* SODIMM 23 */ + , /* SODIMM 25 */ + , /* SODIMM 27 */ + , /* SODIMM 29 */ + , /* SODIMM 31 */ + ; /* SODIMM 37 */ }; /* On module wifi module */ pinctrl_pcieb: pciebgrp { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ - IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ - IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ - >; + fsl,pins = , /* SODIMM 178 */ + , /* SODIMM 94 */ + ; /* SODIMM 81 */ }; /* Colibri PWM_A */ pinctrl_pwm_a: pwmagrp { /* both pins are connected together, reserve the unused CSI_D05 */ - fsl,pins = < - IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ - IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ - >; + fsl,pins = , /* SODIMM 59 */ + ; /* SODIMM 59 */ }; /* Colibri PWM_B */ pinctrl_pwm_b: pwmbgrp { - fsl,pins = < - IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ - >; + fsl,pins = ; /* SODIMM 28 */ }; /* Colibri PWM_C */ pinctrl_pwm_c: pwmcgrp { - fsl,pins = < - IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ - >; + fsl,pins = ; /* SODIMM 30 */ }; /* Colibri PWM_D */ pinctrl_pwm_d: pwmdgrp { /* both pins are connected together, reserve the unused CSI_D04 */ - fsl,pins = < - IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ - IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ - >; + fsl,pins = , /* SODIMM 67 */ + ; /* SODIMM 67 */ }; /* On-module I2S */ pinctrl_sai0: sai0grp { - fsl,pins = < - IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 - IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 - IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 - IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 - >; + fsl,pins = , + , + , + ; }; /* Colibri Audio Analogue Microphone GND */ pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - /* MIC GND EN */ - IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 - >; + fsl,pins = ; }; /* On-module SGTL5000 clock */ pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp { - fsl,pins = < - IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 - >; + fsl,pins = ; }; /* On-module USB interrupt */ pinctrl_usb3503a: usb3503agrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 - >; + fsl,pins = ; }; /* Colibri USB Client Cable Detect */ pinctrl_usbc_det: usbcdetgrp { - fsl,pins = < - IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ - >; + fsl,pins = ; /* SODIMM 137 */ }; /* USB Host Power Enable */ pinctrl_usbh1_reg: usbh1reggrp { - fsl,pins = < - IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ - >; + fsl,pins = ; /* SODIMM 129 */ }; /* On-module eMMC */ pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + ; }; /* Colibri SD/MMC Card Detect */ pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ - >; + fsl,pins = ; /* SODIMM 43 */ }; pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ - >; + fsl,pins = ; /* SODIMM 43 */ }; /* Colibri SD/MMC Card */ pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; + fsl,pins = , /* SODIMM 47 */ + , /* SODIMM 190 */ + , /* SODIMM 192 */ + , /* SODIMM 49 */ + , /* SODIMM 51 */ + , /* SODIMM 53 */ + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; + fsl,pins = , /* SODIMM 47 */ + , /* SODIMM 190 */ + , /* SODIMM 192 */ + , /* SODIMM 49 */ + , /* SODIMM 51 */ + , /* SODIMM 53 */ + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; + fsl,pins = , /* SODIMM 47 */ + , /* SODIMM 190 */ + , /* SODIMM 192 */ + , /* SODIMM 49 */ + , /* SODIMM 51 */ + , /* SODIMM 53 */ + ; }; pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; + fsl,pins = , /* SODIMM 47 */ + , /* SODIMM 190 */ + , /* SODIMM 192 */ + , /* SODIMM 49 */ + , /* SODIMM 51 */ + , /* SODIMM 53 */ + ; }; pinctrl_wifi: wifigrp { - fsl,pins = < - IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 - >; + fsl,pins = ; }; }; From 7ece3cbc8b1efbf48d25a91043e9b410b46a0ccf Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:50 +0100 Subject: [PATCH 0527/1040] arm64: dts: colibri-imx8x: Add atmel pinctrl groups Add pinctrl groups for enabling atmel touchscreen support. Remove the pads out of pinctrl_hog0 as they now can be enabled more specific using pinctrl_atmel_conn label. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8x-colibri.dtsi | 20 ++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 4e0d5762b76c..5019439a3a75 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -134,6 +134,22 @@ ; /* SODIMM 2 */ }; + /* Atmel MXT touchsceen + Capacitive Touch Adapter */ + /* NOTE: This pingroup conflicts with pingroups + * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them + * simultaneously. + */ + pinctrl_atmel_adap: atmeladaptergrp { + fsl,pins = , /* SODIMM 30 */ + ; /* SODIMM 28 */ + }; + + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + pinctrl_atmel_conn: atmelconnectorgrp { + fsl,pins = , /* SODIMM 107 */ + ; /* SODIMM 106 */ + }; + pinctrl_can_int: canintgrp { fsl,pins = ; /* SODIMM 73 */ }; @@ -218,7 +234,6 @@ , /* SODIMM 103 */ , /* SODIMM 103 */ , /* SODIMM 105 */ - , /* SODIMM 107 */ , /* SODIMM 127 */ , /* SODIMM 131 */ , /* SODIMM 133 */ @@ -226,8 +241,7 @@ , /* SODIMM 98 */ , /* SODIMM 100 */ , /* SODIMM 102 */ - , /* SODIMM 104 */ - ; /* SODIMM 106 */ + ; /* SODIMM 104 */ }; pinctrl_hog1: hog1grp { From 5e634a90928b0ba40f75d28a5daa2ad66e932cfc Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:51 +0100 Subject: [PATCH 0528/1040] arm64: dts: colibri-imx8x: Add pinctrl group for csi_mclk Add missing pinctrl groups that can be used to enable the correct muxing if csi_mclk is needed on SODIMM 75. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 5019439a3a75..a352246aa1f3 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -159,6 +159,10 @@ ; /* SODIMM 89 */ }; + pinctrl_csi_mclk: csimclkgrp { + fsl,pins = ; /* SODIMM 75 / X3-12 */ + }; + pinctrl_ext_io0: extio0grp { fsl,pins = ; /* SODIMM 135 */ }; From 4d2adf738169a3492407065fbcefcc8765ce507a Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:52 +0100 Subject: [PATCH 0529/1040] arm64: dts: colibri-imx8x: Split pinctrl_hog1 Split pinctrl_hog1 into a second group so CSI_MCLK can be muxed to a gpio on its own. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index a352246aa1f3..10dce84dc153 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -119,7 +119,8 @@ &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>; + pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>, + <&pinctrl_hog2>; /* On-module touch pen-down interrupt */ pinctrl_ad7879_int: ad7879intgrp { @@ -253,6 +254,10 @@ ; /* SODIMM 93 */ }; + pinctrl_hog2: hog2grp { + fsl,pins = ; /* SODIMM 75 */ + }; + /* * This pin is used in the SCFW as a UART. Using it from * Linux would require rewritting the SCFW board file. From bd74f83de7665dfb5a55db537ed514471b2205b1 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:53 +0100 Subject: [PATCH 0530/1040] arm64: dts: colibri-imx8x: Correct pull on lcdif The pads USDHC1_RESET_B and MCLK_IN1 need a pull-down instead of pull-disabled. Correct this. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 10dce84dc153..26bf14cf5343 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -295,8 +295,8 @@ fsl,pins = , /* SODIMM 56 */ , /* SODIMM 68 */ , /* SODIMM 82 */ - , /* SODIMM 44 */ - , /* SODIMM 44 */ + , /* SODIMM 44 */ + , /* SODIMM 44 */ , /* SODIMM 76 */ , /* SODIMM 76 */ , /* SODIMM 70 */ From 7171ec2953ab34d87d01a8884af3c9e4ba6e515c Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:54 +0100 Subject: [PATCH 0531/1040] arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2 Add a separate pinctrl group for chip-select 2 for Colibri SPI. That way one is able to use it separately. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 26bf14cf5343..1d4e127ffa7e 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -120,7 +120,7 @@ &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>, - <&pinctrl_hog2>; + <&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>; /* On-module touch pen-down interrupt */ pinctrl_ad7879_int: ad7879intgrp { @@ -223,8 +223,7 @@ }; pinctrl_hog0: hog0grp { - fsl,pins = , /* SODIMM 65 */ - , /* SODIMM 65 */ + fsl,pins = , /* SODIMM 65 */ , /* SODIMM 69 */ , /* SODIMM 79 */ , /* SODIMM 79 */ @@ -327,6 +326,10 @@ ; /* SODIMM 88 */ }; + pinctrl_lpspi2_cs2: lpspi2cs2grp { + fsl,pins = ; /* SODIMM 65 */ + }; + /* Colibri UART_B */ pinctrl_lpuart0: lpuart0grp { fsl,pins = , /* SODIMM 36 */ From 9c279d216fbc87727099baab644e8d4a810d9cc7 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:55 +0100 Subject: [PATCH 0532/1040] arm64: dts: colibri-imx8x: Add pinctrl group for hdmi hpd The colibri imx8x contains a dedicated gpio meant for HDMI hot-plug-detect. Add a pinctrl group to make this usable. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 1d4e127ffa7e..cd7de71c6d73 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -218,6 +218,11 @@ fsl,pins = ; /* SODIMM 71 */ }; + /* HDMI Hot Plug Detect on FFC (X2) */ + pinctrl_gpio_hpd: gpiohpdgrp { + fsl,pins = ; /* SODIMM 138 */ + }; + pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = ; /* SODIMM 45 */ }; From a537c9618d0fe9f7954dad0a0827da85c5c25101 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:56 +0100 Subject: [PATCH 0533/1040] arm64: dts: colibri-imx8x: Add SPI Add Colibri SPI to the board. lpspi2 is being exposed on the SoM edge. Add settings to the module-level but finally enable it on the eval-board dtsi. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi | 5 +++++ arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 7 +++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi index dc0339b35a3c..1d0bad085ad4 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi @@ -36,6 +36,11 @@ }; }; +/* Colibri SPI */ +&lpspi2 { + status = "okay"; +}; + /* Colibri UART_B */ &lpuart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index cd7de71c6d73..a2364845e976 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -91,6 +91,13 @@ }; }; +/* Colibri SPI */ +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; +}; + /* On-module eMMC */ &usdhc1 { bus-width = <8>; From 551648021f39727481b7fd0e634411fcf4b4037b Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:57 +0100 Subject: [PATCH 0534/1040] arm64: dts: colibri-imx8x: Add gpio-line-names This commit adds gpio-line-names in line with other SoM from Toradex. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8x-colibri.dtsi | 152 ++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index a2364845e976..26f46fe56aa2 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -98,6 +98,158 @@ cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; }; +&lsio_gpio0 { + gpio-line-names = "", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_68", + "", + "", + "SODIMM_82", + "SODIMM_56", + "SODIMM_28", + "SODIMM_30", + "", + "SODIMM_61", + "SODIMM_103", + "", + "", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_100"; +}; + +&lsio_gpio1 { + gpio-line-names = "SODIMM_86", + "SODIMM_92", + "SODIMM_90", + "SODIMM_88", + "", + "", + "", + "SODIMM_59", + "", + "SODIMM_6", + "SODIMM_8", + "", + "", + "SODIMM_2", + "SODIMM_4", + "SODIMM_34", + "SODIMM_32", + "SODIMM_63", + "SODIMM_55", + "SODIMM_33", + "SODIMM_35", + "SODIMM_36", + "SODIMM_38", + "SODIMM_21", + "SODIMM_19", + "SODIMM_140", + "SODIMM_142", + "SODIMM_196", + "SODIMM_194", + "SODIMM_186", + "SODIMM_188", + "SODIMM_138"; +}; + +&lsio_gpio2 { + gpio-line-names = "SODIMM_23", + "", + "", + "SODIMM_144"; +}; + +&lsio_gpio3 { + gpio-line-names = "SODIMM_96", + "SODIMM_75", + "SODIMM_37", + "SODIMM_29", + "", + "", + "", + "", + "", + "SODIMM_43", + "SODIMM_45", + "SODIMM_69", + "SODIMM_71", + "SODIMM_73", + "SODIMM_77", + "SODIMM_89", + "SODIMM_93", + "SODIMM_95", + "SODIMM_99", + "SODIMM_105", + "SODIMM_107", + "SODIMM_98", + "SODIMM_102", + "SODIMM_104", + "SODIMM_106"; +}; + +&lsio_gpio4 { + gpio-line-names = "", + "", + "", + "SODIMM_129", + "SODIMM_133", + "SODIMM_127", + "SODIMM_131", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_44", + "", + "SODIMM_76", + "SODIMM_31", + "SODIMM_47", + "SODIMM_190", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&lsio_gpio5 { + gpio-line-names = "", + "SODIMM_57", + "SODIMM_65", + "SODIMM_85", + "", + "", + "", + "", + "SODIMM_135", + "SODIMM_137", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184"; +}; + /* On-module eMMC */ &usdhc1 { bus-width = <8>; From 851884b264fe4028bfc5ba6877ac40bdfb46e1cf Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:58 +0100 Subject: [PATCH 0535/1040] arm64: dts: colibri-imx8x: Disable touchscreen by default Do not enable the touchscreen. By default it is not used but should be kept to enable it from a file that includes imx8x-colibri.dtsi. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 26f46fe56aa2..2fd7f3483b3a 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -40,6 +40,7 @@ adi,median-filter-size = /bits/ 8 <2>; adi,averaging = /bits/ 8 <1>; adi,conversion-interval = /bits/ 8 <255>; + status = "disabled"; }; }; From ee9936d64b453c02e217d7e1b93f750d6a609ee7 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:23:59 +0100 Subject: [PATCH 0536/1040] arm64: dts: colibri-imx8x: Add jpegenc/dec jpeg encoder and decoder are available. Do enable them in the module level device-tree since those are self-contained. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 2fd7f3483b3a..778f2f43a8c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -53,6 +53,14 @@ pinctrl-0 = <&pinctrl_i2c1>; }; +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + /* Colibri UART_B */ &lpuart0 { pinctrl-names = "default"; From e74b958c8eafd0e91158401f8e6880131111b28a Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:00 +0100 Subject: [PATCH 0537/1040] arm64: dts: colibri-imx8x: Add colibri pwm b, c, d Add Colibri PWM_B, PWM_C, PWM_D to the module-level device-tree and set the status to ok on the eval-board. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../dts/freescale/imx8x-colibri-eval-v3.dtsi | 15 +++++++++++++ .../boot/dts/freescale/imx8x-colibri.dtsi | 21 +++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi index 1d0bad085ad4..68e34516961a 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi @@ -51,6 +51,21 @@ status = "okay"; }; +/* Colibri PWM_B */ +&lsio_pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&lsio_pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&lsio_pwm2 { + status = "okay"; +}; + /* Colibri UART_A */ &lpuart3 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 778f2f43a8c0..61033b79e44e 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -259,6 +259,27 @@ "UNUSABLE_SODIMM_184"; }; +/* Colibri PWM_B */ +&lsio_pwm0 { + #pwm-cells = <3>; + pinctrl-0 = <&pinctrl_pwm_b>; + pinctrl-names = "default"; +}; + +/* Colibri PWM_C */ +&lsio_pwm1 { + #pwm-cells = <3>; + pinctrl-0 = <&pinctrl_pwm_c>; + pinctrl-names = "default"; +}; + +/* Colibri PWM_D */ +&lsio_pwm2 { + #pwm-cells = <3>; + pinctrl-0 = <&pinctrl_pwm_d>; + pinctrl-names = "default"; +}; + /* On-module eMMC */ &usdhc1 { bus-width = <8>; From 281506130449a197dfd8d7469240716aba6affcd Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:01 +0100 Subject: [PATCH 0538/1040] arm64: dts: colibri-imx8x: eval: Add spi-to-can Add mcp2515 spi-to-can to &lpspi2. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../dts/freescale/imx8x-colibri-eval-v3.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi index 68e34516961a..14d479b50656 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi @@ -11,6 +11,13 @@ rtc1 = &rtc; }; + /* fixed crystal dedicated to mcp25xx */ + clk16m: clock-16mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -39,6 +46,17 @@ /* Colibri SPI */ &lpspi2 { status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_can_int>; + pinctrl-names = "default"; + clocks = <&clk16m>; + spi-max-frequency = <10000000>; + }; }; /* Colibri UART_B */ From 09fad38e261d22dc70a14ce7dd4bb081e028f465 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:02 +0100 Subject: [PATCH 0539/1040] arm64: dts: colibri-imx8x: Add no-1-8-v to sd-card Many Colibri carrier boards are using 3.3V pull-up resistors on the SD-Card connector. Letting it switch to 1.8V is an invalid state. Do prevent this from happening by keeping the signaling voltage at 3.3V. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 61033b79e44e..2e228c5b8109 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -304,6 +304,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; disable-wp; + no-1-8-v; }; &iomuxc { From e2c7fa724626e4bde70e753cdeb7827d0d225364 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:03 +0100 Subject: [PATCH 0540/1040] arm64: dts: colibri-imx8x: Set thermal thresholds Set critical/alert thermal thresholds for all relevant SOC temperature trips to the IT value (max T_junction 105 degree Celsius) in accordance with the IT grade of the SOM. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 2e228c5b8109..1e41965e2d01 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -16,6 +16,18 @@ }; }; +&cpu_alert0 { + hysteresis = <2000>; + temperature = <90000>; + type = "passive"; +}; + +&cpu_crit0 { + hysteresis = <2000>; + temperature = <105000>; + type = "critical"; +}; + /* On-module I2C */ &i2c0 { #address-cells = <1>; From cc900d0ffcae8dae159b762eca3092b24744a91b Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:04 +0100 Subject: [PATCH 0541/1040] arm64: dts: colibri-imx8x: Move gpio-keys to som level SODIMM_45 that is connected to "&lsio_gpio3 10" is defined in the Colibri standard to be a wakeup pin. Move this to the SoM level device-tree and keep it disabled by default but do enable it again on the carrier-board. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../dts/freescale/imx8x-colibri-eval-v3.dtsi | 16 +++------------- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 15 +++++++++++++++ 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi index 14d479b50656..7264d784ae72 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi @@ -17,20 +17,10 @@ #clock-cells = <0>; clock-frequency = <16000000>; }; +}; - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpiokeys>; - - key-wakeup { - label = "Wake-Up"; - gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; - linux,code = ; - debounce-interval = <10>; - wakeup-source; - }; - }; +&colibri_gpio_keys { + status = "okay"; }; &i2c1 { diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 1e41965e2d01..ff5ad88febc8 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -8,6 +8,21 @@ stdout-path = &lpuart3; }; + colibri_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + status = "disabled"; + + key-wakeup { + debounce-interval = <10>; + gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; regulator-name = "+V3.3"; From f018dfb3111ad9f3a6bc93d643c2e368e9ce6dbd Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:05 +0100 Subject: [PATCH 0542/1040] arm64: dts: colibri-imx8x: Add todo comments Highlight what is still missing. Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8x-colibri.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index ff5ad88febc8..7cad79102e1a 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -31,6 +31,10 @@ }; }; +/* TODO Analogue Inputs */ + +/* TODO Cooling maps for DX */ + &cpu_alert0 { hysteresis = <2000>; temperature = <90000>; @@ -43,6 +47,10 @@ type = "critical"; }; +/* TODO flexcan1 - 3 */ + +/* TODO GPU */ + /* On-module I2C */ &i2c0 { #address-cells = <1>; @@ -71,6 +79,10 @@ }; }; +/* TODO i2c lvds0 accessible on FFC (X2) */ + +/* TODO i2c lvds1 accessible on FFC (X3) */ + /* Colibri I2C */ &i2c1 { #address-cells = <1>; @@ -88,6 +100,8 @@ status = "okay"; }; +/* TODO Parallel RRB */ + /* Colibri UART_B */ &lpuart0 { pinctrl-names = "default"; @@ -307,6 +321,14 @@ pinctrl-names = "default"; }; +/* TODO MIPI CSI */ + +/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */ + +/* TODO on-module PCIe for Wi-Fi */ + +/* TODO On-module i2s / Audio */ + /* On-module eMMC */ &usdhc1 { bus-width = <8>; @@ -334,6 +356,12 @@ no-1-8-v; }; +/* TODO USB Client/Host */ + +/* TODO USB Host */ + +/* TODO VPU Encoder/Decoder */ + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>, From 144f67f68af8512426f2127c68ef054815453ff2 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:07 +0100 Subject: [PATCH 0543/1040] arm64: dts: colibri-imx8x: Add aster carrier board Add the Toradex Aster Carrier Board for Colibri iMX8X, small form-factor with header compatible with Arduino Uno and Raspberry Pi (RPi) maker boards. Additional details available at: https://www.toradex.com/products/carrier-boards/aster-carrier-board Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qxp-colibri-aster.dts | 16 +++++++ .../dts/freescale/imx8x-colibri-aster.dtsi | 44 +++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 836dcc501e6f..9f49e47589ab 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts new file mode 100644 index 000000000000..966ecfb2a17e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" +#include "imx8x-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP on Aster Board"; + compatible = "toradex,colibri-imx8x-aster", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi new file mode 100644 index 000000000000..aab655931cde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +&colibri_gpio_keys { + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>; +}; + +/* Colibri SPI */ +&lpspi2 { + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>, + <&lsio_gpio5 2 GPIO_ACTIVE_LOW>; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; From aefb5e2d974df7567bac32f2b0d1c8bcf5d6c94c Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:08 +0100 Subject: [PATCH 0544/1040] arm64: dts: colibri-imx8x: Add iris carrier board Add the Toradex Iris Carrier Board for Colibri iMX8X, small form-factor production ready board. Additional details available at: https://www.toradex.com/products/carrier-boards/iris-carrier-board Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qxp-colibri-iris.dts | 16 +++ .../dts/freescale/imx8x-colibri-iris.dtsi | 115 ++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 9f49e47589ab..48bb0fe4a616 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts new file mode 100644 index 000000000000..fed75b5d4a1c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" +#include "imx8x-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP on Colibri Iris Board"; + compatible = "toradex,colibri-imx8x-iris", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi new file mode 100644 index 000000000000..5f30c88855e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V"; + }; +}; + +&colibri_gpio_keys { + status = "okay"; +}; + +/* Colibri FastEthernet */ +&fec1 { + status = "okay"; +}; + +/* Colibri I2C */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris>; + + pinctrl_gpio_iris: gpioirisgrp { + fsl,pins = , /* SODIMM 98 */ + , /* SODIMM 133 */ + , /* SODIMM 103 */ + , /* SODIMM 101 */ + , /* SODIMM 97 */ + , /* SODIMM 85 */ + , /* SODIMM 79 */ + ; /* SODIMM 45 */ + }; + + pinctrl_uart1_forceoff: uart1forceoffgrp { + fsl,pins = ; /* SODIMM 22 */ + }; + + pinctrl_uart23_forceoff: uart23forceoffgrp { + fsl,pins = ; /* SODIMM 23 */ + }; +}; + +/* Colibri SPI */ +&lpspi2 { + status = "okay"; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +&lsio_gpio3 { + /* + * This turns the LVDS transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + */ + lvds-tx-on-hog { + gpio-hog; + gpios = <18 0>; + output-high; + }; +}; + +/* Colibri PWM_B */ +&lsio_pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&lsio_pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&lsio_pwm2 { + status = "okay"; +}; + +/* Colibri SD/MMC Card */ +&usdhc2 { + status = "okay"; +}; From 1fe5ea7cc22811ea14c7e609cacb4923fc21e050 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Tue, 14 Mar 2023 11:24:09 +0100 Subject: [PATCH 0545/1040] arm64: dts: colibri-imx8x: Add iris v2 carrier board Add the Toradex Iris V2 Carrier Board for Colibri iMX8X, small form-factor production ready board. Additional details available at: https://www.toradex.com/products/carrier-boards/iris-carrier-board Signed-off-by: Philippe Schenker Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8qxp-colibri-iris-v2.dts | 16 +++++++ .../dts/freescale/imx8x-colibri-iris-v2.dtsi | 45 +++++++++++++++++++ 3 files changed, 62 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 48bb0fe4a616..2eb746f6a2c2 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts new file mode 100644 index 000000000000..cca33213fa9b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" +#include "imx8x-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP on Colibri Iris V2 Board"; + compatible = "toradex,colibri-imx8x-iris-v2", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..98202a437040 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2018-2021 Toradex + */ + +#include "imx8x-colibri-iris.dtsi" + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + enable-active-high; + gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3v3_vmmc"; + startup-delay-us = <100>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_converter &pinctrl_gpio_iris>; + + pinctrl_enable_3v3_vmmc: enable_3v3_vmmc { + fsl,pins = ; /* SODIMM 100 */ + }; + + pinctrl_lvds_converter: lcd-lvds { + fsl,pins = , /* SODIMM 55 */ + /* 6B/8B mode. Select LOW - 8B mode (24bit) */ + , /* SODIMM 63 */ + , /* SODIMM 95 */ + ; /* SODIMM 99 */ + }; +}; + +/* Colibri SD/MMC Card */ +&usdhc2 { + cap-power-off-card; + /delete-property/ no-1-8-v; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; From 5c984deedadae311ac057598b3aad11b3950e7bc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Tue, 14 Mar 2023 19:06:07 +0100 Subject: [PATCH 0546/1040] =?UTF-8?q?dt-bindings:=20arm:=20fsl:=20Add=20Y?= =?UTF-8?q?=20Soft=20IOTA=C2=A0Phoenix,=20Lynx,=20Pegasus=20and=20Pegasus+?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These i.MX6 boards are based on a facelifted PCB from the previous designs. Routing for some unused parts was completely removed (uSD card, PCIe, audio codec) and some new parts were added (supercap backed RTC, secure element, PWM audio, GPIO button). Acked-by: Krzysztof Kozlowski Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 2285c8d65a58..acfbc74b0f2b 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -300,6 +300,7 @@ properties: - variscite,dt6customboard - wand,imx6q-wandboard # Wandboard i.MX6 Quad Board - ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board + - ysoft,imx6q-yapp4-pegasus # i.MX6 Quad Y Soft IOTA Pegasus board - zealz,imx6q-gk802 # Zealz GK802 - zii,imx6q-zii-rdu2 # ZII RDU2 Board - const: fsl,imx6q @@ -410,6 +411,7 @@ properties: - prt,prtwd3 # Protonic WD3 board - wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board - ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board + - ysoft,imx6qp-yapp4-pegasus-plus # i.MX6 Quad Plus Y Soft IOTA Pegasus+ board - zii,imx6qp-zii-rdu2 # ZII RDU2+ Board - const: fsl,imx6qp @@ -476,7 +478,9 @@ properties: - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board - ysoft,imx6dl-yapp4-draco # i.MX6 Solo Y Soft IOTA Draco board - ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board + - ysoft,imx6dl-yapp4-lynx # i.MX6 DualLite Y Soft IOTA Lynx board - ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board + - ysoft,imx6dl-yapp4-phoenix # i.MX6 DualLite Y Soft IOTA Phoenix board - ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board - const: fsl,imx6dl From 7da7b84fee58c85a6075022023d31edea40e81a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Tue, 14 Mar 2023 19:06:04 +0100 Subject: [PATCH 0547/1040] ARM: dts: imx6dl-yapp4: Move phy reset into switch node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the phy-reset-duration and phy-reset-gpios deprecated properties and move reset-gpios under the switch node. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index c6afc51bb22b..31b4dd9fc5d6 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -106,8 +106,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - phy-reset-duration = <20>; phy-supply = <&sw2_reg>; status = "okay"; @@ -131,6 +129,7 @@ switch@10 { compatible = "qca,qca8334"; reg = <10>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; switch_ports: ports { #address-cells = <1>; From f87c9b04c6b51e0339f0d3cf7f5a965c0cf939e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Tue, 14 Mar 2023 19:06:05 +0100 Subject: [PATCH 0548/1040] =?UTF-8?q?ARM:=C2=A0dts:=20imx6dl-yapp4:=20Move?= =?UTF-8?q?=20status=20to=20the=20end=20of=20property=20list?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The status property should always be last in the list. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 31b4dd9fc5d6..42df92dd6e59 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -269,9 +269,9 @@ compatible = "ti,lp5562"; reg = <0x30>; clock-mode = /bits/ 8 <1>; - status = "disabled"; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; led@0 { chan-name = "R"; From 0593e164bb05eb16387b137aef8bd8b6b0e9edd0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Tue, 14 Mar 2023 19:06:06 +0100 Subject: [PATCH 0549/1040] ARM: dts: imx6dl-yapp4: Remove unneeded status "okay" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Explicit status = "okay" is not needed as it is the default. Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 42df92dd6e59..3be38a3c4bb1 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -98,7 +98,6 @@ regulator-max-microvolt = <5000000>; gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; - status = "okay"; }; }; @@ -302,7 +301,6 @@ compatible = "atmel,24c128"; reg = <0x57>; pagesize = <64>; - status = "okay"; }; touchscreen: touchscreen@5c { From 7da4734751e075db517cf6ca9cb54db6fb0975a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Tue, 14 Mar 2023 19:06:08 +0100 Subject: [PATCH 0550/1040] =?UTF-8?q?ARM:=20dts:=20imx6dl-yapp43:=20Add=20?= =?UTF-8?q?support=20for=20new=20HW=20revision=20of=20the=20IOTA=C2=A0boar?= =?UTF-8?q?d?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The PCB used for all the current boards (Ursa, Draco, Hydra, Orion, Crux) was slightly redesigned and delivers some new features while some unused components were removed. - External RTC chip with supercap added. - Secure element added. - LCD display power supply enable/disable signal added. - Touch keyboard reset and interrupt signals added. - Factory reset GPIO button added. - Audio codec LM49350 (EoL) removed and replaced by PWM audio output. - QCA8334 switch was replaced by Marvell 88E6141. - PCIe completely removed. - uSD card removed and replaced by board-to-board expansion connector. There are four configuration variants of the new board: 1. Pegasus The board configuration is based on Orion with the following major changes: - Quad core SoC - 4GB of RAM - RTC with supercap added - Secure element added 2. Pegasus+ This is the very same board as Pegasus but uses the i.MX6QuadPlus SoC. 3. Lynx The board configuration is based on Draco with the following major changes: - DualLite SoC - 1GB of RAM - RTC with supercap added - Secure element added 4. Phoenix The board configuration is based on Ursa with the following major changes: - DualLite Soc - 1GB of RAM - RTC with supercap added - Secure element added - LCD display support removed - UART2 removed - Factory reset GPIO button added Signed-off-by: Michal Vokáč Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 4 + arch/arm/boot/dts/imx6dl-yapp4-lynx.dts | 58 ++ arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts | 42 ++ arch/arm/boot/dts/imx6dl-yapp43-common.dtsi | 615 ++++++++++++++++++ arch/arm/boot/dts/imx6q-yapp4-pegasus.dts | 58 ++ .../boot/dts/imx6qp-yapp4-pegasus-plus.dts | 58 ++ 6 files changed, 835 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-lynx.dts create mode 100644 arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts create mode 100644 arch/arm/boot/dts/imx6dl-yapp43-common.dtsi create mode 100644 arch/arm/boot/dts/imx6q-yapp4-pegasus.dts create mode 100644 arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe4152e5846..4f58dba50f0d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -561,7 +561,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-wandboard-revd1.dtb \ imx6dl-yapp4-draco.dtb \ imx6dl-yapp4-hydra.dtb \ + imx6dl-yapp4-lynx.dtb \ imx6dl-yapp4-orion.dtb \ + imx6dl-yapp4-phoenix.dtb \ imx6dl-yapp4-ursa.dtb \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ @@ -668,6 +670,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-wandboard-revb1.dtb \ imx6q-wandboard-revd1.dtb \ imx6q-yapp4-crux.dtb \ + imx6q-yapp4-pegasus.dtb \ imx6q-zii-rdu2.dtb \ imx6qp-mba6b.dtb \ imx6qp-nitrogen6_max.dtb \ @@ -683,6 +686,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6qp-vicutp.dtb \ imx6qp-wandboard-revd1.dtb \ imx6qp-yapp4-crux-plus.dtb \ + imx6qp-yapp4-pegasus-plus.dtb \ imx6qp-zii-rdu2.dtb \ imx6s-dhcom-drc02.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ diff --git a/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts b/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts new file mode 100644 index 000000000000..5c2cd517589b --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-lynx.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Lynx i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-lynx", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&backlight { + status = "okay"; +}; + +&lcd_display { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&panel { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchscreen { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts b/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts new file mode 100644 index 000000000000..e0292f11d03e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp4-phoenix.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Phoenix i.MX6DualLite board"; + compatible = "ysoft,imx6dl-yapp4-phoenix", "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; +}; + +&aliases { + /delete-property/ ethernet1; +}; + +&gpio_keys { + status = "okay"; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&switch_ports { + /delete-node/ port@2; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi new file mode 100644 index 000000000000..52a0f6ee426f --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-yapp43-common.dtsi @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +#include +#include +#include +#include +#include + +/ { + aliases: aliases { + ethernet1 = ð1; + ethernet2 = ð2; + mmc0 = &usdhc3; + mmc1 = &usdhc4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 32 64 128 255>; + default-brightness-level = <32>; + num-interpolated-steps = <8>; + power-supply = <&sw2_reg>; + status = "disabled"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + button { + label = "Factory RESET"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + }; + + lcd_display: display { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + compatible = "dataimage,scf0700c48ggu18"; + power-supply = <&sw2_reg>; + backlight = <&backlight>; + enable-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii-id"; + phy-supply = <&sw2_reg>; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "marvell,mv88e6085"; + reg = <0>; + reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + + switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: port@0 { + reg = <0>; + label = "cpu"; + phy-mode = "rgmii-id"; + ethernet = <&fec>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + eth2: port@1 { + reg = <1>; + label = "eth2"; + phy-handle = <&phy_port1>; + }; + + eth1: port@2 { + reg = <2>; + label = "eth1"; + phy-handle = <&phy_port2>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy_port1: switchphy@11 { + reg = <0x11>; + }; + + phy_port2: switchphy@12 { + reg = <0x12>; + }; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze200"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vsnvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + leds: led-controller@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + clock-mode = /bits/ 8 <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + led@0 { + chan-name = "R"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <0>; + color = ; + }; + + led@1 { + chan-name = "G"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <1>; + color = ; + }; + + led@2 { + chan-name = "B"; + led-cur = /bits/ 8 <0x20>; + max-cur = /bits/ 8 <0x60>; + reg = <2>; + color = ; + }; + }; + + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + pagesize = <64>; + }; + + touchscreen: touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + reg = <0x5c>; + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + attb-gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + status = "disabled"; + }; + + rtc: rtc@68 { + compatible = "dallas,ds1341"; + reg = <0x68>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + oled_1309: oled@3c { + compatible = "solomon,ssd1309fb-i2c"; + reg = <0x3c>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,segment-no-remap; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + oled_1305: oled@3d { + compatible = "solomon,ssd1305fb-i2c"; + reg = <0x3d>; + solomon,height = <64>; + solomon,width = <128>; + solomon,page-offset = <0>; + solomon,col-offset = <4>; + solomon,prechargep2 = <15>; + reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>; + vbat-supply = <&sw2_reg>; + status = "disabled"; + }; + + gpio_oled: gpio@41 { + compatible = "nxp,pca9536"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x41>; + vcc-supply = <&sw2_reg>; + status = "disabled"; + }; + + touchkeys: keys@5a { + compatible = "fsl,mpr121-touchkey"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchkeys>; + reg = <0x5a>; + vdd-supply = <&sw2_reg>; + autorepeat; + linux,keycodes = , , , , , + , , , , + , , ; + poll-interval = <50>; + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b020 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b020 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b020 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b020 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b020 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b020 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b020 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b020 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b020 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b020 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b020 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b020 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b020 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b020 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b010 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x1b010 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b098 + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b899 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b899 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b899 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b899 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b0 + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b098 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x8 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b098 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b098 + >; + }; + + pinctrl_touchkeys: touchkeysgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b098 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b098 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0a8 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0a8 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b098 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b098 + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1b098 + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbus { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x98 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1b098 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b098 + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbus { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x98 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x1f069 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10069 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17069 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17069 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17069 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17069 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17069 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17069 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17069 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17069 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + >; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + over-current-active-low; + status = "disabled"; +}; + +&usbotg { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + vbus-supply = <®_usb_otg_vbus>; + over-current-active-low; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; + status = "okay"; +}; + +&usbphy2 { + fsl,tx-d-cal = <109>; + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + vmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts b/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts new file mode 100644 index 000000000000..ec6651ba4ba2 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-yapp4-pegasus.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Pegasus i.MX6Quad board"; + compatible = "ysoft,imx6q-yapp4-pegasus", "fsl,imx6q"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_pu { + regulator-always-on; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts b/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts new file mode 100644 index 000000000000..4a961a33bf2d --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-yapp4-pegasus-plus.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2021 Y Soft Corporation, a.s. + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6dl-yapp43-common.dtsi" + +/ { + model = "Y Soft IOTA Pegasus+ i.MX6QuadPlus board"; + compatible = "ysoft,imx6qp-yapp4-pegasus-plus", "fsl,imx6qp"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0xf0000000>; + }; +}; + +&gpio_oled { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&leds { + status = "okay"; +}; + +&oled_1305 { + status = "okay"; +}; + +&oled_1309 { + status = "okay"; +}; + +®_pu { + regulator-always-on; +}; + +®_usb_h1_vbus { + status = "okay"; +}; + +&touchkeys { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbphy2 { + status = "okay"; +}; From d37c36001e55137abf3569fdd182735061197db3 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 17 Mar 2023 09:16:17 +0100 Subject: [PATCH 0551/1040] dt-bindings: arm: fsl: add compatible string for Tolino Vision Add a compatible string for the Tolino Vision eBook reader. Signed-off-by: Andreas Kemnade Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index acfbc74b0f2b..b9c08e303b48 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -585,6 +585,7 @@ properties: - kobo,aura2 - kobo,tolino-shine2hd - kobo,tolino-shine3 + - kobo,tolino-vision - kobo,tolino-vision5 - revotics,imx6sl-warp # Revotics WaRP Board - const: fsl,imx6sl From f491698935bf50dea76309eae75ef3511151f8fb Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 17 Mar 2023 09:16:18 +0100 Subject: [PATCH 0552/1040] ARM: dts: imx: Add devicetree for Tolino Vison Add a devicetree for the Tolino Vision Ebook reader. It is based on boards marked with "37NB-E60Q30+4A3". It is equipped with an i.MX6SL SoC. Expected to work: - Buttons - Wifi - LEDs - uSD - eMMC - USB - RTC - Touchscreen - Backlight Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6sl-tolino-vision.dts | 490 +++++++++++++++++++++ 2 files changed, 491 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sl-tolino-vision.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4f58dba50f0d..fd4f7230cb55 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -694,6 +694,7 @@ dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-kobo-aura2.dtb \ imx6sl-tolino-shine2hd.dtb \ imx6sl-tolino-shine3.dtb \ + imx6sl-tolino-vision.dtb \ imx6sl-tolino-vision5.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SLL) += \ diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision.dts b/arch/arm/boot/dts/imx6sl-tolino-vision.dts new file mode 100644 index 000000000000..2694fe18a91b --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-tolino-vision.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device tree for the Tolino Vison ebook reader + * + * Name on mainboard is: 37NB-E60Q30+4A3 + * Serials start with: 6032 + * + * Copyright 2023 Andreas Kemnade + */ + +/dts-v1/; + +#include +#include +#include +#include "imx6sl.dtsi" + +/ { + model = "Tolino Vision"; + compatible = "kobo,tolino-vision", "fsl,imx6sl"; + + aliases { + mmc0 = &usdhc4; + mmc1 = &usdhc2; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&ec 0 50000>; + power-supply = <&backlight_regulator>; + }; + + backlight_regulator: regulator-backlight { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight_power>; + regulator-name = "backlight"; + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-cover { + /* magnetic sensor in the corner next to the uSD slot */ + label = "Cover"; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + + key-fl { + label = "Frontlight"; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-0 { + /* LED on home button */ + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + }; + + led-1 { + /* LED on power button */ + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; + + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; + status = "okay"; + + touchscreen@15 { + compatible = "elan,ektf2132"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ts>; + power-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + interrupts-extended = <&gpio5 6 IRQ_TYPE_EDGE_FALLING>; + }; + + accelerometer@1d { + compatible = "fsl,mma8652"; + reg = <0x1d>; + }; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + ec: embedded-controller@43 { + compatible = "netronix,ntxec"; + reg = <0x43>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ec>; + interrupts-extended = <&gpio5 11 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + }; +}; + +&snvs_rtc { + /* + * We are using the RTC in the PMIC, but this one is not disabled + * in imx6sl.dtsi. + */ + status = "disabled"; +}; + +&uart1 { + /* J4 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart4 { + /* J9 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>; + cd-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* removable uSD card */ +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; + + /* CyberTan WC121 (BCM43362) SDIO WiFi */ +}; + +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc4>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + pinctrl-3 = <&pinctrl_usdhc4_sleep>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; + + /* internal eMMC */ +}; + +&usbotg1 { + pinctrl-names = "default"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight_power: backlight-powergrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 + >; + }; + + pinctrl_ec: ecgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT0__GPIO5_IO11 0x17000 + >; + }; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x110B0 + MX6SL_PAD_SD1_DAT4__GPIO5_IO12 0x110B0 + MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x11030 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2-sleepgrp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_leds: ledsgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT6__GPIO5_IO07 0x17059 + MX6SL_PAD_SD1_DAT7__GPIO5_IO10 0x17059 + MX6SL_PAD_EPDC_SDCE2__GPIO1_IO29 0x17059 + >; + }; + + pinctrl_ts: tsgrp { + fsl,pins = < + MX6SL_PAD_SD1_DAT2__GPIO5_IO13 0x110B0 + MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0x1B0B1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6SL_PAD_KEY_ROW6__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_KEY_COL6__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6SL_PAD_SD2_DAT4__GPIO5_IO02 0x1b0b1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__GPIO5_IO04 0x100f9 + MX6SL_PAD_SD2_CLK__GPIO5_IO05 0x100f9 + MX6SL_PAD_SD2_DAT0__GPIO5_IO01 0x100f9 + MX6SL_PAD_SD2_DAT1__GPIO4_IO30 0x100f9 + MX6SL_PAD_SD2_DAT2__GPIO5_IO03 0x100f9 + MX6SL_PAD_SD2_DAT3__GPIO4_IO28 0x100f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x17059 + MX6SL_PAD_FEC_MDIO__SD4_CLK 0x13059 + MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x17059 + MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x17059 + MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x17059 + MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x17059 + MX6SL_PAD_FEC_MDC__SD4_DATA4 0x17059 + MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x17059 + MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x17059 + MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x17059 + MX6SL_PAD_FEC_REF_CLK__SD4_RESET 0x17068 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170b9 + MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130b9 + MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170b9 + MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170b9 + MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170b9 + MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170b9 + MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170b9 + MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170b9 + MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170b9 + MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__SD4_CMD 0x170f9 + MX6SL_PAD_FEC_MDIO__SD4_CLK 0x130f9 + MX6SL_PAD_FEC_RX_ER__SD4_DATA0 0x170f9 + MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x170f9 + MX6SL_PAD_FEC_RXD1__SD4_DATA2 0x170f9 + MX6SL_PAD_FEC_TXD0__SD4_DATA3 0x170f9 + MX6SL_PAD_FEC_MDC__SD4_DATA4 0x170f9 + MX6SL_PAD_FEC_RXD0__SD4_DATA5 0x170f9 + MX6SL_PAD_FEC_TX_EN__SD4_DATA6 0x170f9 + MX6SL_PAD_FEC_TXD1__SD4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_sleep: usdhc4-sleepgrp { + fsl,pins = < + MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x100c1 + MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x100c1 + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x100c1 + MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x100c1 + MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x100c1 + MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x100c1 + MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x100c1 + MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x100c1 + MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x100c1 + MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; From d757845451d7169ad6dc7053fd2e8ecc4f5749ab Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Mar 2023 10:47:24 +0100 Subject: [PATCH 0553/1040] dt-bindings: arm: Add DH electronics i.MX8M Plus DHCOM on PDK3 Add DT compatible string for DH electronics i.MX8M Plus DHCOM on PDK3 evaluation board into YAML DT binding document. This setup is a general purpose SoM evaluation board. Acked-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b9c08e303b48..b175f2b1bd30 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1025,7 +1025,9 @@ properties: - description: i.MX8MP DHCOM based Boards items: - - const: dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board + - enum: + - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board + - dh,imx8mp-dhcom-pdk3 # i.MX8MP DHCOM SoM on PDK3 board - const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM - const: fsl,imx8mp From 44eeddd6bd185358ecbdfb5c8f4fd24c1d58645f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Mar 2023 10:47:25 +0100 Subject: [PATCH 0554/1040] arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK3 Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK3 carrier board. Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD, SPI NOR, CAN, M.2 E-Key or M.2 M-Key PCIe, USB . Signed-off-by: Marek Vasut Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mp-dhcom-pdk3.dts | 306 ++++++++++++++++++ 2 files changed, 307 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 2eb746f6a2c2..e2f86df16ab0 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts new file mode 100644 index 000000000000..b5e76b992a10 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marek Vasut + * + * DHCOM iMX8MP variant: + * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2 + * DHCOM PCB number: 660-100 or newer + * PDK3 PCB number: 669-100 or newer + */ + +/dts-v1/; + +#include +#include +#include "imx8mp-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX8M Plus DHCOM Premium Developer Kit (3)"; + compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart1; + }; + + clk_pcie: clock-pcie { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_c_0_hs_ep: endpoint { + remote-endpoint = <&dwc3_0_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + + usb_c_0_ss_ep: endpoint { + remote-endpoint = <&ptn5150_in_ep>; + }; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_a>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-1 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_b>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-2 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_c>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-3 { + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; /* GPIO E */ + label = "TA4-GPIO-E"; + linux,code = ; + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; /* GPIO D */ + pinctrl-0 = <&pinctrl_dhcom_d>; + pinctrl-names = "default"; + }; + + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* GPIO F */ + pinctrl-0 = <&pinctrl_dhcom_f>; + pinctrl-names = "default"; + }; + + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; /* GPIO G */ + pinctrl-0 = <&pinctrl_dhcom_g>; + pinctrl-names = "default"; + }; + + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */ + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; + + reg_avdd: regulator-avdd { /* AUDIO_VDD */ + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "AUDIO_VDD"; + }; +}; + +&i2c5 { + i2c-mux@70 { + compatible = "nxp,pca9540"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2cmuxed0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ptn5150_in_ep: endpoint { + remote-endpoint = <&usb_c_0_ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + ptn5150_out_ep: endpoint { + remote-endpoint = <&dwc3_0_ss_ep>; + }; + }; + }; + }; + + power-sensor@40 { + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <20000>; /* 0.02 R */ + ti,shunt-gain = <1>; /* Drop cca. 40mV */ + }; + + eeprom_board: eeprom@54 { + compatible = "atmel,24c04"; + pagesize = <16>; + reg = <0x54>; + }; + }; + + i2cmuxed1: i2c@1 { /* HDMI DDC I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +ðphy0g { + reg = <7>; +}; + +&fec { /* Second ethernet */ + pinctrl-0 = <&pinctrl_fec_rgmii>; + phy-handle = <ðphypdk>; + phy-mode = "rgmii-id"; + + mdio { + ethphypdk: ethernet-phy@7 { /* Micrel KSZ9131RNXI */ + compatible = "ethernet-phy-id0022.1642", + "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ethphy1>; + pinctrl-names = "default"; + reg = <7>; + reset-assert-us = <1000>; + /* RESET_N signal rise time ~100ms */ + reset-deassert-us = <120000>; + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&flexcan1 { + status = "okay"; +}; + +&pcie_phy { + clocks = <&clk_pcie>; + clock-names = "ref"; + fsl,refclk-pad-mode = ; + status = "okay"; +}; + +&pcie { + fsl,max-link-speed = <3>; + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usb_dwc3_0 { + usb-role-switch; + + port { + #address-cells = <1>; + #size-cells = <0>; + + dwc3_0_hs_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&usb_c_0_hs_ep>; + }; + + dwc3_0_ss_ep: endpoint@1 { + reg = <1>; + remote-endpoint = <&ptn5150_out_ep>; + }; + }; +}; + +&usb3_1 { + fsl,disable-port-power-control; + fsl,permanently-attached; +}; + +&usb_dwc3_1 { + /* This port has USB5734 Hub connected to it, PWR/OC pins are unused */ + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; + +&iomuxc { + /* + * GPIO_A,B,C,E are connected to buttons. + * GPIO_D,F,G,I are connected to LEDs. + * GPIO_H is connected to USB Hub RESET_N. + * GPIO_M is connected to CLKOUT2. + */ + pinctrl-0 = <&pinctrl_hog_base + &pinctrl_dhcom_h &pinctrl_dhcom_j &pinctrl_dhcom_k + &pinctrl_dhcom_l + &pinctrl_dhcom_int>; + + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40000000 + >; + }; +}; From 706b511f0c60a844b1e61dc2091054f0a28dcc91 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Mar 2023 10:58:26 +0100 Subject: [PATCH 0555/1040] dt-bindings: soc: imx8m-blk-ctrl: Rename blk_ctrl to blk-ctrl in examples Rename blk_ctrl@ to blk-ctrl (with dash instead of underscore) in examples so that they would match the imx8m[mn].dtsi in current Linux kernel. Signed-off-by: Marek Vasut Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml | 2 +- .../devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml index ecd86cfb3da4..e8da8f413966 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml @@ -70,7 +70,7 @@ examples: #include #include - disp_blk_ctl: blk_ctrl@32e28000 { + disp_blk_ctl: blk-ctrl@32e28000 { compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>, diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml index fbeaac399c50..9fb99fb40733 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml @@ -71,7 +71,7 @@ examples: #include #include - disp_blk_ctl: blk_ctrl@32e28000 { + disp_blk_ctl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; power-domains = <&pgc_dispmix>, <&pgc_dispmix>, From 9320fad102b0d14a007fa6d4293d00eede6e730a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 17 Mar 2023 10:58:27 +0100 Subject: [PATCH 0556/1040] dt-bindings: soc: imx-blk-ctrl: Drop leading label in blk-ctrl in examples Drop the leading label in block controller examples, it is unused. Signed-off-by: Marek Vasut Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml | 2 +- .../devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 2 +- .../devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 2 +- .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 2 +- .../devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml | 2 +- .../devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml index e8da8f413966..a02a09d574a2 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml @@ -70,7 +70,7 @@ examples: #include #include - disp_blk_ctl: blk-ctrl@32e28000 { + blk-ctrl@32e28000 { compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>, diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml index d71bb20d4907..25109376d7d4 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml @@ -150,7 +150,7 @@ examples: #include #include - vpu_blk_ctrl: blk-ctrl@38330000 { + blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml index 9fb99fb40733..eeec9965b091 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml @@ -71,7 +71,7 @@ examples: #include #include - disp_blk_ctl: blk-ctrl@32e28000 { + blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; power-domains = <&pgc_dispmix>, <&pgc_dispmix>, diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml index 1fe68b53b1d8..4214c1ab4971 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -76,7 +76,7 @@ examples: #include #include - hsio_blk_ctrl: blk-ctrl@32f10000 { + blk-ctrl@32f10000 { compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; reg = <0x32f10000 0x24>; clocks = <&clk IMX8MP_CLK_USB_ROOT>, diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml index 7263ebedf09f..ea5c90c6a1b6 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml @@ -59,7 +59,7 @@ examples: #include #include - vpu_blk_ctrl: blk-ctrl@38320000 { + blk-ctrl@38320000 { compatible = "fsl,imx8mq-vpu-blk-ctrl"; reg = <0x38320000 0x100>; power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml index 792ebecec22d..b3554e7f9e76 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -60,7 +60,7 @@ examples: #include #include - media_blk_ctrl: system-controller@4ac10000 { + system-controller@4ac10000 { compatible = "fsl,imx93-media-blk-ctrl", "syscon"; reg = <0x4ac10000 0x10000>; power-domains = <&mediamix>; From 91fa45bd8f8bfb69b0b5af72df93031cb0962d6a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Mar 2023 15:40:49 -0300 Subject: [PATCH 0557/1040] ARM: imx_v6_v7_defconfig: Select CONFIG_DRM_I2C_NXP_TDA998X Select CONFIG_DRM_I2C_NXP_TDA998X so that HDMI output can work by default on a imx6sx-udoo-neo board. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 02ccc86a8d4a..9475839e7fe1 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -274,6 +274,7 @@ CONFIG_VIDEO_OV5645=m CONFIG_VIDEO_ADV7180=m CONFIG_IMX_IPUV3_CORE=y CONFIG_DRM=y +CONFIG_DRM_I2C_NXP_TDA998X=y CONFIG_DRM_MSM=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y From 41e4f807f85d02a44426b87e01ed98b191dbbf9d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2023 16:00:02 -0600 Subject: [PATCH 0558/1040] bus: ti-sysc: Remove open coded "ranges" parsing "ranges" is a standard property and we have common helper functions for parsing it, so let's use them. Signed-off-by: Rob Herring Message-Id: <20230201220002.246907-1-robh@kernel.org> Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 41 +++++++++-------------------------------- 1 file changed, 9 insertions(+), 32 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 6afae9897843..9c8985515376 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -648,43 +648,20 @@ static int sysc_init_resets(struct sysc *ddata) static int sysc_parse_and_check_child_range(struct sysc *ddata) { struct device_node *np = ddata->dev->of_node; - const __be32 *ranges; - u32 nr_addr, nr_size; - int len, error; + struct of_range_parser parser; + struct of_range range; + int error; - ranges = of_get_property(np, "ranges", &len); - if (!ranges) { - dev_err(ddata->dev, "missing ranges for %pOF\n", np); - - return -ENOENT; - } - - len /= sizeof(*ranges); - - if (len < 3) { - dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); - - return -EINVAL; - } - - error = of_property_read_u32(np, "#address-cells", &nr_addr); + error = of_range_parser_init(&parser, np); if (error) - return -ENOENT; + return error; - error = of_property_read_u32(np, "#size-cells", &nr_size); - if (error) - return -ENOENT; - - if (nr_addr != 1 || nr_size != 1) { - dev_err(ddata->dev, "invalid ranges for %pOF\n", np); - - return -EINVAL; + for_each_of_range(&parser, &range) { + ddata->module_pa = range.cpu_addr; + ddata->module_size = range.size; + break; } - ranges++; - ddata->module_pa = of_translate_address(np, ranges++); - ddata->module_size = be32_to_cpup(ranges); - return 0; } From 2ee1bdd3114f62bb542ab51d2fececb20a4481da Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:34 -0600 Subject: [PATCH 0559/1040] bus: ti-sysc: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Message-Id: <20230310144734.1546656-1-robh@kernel.org> Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 9c8985515376..97e6421046ee 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -941,7 +941,7 @@ static int sysc_map_and_check_registers(struct sysc *ddata) sysc_check_children(ddata); - if (!of_get_property(np, "reg", NULL)) + if (!of_property_present(np, "reg")) return 0; error = sysc_parse_registers(ddata); From 78e812f0406c765fc5623b1d68e3c6e86cb32e5a Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Fri, 24 Mar 2023 10:16:26 +0800 Subject: [PATCH 0560/1040] soc: amlogic: meson-pwrc: Use dev_err_probe() Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen Reviewed-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/202303241016261854322@zte.com.cn Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c index 312fd9afccb0..5d4f12800d93 100644 --- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c +++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c @@ -308,11 +308,9 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev) } rstc = devm_reset_control_array_get_exclusive(&pdev->dev); - if (IS_ERR(rstc)) { - if (PTR_ERR(rstc) != -EPROBE_DEFER) - dev_err(&pdev->dev, "failed to get reset lines\n"); - return PTR_ERR(rstc); - } + if (IS_ERR(rstc)) + return dev_err_probe(&pdev->dev, PTR_ERR(rstc), + "failed to get reset lines\n"); vpu_clk = devm_clk_get(&pdev->dev, "vpu"); if (IS_ERR(vpu_clk)) { From 0fff0e49d72a53c51d8903fbadb2e6a84e531c4a Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 7 Mar 2023 10:17:13 -0600 Subject: [PATCH 0561/1040] ARM: dts: ti: Add AM57xx GP EVM board support The AM57xx GP EVM boards are built on top the AM57xx BeagleBoard-X15. The EVM extends the BeagleBoard by adding a touchscreen, some buttons, and a handful of peripheral extension slots. Being a plugin extension of an existing standalone board; we define the am57xx-evm as a composite-DTB of the base am57xx-beagle-x15 and a new am57xx-evm overlay. Signed-off-by: Tero Kristo Signed-off-by: Tomi Valkeinen Signed-off-by: Suman Anna Signed-off-by: Andrew Davis Message-Id: <20230307161715.15209-2-afd@ti.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/am57xx-evm.dtso | 127 ++++++++++++++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 arch/arm/boot/dts/am57xx-evm.dtso diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe4152e5846..7f850cf5f063 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -994,10 +994,12 @@ dtb-$(CONFIG_SOC_OMAP5) += \ omap5-igep0050.dtb \ omap5-sbc-t54.dtb \ omap5-uevm.dtb +am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am57xx-beagle-x15-revc.dtb \ + am57xx-evm.dtb \ am5729-beagleboneai.dtb \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ diff --git a/arch/arm/boot/dts/am57xx-evm.dtso b/arch/arm/boot/dts/am57xx-evm.dtso new file mode 100644 index 000000000000..12385a31061e --- /dev/null +++ b/arch/arm/boot/dts/am57xx-evm.dtso @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DT overlay for AM57xx GP EVM boards + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + model = "TI AM5728 EVM"; + + aliases { + display0 = "/display"; + display1 = "/connector"; // Fixme: &lcd0 and &hdmi0 could be + // resolved here correcly based on + // information in the base dtb symbol + // table with a fix in dtc + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user1 { + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + label = "USER1"; + linux,code = ; + }; + + button-user2 { + gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + label = "USER2"; + linux,code = ; + }; + + button-user3 { + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + label = "USER3"; + linux,code = ; + }; + + button-user4 { + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + label = "USER4"; + linux,code = ; + }; + + button-user5 { + gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + label = "USER5"; + linux,code = ; + }; + }; + + lcd0: display { + compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; + backlight = <&lcd_bl>; + enable-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + label = "lcd"; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 243 245 247 249 251 252 253 255>; + default-brightness-level = <8>; + pwms = <&ehrpwm1 0 50000 0>; + }; +}; + +&ehrpwm1 { + status = "okay"; +}; + +&epwmss1 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@5c { + compatible = "pixcir,pixcir_tangoc"; + attb-gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + reg = <0x5c>; + reset-gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + }; +}; + +&uart8 { + status = "okay"; +}; + +&dss { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpi_out: endpoint { + data-lines = <24>; + remote-endpoint = <&lcd_in>; + }; + }; + }; +}; From 26d03d14171c0e90654f6dcc8551bc58ee6db1e8 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 7 Mar 2023 10:17:14 -0600 Subject: [PATCH 0562/1040] ARM: dts: ti: Add AM57xx GP EVM Rev A3 board support The A3 revision of the AM57xx GP EVM has the same EVM feature set as the original but is paired with an updated revision C BeagleBoard X15. DT Overlays allow us to model this in the same way, we simply apply the EVM overlay to the Rev C BeagleBoard to create the Rev A3 AM57xx GP EVM. Signed-off-by: Andrew Davis Message-Id: <20230307161715.15209-3-afd@ti.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7f850cf5f063..c1297fd06d2a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -995,11 +995,13 @@ dtb-$(CONFIG_SOC_OMAP5) += \ omap5-sbc-t54.dtb \ omap5-uevm.dtb am57xx-evm-dtbs := am57xx-beagle-x15.dtb am57xx-evm.dtbo +am57xx-evm-reva3-dtbs := am57xx-beagle-x15-revc.dtb am57xx-evm.dtbo dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-beagle-x15.dtb \ am57xx-beagle-x15-revb1.dtb \ am57xx-beagle-x15-revc.dtb \ am57xx-evm.dtb \ + am57xx-evm-reva3.dtb \ am5729-beagleboneai.dtb \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ From a63945c3b56174537a4a655676fbe965f974b6b1 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 7 Mar 2023 10:17:15 -0600 Subject: [PATCH 0563/1040] ARM: dts: am57xx-idk: Add IDK displays and touchscreens This is a more interesting use of DT Overlays than the previous patches. Here we have two touchscreen modules. Each is compatible with, and can be attached to, either of the two AM57xx IDK development board variants (AM571x or AM572x). Due to the way the extension header was wired on the development boards, the touch sensor on the touchscreen modules will connect to different SoC pins when connected. For this the touch sensor is modeled as an additional overlay that is specific to the development board for which it is connected. Basically the LCD overlay can be swapped, but the touchscreen overlay that attaches to the LCD must be used with the corresponding base DT and not to the LCD. AM571x -\ /- osd101t2045.dtbo -\ /- am571x-idk-touchscreen.dtbo X X AM572x -/ \- osd101t2587.dtbo -/ \- am572x-idk-touchscreen.dtbo Signed-off-by: Andrew Davis Message-Id: <20230307161715.15209-4-afd@ti.com> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 4 ++ arch/arm/boot/dts/am571x-idk-touchscreen.dtso | 32 +++++++++ arch/arm/boot/dts/am572x-idk-touchscreen.dtso | 32 +++++++++ .../boot/dts/am57xx-idk-lcd-osd101t2045.dtso | 63 ++++++++++++++++++ .../boot/dts/am57xx-idk-lcd-osd101t2587.dtso | 66 +++++++++++++++++++ 5 files changed, 197 insertions(+) create mode 100644 arch/arm/boot/dts/am571x-idk-touchscreen.dtso create mode 100644 arch/arm/boot/dts/am572x-idk-touchscreen.dtso create mode 100644 arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso create mode 100644 arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c1297fd06d2a..ad06ab3c62af 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1006,8 +1006,12 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ am572x-idk.dtb \ + am572x-idk-touchscreen.dtbo \ am571x-idk.dtb \ + am571x-idk-touchscreen.dtbo \ am574x-idk.dtb \ + am57xx-idk-lcd-osd101t2045.dtbo \ + am57xx-idk-lcd-osd101t2587.dtbo \ dra7-evm.dtb \ dra72-evm.dtb \ dra72-evm-revc.dtb \ diff --git a/arch/arm/boot/dts/am571x-idk-touchscreen.dtso b/arch/arm/boot/dts/am571x-idk-touchscreen.dtso new file mode 100644 index 000000000000..c051ee6c1130 --- /dev/null +++ b/arch/arm/boot/dts/am571x-idk-touchscreen.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: edt-ft5506@38 { + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + + /* GPIO line is inverted before going to touch panel */ + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/am572x-idk-touchscreen.dtso b/arch/arm/boot/dts/am572x-idk-touchscreen.dtso new file mode 100644 index 000000000000..573e932b1239 --- /dev/null +++ b/arch/arm/boot/dts/am572x-idk-touchscreen.dtso @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen: edt-ft5506@38 { + compatible = "edt,edt-ft5506", "edt,edt-ft5x06"; + + reg = <0x38>; + + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + + /* GPIO line is inverted before going to touch panel */ + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + touchscreen-size-x = <1920>; + touchscreen-size-y = <1200>; + + wakeup-source; + }; +}; diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso new file mode 100644 index 000000000000..25d74e9f3c9e --- /dev/null +++ b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2045.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + aliases { + display0 = "/display"; + display1 = "/connector"; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 1>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&dsi_bridge { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + lcd: display { + compatible = "osddisplays,osd101t2045-53ts"; + reg = <0>; + + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&lcd_in>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso new file mode 100644 index 000000000000..8cea7ba32487 --- /dev/null +++ b/arch/arm/boot/dts/am57xx-idk-lcd-osd101t2587.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + aliases { + display0 = "/display"; + display1 = "/connector"; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 1>; + brightness-levels = <0 51 53 56 62 75 101 152 255>; + default-brightness-level = <8>; + }; +}; + +&dsi_bridge { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + lcd: display { + compatible = "osddisplays,osd101t2587-53ts"; + reg = <0>; + + label = "lcd"; + + backlight = <&lcd_bl>; + + port { + lcd_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; +}; + +&dsi_bridge_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&lcd_in>; + }; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ecap0 { + status = "okay"; +}; From a622310f7f0185da02e42cdb06475f533efaae60 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Fri, 13 Jan 2023 22:11:51 +0100 Subject: [PATCH 0564/1040] ARM: dts: gta04: fix excess dma channel usage OMAP processors support 32 channels but there is no check or inspect this except booting a device and looking at dmesg reports of not available channels. Recently some more subsystems with DMA (aes1+2) were added filling the list of dma channels beyond the limit of 32 (even if other parameters indicate 96 or 128 channels). This leads to random subsystem failures i(e.g. mcbsp for audio) after boot or boot messages that DMA can not be initialized. Another symptom is that /sys/kernel/debug/dmaengine/summary has 32 entries and does not show all required channels. Fix by disabling unused (on the GTA04 hardware) mcspi1...4. Each SPI channel allocates 4 DMA channels rapidly filling the available ones. Disabling unused SPI modules on the OMAP3 SoC may also save some energy (has not been checked). Fixes: c312f066314e ("ARM: dts: omap3: Migrate AES from hwmods to sysc-omap2") Signed-off-by: H. Nikolaus Schaller [re-enabled aes2, improved commit subject line] Signed-off-by: Andreas Kemnade Message-Id: <20230113211151.2314874-1-andreas@kemnade.info> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 87e0ab1bbe95..e0be0fb23f80 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -612,6 +612,22 @@ clock-frequency = <100000>; }; +&mcspi1 { + status = "disabled"; +}; + +&mcspi2 { + status = "disabled"; +}; + +&mcspi3 { + status = "disabled"; +}; + +&mcspi4 { + status = "disabled"; +}; + &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; From f47fc3aa346a506ac8552eb12dd9240194e01474 Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Thu, 16 Feb 2023 17:46:43 +0100 Subject: [PATCH 0565/1040] ARM: dts: omap3-gta04: fix compatible record for GTA04 board Vendor of the GTA04 boards is and always was Golden Delicious Computers GmbH&Co. KG, Germany and not Texas Instruments. Maybe, TI was references here because the GTA04 was based on the BeagleBoard design which is designated as "ti,omap3-beagle". While we are looking at vendors of omap3 based devices, we also add the record for OpenPandora. The DTS files for the pandora device already make use of it. Signed-off-by: H. Nikolaus Schaller Message-Id: <38b49aad0cf33bb5d6a511edb458139b58e367fd.1676566002.git.hns@goldelico.com> Acked-by: Rob Herring Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ arch/arm/boot/dts/omap3-gta04.dtsi | 3 +-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..d394d25d2162 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -516,6 +516,8 @@ patternProperties: description: GlobalTop Technology, Inc. "^gmt,.*": description: Global Mixed-mode Technology, Inc. + "^goldelico,.*": + description: Golden Delicious Computers GmbH & Co. KG "^goodix,.*": description: Shenzhen Huiding Technology Co., Ltd. "^google,.*": @@ -977,6 +979,8 @@ patternProperties: description: OpenCores.org "^openembed,.*": description: OpenEmbed + "^openpandora,.*": + description: OpenPandora GmbH "^openrisc,.*": description: OpenRISC.io "^option,.*": diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index e0be0fb23f80..4183fde46059 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -11,8 +11,7 @@ / { model = "OMAP3 GTA04"; - compatible = "ti,omap3-gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3"; - + compatible = "goldelico,gta04", "ti,omap3630", "ti,omap36xx", "ti,omap3"; cpus { cpu@0 { cpu0-supply = <&vcc>; From 29f4747a19a53a949b76a587fe3674dd5d7303f9 Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:22:55 +0100 Subject: [PATCH 0566/1040] ARM: dts: am335x-phycore-som: Add alias for TPS65910 RTC Without an alias for the TPS65910 RTC, it snatches the rtc0 device in advance to the I2C RTC assigned to that alias. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-1-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index e2cec1ffaa4c..6819cec588a7 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -14,6 +14,7 @@ aliases { rtc0 = &i2c_rtc; rtc1 = &rtc; + rtc2 = &tps; }; cpus { From d0c46bed1cc020c8e84685c74dec1be3383cfb73 Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:22:56 +0100 Subject: [PATCH 0567/1040] ARM: dts: am335x-wega: Fix audio codec by using simple-audio-card driver. Sound did not work with the previous EVM sound card binding, EVM dts switched to using 'simple-audio-card', so this fixes audio codec by using simple-audio-card driver. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-2-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-wega.dtsi | 45 ++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index f957fea8208e..acff59335f12 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -8,8 +8,34 @@ model = "Phytec AM335x phyBOARD-WEGA"; compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; - sound: sound_iface { - compatible = "ti,da830-evm-audio"; + sound: sound-iface { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-wega"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound_iface_main>; + simple-audio-card,frame-master = <&sound_iface_main>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + + sound_iface_main: simple-audio-card,codec { + sound-dai = <&tlv320aic3007>; + clocks = <&mcasp0_fck>; + }; + }; vcc3v3: fixedregulator1 { @@ -36,6 +62,7 @@ &i2c0 { tlv320aic3007: tlv320aic3007@18 { + #sound-dai-cells = <0>; compatible = "ti,tlv320aic3007"; reg = <0x18>; AVDD-supply = <&vcc3v3>; @@ -47,6 +74,7 @@ }; &mcasp0 { + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&mcasp0_pins>; op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ @@ -59,19 +87,6 @@ status = "okay"; }; -&sound { - ti,model = "AM335x-Wega"; - ti,audio-codec = <&tlv320aic3007>; - ti,mcasp-controller = <&mcasp0>; - ti,audio-routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "LINE1L", "Line In", - "LINE1R", "Line In"; - clocks = <&mcasp0_fck>; - clock-names = "mclk"; - status = "okay"; -}; /* CAN Busses */ &am33xx_pinmux { From 3c556f7990604433165fa052f03a88a2b6bc7638 Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:22:57 +0100 Subject: [PATCH 0568/1040] ARM: dts: am335x-wega: Change node name of sound card, remove underscores. Change node name of sound card to recommended generic and remove also further underscores in other node names. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-3-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-wega.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index acff59335f12..6a103f17585b 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -8,7 +8,7 @@ model = "Phytec AM335x phyBOARD-WEGA"; compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; - sound: sound-iface { + sound: sound { compatible = "simple-audio-card"; simple-audio-card,name = "snd-wega"; simple-audio-card,format = "i2s"; @@ -49,7 +49,7 @@ /* Audio */ &am33xx_pinmux { - mcasp0_pins: pinmux_mcasp0 { + mcasp0_pins: pinmux-mcasp0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0) @@ -90,7 +90,7 @@ /* CAN Busses */ &am33xx_pinmux { - dcan1_pins: pinmux_dcan1 { + dcan1_pins: pinmux-dcan1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ @@ -106,7 +106,7 @@ /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { + ethernet1_pins: pinmux-ethernet1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ @@ -146,7 +146,7 @@ /* MMC */ &am33xx_pinmux { - mmc1_pins: pinmux_mmc1 { + mmc1_pins: pinmux-mmc1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -176,14 +176,14 @@ /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux_uart0 { + uart0_pins: pinmux-uart0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1_pins { + uart1_pins: pinmux-uart1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) From ca607f0bd95c1104c6e515b53064833ddc6fbf40 Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:22:58 +0100 Subject: [PATCH 0569/1040] ARM: dts: am335x-pcm-935: Remove underscore in node names. Remove underscore in node names following conventions. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-4-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-pcm-953.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index 947497413977..92f2a283fe92 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -29,7 +29,7 @@ }; /* User IO */ - user_leds: user_leds { + user_leds: user-leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; @@ -47,7 +47,7 @@ }; }; - user_buttons: user_buttons { + user_buttons: user-buttons { compatible = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&user_buttons_pins>; @@ -70,14 +70,14 @@ }; &am33xx_pinmux { - user_buttons_pins: pinmux_user_buttons { + user_buttons_pins: pinmux-user-buttons { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu0.gpio3_7 */ AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* emu1.gpio3_8 */ >; }; - user_leds_pins: pinmux_user_leds { + user_leds_pins: pinmux-user-leds { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn1.gpio1_30 */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn2.gpio1_31 */ @@ -87,7 +87,7 @@ /* CAN */ &am33xx_pinmux { - dcan1_pins: pinmux_dcan1 { + dcan1_pins: pinmux-dcan1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart1_rxd.dcan1_tx_mux2 */ AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2) /* uart1_txd.dcan1_rx_mux2 */ @@ -144,7 +144,7 @@ pinctrl-names = "default"; pinctrl-0 = <&cb_gpio_pins>; - cb_gpio_pins: pinmux_cb_gpio { + cb_gpio_pins: pinmux-cb-gpio { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* uart0_rtsn.gpio1_9 */ @@ -154,7 +154,7 @@ /* MMC */ &am33xx_pinmux { - mmc1_pins: pinmux_mmc1_pins { + mmc1_pins: pinmux-mmc1-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -178,14 +178,14 @@ /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux_uart0 { + uart0_pins: pinmux-uart0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart1_pins: pinmux_uart1 { + uart1_pins: pinmux-uart1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) @@ -194,14 +194,14 @@ >; }; - uart2_pins: pinmux_uart2 { + uart2_pins: pinmux-uart2 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ >; }; - uart3_pins: pinmux_uart3 { + uart3_pins: pinmux-uart3 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd3.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rxd2.uart3_txd */ From 7395d9d0d438d95a3f6517092af85dfd2ae4406d Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:22:59 +0100 Subject: [PATCH 0570/1040] ARM: dts: am335x-regor: Remove underscore in node names. Remove underscore in node names following conventions. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-5-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-regor.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/am335x-regor.dtsi b/arch/arm/boot/dts/am335x-regor.dtsi index 7b3966ee51b9..3894f14a914c 100644 --- a/arch/arm/boot/dts/am335x-regor.dtsi +++ b/arch/arm/boot/dts/am335x-regor.dtsi @@ -18,7 +18,7 @@ }; /* User IO */ - user_leds: user_leds { + user_leds: user-leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; @@ -39,7 +39,7 @@ /* User Leds */ &am33xx_pinmux { - user_leds_pins: pinmux_user_leds { + user_leds_pins: pinmux-user-leds { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */ @@ -49,7 +49,7 @@ /* CAN Busses */ &am33xx_pinmux { - dcan1_pins: pinmux_dcan1 { + dcan1_pins: pinmux-dcan1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ @@ -65,7 +65,7 @@ /* Ethernet */ &am33xx_pinmux { - ethernet1_pins: pinmux_ethernet1 { + ethernet1_pins: pinmux-ethernet1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */ AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */ @@ -108,7 +108,7 @@ pinctrl-names = "default"; pinctrl-0 = <&user_gpios_pins>; - user_gpios_pins: pinmux_user_gpios { + user_gpios_pins: pinmux-user-gpios { pinctrl-single,pins = < /* DIGIN 1-4 */ AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */ @@ -126,7 +126,7 @@ /* MMC */ &am33xx_pinmux { - mmc1_pins: pinmux_mmc1 { + mmc1_pins: pinmux-mmc1 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) @@ -155,14 +155,14 @@ /* UARTs */ &am33xx_pinmux { - uart0_pins: pinmux_uart0 { + uart0_pins: pinmux-uart0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; - uart2_pins: pinmux_uart2 { + uart2_pins: pinmux-uart2 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */ AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */ @@ -184,7 +184,7 @@ /* RS485 - UART1 */ &am33xx_pinmux { - uart1_rs485_pins: pinmux_uart1_rs485_pins { + uart1_rs485_pins: pinmux-uart1-rs485-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) From a562f0e0514c343c21a19b7575fce72ad08b2fcf Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:23:00 +0100 Subject: [PATCH 0571/1040] ARM: dts: am335x-phycore-som: Remove underscore in node names. Remove underscore in node names following conventions. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-6-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-phycore-som.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 6819cec588a7..5bb05620da56 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -49,7 +49,7 @@ /* EMMC */ &am33xx_pinmux { - emmc_pins: pinmux_emmc_pins { + emmc_pins: pinmux-emmc-pins { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ @@ -125,7 +125,7 @@ /* I2C Busses */ &am33xx_pinmux { - i2c0_pins: pinmux_i2c0 { + i2c0_pins: pinmux-i2c0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) @@ -165,7 +165,7 @@ /* NAND memory */ &am33xx_pinmux { - nandflash_pins: pinmux_nandflash { + nandflash_pins: pinmux-nandflash { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) @@ -317,7 +317,7 @@ /* SPI Busses */ &am33xx_pinmux { - spi0_pins: pinmux_spi0 { + spi0_pins: pinmux-spi0 { pinctrl-single,pins = < AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0) AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0) From 599b0a1bc55920860affc0792894e58de2bb8931 Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:23:01 +0100 Subject: [PATCH 0572/1040] ARM: dts: am335x-pcm-953: Remove superseded/invalid LED trigger. According to docu and dtschema check, 'linux,default-trigger = gpio' is no longer valid, so remove it. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-7-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-pcm-953.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/am335x-pcm-953.dtsi b/arch/arm/boot/dts/am335x-pcm-953.dtsi index 92f2a283fe92..67c7fcc52ce6 100644 --- a/arch/arm/boot/dts/am335x-pcm-953.dtsi +++ b/arch/arm/boot/dts/am335x-pcm-953.dtsi @@ -36,13 +36,11 @@ user-led0 { gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "gpio"; default-state = "on"; }; user-led1 { gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; - linux,default-trigger = "gpio"; default-state = "on"; }; }; From dae557a5af236af2785231410c1fcf09a4b31032 Mon Sep 17 00:00:00 2001 From: Steffen Hemer Date: Tue, 14 Feb 2023 14:23:02 +0100 Subject: [PATCH 0573/1040] ARM: dts: am335x-phycore-som: Remove superseded/invalid GPMC NAND type. According to docu and dtschema check, 'gpmc,device-nand = true' is no longer valid, so remove it. Signed-off-by: Steffen Hemer Message-Id: <20230214132302.39087-8-s.hemer@phytec.de> Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-phycore-som.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 5bb05620da56..034dc5181679 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -203,7 +203,6 @@ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; - gpmc,device-nand = "true"; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; From d4f1d01d3492e18b15df5c680fcaa4e14fc77481 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Sat, 27 Aug 2022 17:46:04 +0800 Subject: [PATCH 0574/1040] bus: ti-sysc: Use list_for_each_entry() helper Convert list_for_each() to list_for_each_entry() where applicable. Signed-off-by: Yang Yingliang Message-Id: <20220827094604.3325887-1-yangyingliang@huawei.com> Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 97e6421046ee..524f4113043c 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -2507,11 +2507,9 @@ static struct dev_pm_domain sysc_child_pm_domain = { static void sysc_reinit_modules(struct sysc_soc_info *soc) { struct sysc_module *module; - struct list_head *pos; struct sysc *ddata; - list_for_each(pos, &sysc_soc->restored_modules) { - module = list_entry(pos, struct sysc_module, node); + list_for_each_entry(module, &sysc_soc->restored_modules, node) { ddata = module->ddata; sysc_reinit_module(ddata, ddata->enabled); } @@ -3191,12 +3189,10 @@ static void sysc_cleanup_static_data(void) static int sysc_check_disabled_devices(struct sysc *ddata) { struct sysc_address *disabled_module; - struct list_head *pos; int error = 0; mutex_lock(&sysc_soc->list_lock); - list_for_each(pos, &sysc_soc->disabled_modules) { - disabled_module = list_entry(pos, struct sysc_address, node); + list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) { if (ddata->module_pa == disabled_module->base) { dev_dbg(ddata->dev, "module disabled for this SoC\n"); error = -ENODEV; From b79ad2307a1dfd9cba3cfce6445fa0be74a757a0 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Thu, 11 Aug 2022 20:11:19 +0800 Subject: [PATCH 0575/1040] bus: ti-sysc: Fix comment typo The double `the' is duplicated in the comment, remove one. Signed-off-by: Jason Wang Message-Id: <20220811121119.20288-1-wangborong@cdjrlc.com> Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 524f4113043c..6c49de37d5e9 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -890,7 +890,7 @@ static int sysc_check_registers(struct sysc *ddata) * within the interconnect target module range. For example, SGX has * them at offset 0x1fc00 in the 32MB module address space. And cpsw * has them at offset 0x1200 in the CPSW_WR child. Usually the - * the interconnect target module registers are at the beginning of + * interconnect target module registers are at the beginning of * the module range though. */ static int sysc_ioremap(struct sysc *ddata) From b2ccba9e8cdc6fb3985cc227844e7c6af309ffb1 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Sun, 26 Mar 2023 21:34:49 +0100 Subject: [PATCH 0576/1040] firmware: arm_scmi: Fix xfers allocation on Rx channel Two distinct pools of xfer descriptors are allocated at initialization time: one (Tx) used to provide xfers to track commands and their replies (or delayed replies) and another (Rx) to pick xfers from to be used for processing notifications. Such pools, though, are allocated globally to be used by the whole SCMI instance, they are not allocated per-channel and as such the allocation of notifications xfers cannot be simply skipped if no Rx channel was found for the base protocol common channel, because there could be defined more optional per-protocol dedicated channels that instead support Rx channels. Change the conditional check to skip allocation for the notification pool only if no Rx channel has been detected on any per-channel protocol at all. Fixes: 4ebd8f6dea81 ("firmware: arm_scmi: Add receive buffer support for notifications") Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230326203449.3492948-1-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/driver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index dbc474ff62b7..e7d97b59963b 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -2289,7 +2289,7 @@ static int scmi_xfer_info_init(struct scmi_info *sinfo) return ret; ret = __scmi_xfer_info_init(sinfo, &sinfo->tx_minfo); - if (!ret && idr_find(&sinfo->rx_idr, SCMI_PROTOCOL_BASE)) + if (!ret && !idr_is_empty(&sinfo->rx_idr)) ret = __scmi_xfer_info_init(sinfo, &sinfo->rx_minfo); return ret; From e45f243409db98d610248c843b25435e7fb0baf3 Mon Sep 17 00:00:00 2001 From: Dmitry Rokosov Date: Fri, 24 Mar 2023 17:55:57 +0300 Subject: [PATCH 0577/1040] firmware: meson_sm: populate platform devices from sm device tree data In some meson boards, secure monitor device has children, for example, power secure controller. By default, secure monitor isn't the bus in terms of device tree subsystem, so the of_platform initialization code doesn't populate its device tree data. As a result, secure monitor's children aren't probed at all. Run the 'of_platform_populate()' routine manually to resolve such issues. Signed-off-by: Dmitry Rokosov Acked-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230324145557.27797-1-ddrokosov@sberdevices.ru Signed-off-by: Neil Armstrong --- drivers/firmware/meson/meson_sm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/meson/meson_sm.c b/drivers/firmware/meson/meson_sm.c index 3f5ff9ed668e..798bcdb05d84 100644 --- a/drivers/firmware/meson/meson_sm.c +++ b/drivers/firmware/meson/meson_sm.c @@ -311,11 +311,14 @@ static int __init meson_sm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, fw); - pr_info("secure-monitor enabled\n"); + if (devm_of_platform_populate(dev)) + goto out_in_base; if (sysfs_create_group(&pdev->dev.kobj, &meson_sm_sysfs_attr_group)) goto out_in_base; + pr_info("secure-monitor enabled\n"); + return 0; out_in_base: From 20c082a2ba25374a13505b78cdad7f6a2cf8d763 Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Fri, 24 Mar 2023 16:51:04 +0100 Subject: [PATCH 0578/1040] memory: stm32-fmc2-ebi: depends on ARCH_STM32 instead of MACH_STM32MP157 To be able to compile the driver on all STM32MP SOCs, we move the "depends on" on ARCH_STM32. Signed-off-by: Christophe Kerello Link: https://lore.kernel.org/r/20230324155105.826063-2-christophe.kerello@foss.st.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index fac290e48e0b..91774e6ee624 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -228,7 +228,7 @@ config RENESAS_RPCIF config STM32_FMC2_EBI tristate "Support for FMC2 External Bus Interface on STM32MP SoCs" - depends on MACH_STM32MP157 || COMPILE_TEST + depends on ARCH_STM32 || COMPILE_TEST select MFD_SYSCON help Select this option to enable the STM32 FMC2 External Bus Interface From d97e712be401a67e0db8e79612b30d65e9619f41 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Mar 2023 14:32:43 +0200 Subject: [PATCH 0579/1040] arm64: dts: qcom: sc8280xp-x13s: drop bogus 'input-enable' The sc8280xp pin controller does not have a way to enable or disable the input buffer so drop the unnecessary 'input-enable' property which is about to be deprecated. Link: https://lore.kernel.org/lkml/20230323102605.6.I291ce0ba2c6ea80b341659c4f75a567a76dd7ca6@changeid Signed-off-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327123243.4527-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 19d5ac6591fa..7c7273e8ce9b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1182,7 +1182,6 @@ hall_int_n_default: hall-int-n-state { pins = "gpio107"; function = "gpio"; - input-enable; bias-disable; }; From 280e05a3942a010cdd3bfd8b32ae00efb6761dea Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 27 Mar 2023 14:29:48 +0200 Subject: [PATCH 0580/1040] arm64: dts: qcom: sc8280xp-pmics: fix pon compatible and registers The pmk8280 PMIC PON peripheral is gen3 and uses two sets of registers; hlos and pbs. This specifically fixes the following error message during boot when the pbs registers are not defined: PON_PBS address missing, can't read HW debounce time Note that this also enables the spurious interrupt workaround introduced by commit 0b65118e6ba3 ("Input: pm8941-pwrkey - add software key press debouncing support") (which may or may not be needed). Fixes: ccd3517faf18 ("arm64: dts: qcom: sc8280xp: Add reference device") Signed-off-by: Johan Hovold Tested-by: Steev Klimaszewski #Thinkpad X13s Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327122948.4323-1-johan+linaro@kernel.org --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index c35e7f6bd657..a0ba535bb6c9 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -59,8 +59,9 @@ #size-cells = <0>; pmk8280_pon: pon@1300 { - compatible = "qcom,pm8998-pon"; - reg = <0x1300>; + compatible = "qcom,pmk8350-pon"; + reg = <0x1300>, <0x800>; + reg-names = "hlos", "pbs"; pmk8280_pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; From c747968cf945d7d57d117e4414465fdacb26ab4b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:43 +0200 Subject: [PATCH 0581/1040] arm64: dts: qcom: sdm845-cheza: use just "port" in Innolux panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sdm845-cheza-r2.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index f2b48241d15c..59ad6a8403d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -135,11 +135,9 @@ backlight = <&backlight>; no-hpd; - ports { - panel_in: port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; }; }; }; From e3cc58599167db818fbcba3b0c3debb3d6776f4a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:44 +0200 Subject: [PATCH 0582/1040] arm64: dts: qcom: sc8280xp-lenovo-thinkpad-x13s: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc8280xp-lenovo-thinkpad-x13s.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-2-krzysztof.kozlowski@linaro.org --- .../arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 7c7273e8ce9b..3bd36a4ac205 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -549,11 +549,9 @@ backlight = <&backlight>; power-supply = <&vreg_edp_3p3>; - ports { - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss0_dp3_out>; - }; + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; }; }; }; From 78f7be3c4c2abcd5845f6acb30754173c4aed4b3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:45 +0200 Subject: [PATCH 0583/1040] arm64: dts: qcom: sc8280xp-crd: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc8280xp-crd.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index d7b537284990..6b4e1541ee39 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -413,11 +413,9 @@ backlight = <&backlight>; - ports { - port { - edp_panel_in: endpoint { - remote-endpoint = <&mdss0_dp3_out>; - }; + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss0_dp3_out>; }; }; }; From 746bda7d9dd9518793034d7008a19e4cf5c3004d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:46 +0200 Subject: [PATCH 0584/1040] arm64: dts: qcom: sc7180-idp: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7180-idp.dtb: panel@0: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' sc7180-idp.dtb: panel@0: 'port' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index c3bdd3295c02..fcabbc6a897f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -312,14 +312,9 @@ reset-gpios = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; }; }; }; From 88904a12fbcbd97e56d341080845ce0807164fb5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:47 +0200 Subject: [PATCH 0585/1040] arm64: dts: qcom: sc7180-trogdor-quackingstick: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7180-trogdor-quackingstick-r0.dtb: panel@0: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-5-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi index cb41ccdaccfd..8e7b42f843d4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi @@ -65,14 +65,9 @@ backlight = <&backlight>; rotation = <270>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; }; }; }; From c28d9029f3b68a42794a0527696c91f7b31e81f3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:48 +0200 Subject: [PATCH 0586/1040] arm64: dts: qcom: sc7180-trogdor-wormdingler: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7180-trogdor-wormdingler-rev1-boe.dtb: panel@0: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-6-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 9832e752da35..262d6691abd9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -124,14 +124,9 @@ backlight = <&backlight>; rotation = <270>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; }; }; }; From ff5508b93b9c5dd723ac68c315be1cf727845063 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:49 +0200 Subject: [PATCH 0587/1040] arm64: dts: qcom: sc7180-qcard: use just "port" in panel The panel bindings expect to have only one port, thus they do not allow to use "ports" node: sc7280-herobrine-zombie-nvme-lte.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index cb0cc2ba2fa3..88b3586e389f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -354,14 +354,9 @@ backlight = <&pm8350c_pwm_backlight>; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - edp_panel_in: endpoint { - remote-endpoint = <&mdss_edp_out>; - }; + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_edp_out>; }; }; }; From 9ec6040a48300a7527e46505e121f71a3e0f924f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:50 +0200 Subject: [PATCH 0588/1040] arm64: dts: qcom: sc7180-trogdor-lazor: correct panel compatible innolux,n116bca-ea1 is not exactly compatible witg innolux,n116bge, as they have their own driver data. Bindings do not allow fallback: sc7180-trogdor-lazor-limozeen-nots-r4.dtb: panel: compatible: ['innolux,n116bca-ea1', 'innolux,n116bge'] is too long Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-8-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts index 235cda2bba5e..7f01573b5543 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts @@ -23,7 +23,7 @@ /delete-node/&ap_ts; &panel { - compatible = "innolux,n116bca-ea1", "innolux,n116bge"; + compatible = "innolux,n116bca-ea1"; }; &sdhc_2 { From 9f3c858ecde007b147491d5f9d19484090fbe3b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:51 +0200 Subject: [PATCH 0589/1040] arm64: dts: qcom: sdm845-oneplus: drop invalid panel properties Panel does not have children with unit-addresses thus address/size-cells are not valid: panel@0: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index b01542d79ae2..0c268c560d37 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -347,8 +347,6 @@ display_panel: panel@0 { status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; reg = <0>; vddio-supply = <&vreg_l14a_1p88>; From e12482e688303d93507ae7c1346a27dbaa1811fb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:52 +0200 Subject: [PATCH 0590/1040] arm64: dts: qcom: sdm845-xiaomi-beryllium: drop invalid panel properties Panel does not have children with unit-addresses thus address/size-cells are not valid: sdm845-xiaomi-beryllium-tianma.dtb: panel@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells' were unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index e0fda4d754fe..e444ef1cd742 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -232,9 +232,6 @@ vddpos-supply = <&lab>; vddneg-supply = <&ibb>; - #address-cells = <1>; - #size-cells = <0>; - backlight = <&pmi8998_wled>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; From 0514b376da09f9e4a6a4581112bcac063ee3ad9b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:57:53 +0200 Subject: [PATCH 0591/1040] arm64: dts: qcom: sdm845-xiaomi-beryllium: correct compatible Tianma FHD panel is supposed to be used with fallback compatible: sdm845-xiaomi-beryllium-tianma.dtb: panel@0: compatible: ['tianma,fhd-video'] is too short Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326155753.92007-11-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts index 8e176111e599..e9427851ebaa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-tianma.dts @@ -10,6 +10,6 @@ }; &display_panel { - compatible = "tianma,fhd-video"; + compatible = "tianma,fhd-video", "novatek,nt36672a"; status = "okay"; }; From a3eebcb61ffb9a26ca77a00ce80050cff0f0ecf3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:46 +0000 Subject: [PATCH 0592/1040] dts: add riscv include prefix link The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical die as their R528/T113-s siblings with ARM Cortex-A7 cores. To allow sharing the basic SoC .dtsi files across those two architectures as well, introduce a symlink to the RISC-V DT directory. Signed-off-by: Andre Przywara Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20230320005249.13403-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- scripts/dtc/include-prefixes/riscv | 1 + 1 file changed, 1 insertion(+) create mode 120000 scripts/dtc/include-prefixes/riscv diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv new file mode 120000 index 000000000000..202509418938 --- /dev/null +++ b/scripts/dtc/include-prefixes/riscv @@ -0,0 +1 @@ +../../../arch/riscv/boot/dts \ No newline at end of file From 927e310e8e9d891b7621f77c369d234624d3a4fe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:47 +0000 Subject: [PATCH 0593/1040] ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi The Allwinner T113-s SoC is apparently using the same (or at least a very similar) die as the D1/D1s, but replaces the single RISC-V core with two Arm Cortex-A7 cores. Since the D1 core .dtsi already describes all common peripherals, we just need a DT describing the ARM specific peripherals: the CPU cores, the Generic Timer, the GIC and the PMU. We include the core .dtsi directly from the riscv DT directory. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230320005249.13403-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-t113s.dtsi | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-t113s.dtsi diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/sun8i-t113s.dtsi new file mode 100644 index 000000000000..804aa197a24f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-t113s.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; From c908060de362b2977db1b0ddba925353bc50aa29 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:48 +0000 Subject: [PATCH 0594/1040] dt-bindings: arm: sunxi: document MangoPi MQ-R board names The MangoPi MQ-R board is a small development board, using Allwinner SoCs with co-packaged DRAM. There are versions with a RISC-V core and ones with two Arm Cortex-A7 cores. Add the board/SoC compatible string pair to the list of known boards. Signed-off-by: Andre Przywara Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230320005249.13403-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ Documentation/devicetree/bindings/riscv/sunxi.yaml | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index cbdfc1c247a2..013821f4a7b8 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -856,6 +856,11 @@ properties: - const: wexler,tab7200 - const: allwinner,sun7i-a20 + - description: MangoPi MQ-R board + items: + - const: widora,mangopi-mq-r-t113 + - const: allwinner,sun8i-t113s + - description: WITS A31 Colombus Evaluation Board items: - const: wits,colombus diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documentation/devicetree/bindings/riscv/sunxi.yaml index 9edb5e5992b1..b36e313e13a6 100644 --- a/Documentation/devicetree/bindings/riscv/sunxi.yaml +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml @@ -64,6 +64,11 @@ properties: - const: widora,mangopi-mq-pro - const: allwinner,sun20i-d1 + - description: MangoPi MQ-R board + items: + - const: widora,mangopi-mq-r-f133 + - const: allwinner,sun20i-d1s + additionalProperties: true ... From 20c5db6c3d79d357c9d787edad3bbf03d98a08bf Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:49 +0000 Subject: [PATCH 0595/1040] ARM: dts: sunxi: add MangoPi MQ-R-T113 board The MangoPi MQ-R-T113 is a small SBC with the Allwinner T113-s3 SoC. The SoC features two Arm Cortex-A7 cores and 128 MB of co-packaged DDR3 DRAM. The board adds mostly connectors and the required regulators, plus a Realtek RTL8189FTV WiFi chip. Power comes in via a USB-C connector wired as a peripheral, and there is a second USB-C connector usable as a host port. Add a .dtsi file describing most of the board's peripherals, and include that from the actual board .dts file. This allows to re-use the .dtsi for the MQ-R-F113 RISC-V variant of that board. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230320005249.13403-5-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/Makefile | 1 + .../dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 +++++ .../boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 ++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts create mode 100644 arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a627d5593e51..3cc32722c394 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1397,6 +1397,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ sun8i-v3s-licheepi-zero.dtb \ diff --git a/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts new file mode 100644 index 000000000000..94e24b5926dd --- /dev/null +++ b/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#include + +/dts-v1/; + +#include "sun8i-t113s.dtsi" +#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" + +/ { + model = "MangoPi MQ-R-T113"; + compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; + + aliases { + ethernet0 = &rtl8189ftv; + }; +}; + +&cpu0 { + cpu-supply = <®_vcc_core>; +}; + +&cpu1 { + cpu-supply = <®_vcc_core>; +}; + +&mmc1 { + rtl8189ftv: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ + interrupt-names = "host-wake"; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi new file mode 100644 index 000000000000..e9bc749488bb --- /dev/null +++ b/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. +/* + * Common peripherals and configurations for MangoPi MQ-R boards. + */ + +#include +#include + +/ { + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ + }; + }; + + /* board wide 5V supply directly from the USB-C socket */ + reg_vcc5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vcc-core"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + vin-supply = <®_vcc5v>; + }; + + /* XC6206 LDO on the board */ + reg_avdd2v8: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "avdd2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_3v3>; + vcc-pd-supply = <®_3v3>; + vcc-pe-supply = <®_avdd2v8>; + vcc-pf-supply = <®_3v3>; + vcc-pg-supply = <®_3v3>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pb_pins>; + status = "okay"; +}; + +/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + status = "okay"; +}; From 6bd577c0a42b219b26ab84b145d10b663667ed00 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Mar 2023 16:07:21 +0800 Subject: [PATCH 0596/1040] arm64: dts: imx8mq: tqma8mq-mba8mx: drop disable-over-current disable-over-current is for chipidea IP, i.MX8MQ use dwc3, this property is not valid. Drop it. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index 344cfdaeb1d5..c5244b608524 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -169,8 +169,6 @@ hnp-disable; srp-disable; adp-disable; - /* OC not supported due to non matching active polarity */ - disable-over-current; dr_mode = "otg"; status = "okay"; }; From 45bd868b5b4bf45efb1ac2335fb2d9cdaab73497 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Mar 2023 16:07:22 +0800 Subject: [PATCH 0597/1040] arm64: dts: imx8mp: verdin-yavia: drop disable-over-current disable-over-current is for chipidea IP, i.MX8MQ use dwc3, this property is not valid. Drop it. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index de5489c2b3e8..db1722f0d80e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -183,7 +183,6 @@ }; &usb_dwc3_1 { - disable-over-current; status = "okay"; }; From c947af2cb2599e78dc839419ef7ef4f4adb42bdb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 23 Mar 2023 19:19:51 +0800 Subject: [PATCH 0598/1040] arm64: dts: imx8dxl: drop clocks from scu clock controller The clocks and clock-names are not documented and not used, drop them. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 97d7df0813a5..70fadd79851a 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -130,8 +130,6 @@ clk: clock-controller { compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; #clock-cells = <2>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; }; scu_gpio: gpio { From e341f338180c84cd98af3016cf5bcfde45a041fb Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Thu, 16 Feb 2023 09:33:38 -0600 Subject: [PATCH 0599/1040] ARM: dts: omap: Drop ti,omap36xx compatible This was not matched anywhere and provides no additional information. The driver code already checks also for "ti,omap3630" compatible. Signed-off-by: Andrew Davis Message-Id: <20230216153339.19987-2-afd@ti.com> [tony@atomide.com: updated comments for ti,omap3630 compatible] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-beagle-xm.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3730.dts | 2 +- arch/arm/boot/dts/omap3-igep0020-rev-f.dts | 2 +- arch/arm/boot/dts/omap3-igep0020.dts | 2 +- arch/arm/boot/dts/omap3-igep0030-rev-g.dts | 2 +- arch/arm/boot/dts/omap3-igep0030.dts | 2 +- arch/arm/boot/dts/omap3-lilly-dbb056.dts | 2 +- arch/arm/boot/dts/omap3-n9.dts | 2 +- arch/arm/boot/dts/omap3-n950.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-alto35.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-gallop43.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-palo35.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-palo43.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-summit.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-tobi.dts | 2 +- arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts | 2 +- arch/arm/boot/dts/omap3-pandora-1ghz.dts | 2 +- arch/arm/boot/dts/omap3-sbc-t3730.dts | 2 +- arch/arm/boot/dts/omap3-sniper.dts | 2 +- arch/arm/boot/dts/omap3-zoom3.dts | 2 +- 21 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 35eced6521ef..1a085bc01317 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -8,7 +8,7 @@ / { model = "TI OMAP3 BeagleBoard xM"; - compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "ti,omap3-beagle-xm", "ti,omap3630", "ti,omap3"; cpus { cpu@0 { diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index 48e48b0c8190..e1b1a047f77a 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -9,7 +9,7 @@ / { model = "CompuLab CM-T3730"; - compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3"; wl12xx_vmmc2: wl12xx_vmmc2 { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts index 9dca5bfc87ab..eadb5b857f48 100644 --- a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -10,7 +10,7 @@ / { model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0020-rev-f", "ti,omap3630", "ti,omap3"; /* Regulator to trigger the WL_EN signal of the Wifi module */ lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index c6f863bc03ad..3f0197ceae09 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -10,7 +10,7 @@ / { model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0020", "ti,omap3630", "ti,omap3"; vmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts index 8e9c12cf51a7..bc95a8df2e6a 100644 --- a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -10,7 +10,7 @@ / { model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0030-rev-g", "ti,omap3630", "ti,omap3"; /* Regulator to trigger the WL_EN signal of the Wifi module */ lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 5188f96f431e..d36ceecb7328 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -10,7 +10,7 @@ / { model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; - compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "isee,omap3-igep0030", "ti,omap3630", "ti,omap3"; vmmcsdio_fixed: fixedregulator-mmcsdio { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/omap3-lilly-dbb056.dts b/arch/arm/boot/dts/omap3-lilly-dbb056.dts index ecb4ef738e07..f6bbea2be54c 100644 --- a/arch/arm/boot/dts/omap3-lilly-dbb056.dts +++ b/arch/arm/boot/dts/omap3-lilly-dbb056.dts @@ -8,7 +8,7 @@ / { model = "INCOstartec LILLY-DBB056 (DM3730)"; - compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "incostartec,omap3-lilly-dbb056", "incostartec,omap3-lilly-a83x", "ti,omap3630", "ti,omap3"; }; &twl { diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index d211bcc31174..a3cf3f443785 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -12,7 +12,7 @@ / { model = "Nokia N9"; - compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "nokia,omap3-n9", "ti,omap3630", "ti,omap3"; }; &i2c2 { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index b2f480022ff6..cbaf79c4e842 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -12,7 +12,7 @@ / { model = "Nokia N950"; - compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "nokia,omap3-n950", "ti,omap3630", "ti,omap3"; keys { compatible = "gpio-keys"; diff --git a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts index 7f04dfad8203..3eb935df04dc 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-alto35.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-alto35.dts @@ -14,5 +14,5 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Alto35"; - compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-alto35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; diff --git a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts index bc5a04e03336..3af8d10d7224 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-chestnut43.dts @@ -14,7 +14,7 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Chestnut43"; - compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-chestnut43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts index 065c31cbf0e2..813e3c9fe3b6 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-gallop43.dts @@ -14,7 +14,7 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Gallop43"; - compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-gallop43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts index e38c1c51392c..8405bd9262de 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-palo35.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-palo35.dts @@ -14,7 +14,7 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo35"; - compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-palo35", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts index e6dc23159c4d..b9558d736e79 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-palo43.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-palo43.dts @@ -14,7 +14,7 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Palo43"; - compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-palo43", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-overo-storm-summit.dts b/arch/arm/boot/dts/omap3-overo-storm-summit.dts index 587c08ce282d..fcfc449f2abe 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-summit.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-summit.dts @@ -14,7 +14,7 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Summit"; - compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-summit", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts index f57de6010994..6d14466c180a 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-tobi.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-tobi.dts @@ -14,6 +14,6 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on Tobi"; - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; diff --git a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts index 281af6c113be..bcf20ff3f281 100644 --- a/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts +++ b/arch/arm/boot/dts/omap3-overo-storm-tobiduo.dts @@ -14,5 +14,5 @@ / { model = "OMAP36xx/AM37xx/DM37xx Gumstix Overo on TobiDuo"; - compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "gumstix,omap3-overo-tobiduo", "gumstix,omap3-overo", "ti,omap3630", "ti,omap3"; }; diff --git a/arch/arm/boot/dts/omap3-pandora-1ghz.dts b/arch/arm/boot/dts/omap3-pandora-1ghz.dts index ea509956d7ac..c0252f8a798a 100644 --- a/arch/arm/boot/dts/omap3-pandora-1ghz.dts +++ b/arch/arm/boot/dts/omap3-pandora-1ghz.dts @@ -16,7 +16,7 @@ / { model = "Pandora Handheld Console 1GHz"; - compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "openpandora,omap3-pandora-1ghz", "ti,omap3630", "ti,omap3"; }; &omap3_pmx_core2 { diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts index eb3893b9535e..4c36bde62491 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts @@ -8,7 +8,7 @@ / { model = "CompuLab SBC-T3730 with CM-T3730"; - compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap3630", "ti,omap3"; aliases { display0 = &dvi0; diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/omap3-sniper.dts index b6879cdc5c13..0591af494184 100644 --- a/arch/arm/boot/dts/omap3-sniper.dts +++ b/arch/arm/boot/dts/omap3-sniper.dts @@ -9,7 +9,7 @@ / { model = "LG Optimus Black"; - compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "lg,omap3-sniper", "ti,omap3630", "ti,omap3"; cpus { cpu@0 { diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index ce58b1f208e8..ab52e8d68f76 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -9,7 +9,7 @@ / { model = "TI Zoom3"; - compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap36xx", "ti,omap3"; + compatible = "ti,omap3-zoom3", "ti,omap3630", "ti,omap3"; cpus { cpu@0 { From 1b61fdfdd656b3940cff24c25c211777389174b0 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 27 Mar 2023 12:02:22 -0500 Subject: [PATCH 0600/1040] dt-bindings: soc: amlogic: Drop unneeded quotes Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230327170222.4107746-1-robh@kernel.org Signed-off-by: Neil Armstrong --- .../bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml | 4 ++-- .../bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml | 4 ++-- .../devicetree/bindings/soc/amlogic/amlogic,canvas.yaml | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml index 1748f1605cc7..7dff32f373cb 100644 --- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson Firmware registers Interface diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml index eee7cda9f91b..09b27e98d4c9 100644 --- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml index c3c599096353..cd06865e1f2a 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/amlogic/amlogic,canvas.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,canvas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Canvas Video Lookup Table From 0fbb60def782c40ac6338e4fed6898b690be50b0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 22:44:52 +0200 Subject: [PATCH 0601/1040] ARM: dts: stm32: drop invalid simple-panel compatible on stm32mp157c-lxa "simple-panel" compatible is not documented and nothing in Linux kernel binds to it. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index cb00ce7cec8b..407ed3952f75 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -73,7 +73,7 @@ }; panel: panel { - compatible = "edt,etm0700g0edh6", "simple-panel"; + compatible = "edt,etm0700g0edh6"; backlight = <&backlight>; enable-gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>; power-supply = <®_3v3>; From 1b9f0ec81af0012aae30aa3b4c711ad71d42e246 Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Mon, 20 Mar 2023 18:03:31 +0100 Subject: [PATCH 0602/1040] ARM: dts: stm32: fix spi1 pin assignment on stm32mp15 Bank A and B IOs can't be handled by the pin controller 'Z'. This patch assign spi1 pin definition to the correct controller. Fixes: 9ad65d245b7b ("ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group") Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 30 ++++++++++++------------ 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index a9d2bec99014..e15a3b2a9b39 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1880,6 +1880,21 @@ }; }; + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = , /* SPI2_SCK */ @@ -2448,19 +2463,4 @@ bias-disable; }; }; - - spi1_pins_b: spi1-1 { - pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - - pins2 { - pinmux = ; /* SPI1_MISO */ - bias-disable; - }; - }; }; From 4d93b3a974a828a5d330075358d55a6a3e2df2f2 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 7 Mar 2023 13:10:07 +0100 Subject: [PATCH 0603/1040] dt-bindings: power: apple,pmgr-pwrstate: Add t8112 compatible Add the apple,t8112-pmgr-pwrstate compatible for the Apple M2 SoC. This goes after t8103. The sort order logic here is having SoC numeric code families in release order, and SoCs within each family in release order: - t8xxx (Apple HxxP/G series, "phone"/"tablet" chips) - t8103 (Apple H13G/M1) - t8112 (Apple H14G/M2) - t6xxx (Apple HxxJ series, "desktop" chips) - t6000 (Apple H13J(S)/M1 Pro) - t6001 (Apple H13J(C)/M1 Max) - t6002 (Apple H13J(D)/M1 Ultra) Note that t600[0-2] share the t6000 compatible where the hardware is 100% compatible, which is usually the case in this highly related set of SoCs. Reviewed-by: Janne Grunau Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 94d369eb85de..59a6af735a21 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -32,6 +32,7 @@ properties: items: - enum: - apple,t8103-pmgr-pwrstate + - apple,t8112-pmgr-pwrstate - apple,t6000-pmgr-pwrstate - const: apple,pmgr-pwrstate From bbdd33769d319d1e7bb8fec09124a49b3573a2d3 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:08 +0100 Subject: [PATCH 0604/1040] dt-bindings: arm: apple: apple,pmgr: Add t8112-pmgr compatible The block on Apple M2 SoCs is compatible with the existing driver so just add its per-SoC compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index 0dc957a56d35..673277a7a224 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -23,6 +23,7 @@ properties: items: - enum: - apple,t8103-pmgr + - apple,t8112-pmgr - apple,t6000-pmgr - const: apple,pmgr - const: syscon From 1f21734b14b4cc93d82374108a549b42a7672c4c Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:09 +0100 Subject: [PATCH 0605/1040] dt-bindings: watchdog: apple,wdt: Add t8112-wdt compatible The block on the Apple M2 SoC is compatible with the existing driver so add its per-SoC compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/watchdog/apple,wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml index e58c56a6fdf6..3d7e2a2bf1f1 100644 --- a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -17,6 +17,7 @@ properties: items: - enum: - apple,t8103-wdt + - apple,t8112-wdt - apple,t6000-wdt - const: apple,wdt From 355d090ecbbc808bcfe21635f5ca7e25ba252846 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:10 +0100 Subject: [PATCH 0606/1040] dt-bindings: arm: cpus: Add apple,avalanche & blizzard compatibles These are the CPU cores in the Apple silicon M2 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/arm/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index c145f6a035ee..e287dcaec203 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -85,6 +85,8 @@ properties: compatible: enum: + - apple,avalanche + - apple,blizzard - apple,icestorm - apple,firestorm - arm,arm710t From 93b415b2e164348bf29fb89b77a3d9585bab76a5 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:11 +0100 Subject: [PATCH 0607/1040] dt-bindings: interrupt-controller: apple,aic2: Add apple,t8112-aic compatible The Apple M2 SoC uses AICv2 and is compatible with the existing driver. Add its per-SoC compatible. Since multi-die versions of the M2 are not expected decrease '#interrupt-cells' to 3 for apple,t8112-aic. This is seamlessly handled inside the driver. Acked-by: Marc Zyngier Signed-off-by: Janne Grunau Reviewed-by: Rob Herring Signed-off-by: Hector Martin --- .../interrupt-controller/apple,aic2.yaml | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml index 06948c0e36a5..2bde6cc6fe0a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -31,19 +31,22 @@ description: | properties: compatible: items: - - const: apple,t6000-aic + - enum: + - apple,t8112-aic + - apple,t6000-aic - const: apple,aic2 interrupt-controller: true '#interrupt-cells': - const: 4 + minimum: 3 + maximum: 4 description: | The 1st cell contains the interrupt type: - 0: Hardware IRQ - 1: FIQ - The 2nd cell contains the die ID. + The 2nd cell contains the die ID (only present on apple,t6000-aic). The next cell contains the interrupt number. - HW IRQs: interrupt number @@ -109,6 +112,19 @@ additionalProperties: false allOf: - $ref: /schemas/interrupt-controller.yaml# + - if: + properties: + compatible: + contains: + const: apple,t8112-aic + then: + properties: + '#interrupt-cells': + const: 3 + else: + properties: + '#interrupt-cells': + const: 4 examples: - | From 667b44ee3aaa10a5aaf9af3f0d1f51716e3132db Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:12 +0100 Subject: [PATCH 0608/1040] dt-bindings: iommu: apple,sart: Add apple,t8112-sart compatible string "apple,t8112-sart" as found on the Apple M2 SoC appears to be SART3 as well. To allow for later discovered incompatibilities use '"apple,t8112-sart", "apple,t6000-sart"' as compatible string. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- .../devicetree/bindings/iommu/apple,sart.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Documentation/devicetree/bindings/iommu/apple,sart.yaml index 1524fa3094ef..e87c1520fea6 100644 --- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml @@ -28,9 +28,13 @@ description: properties: compatible: - enum: - - apple,t6000-sart - - apple,t8103-sart + oneOf: + - items: + - const: apple,t8112-sart + - const: apple,t6000-sart + - enum: + - apple,t6000-sart + - apple,t8103-sart reg: maxItems: 1 From 695ea8cc5eb51b8baece7be07480a13a91bfdf48 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:13 +0100 Subject: [PATCH 0609/1040] dt-bindings: mailbox: apple,mailbox: Add t8112 compatibles The mailbox hardware remains unchanged on M2 SoCs so just add its per-SoC compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 5c5c328b3134..4c0668e5f0bd 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -29,6 +29,7 @@ properties: items: - enum: - apple,t8103-asc-mailbox + - apple,t8112-asc-mailbox - apple,t6000-asc-mailbox - const: apple,asc-mailbox-v4 @@ -39,6 +40,7 @@ properties: items: - enum: - apple,t8103-m3-mailbox + - apple,t8112-m3-mailbox - apple,t6000-m3-mailbox - const: apple,m3-mailbox-v2 From 20fa978cd98c6a44c206bfd7bcb16afa4d4e8a29 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:14 +0100 Subject: [PATCH 0610/1040] dt-bindings: nvme: apple: Add apple,t8112-nvme-ans2 compatible string "apple,t8112-nvme-ans2" as found on Apple M2 SoCs is compatible with the existing driver. Add its SoC specific compatible string to allow special handling if it'll be necessary. t8112 uses only 2 power-domains as no 4 and 8 TB configurations are offered. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml index 34dd1cc67124..fc6555724e18 100644 --- a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml +++ b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - apple,t8103-nvme-ans2 + - apple,t8112-nvme-ans2 - apple,t6000-nvme-ans2 - const: apple,nvme-ans2 @@ -65,7 +66,9 @@ if: properties: compatible: contains: - const: apple,t8103-nvme-ans2 + enum: + - apple,t8103-nvme-ans2 + - apple,t8112-nvme-ans2 then: properties: power-domains: From 869c942fb567c9b1dcc25487200fdcf474157029 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:15 +0100 Subject: [PATCH 0611/1040] dt-bindings: pci: apple,pcie: Add t8112 support The block found in the Apple M2 SoC is compatible with the existing driver, and supports 4 downstream ports like the t6000 one. Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pci/apple,pcie.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index aa38680aaaca..215ff9a9c835 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -33,6 +33,7 @@ properties: items: - enum: - apple,t8103-pcie + - apple,t8112-pcie - apple,t6000-pcie - const: apple,pcie From 43145cfe308214addb3f4ecaa48fd2c415a2938f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:16 +0100 Subject: [PATCH 0612/1040] dt-bindings: pinctrl: apple,pinctrl: Add apple,t8112-pinctrl compatible This new SoC uses the same pinctrl hardware, so just add a new per-SoC compatible. Reviewed-by: Linus Walleij Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index d3b11351ca45..684c03a6bd40 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -19,6 +19,7 @@ properties: items: - enum: - apple,t8103-pinctrl + - apple,t8112-pinctrl - apple,t6000-pinctrl - const: apple,pinctrl From 1e8edd6a6d5f5a604a7f71b90f5dca831c5d3490 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:17 +0100 Subject: [PATCH 0613/1040] dt-bindings: i2c: apple,i2c: Add apple,t8112-i2c compatible This block on the Apple M2 is compatible with the existing driver so just add the per-SoC compatible. Acked-by: Wolfram Sang # for I2C Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/i2c/apple,i2c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 4ac61fec90e2..3f0e94189f2d 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -23,6 +23,7 @@ properties: items: - enum: - apple,t8103-i2c + - apple,t8112-i2c - apple,t6000-i2c - const: apple,i2c From b058e9d8ceb0992dbb7c3f195248442f7f9cca93 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:18 +0100 Subject: [PATCH 0614/1040] dt-bindings: clock: apple,nco: Add t8112-nco compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The block found on Apple's M2 SoC is compatible with the existing driver so add its per-SoC compatible. Acked-by: Martin Povišer Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/clock/apple,nco.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/apple,nco.yaml b/Documentation/devicetree/bindings/clock/apple,nco.yaml index 74eab5c0d24a..8b8411dc42f6 100644 --- a/Documentation/devicetree/bindings/clock/apple,nco.yaml +++ b/Documentation/devicetree/bindings/clock/apple,nco.yaml @@ -23,6 +23,7 @@ properties: - enum: - apple,t6000-nco - apple,t8103-nco + - apple,t8112-nco - const: apple,nco clocks: From 828fe6b6245bd9b20dbf3e0dd54c79b17be758e7 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 7 Mar 2023 13:10:20 +0100 Subject: [PATCH 0615/1040] dt-bindings: arm: apple: Add t8112 j413/j473/j493 compatibles This adds the following apple,t8112 platforms: - apple,j413 - MacBook Air (M2, 2022) - apple,j473 - Mac mini (M2, 2023) - apple,j493 - MacBook Pro (13-inch, M2, 2022) The sort order logic here is having SoC numeric code families in release order, and SoCs within each family in release order: - t8xxx (Apple HxxP/G series, "phone"/"tablet" chips) - t8103 (Apple H13G/M1) - t8112 (Apple H14G/M2) - t6xxx (Apple HxxJ series, "desktop" chips) - t6000 (Apple H13J(S)/M1 Pro) - t6001 (Apple H13J(C)/M1 Max) - t6002 (Apple H13J(D)/M1 Ultra) Acked-by: Krzysztof Kozlowski Signed-off-by: Janne Grunau Signed-off-by: Hector Martin --- Documentation/devicetree/bindings/arm/apple.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index da78c69774f2..883fd67e3752 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -19,6 +19,12 @@ description: | - MacBook Air (M1, 2020) - iMac (24-inch, M1, 2021) + Devices based on the "M2" SoC: + + - MacBook Air (M2, 2022) + - MacBook Pro (13-inch, M2, 2022) + - Mac mini (M2, 2023) + And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: - MacBook Pro (14-inch, M1 Pro, 2021) @@ -70,6 +76,15 @@ properties: - const: apple,t8103 - const: apple,arm-platform + - description: Apple M2 SoC based platforms + items: + - enum: + - apple,j413 # MacBook Air (M2, 2022) + - apple,j473 # Mac mini (M2, 2023) + - apple,j493 # MacBook Pro (13-inch, M2, 2022) + - const: apple,t8112 + - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms items: - enum: From 2d5ce3fbef324295f7c210f29d724b44b5642cb2 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 7 Mar 2023 13:10:21 +0100 Subject: [PATCH 0616/1040] arm64: dts: apple: t8112: Initial t8112 (M2) device trees This adds device trees for the following devices: - Macbook Air (M2, 2022) - Macbook Pro 13" (M2, 2022) - Mac mini (M2, 2023) This brings the hardware support of the machines to the same level as M1 and M1 Pro / Max / Ultra. Supported hardware include NVMe, PCIe, serial, pinctrl/gpio, I2C, iommu, watchdog, admac, nco, cpufreq, boot framebuffer for laptop panels and the interrupt controller. The ethernet LAN device on the M2 Mac mini is the only working PCIe device. The Wlan/BT devices are powered off and controlled by the not yet supported SMC. The ASMedia xHCI on the M2 Mac mini requires firmware to be loaded at startup. The main missing hardware support to make these devices useful are the integrated USB 2/3/4 controller, keyboard and trackpad on the laptops and SMC to power the PCIe Wlan/BT device on. The M2 Mac mini has currently no working display output. Due to changes in the display pipeline it is currently not possible to initialize the HDMI output in the bootloader. Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/Makefile | 3 + arch/arm64/boot/dts/apple/t8112-j413.dts | 63 ++ arch/arm64/boot/dts/apple/t8112-j473.dts | 54 + arch/arm64/boot/dts/apple/t8112-j493.dts | 52 + arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 81 ++ arch/arm64/boot/dts/apple/t8112-pmgr.dtsi | 1140 +++++++++++++++++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 912 +++++++++++++++++ 7 files changed, 2305 insertions(+) create mode 100644 arch/arm64/boot/dts/apple/t8112-j413.dts create mode 100644 arch/arm64/boot/dts/apple/t8112-j473.dts create mode 100644 arch/arm64/boot/dts/apple/t8112-j493.dts create mode 100644 arch/arm64/boot/dts/apple/t8112-jxxx.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8112-pmgr.dtsi create mode 100644 arch/arm64/boot/dts/apple/t8112.dtsi diff --git a/arch/arm64/boot/dts/apple/Makefile b/arch/arm64/boot/dts/apple/Makefile index 5a7506ff5ea3..aec5e29cdfb7 100644 --- a/arch/arm64/boot/dts/apple/Makefile +++ b/arch/arm64/boot/dts/apple/Makefile @@ -10,3 +10,6 @@ dtb-$(CONFIG_ARCH_APPLE) += t6000-j316s.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j316c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6001-j375c.dtb dtb-$(CONFIG_ARCH_APPLE) += t6002-j375d.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8112-j413.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8112-j473.dtb +dtb-$(CONFIG_ARCH_APPLE) += t8112-j493.dtb diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts new file mode 100644 index 000000000000..9e758edeaa82 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Air (M2, 2022) + * + * target-type: J413 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" + +/ { + compatible = "apple,j413", "apple,t8112", "apple,arm-platform"; + model = "Apple MacBook Air (13-inch, M2, 2022)"; + + aliases { + bluetooth0 = &bluetooth0; + wifi0 = &wifi0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range = <1 1>; + wifi0: wifi@0,0 { + compatible = "pci14e4,4433"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 10]; + apple,antenna-sku = "XX"; + brcm,board-type = "apple,hokkaido"; + }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f71"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; + brcm,board-type = "apple,hokkaido"; + }; +}; + +&i2c0 { + /* MagSafe port */ + hpm5: usb-pd@3a { + compatible = "apple,cd321x"; + reg = <0x3a>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts new file mode 100644 index 000000000000..06fe257f08be --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple Mac mini (M2, 2023) + * + * target-type: J473 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" + +/ { + compatible = "apple,j473", "apple,t8112", "apple,arm-platform"; + model = "Apple Mac mini (M2, 2023)"; + + aliases { + ethernet0 = ðernet0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range = <1 1>; +}; + +&port01 { + bus-range = <2 2>; + status = "okay"; +}; + +&port02 { + bus-range = <3 3>; + status = "okay"; + ethernet0: ethernet@0,0 { + reg = <0x30000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 10 18 00 00 00]; + }; +}; + +&pcie1_dart { + status = "okay"; +}; + +&pcie2_dart { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts new file mode 100644 index 000000000000..8552c15be265 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple MacBook Pro (13-inch, M1, 2022) + * + * target-type: J493 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8112.dtsi" +#include "t8112-jxxx.dtsi" + +/ { + compatible = "apple,j493", "apple,t8112", "apple,arm-platform"; + model = "Apple MacBook Pro (13-inch, M2, 2022)"; + + aliases { + bluetooth0 = &bluetooth0; + wifi0 = &wifi0; + }; +}; + +/* + * Force the bus number assignments so that we can declare some of the + * on-board devices and properties that are populated by the bootloader + * (such as MAC addresses). + */ +&port00 { + bus-range = <1 1>; + wifi0: wifi@0,0 { + compatible = "pci14e4,4425"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-mac-address = [00 00 00 00 00 00]; + apple,antenna-sku = "XX"; + brcm,board-type = "apple,kyushu"; + }; + + bluetooth0: bluetooth@0,1 { + compatible = "pci14e4,5f69"; + reg = <0x10100 0x0 0x0 0x0 0x0>; + /* To be filled by the loader */ + local-bd-address = [00 00 00 00 00 00]; + brcm,board-type = "apple,kyushu"; + }; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi new file mode 100644 index 000000000000..f5edf61113e7 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple M2 MacBook Air/Pro (M2, 2022) + * + * This file contains parts common to all Apple M2 devices using the t8112. + * + * target-type: J493, J413 + * + * Copyright The Asahi Linux Contributors + */ + +/ { + aliases { + serial0 = &serial0; + serial2 = &serial2; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + hpm0: usb-pd@38 { + compatible = "apple,cd321x"; + reg = <0x38>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; + + hpm1: usb-pd@3f { + compatible = "apple,cd321x"; + reg = <0x3f>; + interrupt-parent = <&pinctrl_ap>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "irq"; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&nco_clkref { + clock-frequency = <900000000>; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi new file mode 100644 index 000000000000..7c050c6f2707 --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112-pmgr.dtsi @@ -0,0 +1,1140 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8112 "M2" SoC + * + * Copyright The Asahi Linux Contributors + */ + + +&pmgr { + ps_sbr: power-controller@100 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@108 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@110 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + apple,always-on; /* Core device */ + }; + + ps_soc_spmi0: power-controller@118 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_spmi0"; + }; + + ps_gpio: power-controller@120 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms_busif: power-controller@128 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_busif"; + apple,always-on; /* Core device */ + }; + + ps_pms: power-controller@130 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pms_c1ppt: power-controller@160 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_c1ppt"; + power-domains = <&ps_pms>; + }; + + ps_soc_dpe: power-controller@168 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "soc_dpe"; + apple,always-on; /* Core device */ + }; + + ps_pmgr_soc_ocla: power-controller@170 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmgr_soc_ocla"; + power-domains = <&ps_pms>; + }; + + ps_ispsens0: power-controller@178 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@180 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_ispsens2: power-controller@188 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens2"; + }; + + ps_ispsens3: power-controller@190 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens3"; + }; + + ps_pcie_ref: power-controller@198 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_aft0: power-controller@1a0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aft0"; + }; + + ps_imx: power-controller@1a8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "imx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sio_busif: power-controller@1b0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio: power-controller@1b8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + apple,always-on; + power-domains = <&ps_sio_busif>; + }; + + ps_sio_cpu: power-controller@1c0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_cpu"; + power-domains = <&ps_sio>; + }; + + ps_fpwm0: power-controller@1c8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm0"; + power-domains = <&ps_sio>; + }; + + ps_fpwm1: power-controller@1d0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm1"; + power-domains = <&ps_sio>; + }; + + ps_fpwm2: power-controller@1d8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "fpwm2"; + power-domains = <&ps_sio>; + }; + + ps_i2c0: power-controller@1e0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio>; + }; + + ps_i2c1: power-controller@1e8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio>; + }; + + ps_i2c2: power-controller@1f0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio>; + }; + + ps_i2c3: power-controller@1f8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio>; + }; + + ps_i2c4: power-controller@200 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c4"; + power-domains = <&ps_sio>; + }; + + ps_spi_p: power-controller@208 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi_p"; + power-domains = <&ps_sio>; + }; + + ps_uart_p: power-controller@210 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_p"; + power-domains = <&ps_sio>; + }; + + ps_audio_p: power-controller@218 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "audio_p"; + power-domains = <&ps_sio>; + }; + + ps_aes: power-controller@220 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes"; + power-domains = <&ps_sio>; + }; + + ps_spi0: power-controller@228 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_spi_p>; + }; + + ps_spi1: power-controller@230 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_spi_p>; + }; + + ps_spi2: power-controller@238 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_spi_p>; + }; + + ps_spi3: power-controller@240 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_spi_p>; + }; + + ps_spi4: power-controller@248 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi4"; + power-domains = <&ps_spi_p>; + }; + + ps_spi5: power-controller@250 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi5"; + power-domains = <&ps_spi_p>; + }; + + ps_uart_n: power-controller@258 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart_n"; + power-domains = <&ps_uart_p>; + }; + + ps_uart0: power-controller@260 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_uart_p>; + }; + + ps_uart1: power-controller@268 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_uart_p>; + }; + + ps_uart2: power-controller@270 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_uart_p>; + }; + + ps_uart3: power-controller@278 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_uart_p>; + }; + + ps_uart4: power-controller@280 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_uart_p>; + }; + + ps_uart5: power-controller@288 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_uart_p>; + }; + + ps_uart6: power-controller@290 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_uart_p>; + }; + + ps_uart7: power-controller@298 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_uart_p>; + }; + + ps_uart8: power-controller@2a0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_uart_p>; + }; + + ps_sio_adma: power-controller@2a8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_adma"; + power-domains = <&ps_spi_p>, <&ps_audio_p>; + }; + + ps_dpa0: power-controller@2b0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa0"; + power-domains = <&ps_audio_p>; + }; + + ps_dpa1: power-controller@2b8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa1"; + power-domains = <&ps_audio_p>; + }; + + ps_mca0: power-controller@2c0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca1: power-controller@2c8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca2: power-controller@2d0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca3: power-controller@2d8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca4: power-controller@2e0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mca5: power-controller@2e8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca5"; + power-domains = <&ps_sio_adma>, <&ps_audio_p>; + }; + + ps_mcc: power-controller@2f0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory controller */ + }; + + ps_dcs0: power-controller@2f8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x2f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@300 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@308 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@310 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@318 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs5: power-controller@320 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs6: power-controller@328 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs7: power-controller@330 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_smx0: power-controller@338 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx0"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_smx1: power-controller@340 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx1"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_apcie: power-controller@348 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie"; + power-domains = <&ps_imx>, <&ps_pcie_ref>; + }; + + ps_rmx0: power-controller@350 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rmx0"; + /* Apple Fabric, display/image stuff: this can power down */ + }; + + ps_rmx1: power-controller@358 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rmx1"; + /* Apple Fabric, display/image stuff: this can power down */ + }; + + ps_cmx: power-controller@360 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cmx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mmx: power-controller@368 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mmx"; + /* Apple Fabric, media stuff: this can power down */ + }; + + ps_disp0_sys: power-controller@370 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_sys"; + power-domains = <&ps_rmx1>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_disp0_fe: power-controller@378 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_disp0_sys>; + apple,always-on; /* TODO: figure out if we can enable PM here */ + }; + + ps_dispext_sys: power-controller@380 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_sys"; + power-domains = <&ps_rmx0>; + }; + + ps_dispext_fe: power-controller@388 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_fe"; + power-domains = <&ps_dispext_sys>; + }; + + ps_dispext_cpu0: power-controller@3c8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispext_cpu0"; + power-domains = <&ps_dispext_fe>; + apple,min-state = <4>; + }; + + ps_dptx_ext_phy: power-controller@3d8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dptx_ext_phy"; + }; + + ps_dispdfr_fe: power-controller@3e0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispdfr_fe"; + power-domains = <&ps_rmx0>; + }; + + ps_dispdfr_be: power-controller@3e8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dispdfr_be"; + power-domains = <&ps_dispdfr_fe>; + }; + + ps_mipi_dsi: power-controller@3f0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_dispdfr_be>; + }; + + ps_jpg: power-controller@3f8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_cmx>; + }; + + ps_apcie_gp: power-controller@400 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_gp"; + power-domains = <&ps_apcie>; + apple,always-on; /* Breaks things if shut down */ + }; + + ps_msr: power-controller@408 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x408 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_imx>; + }; + + ps_pmp: power-controller@410 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x410 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + apple,always-on; + }; + + ps_pms_sram: power-controller@418 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x418 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + apple,always-on; + }; + + ps_msr_ase_core: power-controller@420 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x420 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr_ase_core"; + power-domains = <&ps_msr>; + }; + + ps_ans: power-controller@428 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x428 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + power-domains = <&ps_imx>; + }; + + ps_gfx: power-controller@430 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x430 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_isp_sys: power-controller@438 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x438 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rmx1>; + }; + + ps_venc_sys: power-controller@440 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x440 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_rmx1>; + }; + + ps_avd_sys: power-controller@448 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x448 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "avd_sys"; + power-domains = <&ps_mmx>; + }; + + ps_apcie_st: power-controller@450 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x450 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "apcie_st"; + power-domains = <&ps_apcie>, <&ps_ans>; + }; + + ps_atc0_common: power-controller@458 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x458 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_common"; + power-domains = <&ps_imx>; + }; + + ps_atc0_pcie: power-controller@460 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x460 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_pcie"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio: power-controller@468 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x468 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio"; + power-domains = <&ps_atc0_common>; + }; + + ps_atc0_cio_pcie: power-controller@470 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x470 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_pcie"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc0_cio_usb: power-controller@478 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x478 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_cio_usb"; + power-domains = <&ps_atc0_cio>; + }; + + ps_atc1_common: power-controller@480 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x480 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_common"; + power-domains = <&ps_rmx0>; + }; + + ps_atc1_pcie: power-controller@488 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x488 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_pcie"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio: power-controller@490 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x490 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio"; + power-domains = <&ps_atc1_common>; + }; + + ps_atc1_cio_pcie: power-controller@498 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x498 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_pcie"; + power-domains = <&ps_atc1_cio>; + }; + + ps_atc1_cio_usb: power-controller@4a0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_cio_usb"; + power-domains = <&ps_atc1_cio>; + }; + + ps_ane_sys: power-controller@4a8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ane_sys"; + power-domains = <&ps_mmx>; + }; + + ps_scodec: power-controller@4b0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x4b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "scodec"; + power-domains = <&ps_rmx0>; + }; + + ps_sep: power-controller@c00 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xc00 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; + }; + + ps_venc_dma: power-controller@8000 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_dma"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe4: power-controller@8008 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_pipe5: power-controller@8010 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_dma>; + }; + + ps_venc_me0: power-controller@8018 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc_pipe5>, <&ps_venc_pipe4>; + }; + + ps_venc_me1: power-controller@8020 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x8020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc_pipe5>, <&ps_venc_pipe4>; + }; + + ps_disp0_cpu0: power-controller@10000 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x10000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_cpu0"; + power-domains = <&ps_disp0_fe>; + apple,min-state = <4>; + }; +}; + +&pmgr_mini { + + ps_debug_gated: power-controller@58 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x58 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_gated"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_spmi0: power-controller@60 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x60 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi0"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_spmi1: power-controller@68 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x68 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_spmi1"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_aon: power-controller@70 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x70 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_msg: power-controller@78 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x78 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msg"; + }; + + ps_nub_gpio: power-controller@80 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_gpio"; + apple,always-on; + }; + + ps_atc0_usb_aon: power-controller@88 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + ps_atc1_usb_aon: power-controller@90 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x90 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ + }; + + ps_atc0_usb: power-controller@98 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x98 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc0_usb"; + power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>; + }; + + ps_atc1_usb: power-controller@a0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "atc1_usb"; + power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>; + }; + + ps_nub_fabric: power-controller@a8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xa8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_sram: power-controller@b0 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_sram"; + apple,always-on; /* Core AON device */ + }; + + ps_debug_switch: power-controller@b8 { + compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0xb8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug_switch"; + apple,always-on; /* Core AON device */ + }; +}; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi new file mode 100644 index 000000000000..698a436e7dac --- /dev/null +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8112 "M2" SoC + * + * Other names: H14G + * + * Copyright The Asahi Linux Contributors + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "apple,t8112", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_e0>; + }; + core1 { + cpu = <&cpu_e1>; + }; + core2 { + cpu = <&cpu_e2>; + }; + core3 { + cpu = <&cpu_e3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_p0>; + }; + core1 { + cpu = <&cpu_p1>; + }; + core2 { + cpu = <&cpu_p2>; + }; + core3 { + cpu = <&cpu_p3>; + }; + }; + }; + + cpu_e0: cpu@0 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e1: cpu@1 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e2: cpu@2 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_e3: cpu@3 { + compatible = "apple,blizzard"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&ecluster_opp>; + capacity-dmips-mhz = <756>; + performance-domains = <&cpufreq_e>; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x20000>; + d-cache-size = <0x10000>; + }; + + cpu_p0: cpu@10100 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p1: cpu@10101 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p2: cpu@10102 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + cpu_p3: cpu@10103 { + compatible = "apple,avalanche"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&pcluster_opp>; + capacity-dmips-mhz = <1024>; + performance-domains = <&cpufreq_p>; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x30000>; + d-cache-size = <0x20000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x400000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x1000000>; + }; + }; + + ecluster_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <1>; + clock-latency-ns = <7500>; + }; + opp02 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <2>; + clock-latency-ns = <20000>; + }; + opp03 { + opp-hz = /bits/ 64 <1284000000>; + opp-level = <3>; + clock-latency-ns = <22000>; + }; + opp04 { + opp-hz = /bits/ 64 <1752000000>; + opp-level = <4>; + clock-latency-ns = <30000>; + }; + opp05 { + opp-hz = /bits/ 64 <2004000000>; + opp-level = <5>; + clock-latency-ns = <35000>; + }; + opp06 { + opp-hz = /bits/ 64 <2256000000>; + opp-level = <6>; + clock-latency-ns = <39000>; + }; + opp07 { + opp-hz = /bits/ 64 <2424000000>; + opp-level = <7>; + clock-latency-ns = <53000>; + }; + }; + + pcluster_opp: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp01 { + opp-hz = /bits/ 64 <660000000>; + opp-level = <1>; + clock-latency-ns = <9000>; + }; + opp02 { + opp-hz = /bits/ 64 <924000000>; + opp-level = <2>; + clock-latency-ns = <19000>; + }; + opp03 { + opp-hz = /bits/ 64 <1188000000>; + opp-level = <3>; + clock-latency-ns = <22000>; + }; + opp04 { + opp-hz = /bits/ 64 <1452000000>; + opp-level = <4>; + clock-latency-ns = <24000>; + }; + opp05 { + opp-hz = /bits/ 64 <1704000000>; + opp-level = <5>; + clock-latency-ns = <26000>; + }; + opp06 { + opp-hz = /bits/ 64 <1968000000>; + opp-level = <6>; + clock-latency-ns = <28000>; + }; + opp07 { + opp-hz = /bits/ 64 <2208000000>; + opp-level = <7>; + clock-latency-ns = <30000>; + }; + opp08 { + opp-hz = /bits/ 64 <2400000000>; + opp-level = <8>; + clock-latency-ns = <33000>; + }; + opp09 { + opp-hz = /bits/ 64 <2568000000>; + opp-level = <9>; + clock-latency-ns = <34000>; + }; + opp10 { + opp-hz = /bits/ 64 <2724000000>; + opp-level = <10>; + clock-latency-ns = <36000>; + }; + opp11 { + opp-hz = /bits/ 64 <2868000000>; + opp-level = <11>; + clock-latency-ns = <41000>; + }; + opp12 { + opp-hz = /bits/ 64 <2988000000>; + opp-level = <12>; + clock-latency-ns = <42000>; + }; + opp13 { + opp-hz = /bits/ 64 <3096000000>; + opp-level = <13>; + clock-latency-ns = <44000>; + }; + opp14 { + opp-hz = /bits/ 64 <3204000000>; + opp-level = <14>; + clock-latency-ns = <46000>; + }; + /* Not available until CPU deep sleep is implemented */ +#if 0 + opp15 { + opp-hz = /bits/ 64 <3324000000>; + opp-level = <15>; + clock-latency-ns = <62000>; + turbo-mode; + }; + opp16 { + opp-hz = /bits/ 64 <3408000000>; + opp-level = <16>; + clock-latency-ns = <62000>; + turbo-mode; + }; + opp17 { + opp-hz = /bits/ 64 <3504000000>; + opp-level = <17>; + clock-latency-ns = <62000>; + turbo-mode; + }; +#endif + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; + interrupts = , + , + , + ; + }; + + pmu-e { + compatible = "apple,blizzard-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pmu-p { + compatible = "apple,avalanche-pmu"; + interrupt-parent = <&aic>; + interrupts = ; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + /* + * This is a fabulated representation of the input clock + * to NCO since we don't know the true clock tree. + */ + nco_clkref: clock-ref-nco { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "nco_ref"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + nonposted-mmio; + + cpufreq_e: cpufreq@210e20000 { + compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x10e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + cpufreq_p: cpufreq@211e20000 { + compatible = "apple,t8112-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x11e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + sio_dart: iommu@235004000 { + compatible = "apple,t8110-dart"; + reg = <0x2 0x35004000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_sio_cpu>; + }; + + i2c0: i2c@235010000 { + compatible = "apple,t8112-i2c", "apple,i2c"; + reg = <0x2 0x35010000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c0>; + status = "disabled"; + }; + + i2c1: i2c@235014000 { + compatible = "apple,t8112-i2c", "apple,i2c"; + reg = <0x2 0x35014000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c1>; + status = "disabled"; + }; + + i2c2: i2c@235018000 { + compatible = "apple,t8112-i2c", "apple,i2c"; + reg = <0x2 0x35018000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c2>; + status = "disabled"; + }; + + i2c3: i2c@23501c000 { + compatible = "apple,t8112-i2c", "apple,i2c"; + reg = <0x2 0x3501c000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c3>; + status = "disabled"; + }; + + i2c4: i2c@235020000 { + compatible = "apple,t8112-i2c", "apple,i2c"; + reg = <0x2 0x35020000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + power-domains = <&ps_i2c4>; + status = "disabled"; + }; + + serial0: serial@235200000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x35200000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* + * TODO: figure out the clocking properly, there may + * be a third selectable clock. + */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + serial2: serial@235208000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x35208000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart2>; + status = "disabled"; + }; + + admac: dma-controller@238200000 { + compatible = "apple,t8112-admac", "apple,admac"; + reg = <0x2 0x38200000 0x0 0x34000>; + dma-channels = <24>; + interrupts-extended = <0>, + <&aic AIC_IRQ 760 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>; + #dma-cells = <1>; + iommus = <&sio_dart 2>; + power-domains = <&ps_sio_adma>; + resets = <&ps_audio_p>; + }; + + mca: i2s@238400000 { + compatible = "apple,t8112-mca", "apple,mca"; + reg = <0x2 0x38400000 0x0 0x18000>, + <0x2 0x38300000 0x0 0x30000>; + + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + ; + + resets = <&ps_audio_p>; + clocks = <&nco 0>, <&nco 1>, <&nco 2>, + <&nco 3>, <&nco 4>, <&nco 4>; + power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, + <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>; + dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, + <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, + <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, + <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>, + <&admac 16>, <&admac 17>, <&admac 18>, <&admac 19>, + <&admac 20>, <&admac 21>, <&admac 22>, <&admac 23>; + dma-names = "tx0a", "rx0a", "tx0b", "rx0b", + "tx1a", "rx1a", "tx1b", "rx1b", + "tx2a", "rx2a", "tx2b", "rx2b", + "tx3a", "rx3a", "tx3b", "rx3b", + "tx4a", "rx4a", "tx4b", "rx4b", + "tx5a", "rx5a", "tx5b", "rx5b"; + + #sound-dai-cells = <1>; + }; + + nco: clock-controller@23b044000 { + compatible = "apple,t8112-nco", "apple,nco"; + reg = <0x2 0x3b044000 0x0 0x14000>; + clocks = <&nco_clkref>; + #clock-cells = <1>; + }; + + aic: interrupt-controller@23b0c0000 { + compatible = "apple,t8112-aic", "apple,aic2"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2 0x3b0c0000 0x0 0x8000>, + <0x2 0x3b0c8000 0x0 0x4>; + reg-names = "core", "event"; + power-domains = <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index = ; + cpus = <&cpu_p0 &cpu_p1 &cpu_p2 &cpu_p3>; + }; + }; + }; + + pmgr: power-management@23b700000 { + compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3b700000 0 0x14000>; + /* child nodes are added in t8103-pmgr.dtsi */ + }; + + pinctrl_ap: pinctrl@23c100000 { + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3c100000 0x0 0x100000>; + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 213>; + apple,npins = <213>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + i2c0_pins: i2c0-pins { + pinmux = , + ; + }; + + i2c1_pins: i2c1-pins { + pinmux = , + ; + }; + + i2c2_pins: i2c2-pins { + pinmux = , + ; + }; + + i2c3_pins: i2c3-pins { + pinmux = , + ; + }; + + i2c4_pins: i2c4-pins { + pinmux = , + ; + }; + + spi3_pins: spi3-pins { + pinmux = , + , + , + ; + }; + + pcie_pins: pcie-pins { + pinmux = , + , + ; + // TODO: 1 more CLKREQs + }; + }; + + pinctrl_nub: pinctrl@23d1f0000 { + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3d1f0000 0x0 0x4000>; + power-domains = <&ps_nub_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_nub 0 0 24>; + apple,npins = <24>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pmgr_mini: power-management@23d280000 { + compatible = "apple,t8112-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2 0x3d280000 0 0x4000>; + /* child nodes are added in t8103-pmgr.dtsi */ + }; + + wdt: watchdog@23d2b0000 { + compatible = "apple,t8112-wdt", "apple,wdt"; + reg = <0x2 0x3d2b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pinctrl_smc: pinctrl@23e820000 { + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3e820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 18>; + apple,npins = <18>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@24a820000 { + compatible = "apple,t8112-pinctrl", "apple,pinctrl"; + reg = <0x2 0x4a820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 54>; + apple,npins = <54>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + ans_mbox: mbox@277408000 { + compatible = "apple,t8112-asc-mailbox", "apple,asc-mailbox-v4"; + reg = <0x2 0x77408000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + interrupt-names = "send-empty", "send-not-empty", + "recv-empty", "recv-not-empty"; + #mbox-cells = <0>; + power-domains = <&ps_ans>; + }; + + sart: sart@27bc50000 { + compatible = "apple,t8112-sart", "apple,t6000-sart"; + reg = <0x2 0x7bc50000 0x0 0x10000>; + power-domains = <&ps_ans>; + }; + + nvme@27bcc0000 { + compatible = "apple,t8112-nvme-ans2", "apple,nvme-ans2"; + reg = <0x2 0x7bcc0000 0x0 0x40000>, + <0x2 0x77400000 0x0 0x4000>; + reg-names = "nvme", "ans"; + interrupt-parent = <&aic>; + interrupts = ; + mboxes = <&ans_mbox>; + apple,sart = <&sart>; + power-domains = <&ps_ans>, <&ps_apcie_st>; + power-domain-names = "ans", "apcie0"; + resets = <&ps_ans>; + }; + + pcie0_dart: iommu@681008000 { + compatible = "apple,t8110-dart"; + reg = <0x6 0x81008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp>; + }; + + pcie1_dart: iommu@682008000 { + compatible = "apple,t8110-dart"; + reg = <0x6 0x82008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp>; + status = "disabled"; + }; + + pcie2_dart: iommu@683008000 { + compatible = "apple,t8110-dart"; + reg = <0x6 0x83008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp>; + status = "disabled"; + }; + + pcie3_dart: iommu@684008000 { + compatible = "apple,t8110-dart"; + reg = <0x6 0x84008000 0x0 0x4000>; + #iommu-cells = <1>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&ps_apcie_gp>; + status = "disabled"; + }; + + pcie0: pcie@690000000 { + compatible = "apple,t8112-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x100000>, + <0x6 0x81000000 0x0 0x4000>, + <0x6 0x82000000 0x0 0x4000>, + <0x6 0x83000000 0x0 0x4000>, + <0x6 0x84000000 0x0 0x4000>; + reg-names = "config", "rc", "port0", "port1", "port2", "port3"; + + interrupt-parent = <&aic>; + interrupts = , + , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 793 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &pcie0_dart 0 1>, + <0x200 &pcie1_dart 1 1>, + <0x300 &pcie2_dart 2 1>, + <0x400 &pcie3_dart 3 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 4>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + power-domains = <&ps_apcie_gp>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + port00: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 166 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port00 0 0 0 0>, + <0 0 0 2 &port00 0 0 0 1>, + <0 0 0 3 &port00 0 0 0 2>, + <0 0 0 4 &port00 0 0 0 3>; + }; + + port01: pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 167 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port01 0 0 0 0>, + <0 0 0 2 &port01 0 0 0 1>, + <0 0 0 3 &port01 0 0 0 2>, + <0 0 0 4 &port01 0 0 0 3>; + + status = "disabled"; + }; + + port02: pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 168 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port02 0 0 0 0>, + <0 0 0 2 &port02 0 0 0 1>, + <0 0 0 3 &port02 0 0 0 2>, + <0 0 0 4 &port02 0 0 0 3>; + + status = "disabled"; + }; + + /* TODO: GPIO unknown */ + port03: pci@3,0 { + device_type = "pci"; + reg = <0x1800 0x0 0x0 0x0 0x0>; + //reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &port03 0 0 0 0>, + <0 0 0 2 &port03 0 0 0 1>, + <0 0 0 3 &port03 0 0 0 2>, + <0 0 0 4 &port03 0 0 0 3>; + + status = "disabled"; + }; + }; + }; +}; + +#include "t8112-pmgr.dtsi" From 223444882d9bb30d2eaa9e221f2939f881dec4aa Mon Sep 17 00:00:00 2001 From: Asahi Lina Date: Fri, 24 Feb 2023 15:49:44 +0900 Subject: [PATCH 0617/1040] soc: apple: rtkit: Fix buffer address field width The buffer address field is missing two bits. This matters for the GPU, which uses upper-half 64-bit addresses on the ASC and those get sign extended from the mailbox message field, so the right number of high bits need to be set. Signed-off-by: Asahi Lina Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- drivers/soc/apple/rtkit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/apple/rtkit.c b/drivers/soc/apple/rtkit.c index 35ec35aa500d..a02a44a745f6 100644 --- a/drivers/soc/apple/rtkit.c +++ b/drivers/soc/apple/rtkit.c @@ -55,7 +55,7 @@ enum { #define APPLE_RTKIT_BUFFER_REQUEST 1 #define APPLE_RTKIT_BUFFER_REQUEST_SIZE GENMASK_ULL(51, 44) -#define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK_ULL(41, 0) +#define APPLE_RTKIT_BUFFER_REQUEST_IOVA GENMASK_ULL(43, 0) #define APPLE_RTKIT_SYSLOG_TYPE GENMASK_ULL(59, 52) From bdfe6de2695c5bccc663a5a7d530f81925d8bc10 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 24 Feb 2023 17:21:59 +0100 Subject: [PATCH 0618/1040] soc: apple: rtkit: Crop syslog messages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Crop trailing whitespace, null, and newline characters in syslog messages received from coprocessors. Notably DCP sends its messages including a trailing newline, so prior to this change we would end up cluttering the kernel log by repeated newlines at the end of messages. Signed-off-by: Martin Povišer Reviewed-by: Hector Martin Signed-off-by: Hector Martin --- drivers/soc/apple/rtkit.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/soc/apple/rtkit.c b/drivers/soc/apple/rtkit.c index a02a44a745f6..d9f19dc99da5 100644 --- a/drivers/soc/apple/rtkit.c +++ b/drivers/soc/apple/rtkit.c @@ -409,11 +409,17 @@ static void apple_rtkit_syslog_rx_init(struct apple_rtkit *rtk, u64 msg) rtk->syslog_n_entries, rtk->syslog_msg_size); } +static bool should_crop_syslog_char(char c) +{ + return c == '\n' || c == '\r' || c == ' ' || c == '\0'; +} + static void apple_rtkit_syslog_rx_log(struct apple_rtkit *rtk, u64 msg) { u8 idx = msg & 0xff; char log_context[24]; size_t entry_size = 0x20 + rtk->syslog_msg_size; + int msglen; if (!rtk->syslog_msg_buffer) { dev_warn( @@ -446,7 +452,13 @@ static void apple_rtkit_syslog_rx_log(struct apple_rtkit *rtk, u64 msg) rtk->syslog_msg_size); log_context[sizeof(log_context) - 1] = 0; - rtk->syslog_msg_buffer[rtk->syslog_msg_size - 1] = 0; + + msglen = rtk->syslog_msg_size - 1; + while (msglen > 0 && + should_crop_syslog_char(rtk->syslog_msg_buffer[msglen - 1])) + msglen--; + + rtk->syslog_msg_buffer[msglen] = 0; dev_info(rtk->dev, "RTKit: syslog message: %s: %s\n", log_context, rtk->syslog_msg_buffer); From a0189fdfb73dac856b8fa9b9f9581e5099c9391f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 14 Feb 2023 15:07:22 +0100 Subject: [PATCH 0619/1040] arm64: dts: apple: t8103: Disable unused PCIe ports The PCIe ports are unused (without devices) so disable them instead of removing them. Fixes: 7c77ab91b33d ("arm64: dts: apple: Add missing M1 (t8103) devices") Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-j274.dts | 10 ++++++++++ arch/arm64/boot/dts/apple/t8103-j293.dts | 15 --------------- arch/arm64/boot/dts/apple/t8103-j313.dts | 15 --------------- arch/arm64/boot/dts/apple/t8103-j456.dts | 10 ++++++++++ arch/arm64/boot/dts/apple/t8103-j457.dts | 11 +++-------- arch/arm64/boot/dts/apple/t8103.dtsi | 4 ++++ 6 files changed, 27 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index b52ddc409893..1c3e37f86d46 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -37,10 +37,12 @@ &port01 { bus-range = <2 2>; + status = "okay"; }; &port02 { bus-range = <3 3>; + status = "okay"; ethernet0: ethernet@0,0 { reg = <0x30000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ @@ -48,6 +50,14 @@ }; }; +&pcie0_dart_1 { + status = "okay"; +}; + +&pcie0_dart_2 { + status = "okay"; +}; + &i2c2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 151074109a11..c363dfef8070 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -25,21 +25,6 @@ brcm,board-type = "apple,honshu"; }; -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; - &i2c2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts index bc1f865aa790..08409be1cf35 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -24,18 +24,3 @@ &wifi0 { brcm,board-type = "apple,shikoku"; }; - -/* - * Remove unused PCIe ports and disable the associated DARTs. - */ - -&pcie0_dart_1 { - status = "disabled"; -}; - -&pcie0_dart_2 { - status = "disabled"; -}; - -/delete-node/ &port01; -/delete-node/ &port02; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts index 2db425ceb30f..58c8e43789b4 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -55,13 +55,23 @@ &port01 { bus-range = <2 2>; + status = "okay"; }; &port02 { bus-range = <3 3>; + status = "okay"; ethernet0: ethernet@0,0 { reg = <0x30000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ local-mac-address = [00 10 18 00 00 00]; }; }; + +&pcie0_dart_1 { + status = "okay"; +}; + +&pcie0_dart_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts index 3821ff146c56..152f95fd49a2 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -37,6 +37,7 @@ &port02 { bus-range = <3 3>; + status = "okay"; ethernet0: ethernet@0,0 { reg = <0x30000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ @@ -44,12 +45,6 @@ }; }; -/* - * Remove unused PCIe port and disable the associated DART. - */ - -&pcie0_dart_1 { - status = "disabled"; +&pcie0_dart_2 { + status = "okay"; }; - -/delete-node/ &port01; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 9859219699f4..87a9c1ba6d0f 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -724,6 +724,7 @@ interrupt-parent = <&aic>; interrupts = ; power-domains = <&ps_apcie_gp>; + status = "disabled"; }; pcie0_dart_2: iommu@683008000 { @@ -733,6 +734,7 @@ interrupt-parent = <&aic>; interrupts = ; power-domains = <&ps_apcie_gp>; + status = "disabled"; }; pcie0: pcie@690000000 { @@ -807,6 +809,7 @@ <0 0 0 2 &port01 0 0 0 1>, <0 0 0 3 &port01 0 0 0 2>, <0 0 0 4 &port01 0 0 0 3>; + status = "disabled"; }; port02: pci@2,0 { @@ -826,6 +829,7 @@ <0 0 0 2 &port02 0 0 0 1>, <0 0 0 3 &port02 0 0 0 2>, <0 0 0 4 &port02 0 0 0 3>; + status = "disabled"; }; }; }; From 8d59efc33fdaa2c82072b4d3ba5f67d7dd9270d0 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 14 Feb 2023 15:07:23 +0100 Subject: [PATCH 0620/1040] arm64: dts: apple: t600x: Disable unused PCIe ports The PCIe ports are unused (without devices) so disable them instead of removing them. Signed-off-by: Janne Grunau Reviewed-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 4 ++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 11 ----------- arch/arm64/boot/dts/apple/t600x-j375.dtsi | 11 +++++++++++ 3 files changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 1c41954e3899..273d7060d031 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -233,6 +233,7 @@ interrupt-parent = <&aic>; interrupts = ; power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; }; pcie0_dart_3: iommu@584008000 { @@ -242,6 +243,7 @@ interrupt-parent = <&aic>; interrupts = ; power-domains = <&ps_apcie_gp_sys>; + status = "disabled"; }; pcie0: pcie@590000000 { @@ -338,6 +340,7 @@ <0 0 0 2 &port02 0 0 0 1>, <0 0 0 3 &port02 0 0 0 2>, <0 0 0 4 &port02 0 0 0 3>; + status = "disabled"; }; port03: pci@3,0 { @@ -357,5 +360,6 @@ <0 0 0 2 &port03 0 0 0 1>, <0 0 0 3 &port03 0 0 0 2>, <0 0 0 4 &port03 0 0 0 3>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index 34906d522f0a..356a73d1ce4c 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -101,14 +101,3 @@ wp-inverted; }; }; - -&pcie0_dart_2 { - status = "disabled"; -}; - -&pcie0_dart_3 { - status = "disabled"; -}; - -/delete-node/ &port02; -/delete-node/ &port03; diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index 00d3a9447c89..1e5a19e49b08 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -104,6 +104,7 @@ &port02 { /* 10 Gbit Ethernet */ bus-range = <3 3>; + status = "okay"; ethernet0: ethernet@0,0 { reg = <0x30000 0x0 0x0 0x0 0x0>; /* To be filled by the loader */ @@ -114,4 +115,14 @@ &port03 { /* USB xHCI */ bus-range = <4 4>; + status = "okay"; +}; + + +&pcie0_dart_2 { + status = "okay"; +}; + +&pcie0_dart_3 { + status = "okay"; }; From 2b48106419288b78ff934601c4c5c1c84532fcab Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 27 Mar 2023 18:02:18 +0300 Subject: [PATCH 0621/1040] ARM: tegra: transformers: Update WM8903 sound nodes Fix headset detection and use device GPIO microphone detection on WM8903 Transformers. Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-asus-tf101.dts | 13 +++++++------ arch/arm/boot/dts/tegra30-asus-tf300t.dts | 6 ++---- .../boot/dts/tegra30-asus-transformer-common.dtsi | 9 +++++---- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index 7b2969656ec9..3f1da75a2736 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -520,10 +520,10 @@ micdet-delay = <100>; gpio-cfg = < - 0xffffffff /* don't touch */ - 0xffffffff /* don't touch */ + 0x00000600 /* DMIC_LR, output */ + 0x00000680 /* DMIC_DAT, input */ 0x00000000 /* Speaker-enable GPIO, output, low */ - 0x00000400 /* Mic bias current detect */ + 0xffffffff /* don't touch */ 0xffffffff /* don't touch */ >; @@ -1184,15 +1184,16 @@ "Int Spk", "RON", "Int Spk", "LOP", "Int Spk", "LON", - "Mic Jack", "MICBIAS", - "IN1L", "Mic Jack"; + "IN2L", "Mic Jack", + "DMICDAT", "Int Mic"; nvidia,i2s-controller = <&tegra_i2s1>; nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,headset; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; + nvidia,coupled-mic-hp-det; clocks = <&tegra_car TEGRA20_CLK_PLL_A>, <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts index 506ae3626731..970a1f08dc8c 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts @@ -128,8 +128,8 @@ micdet-delay = <100>; gpio-cfg = < - 0xffffffff /* don't touch */ - 0xffffffff /* don't touch */ + 0x00000600 /* DMIC_LR, output */ + 0x00000680 /* DMIC_DAT, input */ 0x00000000 /* Speaker-enable GPIO, output, low */ 0xffffffff /* don't touch */ 0xffffffff /* don't touch */ @@ -1023,12 +1023,10 @@ "Int Spk", "RON", "Int Spk", "LOP", "Int Spk", "LON", - "IN1L", "Mic Jack", "IN2L", "Mic Jack", "DMICDAT", "Int Mic"; nvidia,audio-codec = <&wm8903>; nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,headset; }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index 1861b2de2dc3..bdb898ad6262 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -558,7 +558,7 @@ nvidia,enable-input = ; }; - spi2_cs1_n_pw2 { + hp_detect { nvidia,pins = "spi2_cs1_n_pw2"; nvidia,function = "spi2"; nvidia,pull = ; @@ -566,10 +566,10 @@ nvidia,enable-input = ; }; - spi2_sck_px2 { + mic_detect { nvidia,pins = "spi2_sck_px2"; nvidia,function = "spi2"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; @@ -1674,7 +1674,8 @@ nvidia,i2s-controller = <&tegra_i2s1>; nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,hp-mute-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; + nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>; + nvidia,coupled-mic-hp-det; clocks = <&tegra_car TEGRA30_CLK_PLL_A>, <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, From e9e17bcd554e29d18b065f48eca355382f06e9cb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 27 Mar 2023 18:02:19 +0300 Subject: [PATCH 0622/1040] ARM: tegra: transformers: Bind RT5631 sound nodes TF201, TF300TG and TF700T support RT5631 codec. Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-asus-tf201.dts | 17 +++++++++++++++++ arch/arm/boot/dts/tegra30-asus-tf300tg.dts | 17 +++++++++++++++++ arch/arm/boot/dts/tegra30-asus-tf700t.dts | 17 +++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts index 3c2b9e93e028..0406c5a69c12 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf201.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts @@ -624,4 +624,21 @@ /delete-node/ opp-800000000-1300; /delete-node/ opp-900000000-1350; }; + + sound { + compatible = "asus,tegra-audio-rt5631-tf201", + "nvidia,tegra-audio-rt5631"; + nvidia,model = "Asus Transformer Prime TF201 RT5631"; + + nvidia,audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Int Spk", "SPOL", + "Int Spk", "SPOR", + "MIC1", "MIC Bias1", + "MIC Bias1", "Mic Jack", + "DMIC", "Int Mic"; + + nvidia,audio-codec = <&rt5631>; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts index 573deeafb7ba..4861db8e1e59 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts @@ -1084,4 +1084,21 @@ /delete-node/ opp-800000000; /delete-node/ opp-900000000; }; + + sound { + compatible = "asus,tegra-audio-rt5631-tf300tg", + "nvidia,tegra-audio-rt5631"; + nvidia,model = "Asus Transformer Pad TF300TG RT5631"; + + nvidia,audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Int Spk", "SPOL", + "Int Spk", "SPOR", + "MIC1", "MIC Bias1", + "MIC Bias1", "Mic Jack", + "DMIC", "Int Mic"; + + nvidia,audio-codec = <&rt5631>; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts index e7fe8c7a7435..efde7dad718a 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -820,4 +820,21 @@ enable-active-high; vin-supply = <&vdd_3v3_sys>; }; + + sound { + compatible = "asus,tegra-audio-rt5631-tf700t", + "nvidia,tegra-audio-rt5631"; + nvidia,model = "Asus Transformer Infinity TF700T RT5631"; + + nvidia,audio-routing = + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Int Spk", "SPOL", + "Int Spk", "SPOR", + "MIC1", "MIC Bias1", + "MIC Bias1", "Mic Jack", + "DMIC", "Int Mic"; + + nvidia,audio-codec = <&rt5631>; + }; }; From a33bfafd99e0d1e33dfe910f751426f298a218b6 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Thu, 23 Mar 2023 16:09:52 +0800 Subject: [PATCH 0623/1040] soc: ti: Use devm_platform_ioremap_resource() According to commit 7945f929f1a7 ("drivers: provide devm_platform_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to use devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yang Li Link: https://lore.kernel.org/r/20230323080952.124410-1-yang.lee@linux.alibaba.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/wkup_m3_ipc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 6970478b40f3..c9197912ec24 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -615,7 +615,6 @@ static int wkup_m3_ipc_probe(struct platform_device *pdev) int irq, ret, temp; phandle rproc_phandle; struct rproc *m3_rproc; - struct resource *res; struct task_struct *task; struct wkup_m3_ipc *m3_ipc; struct device_node *np = dev->of_node; @@ -624,8 +623,7 @@ static int wkup_m3_ipc_probe(struct platform_device *pdev) if (!m3_ipc) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res); + m3_ipc->ipc_mem_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(m3_ipc->ipc_mem_base)) return PTR_ERR(m3_ipc->ipc_mem_base); From 76afff432f262712044864e3835841b1b41835a9 Mon Sep 17 00:00:00 2001 From: Roan van Dijk Date: Tue, 28 Mar 2023 11:33:11 +0200 Subject: [PATCH 0624/1040] ARM: stm32: add support for STM32MP151 This patch adds initial support of STM32MP151 microprocessor (MPU) based on Arm Cortex-A7. New Cortex-A infrastructure (gic, timer,...) are selected if ARCH_MULTI_V7 is defined. Signed-off-by: David Jander Signed-off-by: Roan van Dijk Signed-off-by: Alexandre Torgue --- arch/arm/mach-stm32/board-dt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c index 2ccaa11aaa56..5dcc4ddd1a56 100644 --- a/arch/arm/mach-stm32/board-dt.c +++ b/arch/arm/mach-stm32/board-dt.c @@ -21,6 +21,7 @@ static const char *const stm32_compat[] __initconst = { "st,stm32mp131", "st,stm32mp133", "st,stm32mp135", + "st,stm32mp151", "st,stm32mp157", NULL }; From dcbce56cac2676a6ca1ca33f352c8d46dd9626d6 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:18 +0200 Subject: [PATCH 0625/1040] ARM: dts: stm32: fix slew-rate of USART2 on stm32mp15xx-dkx On stm32mp15xx-dkx boards: - Fix slew-rate of USART 2 to 0 like other USARTs, because frequency of USART pins doesn't exceed 10Mhz. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index e15a3b2a9b39..e86d989dd351 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2178,7 +2178,7 @@ ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins2 { pinmux = , /* USART2_RX */ @@ -2196,7 +2196,7 @@ pinmux = ; /* USART2_RTS */ bias-disable; drive-push-pull; - slew-rate = <3>; + slew-rate = <0>; }; pins3 { pinmux = ; /* USART2_RX */ From abf52335762e7048e9fa5bc6f4c56a3e63b5bc80 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:19 +0200 Subject: [PATCH 0626/1040] ARM: dts: stm32: clean uart aliases on stm32mp15xx-dkx boards Remove duplicates and clean uart aliases. Uart aliases and uart pins should be declared and associated to uart instance at the same time. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1.dts | 3 --- arch/arm/boot/dts/stm32mp157c-dk2.dts | 3 --- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 6 ++++++ 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157a-dk1.dts b/arch/arm/boot/dts/stm32mp157a-dk1.dts index 4c8be9c8eb20..0da3667ab1e0 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1.dts @@ -17,9 +17,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; }; chosen { diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm32mp157c-dk2.dts index 2bc92ef3aeb9..ab13e340f4ef 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -18,9 +18,6 @@ aliases { ethernet0 = ðernet0; - serial0 = &uart4; - serial1 = &usart3; - serial2 = &uart7; serial3 = &usart2; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 11370ae0d868..ded5ab9a4798 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -8,6 +8,12 @@ #include / { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; From 92fd4848a181e1d8c118106d222d01a5172325d0 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:20 +0200 Subject: [PATCH 0627/1040] ARM: dts: stm32: clean uart aliases on stm32mp15xx-exx boards Remove duplicates and clean uart aliases. Uart aliases and uart pins should be declared and associated to uart instance at the same time. Put also aliases node above chosen node as same as stm32mp157c-dk2.dts. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 8 ++++---- arch/arm/boot/dts/stm32mp157c-ev1.dts | 9 ++++----- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index b1eb688a278a..2dfde6292668 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -16,6 +16,10 @@ model = "STMicroelectronics STM32MP157C eval daughter"; compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; + aliases { + serial0 = &uart4; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -72,10 +76,6 @@ }; }; - aliases { - serial0 = &uart4; - }; - sd_switch: regulator-sd_switch { compatible = "regulator-gpio"; regulator-name = "sd_switch"; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 542226cfcfdf..ba8e9d9a42fa 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -14,16 +14,15 @@ model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157"; - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { - serial0 = &uart4; serial1 = &usart3; ethernet0 = ðernet0; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + clocks { clk_ext_camera: clk-ext-camera { #clock-cells = <0>; From c1689f854cb9daa5f2ea098462107969452b0492 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:21 +0200 Subject: [PATCH 0628/1040] ARM: dts: stm32: add uart nodes on stm32mp13 Update device-tree stm32mp131.dtsi to add some uart features. On uart 1, 2, 3, 5, 6, 7, 8 nodes, add compabible, exti interrupts, clock, reset properties, dma config. On uart 4 node, only add dma configuration and use exti interrupt. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 97 ++++++++++++++++++++++++++++++- 1 file changed, 96 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 5949473cbbfd..9ea61687f023 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -397,12 +397,42 @@ status = "disabled"; }; + usart3: serial@4000f000 { + compatible = "st,stm32h7-uart"; + reg = <0x4000f000 0x400>; + interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART3_K>; + resets = <&rcc USART3_R>; + wakeup-source; + dmas = <&dmamux1 45 0x400 0x5>, + <&dmamux1 46 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; - interrupts = ; + interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; resets = <&rcc UART4_R>; + wakeup-source; + dmas = <&dmamux1 63 0x400 0x5>, + <&dmamux1 64 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@40011000 { + compatible = "st,stm32h7-uart"; + reg = <0x40011000 0x400>; + interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART5_K>; + resets = <&rcc UART5_R>; + wakeup-source; + dmas = <&dmamux1 65 0x400 0x5>, + <&dmamux1 66 0x400 0x1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -442,6 +472,32 @@ status = "disabled"; }; + uart7: serial@40018000 { + compatible = "st,stm32h7-uart"; + reg = <0x40018000 0x400>; + interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART7_K>; + resets = <&rcc UART7_R>; + wakeup-source; + dmas = <&dmamux1 79 0x400 0x5>, + <&dmamux1 80 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart8: serial@40019000 { + compatible = "st,stm32h7-uart"; + reg = <0x40019000 0x400>; + interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc UART8_K>; + resets = <&rcc UART8_R>; + wakeup-source; + dmas = <&dmamux1 81 0x400 0x5>, + <&dmamux1 82 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + timers1: timer@44000000 { #address-cells = <1>; #size-cells = <0>; @@ -524,6 +580,19 @@ }; }; + usart6: serial@44003000 { + compatible = "st,stm32h7-uart"; + reg = <0x44003000 0x400>; + interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART6_K>; + resets = <&rcc USART6_R>; + wakeup-source; + dmas = <&dmamux1 71 0x400 0x5>, + <&dmamux1 72 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s1: audio-controller@44004000 { compatible = "st,stm32h7-i2s"; reg = <0x44004000 0x400>; @@ -748,6 +817,32 @@ status = "disabled"; }; + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + i2s4: audio-controller@4c002000 { compatible = "st,stm32h7-i2s"; reg = <0x4c002000 0x400>; From 8d696053f308cb5b242fb5b7f66500310b3087a1 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:22 +0200 Subject: [PATCH 0629/1040] ARM: dts: stm32: add pins for usart2/1/4/8 in stm32mp13-pinctrl Add pins for uart4, uart8, usart1 and usart2 in stm32mp13-pinctrl.dtsi Theses pins have three states: default, sleep and idle. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 129 +++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index b2dce3a29f39..27e0c3826789 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -258,4 +258,133 @@ bias-disable; }; }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = ; /* UART8_TX */ + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = , /* UART8_TX */ + ; /* UART8_RX */ + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_TX */ + , /* USART1_RTS */ + , /* USART1_CTS_NSS */ + ; /* USART1_RX */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; }; From 623ac593a360f5c5fe34a002d006844f087549ce Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 28 Mar 2023 17:37:23 +0200 Subject: [PATCH 0630/1040] ARM: dts: stm32: add uart nodes and uart aliases on stm32mp135f-dk Update device-tree stm32mp135f-dk.dts to add usart1, uart8, usart2 and uart aliases. - Usart2 is used to interface a BT device, enable it by default. - Usart1 and uart8 are available on expansion connector. They are kept disabled. So, the pins are kept in analog state to lower power consumption by default or can be used as GPIO. - Uart4 is used for console. Signed-off-by: Valentin Caron Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 42 +++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index c40686cb2b9a..f0900ca672b5 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -19,6 +19,13 @@ aliases { serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; memory@c0000000 { @@ -267,8 +274,41 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +&usart1 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_a>; + pinctrl-1 = <&usart1_sleep_pins_a>; + pinctrl-2 = <&usart1_idle_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + pinctrl-2 = <&usart2_idle_pins_a>; + uart-has-rtscts; status = "okay"; }; From c4a48b0df8bfcf45256e8690f959a5af39c20ce7 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:10 -0700 Subject: [PATCH 0631/1040] dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable As evidenced by the Qualcomm TLMM Linux driver, the TLMM IP block in Qualcomm SoCs has a bit to enable/disable the output for a pin that's configured as a GPIO but _not_ a bit to enable/disable an input buffer. Current device trees that are specifying "input-enable" for pins managed by TLMM are either doing so needlessly or are using it to mean "output-disable". Presumably the current convention of using "input-enable" to mean "output-disable" stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Given that there's no other use for "input-enable" for TLMM, we can still handle old device trees in code, but let's encourage people to move to the proper / documented property by updating the bindings. Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230323102605.6.I291ce0ba2c6ea80b341659c4f75a567a76dd7ca6@changeid Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/qcom,tlmm-common.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index cb5ba1bd6f8d..5a815c199642 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -75,7 +75,8 @@ $defs: bias-pull-down: true bias-pull-up: true bias-disable: true - input-enable: true + input-enable: false + output-disable: true output-high: true output-low: true From 988a9eab4d9a0eb07339b9d3f2bc9bee66af47b1 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:11 -0700 Subject: [PATCH 0632/1040] dt-bindings: pinctrl: qcom: Add output-enable In the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") we allowed setting "output-disable" for TLMM pinctrl states. Let's also add "output-enable". At first blush this seems a needless thing to do. Specifically: - In Linux (and presumably any other OSes using the same device trees) the GPIO/pinctrl driver knows to automatically enable the output when a GPIO is changed to an output. Thus in most cases specifying "output-enable" is superfluous and should be avoided. - If we need to set a pin's default state we already have "output-high" and "output-low" and these properties already imply "output-enabled" (at least on the Linux Qualcomm TLMM driver). However, there is one instance where "output-enable" seems like it could be useful: sleep states. It's not uncommon to want to configure pins as inputs (with appropriate pulls) when the driver controlling them is in a low power state. Then we want the pins back to outputs when the driver wants things running normally. To accomplish this we'd want to be able to use "output-enable". Then the "default" state could have "output-enable" and the "sleep" state could have "output-disable". NOTE: in all instances I'm aware of, we'd only want to use "output-enable" on pins that are configured as "gpio". The Qualcomm documentation that I have access to says that "output-enable" only does something useful when in GPIO mode. Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230323102605.7.I7874c00092115c45377c2a06f7f133356956686e@changeid Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index 5a815c199642..90b7d75840c1 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -77,6 +77,7 @@ $defs: bias-disable: true input-enable: false output-disable: true + output-enable: true output-high: true output-low: true From e49eabe3e13f295e4f46daa897a0575654789a8c Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:12 -0700 Subject: [PATCH 0633/1040] pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE The Qualcomm pinctrl driver has been violating the documented meaning of PIN_CONFIG_INPUT_ENABLE. That documentation says: Note that this does not affect the pin's ability to drive output. ...yet the Qualcomm driver's sole action when asked to "enable input" on a pin is to disable its output. The Qualcomm driver's implementation stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Let's change the Qualcomm driver to move us in the right direction. As part of this: 1. We'll now support PIN_CONFIG_OUTPUT_ENABLE 2. We'll still support using PIN_CONFIG_INPUT_ENABLE to disable a pin's output (in violation of the docs) with a big comment in the code. This is needed because old device trees have "input-enable" in them and, in some cases, people might need the old behavior. While we could programmatically change all old device trees, it doesn't really hurt to keep supporting the old behavior and we're _supposed_ to try to be compatible with old device trees anyway. It can also be noted that the PIN_CONFIG_INPUT_ENABLE handling code seems to have purposefully ignored its argument. That means that old boards that had _either_ "input-disable" or "input-enable" in them would have had the effect of disabling a pin's output. While we could change this behavior, since we're only leaving the PIN_CONFIG_INPUT_ENABLE there for backward compatibility we might as well be fully backward compatible. NOTE: despite the fact that we'll still support PIN_CONFIG_INPUT_ENABLE for _setting_ config, we take it away from msm_config_group_get(). This appears to be only used for populating debugfs and fixing debugfs to "output enabled" where relevant instead of "input enabled" makes more sense and has more truthiness. Signed-off-by: Douglas Anderson Reviewed-by: Bjorn Andersson Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20230323102605.8.Id740ae6a993f9313b58add6b10f6a92795d510d4@changeid Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 36 +++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index daeb79a9a602..4515f375c5e8 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -323,6 +323,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, break; case PIN_CONFIG_OUTPUT: case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT_ENABLE: *bit = g->oe_bit; *mask = 1; break; @@ -414,11 +415,9 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, val = msm_readl_io(pctrl, g); arg = !!(val & BIT(g->in_bit)); break; - case PIN_CONFIG_INPUT_ENABLE: - /* Pin is output */ - if (arg) + case PIN_CONFIG_OUTPUT_ENABLE: + if (!arg) return -EINVAL; - arg = 1; break; default: return -ENOTSUPP; @@ -502,9 +501,36 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, arg = 1; break; case PIN_CONFIG_INPUT_ENABLE: - /* disable output */ + /* + * According to pinctrl documentation this should + * actually be a no-op. + * + * The docs are explicit that "this does not affect + * the pin's ability to drive output" but what we do + * here is to modify the output enable bit. Thus, to + * follow the docs we should remove that. + * + * The docs say that we should enable any relevant + * input buffer, but TLMM there is no input buffer that + * can be enabled/disabled. It's always on. + * + * The points above, explain why this _should_ be a + * no-op. However, for historical reasons and to + * support old device trees, we'll violate the docs + * still affect the output. + * + * It should further be noted that this old historical + * behavior actually overrides arg to 0. That means + * that "input-enable" and "input-disable" in a device + * tree would _both_ disable the output. We'll + * continue to preserve this behavior as well since + * we have no other use for this attribute. + */ arg = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = !!arg; + break; default: dev_err(pctrl->dev, "Unsupported config parameter: %x\n", param); From 0d0eaa780ba3b8a02a1ac87f38c34dfe365f27d6 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 22 Mar 2023 14:22:11 +0100 Subject: [PATCH 0634/1040] dt-bindings: optee driver interrupt can be a per-cpu interrupt Explicit in optee firmware device tree bindings that the interrupt used by optee driver for async notification can be a peripheral interrupt or a per-cpu interrupt. Signed-off-by: Etienne Carriere Reviewed-by: Sumit Garg Signed-off-by: Jens Wiklander --- .../devicetree/bindings/arm/firmware/linaro,optee-tz.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml index d4dc0749f9fd..5d033570b57b 100644 --- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml @@ -28,7 +28,8 @@ properties: maxItems: 1 description: | This interrupt which is used to signal an event by the secure world - software is expected to be edge-triggered. + software is expected to be either a per-cpu interrupt or an + edge-triggered peripheral interrupt. method: enum: [smc, hvc] From b3b4ced12c1bc829888803ce07fff317e590ec1c Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 22 Mar 2023 14:22:12 +0100 Subject: [PATCH 0635/1040] optee: add per cpu asynchronous notification Implements use of per-cpu irq for optee asynchronous notification. Existing optee async notif implementation allows OP-TEE world to raise an interrupt on which Linux optee driver will query some pending events. This change allows the signaling interrupt to be a per-cpu interrupt as with Arm GIC PPIs. Using a PPI instead of an SPI is useful when no GIC lines are provisioned in the chip design and there are spare PPI lines. Cc: Jens Wiklander Cc: Sumit Garg Cc: Marc Zyngier Co-developed-by: Alexandre Torgue Signed-off-by: Alexandre Torgue Signed-off-by: Etienne Carriere Reviewed-by: Sumit Garg [JW: fixing a spell error in @notif_pcpu_wq description] Signed-off-by: Jens Wiklander --- drivers/tee/optee/optee_private.h | 24 ++++++ drivers/tee/optee/smc_abi.c | 122 +++++++++++++++++++++++++++++- 2 files changed, 142 insertions(+), 4 deletions(-) diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index 04ae58892608..72685ee0d53f 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -94,11 +94,35 @@ struct optee_supp { struct completion reqs_c; }; +/* + * struct optee_pcpu - per cpu notif private struct passed to work functions + * @optee optee device reference + */ +struct optee_pcpu { + struct optee *optee; +}; + +/* + * struct optee_smc - optee smc communication struct + * @invoke_fn handler function to invoke secure monitor + * @memremaped_shm virtual address of memory in shared memory pool + * @sec_caps: secure world capabilities defined by + * OPTEE_SMC_SEC_CAP_* in optee_smc.h + * @notif_irq interrupt used as async notification by OP-TEE or 0 + * @optee_pcpu per_cpu optee instance for per cpu work or NULL + * @notif_pcpu_wq workqueue for per cpu asynchronous notification or NULL + * @notif_pcpu_work work for per cpu asynchronous notification + * @notif_cpuhp_state CPU hotplug state assigned for pcpu interrupt management + */ struct optee_smc { optee_invoke_fn *invoke_fn; void *memremaped_shm; u32 sec_caps; unsigned int notif_irq; + struct optee_pcpu __percpu *optee_pcpu; + struct workqueue_struct *notif_pcpu_wq; + struct work_struct notif_pcpu_work; + unsigned int notif_cpuhp_state; }; /** diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index a1c1fa1a9c28..de7ac9a46354 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -52,6 +52,23 @@ */ #define OPTEE_MIN_STATIC_POOL_ALIGN 9 /* 512 bytes aligned */ +/* SMC ABI considers at most a single TEE firmware */ +static unsigned int pcpu_irq_num; + +static int optee_cpuhp_enable_pcpu_irq(unsigned int cpu) +{ + enable_percpu_irq(pcpu_irq_num, IRQ_TYPE_NONE); + + return 0; +} + +static int optee_cpuhp_disable_pcpu_irq(unsigned int cpu) +{ + disable_percpu_irq(pcpu_irq_num); + + return 0; +} + /* * 1. Convert between struct tee_param and struct optee_msg_param * @@ -991,9 +1008,8 @@ static u32 get_async_notif_value(optee_invoke_fn *invoke_fn, bool *value_valid, return res.a1; } -static irqreturn_t notif_irq_handler(int irq, void *dev_id) +static irqreturn_t irq_handler(struct optee *optee) { - struct optee *optee = dev_id; bool do_bottom_half = false; bool value_valid; bool value_pending; @@ -1016,6 +1032,13 @@ static irqreturn_t notif_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static irqreturn_t notif_irq_handler(int irq, void *dev_id) +{ + struct optee *optee = dev_id; + + return irq_handler(optee); +} + static irqreturn_t notif_irq_thread_fn(int irq, void *dev_id) { struct optee *optee = dev_id; @@ -1025,7 +1048,7 @@ static irqreturn_t notif_irq_thread_fn(int irq, void *dev_id) return IRQ_HANDLED; } -static int optee_smc_notif_init_irq(struct optee *optee, u_int irq) +static int init_irq(struct optee *optee, u_int irq) { int rc; @@ -1040,12 +1063,103 @@ static int optee_smc_notif_init_irq(struct optee *optee, u_int irq) return 0; } +static irqreturn_t notif_pcpu_irq_handler(int irq, void *dev_id) +{ + struct optee_pcpu *pcpu = dev_id; + struct optee *optee = pcpu->optee; + + if (irq_handler(optee) == IRQ_WAKE_THREAD) + queue_work(optee->smc.notif_pcpu_wq, + &optee->smc.notif_pcpu_work); + + return IRQ_HANDLED; +} + +static void notif_pcpu_irq_work_fn(struct work_struct *work) +{ + struct optee_smc *optee_smc = container_of(work, struct optee_smc, + notif_pcpu_work); + struct optee *optee = container_of(optee_smc, struct optee, smc); + + optee_smc_do_bottom_half(optee->ctx); +} + +static int init_pcpu_irq(struct optee *optee, u_int irq) +{ + struct optee_pcpu __percpu *optee_pcpu; + int cpu, rc; + + optee_pcpu = alloc_percpu(struct optee_pcpu); + if (!optee_pcpu) + return -ENOMEM; + + for_each_present_cpu(cpu) + per_cpu_ptr(optee_pcpu, cpu)->optee = optee; + + rc = request_percpu_irq(irq, notif_pcpu_irq_handler, + "optee_pcpu_notification", optee_pcpu); + if (rc) + goto err_free_pcpu; + + INIT_WORK(&optee->smc.notif_pcpu_work, notif_pcpu_irq_work_fn); + optee->smc.notif_pcpu_wq = create_workqueue("optee_pcpu_notification"); + if (!optee->smc.notif_pcpu_wq) { + rc = -EINVAL; + goto err_free_pcpu_irq; + } + + optee->smc.optee_pcpu = optee_pcpu; + optee->smc.notif_irq = irq; + + pcpu_irq_num = irq; + rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "optee/pcpu-notif:starting", + optee_cpuhp_enable_pcpu_irq, + optee_cpuhp_disable_pcpu_irq); + if (!rc) + rc = -EINVAL; + if (rc < 0) + goto err_free_pcpu_irq; + + optee->smc.notif_cpuhp_state = rc; + + return 0; + +err_free_pcpu_irq: + free_percpu_irq(irq, optee_pcpu); +err_free_pcpu: + free_percpu(optee_pcpu); + + return rc; +} + +static int optee_smc_notif_init_irq(struct optee *optee, u_int irq) +{ + if (irq_is_percpu_devid(irq)) + return init_pcpu_irq(optee, irq); + else + return init_irq(optee, irq); +} + +static void uninit_pcpu_irq(struct optee *optee) +{ + cpuhp_remove_state(optee->smc.notif_cpuhp_state); + + destroy_workqueue(optee->smc.notif_pcpu_wq); + + free_percpu_irq(optee->smc.notif_irq, optee->smc.optee_pcpu); + free_percpu(optee->smc.optee_pcpu); +} + static void optee_smc_notif_uninit_irq(struct optee *optee) { if (optee->smc.sec_caps & OPTEE_SMC_SEC_CAP_ASYNC_NOTIF) { optee_smc_stop_async_notif(optee->ctx); if (optee->smc.notif_irq) { - free_irq(optee->smc.notif_irq, optee); + if (irq_is_percpu_devid(optee->smc.notif_irq)) + uninit_pcpu_irq(optee); + else + free_irq(optee->smc.notif_irq, optee); + irq_dispose_mapping(optee->smc.notif_irq); } } From 2690e80bc29e8f1a369e36458b4a72c151178fbc Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:05 +0100 Subject: [PATCH 0636/1040] arm64: dts: mediatek: mt8183-kukui: Couple VGPU and VSRAM_GPU regulators Add coupling for these regulators, as they have a strict voltage output relation to satisfy in order to ensure GPU stable operation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index fbe14b13051a..de9778c85b94 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -294,7 +294,6 @@ &gpu { mali-supply = <&mt6358_vgpu_reg>; - sram-supply = <&mt6358_vsram_gpu_reg>; }; &i2c0 { @@ -401,6 +400,11 @@ Avdd-supply = <&mt6358_vaud28_reg>; }; +&mt6358_vgpu_reg { + regulator-coupled-with = <&mt6358_vsram_gpu_reg>; + regulator-coupled-max-spread = <100000>; +}; + &mt6358_vsim1_reg { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2700000>; @@ -411,6 +415,11 @@ regulator-max-microvolt = <2700000>; }; +&mt6358_vsram_gpu_reg { + regulator-coupled-with = <&mt6358_vgpu_reg>; + regulator-coupled-max-spread = <100000>; +}; + &pio { aud_pins_default: audiopins { pins_bus { From 31c6732da9d549af92732d8126f46c1c9d7fa8d4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:06 +0100 Subject: [PATCH 0637/1040] arm64: dts: mediatek: mt8183-kukui: Override vgpu/vsram_gpu constraints Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU with the platform specific vmin/vmax for the highest possible SoC binning. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index de9778c85b94..63952c1251df 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -401,6 +401,9 @@ }; &mt6358_vgpu_reg { + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <900000>; + regulator-coupled-with = <&mt6358_vsram_gpu_reg>; regulator-coupled-max-spread = <100000>; }; @@ -416,6 +419,9 @@ }; &mt6358_vsram_gpu_reg { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-coupled-with = <&mt6358_vgpu_reg>; regulator-coupled-max-spread = <100000>; }; From dbe602b27793afd18e4dbc15c8d308ef28f49056 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:07 +0100 Subject: [PATCH 0638/1040] arm64: dts: mediatek: mt8183: Remove second opp-microvolt entries from gpu table This was done to keep a strict relation between VSRAM and VGPU, but it never worked: now we're doing it transparently with the new mediatek-regulator-coupler driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 3d1d7870a5f1..e01b96adef02 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -563,82 +563,82 @@ opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <625000>, <850000>; + opp-microvolt = <625000>; }; opp-320000000 { opp-hz = /bits/ 64 <320000000>; - opp-microvolt = <631250>, <850000>; + opp-microvolt = <631250>; }; opp-340000000 { opp-hz = /bits/ 64 <340000000>; - opp-microvolt = <637500>, <850000>; + opp-microvolt = <637500>; }; opp-360000000 { opp-hz = /bits/ 64 <360000000>; - opp-microvolt = <643750>, <850000>; + opp-microvolt = <643750>; }; opp-380000000 { opp-hz = /bits/ 64 <380000000>; - opp-microvolt = <650000>, <850000>; + opp-microvolt = <650000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <656250>, <850000>; + opp-microvolt = <656250>; }; opp-420000000 { opp-hz = /bits/ 64 <420000000>; - opp-microvolt = <662500>, <850000>; + opp-microvolt = <662500>; }; opp-460000000 { opp-hz = /bits/ 64 <460000000>; - opp-microvolt = <675000>, <850000>; + opp-microvolt = <675000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <687500>, <850000>; + opp-microvolt = <687500>; }; opp-540000000 { opp-hz = /bits/ 64 <540000000>; - opp-microvolt = <700000>, <850000>; + opp-microvolt = <700000>; }; opp-580000000 { opp-hz = /bits/ 64 <580000000>; - opp-microvolt = <712500>, <850000>; + opp-microvolt = <712500>; }; opp-620000000 { opp-hz = /bits/ 64 <620000000>; - opp-microvolt = <725000>, <850000>; + opp-microvolt = <725000>; }; opp-653000000 { opp-hz = /bits/ 64 <653000000>; - opp-microvolt = <743750>, <850000>; + opp-microvolt = <743750>; }; opp-698000000 { opp-hz = /bits/ 64 <698000000>; - opp-microvolt = <768750>, <868750>; + opp-microvolt = <768750>; }; opp-743000000 { opp-hz = /bits/ 64 <743000000>; - opp-microvolt = <793750>, <893750>; + opp-microvolt = <793750>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <825000>, <925000>; + opp-microvolt = <825000>; }; }; From 5dba6621771d37587c1fe929acde21759e3d56d7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:08 +0100 Subject: [PATCH 0639/1040] arm64: dts: mt8183-pumpkin: Couple VGPU and VSRAM_GPU regulators Add coupling for these regulators, as they have a strict voltage output relation to satisfy in order to ensure GPU stable operation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index a1d01639df30..c228f04d086b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -71,7 +71,6 @@ &gpu { mali-supply = <&mt6358_vgpu_reg>; - sram-supply = <&mt6358_vsram_gpu_reg>; }; &i2c0 { @@ -176,6 +175,16 @@ non-removable; }; +&mt6358_vgpu_reg { + regulator-coupled-with = <&mt6358_vsram_gpu_reg>; + regulator-coupled-max-spread = <100000>; +}; + +&mt6358_vsram_gpu_reg { + regulator-coupled-with = <&mt6358_vgpu_reg>; + regulator-coupled-max-spread = <100000>; +}; + &pio { i2c_pins_0: i2c0 { pins_i2c{ From 85ae8a51437e8ff1d08b266129bddd0561c1bdfe Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:09 +0100 Subject: [PATCH 0640/1040] arm64: dts: mediatek: mt8183-evb: Couple VGPU and VSRAM_GPU regulators Add coupling for these regulators, as they have a strict voltage output relation to satisfy in order to ensure GPU stable operation. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 52dc4a50e34d..fd327437e932 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -52,7 +52,6 @@ &gpu { mali-supply = <&mt6358_vgpu_reg>; - sram-supply = <&mt6358_vsram_gpu_reg>; }; &i2c0 { @@ -138,6 +137,16 @@ non-removable; }; +&mt6358_vgpu_reg { + regulator-coupled-with = <&mt6358_vsram_gpu_reg>; + regulator-coupled-max-spread = <100000>; +}; + +&mt6358_vsram_gpu_reg { + regulator-coupled-with = <&mt6358_vgpu_reg>; + regulator-coupled-max-spread = <100000>; +}; + &pio { i2c_pins_0: i2c0{ pins_i2c{ From c78838d803150644e33aeb1bd0df07c9e357302a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:10 +0100 Subject: [PATCH 0641/1040] arm64: dts: mediatek: mt8183: Use mediatek,mt8183b-mali as GPU compatible Use the new GPU related compatible to finally enable GPU DVFS on the MT8183 SoC. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index e01b96adef02..5169779d01df 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1752,7 +1752,7 @@ }; gpu: gpu@13040000 { - compatible = "mediatek,mt8183-mali", "arm,mali-bifrost"; + compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost"; reg = <0 0x13040000 0 0x4000>; interrupts = , From e12333451e76e1fe9121a3ce30b930c719fc04dd Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 1 Mar 2023 10:55:11 +0100 Subject: [PATCH 0642/1040] arm64: dts: mediatek: mt8192: Add GPU nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MediaTek MT8192 includes a Mali-G57 GPU supported in Panfrost. Add the GPU node to the device tree to enable 3D acceleration. The GPU node is disabled by default. It should be enabled by board with its power supplies correctly assigned. Signed-off-by: Alyssa Rosenzweig [nfraprado: removed sram supply, tweaked opp node name, adjusted commit message] Signed-off-by: Nícolas F. R. A. Prado [wenst@: disable GPU by default; adjusted prefix; split out board change] Signed-off-by: Chen-Yu Tsai [Angelo: cosmetic fixes] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-8-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 107 +++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 87b91c8feaf9..34631adc52c6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -312,6 +312,91 @@ clock-frequency = <13000000>; }; + gpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + opp-microvolt = <606250>; + }; + + opp-399000000 { + opp-hz = /bits/ 64 <399000000>; + opp-microvolt = <618750>; + }; + + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-microvolt = <631250>; + }; + + opp-482000000 { + opp-hz = /bits/ 64 <482000000>; + opp-microvolt = <643750>; + }; + + opp-523000000 { + opp-hz = /bits/ 64 <523000000>; + opp-microvolt = <656250>; + }; + + opp-564000000 { + opp-hz = /bits/ 64 <564000000>; + opp-microvolt = <668750>; + }; + + opp-605000000 { + opp-hz = /bits/ 64 <605000000>; + opp-microvolt = <681250>; + }; + + opp-647000000 { + opp-hz = /bits/ 64 <647000000>; + opp-microvolt = <693750>; + }; + + opp-688000000 { + opp-hz = /bits/ 64 <688000000>; + opp-microvolt = <706250>; + }; + + opp-724000000 { + opp-hz = /bits/ 64 <724000000>; + opp-microvolt = <725000>; + }; + + opp-748000000 { + opp-hz = /bits/ 64 <748000000>; + opp-microvolt = <737500>; + }; + + opp-772000000 { + opp-hz = /bits/ 64 <772000000>; + opp-microvolt = <750000>; + }; + + opp-795000000 { + opp-hz = /bits/ 64 <795000000>; + opp-microvolt = <762500>; + }; + + opp-819000000 { + opp-hz = /bits/ 64 <819000000>; + opp-microvolt = <775000>; + }; + + opp-843000000 { + opp-hz = /bits/ 64 <843000000>; + opp-microvolt = <787500>; + }; + + opp-866000000 { + opp-hz = /bits/ 64 <866000000>; + opp-microvolt = <800000>; + }; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -1266,6 +1351,28 @@ status = "disabled"; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt8192-mali", "arm,mali-valhall-jm"; + reg = <0 0x13000000 0 0x4000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; + + power-domains = <&spm MT8192_POWER_DOMAIN_MFG2>, + <&spm MT8192_POWER_DOMAIN_MFG3>, + <&spm MT8192_POWER_DOMAIN_MFG4>, + <&spm MT8192_POWER_DOMAIN_MFG5>, + <&spm MT8192_POWER_DOMAIN_MFG6>; + power-domain-names = "core0", "core1", "core2", "core3", "core4"; + + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + }; + mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8192-mfgcfg"; reg = <0 0x13fbf000 0 0x1000>; From 61348fe9e75b7edb25b26ce789a9aec617b20090 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:12 +0100 Subject: [PATCH 0643/1040] arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain The mfg_ref_sel clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-9-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 34631adc52c6..a29cdff8a095 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -499,8 +499,9 @@ power-domain@MT8192_POWER_DOMAIN_MFG0 { reg = ; - clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; - clock-names = "mfg"; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, + <&topckgen CLK_TOP_MFG_REF_SEL>; + clock-names = "mfg", "alt"; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <1>; From 6fe90cc51988f929d96a2b69417b442413145732 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Wed, 1 Mar 2023 10:55:13 +0100 Subject: [PATCH 0644/1040] arm64: dts: mediatek: mt8192-asurada: Add MFG0 domain supply MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The mfg0 power domain encompasses the whole GPU and its surrounding glue logic. This power domain has a separate power rail. Add its power supply for Asurada. Signed-off-by: Nícolas F. R. A. Prado [wenst@chromium.org: fix subject prefix and add commit message] Signed-off-by: Chen-Yu Tsai [Angelo: Reordered commits to address DVFS stability issues] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-10-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 9f12257ab4e7..ec013d5ef157 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -380,6 +380,10 @@ pinctrl-0 = <&i2c7_pins>; }; +&mfg0 { + domain-supply = <&mt6315_7_vbuck1>; +}; + &mipi_tx0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a29cdff8a095..f19d4a8ef3f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -497,7 +497,7 @@ #power-domain-cells = <0>; }; - power-domain@MT8192_POWER_DOMAIN_MFG0 { + mfg0: power-domain@MT8192_POWER_DOMAIN_MFG0 { reg = ; clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>, <&topckgen CLK_TOP_MFG_REF_SEL>; From 3daabcb2392678c1d5997404b29c13bc27dac306 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:14 +0100 Subject: [PATCH 0645/1040] arm64: dts: mediatek: mt8192-asurada: Assign sram supply to MFG1 pd Add a phandle to the MT8192_POWER_DOMAIN_MFG1 power domain and assign the GPU VSRAM supply to this in mt8192-asurada: this allows to keep the sram powered up while the GPU is used. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-11-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 ++++ arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index ec013d5ef157..df477eb89f21 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -384,6 +384,10 @@ domain-supply = <&mt6315_7_vbuck1>; }; +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + &mipi_tx0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index f19d4a8ef3f6..5c30caf74026 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -506,7 +506,7 @@ #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8192_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { reg = ; mediatek,infracfg = <&infracfg>; #address-cells = <1>; From ff4c868ba8df9dcd144ab4943a50adca1cf33ba2 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:15 +0100 Subject: [PATCH 0646/1040] arm64: dts: mediatek: mt8192-asurada: Fix voltage constraint for Vgpu The MT8192 SoC specifies a maximum voltage for the GPU's digital supply of 0.88V and the GPU OPPs are declaring a maximum voltage of 0.80V. In order to keep the GPU voltage in the safe range, change the maximum voltage for mt6315@7's vbuck1 to 0.80V as sending, for any mistake, 1.193V would be catastrophic. Fixes: 3183cb62b033 ("arm64: dts: mediatek: asurada: Add SPMI regulators") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-12-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index df477eb89f21..8570b78c04a4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -1408,7 +1408,7 @@ regulator-compatible = "vbuck1"; regulator-name = "Vgpu"; regulator-min-microvolt = <606250>; - regulator-max-microvolt = <1193750>; + regulator-max-microvolt = <800000>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; }; From c4ce03bf0f9dcccf630a4091a038cd8ad11646ff Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:16 +0100 Subject: [PATCH 0647/1040] arm64: dts: mediatek: mt8192-asurada: Couple VGPU and VSRAM_OTHER regulators Add coupling for these regulators, as VSRAM_OTHER is used to power the GPU SRAM, and they have a strict voltage output relation to satisfy in order to ensure GPU stable operation. While at it, also add voltage constraint overrides for the GPU SRAM regulator "mt6359_vsram_others" so that we stay in a safe range of 0.75-0.80V. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-13-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 8570b78c04a4..f858eca219d7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -447,6 +447,13 @@ regulator-always-on; }; +&mt6359_vsram_others_ldo_reg { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6315_7_vbuck1>; + regulator-coupled-max-spread = <10000>; +}; + &mt6359_vufs_ldo_reg { regulator-always-on; }; @@ -1411,6 +1418,8 @@ regulator-max-microvolt = <800000>; regulator-enable-ramp-delay = <256>; regulator-allowed-modes = <0 1 2>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <10000>; }; }; }; From 309460b6260195ae0631c8f15ddb1c23a00b4562 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 1 Mar 2023 10:55:17 +0100 Subject: [PATCH 0648/1040] arm64: dts: mediatek: mt8192-asurada: Enable GPU Enable the GPU with its power supplies described. Signed-off-by: Alyssa Rosenzweig [wenst@: patch split out from MT8192 GPU node patch] Signed-off-by: Chen-Yu Tsai [Angelo: Minor commit title fix] Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-14-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index f858eca219d7..5a440504d4f9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -275,6 +275,11 @@ remote-endpoint = <&anx7625_in>; }; +&gpu { + mali-supply = <&mt6315_7_vbuck1>; + status = "okay"; +}; + &i2c0 { status = "okay"; From d434abbb560aae20b31caa34088c3677fe925be6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:18 +0100 Subject: [PATCH 0649/1040] arm64: dts: mediatek: mt8195: Add mfg_core_tmp clock to MFG1 domain Similarly to what can be seen in MT8192, on MT8195 the mfg_core_tmp clock is a mux used to switch between different "safe" (and slower) clock sources for the GPU: this is used during MFGPLL reconfiguration and eventually during idling at very low frequencies. This clock getting turned off means that the GPU will occasionally be unclocked, producing obvious consequences such as system crash or unpredictable behavior: assigning it to the top level MFG power domain will make sure that this stays on at all times during any operation on the MFG domain (only GPU-related transactions). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-15-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 8fc527570791..6767bac3f69e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -446,8 +446,9 @@ power-domain@MT8195_POWER_DOMAIN_MFG1 { reg = ; - clocks = <&apmixedsys CLK_APMIXED_MFGPLL>; - clock-names = "mfg"; + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, + <&topckgen CLK_TOP_MFG_CORE_TMP>; + clock-names = "mfg", "alt"; mediatek,infracfg = <&infracfg_ao>; #address-cells = <1>; #size-cells = <0>; From 9a512b4d7a7b262496dbf68c01c11b0536dfcf0b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:19 +0100 Subject: [PATCH 0650/1040] arm64: dts: mt8195: Add panfrost node for Mali-G57 Valhall Natt GPU Add GPU support through panfrost for the Mali-G57 GPU on MT8195 with its OPP table but keep it in disabled state. This is expected to be enabled only on boards which make use of the GPU. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-16-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 90 ++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 6767bac3f69e..b0ee4dc4ce20 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -333,6 +333,76 @@ #performance-domain-cells = <1>; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-microvolt = <625000>; + }; + opp-410000000 { + opp-hz = /bits/ 64 <410000000>; + opp-microvolt = <631250>; + }; + opp-431000000 { + opp-hz = /bits/ 64 <431000000>; + opp-microvolt = <631250>; + }; + opp-473000000 { + opp-hz = /bits/ 64 <473000000>; + opp-microvolt = <637500>; + }; + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + opp-microvolt = <637500>; + }; + opp-556000000 { + opp-hz = /bits/ 64 <556000000>; + opp-microvolt = <643750>; + }; + opp-598000000 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <650000>; + }; + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-microvolt = <650000>; + }; + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + opp-microvolt = <662500>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <675000>; + }; + opp-730000000 { + opp-hz = /bits/ 64 <730000000>; + opp-microvolt = <687500>; + }; + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-microvolt = <700000>; + }; + opp-790000000 { + opp-hz = /bits/ 64 <790000000>; + opp-microvolt = <712500>; + }; + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + opp-microvolt = <725000>; + }; + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <737500>; + }; + opp-880000000 { + opp-hz = /bits/ 64 <880000000>; + opp-microvolt = <750000>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; @@ -1790,6 +1860,26 @@ status = "disabled"; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", + "arm,mali-valhall-jm"; + reg = <0 0x13000000 0 0x4000>; + + clocks = <&mfgcfg CLK_MFG_BG3D>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, + <&spm MT8195_POWER_DOMAIN_MFG3>, + <&spm MT8195_POWER_DOMAIN_MFG4>, + <&spm MT8195_POWER_DOMAIN_MFG5>, + <&spm MT8195_POWER_DOMAIN_MFG6>; + power-domain-names = "core0", "core1", "core2", "core3", "core4"; + status = "disabled"; + }; + mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8195-mfgcfg"; reg = <0 0x13fbf000 0 0x1000>; From 673f8b60c610e9ac3d09c8ba97805df24c034024 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:20 +0100 Subject: [PATCH 0651/1040] arm64: dts: mediatek: mt8195-cherry: Enable Mali-G57 GPU Enable the Mali-G57 found on this platform with the open-source Panfrost driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-17-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 56749cfe7c33..24669093fbed 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -238,6 +238,11 @@ }; }; +&gpu { + status = "okay"; + mali-supply = <&mt6315_7_vbuck1>; +}; + &i2c0 { status = "okay"; From ee63f4144d8c55ada20216c862fdf46b2cd02998 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:21 +0100 Subject: [PATCH 0652/1040] arm64: dts: mediatek: mt8186: Add GPU node Add a GPU node for MT8186 SoC but keep it disabled. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index a0d3e1f731bd..78ff8ba5718e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1075,6 +1075,23 @@ #clock-cells = <1>; }; + gpu: gpu@13040000 { + compatible = "mediatek,mt8186-mali", + "arm,mali-bifrost"; + reg = <0 0x13040000 0 0x4000>; + + clocks = <&mfgsys CLK_MFG_BG3D>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, + <&spm MT8186_POWER_DOMAIN_MFG3>; + power-domain-names = "core0", "core1"; + #cooling-cells = <2>; + status = "disabled"; + }; + mmsys: syscon@14000000 { compatible = "mediatek,mt8186-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; From ba4927d16e3a841e3d8380092b5dc33604bc90f4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:22 +0100 Subject: [PATCH 0653/1040] arm64: dts: mediatek: mt8183-pumpkin: Override vgpu/vsram_gpu constraints Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU with the platform specific vmin/vmax for the highest possible SoC binning. Signed-off-by: AngeloGioacchino Del Regno Suggested-by: Chen-Yu Tsai Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-19-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index c228f04d086b..526bcae7a3f8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -176,11 +176,17 @@ }; &mt6358_vgpu_reg { + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <900000>; + regulator-coupled-with = <&mt6358_vsram_gpu_reg>; regulator-coupled-max-spread = <100000>; }; &mt6358_vsram_gpu_reg { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-coupled-with = <&mt6358_vgpu_reg>; regulator-coupled-max-spread = <100000>; }; From 61ac25e5296015c7a5d49cd7405459d4f47f28e6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Mar 2023 10:55:23 +0100 Subject: [PATCH 0654/1040] arm64: dts: mediatek: mt8183-evb: Override vgpu/vsram_gpu constraints Override the PMIC-default voltage constraints for VGPU and VSRAM_GPU with the platform specific vmin/vmax for the highest possible SoC binning. Signed-off-by: AngeloGioacchino Del Regno Suggested-by: Chen-Yu Tsai Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230301095523.428461-20-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index fd327437e932..3e3f4b1b00f0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -138,11 +138,17 @@ }; &mt6358_vgpu_reg { + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <900000>; + regulator-coupled-with = <&mt6358_vsram_gpu_reg>; regulator-coupled-max-spread = <100000>; }; &mt6358_vsram_gpu_reg { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-coupled-with = <&mt6358_vgpu_reg>; regulator-coupled-max-spread = <100000>; }; From 92d2c23dc269985fdf098735710b2ac3f91801dd Mon Sep 17 00:00:00 2001 From: "Nancy.Lin" Date: Thu, 23 Mar 2023 09:37:30 +0800 Subject: [PATCH 0655/1040] arm64: dts: mt8195: add display node for vdosys1 Add display node for vdosys1. Signed-off-by: Nancy.Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230323013730.1378-1-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 223 +++++++++++++++++++++++ 1 file changed, 223 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index b0ee4dc4ce20..c5248deaac99 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -24,6 +24,22 @@ aliases { gce0 = &gce0; gce1 = &gce1; + ethdr0 = ðdr0; + mutex0 = &mutex; + mutex1 = &mutex1; + merge1 = &merge1; + merge2 = &merge2; + merge3 = &merge3; + merge4 = &merge4; + merge5 = &merge5; + vdo1-rdma0 = &vdo1_rdma0; + vdo1-rdma1 = &vdo1_rdma1; + vdo1-rdma2 = &vdo1_rdma2; + vdo1-rdma3 = &vdo1_rdma3; + vdo1-rdma4 = &vdo1_rdma4; + vdo1-rdma5 = &vdo1_rdma5; + vdo1-rdma6 = &vdo1_rdma6; + vdo1-rdma7 = &vdo1_rdma7; }; cpus { @@ -2666,7 +2682,10 @@ vdosys1: syscon@1c100000 { compatible = "mediatek,mt8195-vdosys1", "syscon"; reg = <0 0x1c100000 0 0x1000>; + mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; smi_common_vdo: smi@1c01b000 { @@ -2695,6 +2714,17 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; }; + mutex1: mutex@1c101000 { + compatible = "mediatek,mt8195-disp-mutex"; + reg = <0 0x1c101000 0 0x1000>; + reg-names = "vdo1_mutex"; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; + clock-names = "vdo1_mutex"; + mediatek,gce-events = ; + }; + larb2: larb@1c102000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1c102000 0 0x1000>; @@ -2719,6 +2749,151 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + vdo1_rdma0: rdma@1c104000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: rdma@1c105000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c105000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: rdma@1c106000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c106000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: rdma@1c107000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c107000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: rdma@1c108000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c108000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: rdma@1c109000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c109000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: rdma@1c10a000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10a000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: rdma@1c10b000 { + compatible = "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10b000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge1: vpp-merge@1c10c000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10c000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; + }; + + merge2: vpp-merge@1c10d000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10d000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; + }; + + merge3: vpp-merge@1c10e000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10e000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; + }; + + merge4: vpp-merge@1c10f000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10f000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; + }; + + merge5: vpp-merge@1c110000 { + compatible = "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + interrupts = ; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge","merge_async"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en = <1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; + }; + dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8195-dp-intf"; reg = <0 0x1c113000 0 0x1000>; @@ -2731,6 +2906,54 @@ status = "disabled"; }; + ethdr0: hdr-engine@1c114000 { + compatible = "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", + "ethdr_top"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; + interrupts = ; /* disp mixer */ + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; + reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", + "gfx_fe1_async", "vdo_be_async"; + }; + edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8195-edp-tx"; reg = <0 0x1c500000 0 0x8000>; From edecdcccc1e971b1f0c077ef1f1f714251864aa1 Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Thu, 16 Feb 2023 21:25:43 +0800 Subject: [PATCH 0656/1040] soc: mediatek: mtk-svs: fix passing zero to 'PTR_ERR' nvmem_cell_get() cannot return NULL so checking for NULL is wrong here. Signed-off-by: Roger Lu Fixes: 6c7174fd90a4690 ("soc: mediatek: mtk-svs: use svs get efuse common function") Reported-by: kernel test robot Reported-by: Dan Carpenter Link: https://lore.kernel.org/r/202302160720.N64SWT4l-lkp@intel.com/ Link: https://lore.kernel.org/r/20230216132543.814-1-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index a7eb019b5157..8127fb6d587b 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1726,7 +1726,7 @@ static int svs_get_efuse_data(struct svs_platform *svsp, struct nvmem_cell *cell; cell = nvmem_cell_get(svsp->dev, nvmem_cell_name); - if (IS_ERR_OR_NULL(cell)) { + if (IS_ERR(cell)) { dev_err(svsp->dev, "no \"%s\"? %ld\n", nvmem_cell_name, PTR_ERR(cell)); return PTR_ERR(cell); From bd0a62a667c4a4ee790376641e06f7b17000496f Mon Sep 17 00:00:00 2001 From: Roger Lu Date: Thu, 2 Feb 2023 20:41:04 +0800 Subject: [PATCH 0657/1040] soc: mediatek: mtk-svs: add thermal voltage compensation if needed Some extreme test environment may keep IC temperature very low or very high during system boot stage. For stability concern, we add thermal voltage compenstation if needed no matter svs bank phase is in init02 or mon mode. Signed-off-by: Roger Lu Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230202124104.16504-4-roger.lu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-svs.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 8127fb6d587b..b9c96182a46a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -558,7 +558,7 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) } /* Get thermal effect */ - if (svsb->phase == SVSB_PHASE_MON) { + if (!IS_ERR_OR_NULL(svsb->tzd)) { ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp); if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND && svsb->temp < SVSB_TEMP_LOWER_BOUND)) { @@ -573,7 +573,8 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) temp_voffset += svsb->tzone_ltemp_voffset; /* 2-line bank update all opp volts when running mon mode */ - if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) { + if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH || + svsb->type == SVSB_LOW)) { opp_start = 0; opp_stop = svsb->opp_count; } @@ -589,11 +590,6 @@ static int svs_adjust_pm_opp_volts(struct svs_bank *svsb) /* do nothing */ goto unlock_mutex; case SVSB_PHASE_INIT02: - svsb_volt = max(svsb->volt[i], svsb->vmin); - opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, - svsb->volt_step, - svsb->volt_base); - break; case SVSB_PHASE_MON: svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin); opp_volt = svs_bank_volt_to_opp_volt(svsb_volt, @@ -1683,7 +1679,7 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) } } - if (svsb->mode_support & SVSB_MODE_MON) { + if (!IS_ERR_OR_NULL(svsb->tzone_name)) { svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name); if (IS_ERR(svsb->tzd)) { dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", @@ -2122,6 +2118,7 @@ static struct svs_bank svs_mt8192_banks[] = { .type = SVSB_LOW, .set_freq_pct = svs_set_bank_freq_pct_v3, .get_volts = svs_get_bank_volts_v3, + .tzone_name = "gpu1", .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT, .mode_support = SVSB_MODE_INIT02, .opp_count = MAX_OPP_ENTRIES, @@ -2139,6 +2136,10 @@ static struct svs_bank svs_mt8192_banks[] = { .core_sel = 0x0fff0100, .int_st = BIT(0), .ctl0 = 0x00540003, + .tzone_htemp = 85000, + .tzone_htemp_voffset = 0, + .tzone_ltemp = 25000, + .tzone_ltemp_voffset = 7, }, { .sw_id = SVSB_GPU, From 932d139e4db18d535dea271df51db5216b8787b3 Mon Sep 17 00:00:00 2001 From: Shreeya Patel Date: Wed, 29 Mar 2023 02:30:47 +0530 Subject: [PATCH 0658/1040] arm64: dts: rockchip: Enable watchdog support for RK3588 Add DT node for watchdog support in RK3588. Signed-off-by: Shreeya Patel Link: https://lore.kernel.org/r/20230328210048.195124-2-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index fca8503aed8c..4bd8697c6b48 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1241,6 +1241,14 @@ status = "disabled"; }; + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = ; + }; + spi0: spi@feb00000 { compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; reg = <0x0 0xfeb00000 0x0 0x1000>; From e1a234eb3d1507b942c25e5a5ae0d6fb9036f1ff Mon Sep 17 00:00:00 2001 From: Shreeya Patel Date: Wed, 29 Mar 2023 02:30:48 +0530 Subject: [PATCH 0659/1040] dt-bindings: watchdog: rockchip: Add rockchip,rk3588-wdt string Add rockchip,rk3588-wdt compatible string. Signed-off-by: Shreeya Patel Acked-by: Guenter Roeck Reviewed-by: Guenter Roeck Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230328210048.195124-3-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml index 92df6e453f64..e7a87ce94772 100644 --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml @@ -29,6 +29,7 @@ properties: - rockchip,rk3368-wdt - rockchip,rk3399-wdt - rockchip,rk3568-wdt + - rockchip,rk3588-wdt - rockchip,rv1108-wdt - const: snps,dw-wdt From 3e987e1f22b9b9fdb652a5f3f4aff24265c9af05 Mon Sep 17 00:00:00 2001 From: Martijn Braam Date: Tue, 28 Mar 2023 09:33:08 +0200 Subject: [PATCH 0660/1040] arm64: dts: rockchip: Add internal display support to rk3399-pinephone-pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The phone's display is using a Hannstar LCD panel. Support it by adding a panel DT node and all needed nodes (backlight, MIPI DSI, regulators, etc). Signed-off-by: Martijn Braam Co-developed-by: Kamil Trzciński Signed-off-by: Kamil Trzciński Co-developed-by: Ondrej Jirman Signed-off-by: Ondrej Jirman Signed-off-by: Javier Martinez Canillas Tested-by: Ondrej Jirman Link: https://lore.kernel.org/r/20230328073309.1743112-2-javierm@redhat.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-pinephone-pro.dts | 95 +++++++++++++++++++ 1 file changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index a0795a2b1cb1..539b36e8bff5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -29,6 +29,11 @@ stdout-path = "serial2:115200n8"; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 50000 0>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -102,6 +107,30 @@ /* WL_REG_ON on module */ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; }; + + /* MIPI DSI panel 1.8v supply */ + vcc1v8_lcd: vcc1v8-lcd { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc1v8_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + }; + + /* MIPI DSI panel 2.8v supply */ + vcc2v8_lcd: vcc2v8-lcd { + compatible = "regulator-fixed"; + enable-active-high; + regulator-name = "vcc2v8_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc3v3_sys>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + }; }; &cpu_alert0 { @@ -139,6 +168,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { clock-frequency = <400000>; i2c-scl-rising-time-ns = <168>; @@ -362,6 +396,39 @@ status = "okay"; }; +&mipi_dsi { + status = "okay"; + clock-master; + + ports { + mipi_out: port@1 { + #address-cells = <0>; + #size-cells = <0>; + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "hannstar,hsd060bhw4"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>; + vcc-supply = <&vcc2v8_lcd>; + iovcc-supply = <&vcc1v8_lcd>; + pinctrl-names = "default"; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + &pmu_io_domains { pmu1830-supply = <&vcc_1v8>; status = "okay"; @@ -429,6 +496,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-sd-highspeed; @@ -479,3 +550,27 @@ &uart2 { status = "okay"; }; + +&vopb { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>, + <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>, + <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + assigned-clock-rates = <0>, <0>, <400000000>, <100000000>; + assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>; +}; + +&vopl_mmu { + status = "okay"; +}; From 17a23ce930e35d5a84889441efd9208d0445bf18 Mon Sep 17 00:00:00 2001 From: Martijn Braam Date: Tue, 28 Mar 2023 09:33:09 +0200 Subject: [PATCH 0661/1040] arm64: dts: rockchip: Add touchscreen support to rk3399-pinephone-pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The phone has a Goodix GT1158 touchscreen, add a DT node for it. Signed-off-by: Martijn Braam Co-developed-by: Kamil Trzciński Signed-off-by: Kamil Trzciński Co-developed-by: Ondrej Jirman Signed-off-by: Ondrej Jirman Signed-off-by: Javier Martinez Canillas Link: https://lore.kernel.org/r/20230328073309.1743112-3-javierm@redhat.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-pinephone-pro.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 539b36e8bff5..475ba78acc09 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -367,6 +367,25 @@ }; }; +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + touchscreen@14 { + compatible = "goodix,gt1158"; + reg = <0x14>; + interrupt-parent = <&gpio3>; + interrupts = ; + irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc3v0_touch>; + VDDIO-supply = <&vcc3v0_touch>; + touchscreen-size-x = <720>; + touchscreen-size-y = <1440>; + }; +}; + &cluster0_opp { opp04 { status = "disabled"; From ceb2e18487c322f3becae0959d48ef12a829a2dc Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 25 Mar 2023 15:40:19 +0800 Subject: [PATCH 0662/1040] dt-bindings: Add doc for FriendlyARM NanoPi R2C Add devicetree binding documentation for the FriendlyARM NanoPi R2C. Signed-off-by: Tianling Shen Reviewed-by: Jagan Teki Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230325074022.9818-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 6f4270f2bd9e..883c9d36e4e5 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -185,9 +185,11 @@ properties: - const: firefly,rk3566-roc-pc - const: rockchip,rk3566 - - description: FriendlyElec NanoPi R2S + - description: FriendlyElec NanoPi R2 series boards items: - - const: friendlyarm,nanopi-r2s + - enum: + - friendlyarm,nanopi-r2c + - friendlyarm,nanopi-r2s - const: rockchip,rk3328 - description: FriendlyElec NanoPi4 series boards From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 25 Mar 2023 15:40:20 +0800 Subject: [PATCH 0663/1040] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC chip changed from rtl8211e to yt8521s, and otherwise identical to R2S. Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a315a8117b0f..0bdcddd221f8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts new file mode 100644 index 000000000000..a07a26b944a0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2021-2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3328-nanopi-r2s.dts" + +/ { + model = "FriendlyElec NanoPi R2C"; + compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; +}; + +&gmac2io { + phy-handle = <&yt8521s>; + tx_delay = <0x22>; + rx_delay = <0x12>; + + mdio { + /delete-node/ ethernet-phy@1; + + yt8521s: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + + motorcomm,clk-out-frequency-hz = <125000000>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; From 564cfdb866535662d74a6a1c5b5e7e99845d7e25 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 25 Mar 2023 15:40:21 +0800 Subject: [PATCH 0664/1040] dt-bindings: Add doc for Xunlong OrangePi R1 Plus LTS Add devicetree binding documentation for the Xunlong OrangePi R1 Plus LTS. Signed-off-by: Tianling Shen Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230325074022.9818-4-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 883c9d36e4e5..ec141c937b8b 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -831,9 +831,11 @@ properties: - const: tronsmart,orion-r68-meta - const: rockchip,rk3368 - - description: Xunlong Orange Pi R1 Plus + - description: Xunlong Orange Pi R1 Plus / LTS items: - - const: xunlong,orangepi-r1-plus + - enum: + - xunlong,orangepi-r1-plus + - xunlong,orangepi-r1-plus-lts - const: rockchip,rk3328 - description: Zkmagic A95X Z2 From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001 From: Tianling Shen Date: Sat, 25 Mar 2023 15:40:22 +0800 Subject: [PATCH 0665/1040] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise identical to OrangePi R1 Plus. Signed-off-by: Tianling Shen Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 0bdcddd221f8..2d585bbb8f3a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts new file mode 100644 index 000000000000..5d7d567283e5 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2016 Xunlong Software. Co., Ltd. + * (http://www.orangepi.org) + * + * Copyright (c) 2021-2023 Tianling Shen + */ + +/dts-v1/; +#include "rk3328-orangepi-r1-plus.dts" + +/ { + model = "Xunlong Orange Pi R1 Plus LTS"; + compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; +}; + +&gmac2io { + phy-handle = <&yt8531c>; + tx_delay = <0x19>; + rx_delay = <0x05>; + + mdio { + /delete-node/ ethernet-phy@1; + + yt8531c: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + + motorcomm,clk-out-frequency-hz = <125000000>; + motorcomm,keep-pll-enabled; + motorcomm,auto-sleep-disabled; + + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <15000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; From 1e135922f608572f216c959202d0ef303aa2a0c1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 17 Mar 2023 08:59:00 +0100 Subject: [PATCH 0666/1040] MAINTAINERS: renesas: Add "renesas," file contents pattern MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a keyword match pattern for the word "renesas," in files to the ARM/RISC-V/RENESAS ARCHITECTURE section. This make sure patches changing drivers that match against "renesas," (as used mostly for Renesas on-SoC components) are CCed to the linux-renesas-soc mailing list. Signed-off-by: Geert Uytterhoeven Acked-by: Wolfram Sang Acked-by: Niklas Söderlund Link: https://lore.kernel.org/r/c1be1e97c5457eade25b0eb5118196677cecfc08.1679039809.git.geert+renesas@glider.be --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..91496d20d997 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2654,6 +2654,7 @@ F: arch/arm64/boot/dts/renesas/ F: arch/riscv/boot/dts/renesas/ F: drivers/soc/renesas/ F: include/linux/soc/renesas/ +K: \brenesas, ARM/RISCPC ARCHITECTURE M: Russell King From 05d11e2f4460752fa5f7ce7657e1b040056c1736 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 15 Mar 2023 06:47:26 +0000 Subject: [PATCH 0667/1040] arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and RZ/Five DMAC nodes. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 ++ arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 ++ 3 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index a9700654b421..27c35a657b15 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -564,9 +564,11 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G043_DMAC_ARESETN>, <&cpg R9A07G043_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 79cffbf20c55..7b68bbebb5bd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -740,9 +740,11 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G044_DMAC_ARESETN>, <&cpg R9A07G044_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index c0ae9c7c10fc..cc11e5855d62 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -746,9 +746,11 @@ "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; + clock-names = "main", "register"; power-domains = <&cpg>; resets = <&cpg R9A07G054_DMAC_ARESETN>, <&cpg R9A07G054_DMAC_RST_ASYNC>; + reset-names = "arst", "rst_async"; #dma-cells = <1>; dma-channels = <16>; }; From f0545078e13973ca032cf131eb7580d86b78d147 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Mar 2023 17:30:05 +0100 Subject: [PATCH 0668/1040] dt-bindings: clock: r8a7779: Add PWM module clock Add the module clock used by the PWM Timers on the Renesas R-Car H1 (R8A7779) SoC. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/1397b517fccbe716a71cfae770512ed577730a25.1679329211.git.geert+renesas@glider.be --- include/dt-bindings/clock/r8a7779-clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/r8a7779-clock.h b/include/dt-bindings/clock/r8a7779-clock.h index f0549234b7d8..342a60b11934 100644 --- a/include/dt-bindings/clock/r8a7779-clock.h +++ b/include/dt-bindings/clock/r8a7779-clock.h @@ -19,6 +19,7 @@ #define R8A7779_CLK_OUT 7 /* MSTP 0 */ +#define R8A7779_CLK_PWM 5 #define R8A7779_CLK_HSPI 7 #define R8A7779_CLK_TMU2 14 #define R8A7779_CLK_TMU1 15 From 2114ab85f3fc8f833508d763a59459be8f2e9ad2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Mar 2023 17:30:06 +0100 Subject: [PATCH 0669/1040] ARM: dts: r8a7779: Add PWM support Add support for the 7 PWM channels provided by PWM Timers on R-Car H1, by describing the PWM Timers and their module clock. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/71622584db692f571d542ef2dcf088ce549aed3f.1679329211.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7779.dtsi | 91 +++++++++++++++++++++++++++++----- 1 file changed, 78 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 39fc58f32df6..97b767d81d92 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -324,6 +324,69 @@ status = "disabled"; }; + pwm0: pwm@ffe50000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe50000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@ffe51000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe51000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@ffe52000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe52000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@ffe53000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe53000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@ffe54000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe54000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@ffe55000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe55000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@ffe56000 { + compatible = "renesas,pwm-r8a7779", "renesas,pwm-rcar"; + reg = <0xffe56000 0x8>; + clocks = <&mstp0_clks R8A7779_CLK_PWM>; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #pwm-cells = <2>; + status = "disabled"; + }; + pfc: pinctrl@fffc0000 { compatible = "renesas,pfc-r8a7779"; reg = <0xfffc0000 0x23c>; @@ -554,7 +617,8 @@ compatible = "renesas,r8a7779-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0xffc80030 4>; - clocks = <&cpg_clocks R8A7779_CLK_S>, + clocks = <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_S>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, @@ -572,20 +636,21 @@ <&cpg_clocks R8A7779_CLK_P>; #clock-cells = <1>; clock-indices = < - R8A7779_CLK_HSPI R8A7779_CLK_TMU2 - R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 - R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 - R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 - R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 - R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 - R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 - R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 + R8A7779_CLK_PWM R8A7779_CLK_HSPI + R8A7779_CLK_TMU2 R8A7779_CLK_TMU1 + R8A7779_CLK_TMU0 R8A7779_CLK_HSCIF1 + R8A7779_CLK_HSCIF0 R8A7779_CLK_SCIF5 + R8A7779_CLK_SCIF4 R8A7779_CLK_SCIF3 + R8A7779_CLK_SCIF2 R8A7779_CLK_SCIF1 + R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 + R8A7779_CLK_I2C2 R8A7779_CLK_I2C1 + R8A7779_CLK_I2C0 >; clock-output-names = - "hspi", "tmu2", "tmu1", "tmu0", "hscif1", - "hscif0", "scif5", "scif4", "scif3", "scif2", - "scif1", "scif0", "i2c3", "i2c2", "i2c1", - "i2c0"; + "pwm", "hspi", "tmu2", "tmu1", "tmu0", + "hscif1", "hscif0", "scif5", "scif4", "scif3", + "scif2", "scif1", "scif0", "i2c3", "i2c2", + "i2c1", "i2c0"; }; mstp1_clks: clocks@ffc80034 { compatible = "renesas,r8a7779-mstp-clocks", From cab3511ea7a0b1fc0c664e654f948f7ebe4f9072 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Mar 2023 17:33:22 +0100 Subject: [PATCH 0670/1040] ARM: dts: marzen: Add slide switches Describe the four General Purpose Switches on the Marzen development board, so they can be used for user input and/or for wake-up from s2ram. The GPIO block on R-Car H1 does not support triggering interrupts on both edges of a changing input signal, hence one cannot use gpio-keys with gpios properties. Instead, one of two alternatives needs to be used: 1. Use gpio-keys with interrupts instead of gpios properties, at the expense of receiving only key presses (release events will be auto-generated), 2. Use gpio-keys-polled with gpios properties, at the expense of making these keys unusable as wake-up sources. As the DTS for the Marzen development board serves mainly as an example, the approach taken is to use the first alternative for the first two switches, and the second alternative for the last two switches. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/f834a3c397362f2424fcae6a0c0440356208b182.1679329829.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7779-marzen.dts | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 5f05f2b44a48..60c9c4b7faa1 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "r8a7779.dtsi" #include +#include #include / { @@ -66,6 +67,51 @@ vdd33a-supply = <&fixedregulator3v3>; }; + keyboard-irq { + compatible = "gpio-keys"; + + pinctrl-0 = <&keyboard_irq_pins>; + pinctrl-names = "default"; + + interrupt-parent = <&gpio0>; + + key-1 { + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW1-1"; + wakeup-source; + debounce-interval = <20>; + }; + key-2 { + interrupts = <18 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW1-2"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + keyboard-gpio { + compatible = "gpio-keys-polled"; + poll-interval = <50>; + + pinctrl-0 = <&keyboard_gpio_pins>; + pinctrl-names = "default"; + + key-3 { + gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW1-3"; + debounce-interval = <20>; + }; + key-4 { + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW1-4"; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; led2 { @@ -161,6 +207,14 @@ }; }; +&gpio0 { + keyboard-irq-hog { + gpio-hog; + gpios = <17 GPIO_ACTIVE_LOW>, <18 GPIO_ACTIVE_LOW>; + input; + }; +}; + &irqpin0 { status = "okay"; }; @@ -223,6 +277,15 @@ groups = "hspi0"; function = "hspi0"; }; + + keyboard_irq_pins: keyboard-irq { + pins = "GP_0_17", "GP_0_18"; + bias-pull-up; + }; + keyboard_gpio_pins: keyboard-gpio { + pins = "GP_0_19", "GP_0_20"; + bias-pull-up; + }; }; &sata { From 1b4d507e89136e60c6b1db4543cae5f8e20085ae Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Mar 2023 17:34:24 +0100 Subject: [PATCH 0671/1040] ARM: dts: marzen: Enable I2C support Enable the single I2C bus available on the Marzen development board. As this bus contains an AK4643 codec, it must be limited to 100 kHz. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/77b87378397fd26f39c73f68e3ea465db6d38fb1.1679330016.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7779-marzen.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 60c9c4b7faa1..fd40890bd77b 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -215,6 +215,12 @@ }; }; +&i2c0 { + status = "okay"; + + clock-frequency = <100000>; +}; + &irqpin0 { status = "okay"; }; From 82e6c62820d758c37eabb9b4bee157068ff6835d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Mar 2023 17:47:44 +0100 Subject: [PATCH 0672/1040] ARM: dts: r8a7790: Add TPU device node Add support for the 4 PWM channels provided by the 16-bit Timer Pulse Unit on R-Car H2, by adding a device node describing the TPU. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/75da1e63135a3fc8a3aaafbff7139bd5d7509be3.1679330727.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7790.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 2f2e483a2c2a..7211a5bb18a3 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -376,6 +376,17 @@ reg = <0 0xe6060000 0 0x250>; }; + tpu: pwm@e60f0000 { + compatible = "renesas,tpu-r8a7790", "renesas,tpu"; + reg = <0 0xe60f0000 0 0x148>; + interrupts = ; + clocks = <&cpg CPG_MOD 304>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 304>; + #pwm-cells = <3>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7790-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; From c21a1fc21727defdba1ad00e75c94bd497681dd3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 20 Mar 2023 17:49:27 +0100 Subject: [PATCH 0673/1040] ARM: dts: r8a7790: Add PWM device nodes Add support for the 7 PWM channels provided by PWM Timers on R-Car H2, by adding device nodes describing the PWM Timers. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/9755b3af4296060ee31c4652def639574cbbd2fb.1679330878.git.geert+renesas@glider.be --- arch/arm/boot/dts/r8a7790.dtsi | 70 ++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 7211a5bb18a3..46fb81f5062f 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1048,6 +1048,76 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + can0: can@e6e80000 { compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; From 52a3554bdf9dbaff42b42f0e0360f456890894d9 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 21 Mar 2023 11:47:53 +0000 Subject: [PATCH 0674/1040] arm64: dts: renesas: r9a07g044: Enable SCI0 using DT overlay Enable sci0 node using dt overlay and disable can{0,1}-stb-hog nodes in DT overlay as its pins are shared with sci0 pins. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230321114753.75038-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../dts/renesas/r9a07g043-smarc-pmod.dtso | 45 +++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 23b10c03091c..d1f10ae85f9f 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso b/arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso new file mode 100644 index 000000000000..4edd103c7711 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043-smarc-pmod.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the RZ/{G2UL, Five} SMARC EVK PMOD parts + * + * Copyright (C) 2023 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC EVK + * +----------------------------+ + * |CN7 (PMOD1 PIN HEADER) | + * | SCI0_TXD pin7 | + * | SCI0_RXD pin8 | + * | Gnd pin11 | + * | Vcc pin12 | + * +----------------------------+ + * + */ + +/dts-v1/; +/plugin/; + +#include + +&pinctrl { + can0-stb-hog { + status = "disabled"; + }; + + can1-stb-hog { + status = "disabled"; + }; + + sci0_pins: sci0-pins { + pinmux = , /* TxD */ + ; /* RxD */ + }; +}; + +&sci0 { + pinctrl-0 = <&sci0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From 95c91e77664866517a999abdb246ffb207882c30 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 22 Mar 2023 12:56:47 +0000 Subject: [PATCH 0675/1040] arm64: dts: renesas: r9a07g044: Add CSI and CRU nodes Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 79 ++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 7b68bbebb5bd..1315be5167b9 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -618,6 +618,85 @@ status = "disabled"; }; + cru: video@10830000 { + compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, + <&cpg CPG_MOD R9A07G044_CRU_PCLK>, + <&cpg CPG_MOD R9A07G044_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = , + , + ; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G044_CRU_PRESETN>, + <&cpg R9A07G044_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + cruparallel: endpoint@0 { + reg = <0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G044_CRU_VCLK>, + <&cpg CPG_MOD R9A07G044_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G044_CRU_PRESETN>, + <&cpg R9A07G044_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>; From 3d52973db7457362e54b5b62242671eee80b2c14 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 22 Mar 2023 12:56:48 +0000 Subject: [PATCH 0676/1040] arm64: dts: renesas: rzg2l-smarc: Enable CRU, CSI support Enable CRU, CSI on RZ/G2L SMARC EVK and tie the CSI to OV5645 sensor using Device Tree overlay. rz-smarc-cru-csi-ov5645.dtsi is created so that RZ/G2L alike EVKs can make use of it. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230322125648.24948-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../r9a07g044l2-smarc-cru-csi-ov5645.dtso | 21 +++++ .../dts/renesas/rz-smarc-cru-csi-ov5645.dtsi | 80 +++++++++++++++++++ 3 files changed, 102 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d1f10ae85f9f..f130165577a8 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso new file mode 100644 index 000000000000..d834bff9bda2 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc-cru-csi-ov5645.dtso @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G2L SMARC EVK with OV5645 camera + * connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +#define OV5645_PARENT_I2C i2c0 +#include "rz-smarc-cru-csi-ov5645.dtsi" + +&ov5645 { + enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>; + reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi new file mode 100644 index 000000000000..c5bb63c63b47 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rz-smarc-cru-csi-ov5645.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common Device Tree for the RZ/G2L SMARC EVK (and alike EVKs) with + * OV5645 camera connected to CSI and CRU enabled. + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +&{/} { + ov5645_vdddo_1v8: 1p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ov5645_vdda_2v8: 2p8v { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ov5645_vddd_1v5: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + ov5645_fixed_clk: osc25250-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&cru { + status = "okay"; +}; + +&csi2 { + status = "okay"; + + ports { + port@0 { + csi2_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&ov5645_ep>; + }; + }; + }; +}; + +&OV5645_PARENT_I2C { + #address-cells = <1>; + #size-cells = <0>; + + ov5645: camera@3c { + compatible = "ovti,ov5645"; + reg = <0x3c>; + clocks = <&ov5645_fixed_clk>; + clock-frequency = <24000000>; + vdddo-supply = <&ov5645_vdddo_1v8>; + vdda-supply = <&ov5645_vdda_2v8>; + vddd-supply = <&ov5645_vddd_1v5>; + + port { + ov5645_ep: endpoint { + clock-lanes = <0>; + data-lanes = <1 2>; + remote-endpoint = <&csi2_in>; + }; + }; + }; +}; From 38f250cf9615d762a4dc1179bb063c66762a76e6 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 16 Mar 2023 10:21:43 -0500 Subject: [PATCH 0677/1040] arm64: defconfig: Enable drivers for BeaglePlay Enable drivers used on BeaglePlay[1]: * MDIO_GPIO driver to workaround erratum i2329, DP83TD510 SPE phy (enabled in-kernel to ease usage) * TPS65219 PMIC, regulator as built-in for sd boot and power button as modules. (note: this is also used by am62x-lp-sk as well) * BQ32K battery backedup RTC and the K3 RTC drivers as modules * OMAP2 SPI driver as module for accessing mikrobus bloat-o-meter reports after this change (v6.3-rc1, clang 17.0.0): add/remove: 63/2 grow/shrink: 3/0 up/down: 17660/-16 (17644) [...] Total: Before=27747186, After=27764830, chg +0.06% [1] https://beagleplay.org Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230316152143.2438928-4-nm@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/configs/defconfig | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..8ba6aa0b9e7c 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -367,11 +367,13 @@ CONFIG_AT803X_PHY=y CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y +CONFIG_DP83TD510_PHY=y CONFIG_VITESSE_PHY=y CONFIG_CAN_FLEXCAN=m CONFIG_CAN_RCAR=m CONFIG_CAN_RCAR_CANFD=m CONFIG_CAN_MCP251XFD=m +CONFIG_MDIO_GPIO=y CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y CONFIG_MDIO_BUS_MUX_MMIOREG=y CONFIG_USB_PEGASUS=m @@ -418,6 +420,7 @@ CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_PM8XXX_VIBRATOR=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m CONFIG_INPUT_PWM_BEEPER=m CONFIG_INPUT_PWM_VIBRA=m CONFIG_INPUT_HISI_POWERKEY=y @@ -513,6 +516,7 @@ CONFIG_SPI_MESON_SPICC=m CONFIG_SPI_MESON_SPIFC=m CONFIG_SPI_MT65XX=y CONFIG_SPI_MTK_NOR=m +CONFIG_SPI_OMAP24XX=m CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y @@ -670,6 +674,7 @@ CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_RK808=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SL28CPLD=y +CONFIG_MFD_TPS65219=y CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_WCD934X=m CONFIG_REGULATOR_FIXED_VOLTAGE=y @@ -699,6 +704,7 @@ CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65219=y CONFIG_REGULATOR_VCTRL=m CONFIG_RC_CORE=m CONFIG_RC_DECODERS=y @@ -1026,6 +1032,7 @@ CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_RX8581=m CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV8803=m @@ -1045,6 +1052,7 @@ CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_MT6397=m CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_TI_K3=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m From 44b263bf040a8e819da11c45f14a80de8866461a Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 30 Mar 2023 15:14:07 +0530 Subject: [PATCH 0678/1040] arm64: defconfig: Enable audio drivers for AM62-SK TI's K3 platform uses McASP as the digital audio interface on the SoCs. AM62-SK, AM62-LP-SK and AM62A-SK also use the TLV320AIC3106 codec with a 3.5mm jack for analog audio input and output. Signed-off-by: Jai Luthra Reviewed-by: Devarsh Thakkar Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-3-94332149657a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 8ba6aa0b9e7c..f1fe5703cc4f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -877,6 +877,7 @@ CONFIG_SND_SOC_TEGRA210_AMX=m CONFIG_SND_SOC_TEGRA210_ADX=m CONFIG_SND_SOC_TEGRA210_MIXER=m CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m +CONFIG_SND_SOC_DAVINCI_MCASP=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m @@ -891,6 +892,7 @@ CONFIG_SND_SOC_SIMPLE_MUX=m CONFIG_SND_SOC_TAS2552=m CONFIG_SND_SOC_TAS571X=m CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m CONFIG_SND_SOC_WM8524=m From f5a731f0787fd63d81ab0e1457c44c65fa9d7b41 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Thu, 16 Mar 2023 10:21:42 -0500 Subject: [PATCH 0679/1040] arm64: dts: ti: Add k3-am625-beagleplay BeagleBoard.org BeaglePlay is an easy to use, affordable open source hardware single board computer based on the Texas Instruments AM625 SoC that allows you to create connected devices that work even at long distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L. Expansion is provided over open standards based mikroBUS, Grove and QWIIC headers among other interfaces. This board family can be identified by the 24c32 eeprom: [aa 55 33 ee 01 37 00 10 2e 00 42 45 41 47 4c 45 |.U3..7....BEAGLE|] [50 4c 41 59 2d 41 30 2d 00 00 30 32 30 30 37 38 |PLAY-A0-..020078|] https://beagleplay.org/ https://git.beagleboard.org/beagleplay/beagleplay Signed-off-by: Robert Nelson Reviewed-by: Andrew Davis Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230316152143.2438928-3-nm@ti.com Co-developed-by: Nishanth Menon Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + .../arm64/boot/dts/ti/k3-am625-beagleplay.dts | 758 ++++++++++++++++++ 2 files changed, 759 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 5312e4adc4e3..541970a8ed0a 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -9,6 +9,7 @@ # alphabetically. # Boards with AM62x SoC +dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts new file mode 100644 index 000000000000..cb46c38ce2cc --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -0,0 +1,758 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * https://beagleplay.org/ + * + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "beagle,am625-beagleplay", "ti,am625"; + model = "BeagleBoard.org BeaglePlay"; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + gpio2 = &mcu_gpio0; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + i2c2 = &main_i2c2; + i2c3 = &main_i2c3; + i2c4 = &wkup_i2c0; + i2c5 = &mcu_i2c0; + mdio-gpio0 = &mdio0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &rtc; + serial0 = &main_uart5; + serial1 = &main_uart6; + serial2 = &main_uart0; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops: ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9c700000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + vsys_5v0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v3: regulator-2 { + /* output of TLV62595DMQR-U12 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_5v0>; + regulator-always-on; + regulator-boot-on; + }; + + wlan_en: regulator-3 { + /* OUTPUT of SN74AVC2T244DQMR */ + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + vin-supply = <&vdd_3v3>; + gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pins_default>; + }; + + vdd_3v3_sd: regulator-4 { + /* output of TPS22918DBVR-U21 */ + pinctrl-names = "default"; + pinctrl-0 = <&vdd_3v3_sd_pins_default>; + + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + vin-supply = <&vdd_3v3>; + gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-5 { + compatible = "regulator-gpio"; + regulator-name = "sd_hs200_switch"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1_reg>; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + + led-1 { + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + function = LED_FUNCTION_DISK_ACTIVITY; + default-state = "keep"; + }; + + led-2 { + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_CPU; + }; + + led-3 { + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_LAN; + }; + + led-4 { + gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_WLAN; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&usr_button_pins_default>; + + usr: button-usr { + label = "User Key"; + linux,code = ; + gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>; + }; + + }; + + /* Workaround for errata i2329 - just use mdio bitbang */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_pins_default>; + gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ + <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ + #address-cells = <1>; + #size-cells = <0>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <25>; + reset-deassert-us = <60000>; /* T2 */ + }; + }; +}; + +&main_pmx0 { + gpio0_pins_default: gpio0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ + AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ + AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */ + AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */ + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ + AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */ + AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */ + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + usr_button_pins_default: usr-button-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ + >; + }; + + grove_pins_default: grove-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + local_i2c_pins_default: local-i2c-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + i2c2_1v8_pins_default: i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + mdio0_pins_default: mdio0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ + AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ + >; + }; + + rgmii1_pins_default: rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + emmc_pins_default: emmc-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + vdd_3v3_sd_pins_default: vdd-3v3-sd-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ + >; + }; + + sd_pins_default: sd-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ + >; + }; + + wifi_pins_default: wifi-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ + AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ + AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ + AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ + AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ + AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ + AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + wifi_en_pins_default: wifi-en-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ + >; + }; + + wifi_wlirq_pins_default: wifi-wlirq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ + >; + }; + + spe_pins_default: spe-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ + AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ + AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */ + AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */ + AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */ + AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ + AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ + AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ + AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ + AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ + AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ + >; + }; + + mikrobus_i2c_pins_default: mikrobus-i2c-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ + AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ + >; + }; + + mikrobus_uart_pins_default: mikrobus-uart-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ + >; + }; + + mikrobus_spi_pins_default: mikrobus-spi-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ + AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ + AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */ + AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ + >; + }; + + mikrobus_gpio_pins_default: mikrobus-gpio-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ + AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + console_pins_default: console-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + wifi_debug_uart_pins_default: wifi-debug-uart-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ + AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ + >; + }; + + usb1_pins_default: usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&mcu_pmx0 { + i2c_qwiic_pins_default: i2c-qwiic-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ + >; + }; + + gbe_pmx_obsclk: gbe-pmx-clk-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ + >; + }; + + i2c_csi_pins_default: i2c-csi-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ + AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ + >; + }; + + wifi_32k_clk: mcu-clk-out-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ + >; + }; +}; + +&a53_opp_table { + /* Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + }; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_csi_pins_default>; + clock-frequency = <400000>; + /* Enable with overlay for camera sensor */ +}; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_qwiic_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins_default>; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>, + <&gbe_pmx_obsclk>; + assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rmii"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + /* Workaround for errata i2329 - Use mdio bitbang */ + status = "disabled"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_pins_default>; + gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */ + "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ + "EEPROM_WP", /* 10 */ + "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ + "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ + "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ + "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ + "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */ + "", "", "", "", "", "", /* 79-84 */ + "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */ + "", "", "", "", ""; /* 87-91 */ +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_gpio_pins_default>; + gpio-line-names = "", "", "", "", "", /* 0-4 */ + "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */ + "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */ + "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */ + "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */ + "MIKROBUS_GPIO1_14", /* 14 */ + "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */ + "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */ + "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */ + "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */ + "", "", "", "", "", "", "", "", "", "", /* 38-47 */ + "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */ +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&local_i2c_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + + rtc: rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + interrupt-parent = <&main_gpio0>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + }; + + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vsys_5v0>; + buck2-supply = <&vsys_5v0>; + buck3-supply = <&vsys_5v0>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vdd_3v3>; + ldo4-supply = <&vdd_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + system-power-controller; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* + * Regulator is left as is unused, vdd_sd + * is controlled via GPIO with bypass config + * as per the NVM configuration + */ + regulator-name = "VDD_SD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDA_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&grove_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_1v8_pins_default>; + clock-frequency = <100000>; + status = "okay"; +}; + +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_i2c_pins_default>; + clock-frequency = <400000>; + status = "okay"; +}; + +&main_spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_spi_pins_default>; + status = "okay"; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + status = "okay"; +}; + +&sdhci1 { + /* SD/MMC */ + pinctrl-names = "default"; + pinctrl-0 = <&sd_pins_default>; + + vmmc-supply = <&vdd_3v3_sd>; + vqmmc-supply = <&vdd_sd_dv>; + ti,driver-strength-ohm = <50>; + disable-wp; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms = <100>; + ti,fails-without-test-cd; + status = "okay"; +}; + +&sdhci2 { + vmmc-supply = <&wlan_en>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; + bus-width = <4>; + non-removable; + ti,fails-without-test-cd; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + assigned-clocks = <&k3_clks 157 158>; + assigned-clock-parents = <&k3_clks 157 160>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wlcore: wlcore@2 { + compatible = "ti,wl1807"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wlirq_pins_default>; + interrupt-parent = <&main_gpio0>; + interrupts = <41 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&console_pins_default>; + status = "okay"; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&mikrobus_uart_pins_default>; + status = "okay"; +}; + +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_debug_uart_pins_default>; + status = "okay"; +}; From fee4f08db8ae40114cf729ebd022fc43df55f68b Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Wed, 15 Mar 2023 17:39:34 +0530 Subject: [PATCH 0680/1040] arm64: dts: ti: k3-am68-sk-base-board: Update IO EXP GPIO lines for Rev E2 Rev E2 of the AM68 SK baseboard has updated the GPIO IO expander pins functionality. To match the Rev E2 schematics, update existing IO expander GPIO line names and the corresponding node which uses the expansion(exp1) node. Signed-off-by: Sinthu Raja Link: https://lore.kernel.org/r/20230315120934.16954-1-sinthu.raja@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 2091cd2431fb..27a43a8ecffd 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -60,7 +60,7 @@ regulator-boot-on; enable-active-high; vin-supply = <&vsys_3v3>; - gpio = <&exp1 10 GPIO_ACTIVE_HIGH>; + gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; }; vdd_sd_dv: regulator-tlv71033 { @@ -264,12 +264,10 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; - gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", "HDMI_PDn", - "HDMI_LS_OE", "DP0_3V3 _EN", "BOARDID_EEPROM_WP", - "CAN_STB", " ", "GPIO_uSD_PWR_EN", "eDP_ENABLE", - "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_MCU_RGMII_RSTz", - "IO_EXP_CSI2_EXP_RSTz", " ", "CSI0_B_GPIO1", - "CSI1_B_GPIO1"; + gpio-line-names = " ", " ", " ", " ", " ", + "BOARDID_EEPROM_WP", "CAN_STB", " ", + "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", + "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; }; }; From 4b71618cb772f20dfeeba826e9d1713a04f9687f Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Tue, 28 Mar 2023 15:43:14 +0300 Subject: [PATCH 0681/1040] arm64: dts: ti: k3-am625-sk: Add ti,vbus-divider property to usbss1 The property "ti,vbus-divider" is needed for both usbss0 and usbss1 as both USB0 and USB1 have the same external voltage divider circuit. Fixes: 2d94dfc43885 ("arm64: dts: ti: k3-am625-sk: Add support for USB") Signed-off-by: Dhruva Gole Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20230328124315.123778-2-rogerq@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 6bc7d63cf52f..4d5dec890ad6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -480,6 +480,7 @@ &usbss1 { status = "okay"; + ti,vbus-divider; }; &usb0 { From 3bc4f501be71766e5988d8233fc29196f552b9b0 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 22 Mar 2023 18:09:20 +0530 Subject: [PATCH 0682/1040] dt-bindings: arm: ti: k3: Add compatible for AM62x LP SK Add compatible for AM62x SoC based Low Power Starter Kit board[1] [1] https://www.ti.com/tool/SK-AM62-LP Signed-off-by: Vignesh Raghavendra Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-1-0a56e1694804@ti.com Signed-off-by: Nishanth Menon --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index b4703ac88f04..e1183f90bb06 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -30,6 +30,7 @@ properties: - enum: - beagle,am625-beagleplay - ti,am625-sk + - ti,am62-lp-sk - const: ti,am625 - description: K3 AM642 SoC From a841581451af7beaf4c77b0c48ae3dd3205ab3bc Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Wed, 22 Mar 2023 18:09:21 +0530 Subject: [PATCH 0683/1040] arm64: dts: ti: Refractor AM625 SK dts To prepare for upcoming derivative boards based on the AM625 SK, refactor the dts file for this board into a common dtsi file that the derivative boards will inherit and retain only those parts that are different in the current dts file. Signed-off-by: Anand Gadiyar Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-2-0a56e1694804@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 238 +-------------- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 275 ++++++++++++++++++ 2 files changed, 276 insertions(+), 237 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 4d5dec890ad6..cdc0858dd1b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -7,32 +7,12 @@ /dts-v1/; -#include -#include -#include -#include "k3-am625.dtsi" +#include "k3-am62x-sk-common.dtsi" / { compatible = "ti,am625-sk", "ti,am625"; model = "Texas Instruments AM625 SK"; - aliases { - serial2 = &main_uart0; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - spi0 = &ospi0; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - usb0 = &usb0; - usb1 = &usb1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; - }; - opp-table { /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ opp-1400000000 { @@ -49,39 +29,6 @@ }; - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ramoops@9ca00000 { - compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; - record-size = <0x8000>; - console-size = <0x8000>; - ftrace-size = <0x00>; - pmsg-size = <0x8000>; - }; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - alignment = <0x1000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - alignment = <0x1000>; - no-map; - }; - - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; - }; - vmain_pd: regulator-0 { /* TPS65988 PD CONTROLLER OUTPUT */ compatible = "regulator-fixed"; @@ -140,108 +87,9 @@ states = <1800000 0x0>, <3300000 0x1>; }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&usr_led_pins_default>; - - led-0 { - label = "am62-sk:green:heartbeat"; - gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - function = LED_FUNCTION_HEARTBEAT; - default-state = "off"; - }; - }; }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ - >; - }; - - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ - AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ - >; - }; - - main_i2c1_pins_default: main-i2c1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ - AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ - >; - }; - - main_i2c2_pins_default: main-i2c2-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ - AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ - >; - }; - - main_mmc0_pins_default: main-mmc0-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ - >; - }; - - main_mmc1_pins_default: main-mmc1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ - AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ - AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ - AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ - AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ - AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ - AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ - >; - }; - - usr_led_pins_default: usr-led-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ - >; - }; - - main_mdio1_pins_default: main-mdio1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ - AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ - >; - }; - - main_rgmii1_pins_default: main-rgmii1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ - AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ - AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ - AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ - AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ - AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ - AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ - AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ - AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ - AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ - AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ - AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ - >; - }; - main_rgmii2_pins_default: main-rgmii2-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ @@ -286,43 +134,9 @@ AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; }; - - main_usb1_pins_default: main-usb1-pins-default { - pinctrl-single,pins = < - AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ - >; - }; -}; - -&wkup_uart0 { - /* WKUP UART0 is used by DM firmware */ - status = "reserved"; -}; - -&main_uart0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_uart0_pins_default>; -}; - -&main_uart1 { - /* Main UART1 is used by TIFS firmware */ - status = "reserved"; -}; - -&main_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c0_pins_default>; - clock-frequency = <400000>; }; &main_i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; - exp1: gpio@22 { compatible = "ti,tca6424"; reg = <0x22>; @@ -351,23 +165,9 @@ }; }; -&sdhci0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc0_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; -}; - &sdhci1 { - /* SD/MMC */ - status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv>; - pinctrl-names = "default"; - pinctrl-0 = <&main_mmc1_pins_default>; - ti,driver-strength-ohm = <50>; - disable-wp; }; &cpsw3g { @@ -376,28 +176,12 @@ &main_rgmii2_pins_default>; }; -&cpsw_port1 { - phy-mode = "rgmii-rxid"; - phy-handle = <&cpsw3g_phy0>; -}; - &cpsw_port2 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; }; &cpsw3g_mdio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&main_mdio1_pins_default>; - - cpsw3g_phy0: ethernet-phy@0 { - reg = <0>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; - ti,min-output-impedance; - }; - cpsw3g_phy1: ethernet-phy@1 { reg = <1>; ti,rx-internal-delay = ; @@ -472,23 +256,3 @@ }; }; }; - -&usbss0 { - status = "okay"; - ti,vbus-divider; -}; - -&usbss1 { - status = "okay"; - ti,vbus-divider; -}; - -&usb0 { - dr_mode = "peripheral"; -}; - -&usb1 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&main_usb1_pins_default>; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi new file mode 100644 index 000000000000..80e8b9b9a5f5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for AM62x SK and derivatives + * + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include "k3-am625.dtsi" + +/ { + aliases { + serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; +}; + +&main_pmx0 { + /* First pad number is ALW package and second is AMC package */ + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ + >; + }; + + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ + >; + }; + + main_usb1_pins_default: main-usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&main_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&sdhci0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&sdhci1 { + /* SD/MMC */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw3g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usbss1 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; From e6a51ffabfc16b1df9607e674ddf377673627513 Mon Sep 17 00:00:00 2001 From: Anand Gadiyar Date: Wed, 22 Mar 2023 18:09:22 +0530 Subject: [PATCH 0684/1040] arm64: ti: dts: Add support for AM62x LP SK The AM62x LP SK board is similar to the AM62x SK board, but has some not-so-minor changes that requires different device tree. The differences are mainly: - AM62x SoC in the AMC package that meets AECQ100 automotive standard. - LPDDR4 versus DDR4 on the AM62x SK. - TPS65219 PMIC instead of discrete regulators. - IO expander pin names are wired differently. - Second ethernet port is currently disabled as the boards do not have the part physically installed. - OSPI NAND vs OSPI NOR. - No WLAN chip instead a SDIO M.2 connector. Signed-off-by: Anand Gadiyar [vigneshr@ti.com: Add PMIC node] Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20230321-am62-lp-sk-v2-3-0a56e1694804@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/Makefile | 1 + arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 227 +++++++++++++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 541970a8ed0a..c83c9d772b81 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -11,6 +11,7 @@ # Boards with AM62x SoC dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts new file mode 100644 index 000000000000..b2ca19e3042e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP + * + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62x-sk-common.dtsi" + +/ { + compatible = "ti,am62-lp-sk", "ti,am625"; + model = "Texas Instruments AM62x LP SK"; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of TPS630702RNMR */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vddshv_sdio: regulator-4 { + compatible = "regulator-gpio"; + regulator-name = "vddshv_sdio"; + pinctrl-names = "default"; + pinctrl-0 = <&vddshv_sdio_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&ldo1_reg>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; +}; + +&main_pmx0 { + vddshv_sdio_pins_default: vddshv-sdio-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */ + >; + }; +}; + +&main_i2c1 { + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", + "GPIO_HDMI_RSTn", "CSI_GPIO0", + "CSI_GPIO1", "GPIO_OLDI_INT", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; + + exp2: gpio@23 { + compatible = "ti,tca6424"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "", "", + "", "", + "", "", + "", "", + "WL_LT_EN", "CSI_RSTz", + "", "", + "", "", + "", "", + "SPI0_FET_SEL", "SPI0_FET_OE", + "GPIO_OLDI_RSTn", "PRU_3V3_EN", + "", "", + "CSI_VLDO_SEL", "SOC_WLAN_SDIO_RST"; + }; +}; + +&sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&main_i2c0 { + tps65219: pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_3v3_sys>; + buck2-supply = <&vcc_3v3_sys>; + buck3-supply = <&vcc_3v3_sys>; + ldo1-supply = <&vcc_3v3_sys>; + ldo2-supply = <&buck2_reg>; + ldo3-supply = <&vcc_3v3_sys>; + ldo4-supply = <&vcc_3v3_sys>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + + interrupt-parent = <&gic500>; + interrupts = ; + ti,power-button; + + regulators { + buck1_reg: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + buck2_reg: buck2 { + regulator-name = "VCC1V8_SYS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck3_reg: buck3 { + regulator-name = "VDD_LPDDR4"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-name = "VDDSHV_SDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2_reg: ldo2 { + regulator-name = "VDDAR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: ldo4 { + regulator-name = "VDD_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; From 76aa309f9fa7e8c9b25234e1d1641d0b05e43e52 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 21 Mar 2023 13:58:24 +0530 Subject: [PATCH 0685/1040] arm64: dts: ti: k3-j721e: Add MCSPI nodes J721E has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Co-developed-by: Keerthy Signed-off-by: Keerthy Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra Link: https://lore.kernel.org/r/20230321082827.14274-2-vaishnav.a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 42eb6ed4b195..10c8a5fb4ee2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2444,4 +2444,92 @@ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 266 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 267 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 268 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 269 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 270 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 271 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 272 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 273 1>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 8ac78034d5d6..24e8125db8c4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -425,4 +425,37 @@ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 274 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 275 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 0>; + status = "disabled"; + }; }; From 8f6c475f4ca7a82d5203e20d33a6bb522902b44c Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 21 Mar 2023 13:58:25 +0530 Subject: [PATCH 0686/1040] arm64: dts: ti: k3-j7200: Add MCSPI nodes J7200 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath Reviewed-by: Keerthy Link: https://lore.kernel.org/r/20230321082827.14274-3-vaishnav.a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index abad0cb441ad..ef352e32f19d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -865,6 +865,94 @@ clock-names = "gpio"; }; + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 266 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 267 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 268 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 269 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 270 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 271 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 272 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 273 1>; + status = "disabled"; + }; + watchdog0: watchdog@2200000 { compatible = "ti,j7-rti-wdt"; reg = <0x0 0x2200000 0x0 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index de56a0165bd0..331b4e482e41 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -305,6 +305,39 @@ status = "disabled"; }; + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 274 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 275 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 0>; + status = "disabled"; + }; + fss: syscon@47000000 { compatible = "syscon", "simple-mfd"; reg = <0x00 0x47000000 0x00 0x100>; From 04d7cb647b8527398e292c0b6960980de5359d09 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 21 Mar 2023 13:58:26 +0530 Subject: [PATCH 0687/1040] arm64: dts: ti: k3-j721s2: Add MCSPI nodes J721S2 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath Reviewed-by: Keerthy Link: https://lore.kernel.org/r/20230321082827.14274-4-vaishnav.a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 8915132efcc1..2dd7865f7654 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1014,4 +1014,92 @@ bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; status = "disabled"; }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 339 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 340 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 341 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 342 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 343 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 344 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 345 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 346 1>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 5da5f0cf7009..a353705a7463 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -203,6 +203,39 @@ status = "disabled"; }; + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 347 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 348 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 349 0>; + status = "disabled"; + }; + mcu_navss: bus@28380000{ compatible = "simple-mfd"; #address-cells = <2>; From e23d5a3d116dce2152c56ee55d802630c92636bc Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Tue, 21 Mar 2023 13:58:27 +0530 Subject: [PATCH 0688/1040] arm64: dts: ti: k3-j784s4: Add MCSPI nodes J784S4 has 8 MCSPI instances in the main domain and 3 instances in the MCU domain. Add the DT nodes for all the 11 instances and keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2 by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out externally. Signed-off-by: Vaishnav Achath Reviewed-by: Keerthy Link: https://lore.kernel.org/r/20230321082827.14274-5-vaishnav.a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 88 +++++++++++++++++++ .../boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 33 +++++++ 2 files changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 8c1474a7bd0f..e9169eb358c1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1024,4 +1024,92 @@ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; status = "disabled"; }; + + main_spi0: spi@2100000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 376 1>; + status = "disabled"; + }; + + main_spi1: spi@2110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 377 1>; + status = "disabled"; + }; + + main_spi2: spi@2120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 378 1>; + status = "disabled"; + }; + + main_spi3: spi@2130000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02130000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 379 1>; + status = "disabled"; + }; + + main_spi4: spi@2140000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02140000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 380 1>; + status = "disabled"; + }; + + main_spi5: spi@2150000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02150000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 381 1>; + status = "disabled"; + }; + + main_spi6: spi@2160000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02160000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 382 1>; + status = "disabled"; + }; + + main_spi7: spi@2170000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x02170000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 383 1>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 64bd3dee14aa..f04fcb614cbe 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -204,6 +204,39 @@ status = "disabled"; }; + mcu_spi0: spi@40300000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040300000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 384 0>; + status = "disabled"; + }; + + mcu_spi1: spi@40310000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040310000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 385 0>; + status = "disabled"; + }; + + mcu_spi2: spi@40320000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x040320000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 386 0>; + status = "disabled"; + }; + mcu_navss: bus@28380000{ compatible = "simple-bus"; #address-cells = <2>; From d4b0379af83b67ef85bf90639cd38eb910dc507d Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Thu, 30 Mar 2023 15:14:05 +0530 Subject: [PATCH 0689/1040] arm64: dts: ti: k3-am62-main: Add McASP nodes Add the nodes for McASP 0-2. Use the audio-friendly 96MHz main_1_hsdivout6_clk as clock parent instead of the default 100Mhz main_2_hsdivout8_clk source. Signed-off-by: Jayesh Choudhary Signed-off-by: Jai Luthra Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-1-94332149657a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 16e14863d7df..b3e4857bbbe4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -832,4 +832,64 @@ clock-names = "tbclk", "fck"; status = "disabled"; }; + + mcasp0: audio-controller@2b00000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b00000 0x00 0x2000>, + <0x00 0x02b08000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 190 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 190 0>; + assigned-clock-parents = <&k3_clks 190 2>; + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp1: audio-controller@2b10000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b10000 0x00 0x2000>, + <0x00 0x02b18000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 191 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 191 0>; + assigned-clock-parents = <&k3_clks 191 2>; + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + mcasp2: audio-controller@2b20000 { + compatible = "ti,am33xx-mcasp-audio"; + reg = <0x00 0x02b20000 0x00 0x2000>, + <0x00 0x02b28000 0x00 0x400>; + reg-names = "mpu", "dat"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; + dma-names = "tx", "rx"; + + clocks = <&k3_clks 192 0>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 192 0>; + assigned-clock-parents = <&k3_clks 192 2>; + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; }; From b94b43715e91646a7023e5837941a514c9e2f934 Mon Sep 17 00:00:00 2001 From: Jai Luthra Date: Thu, 30 Mar 2023 15:14:06 +0530 Subject: [PATCH 0690/1040] arm64: dts: ti: Enable audio on SK-AM62(-LP) Add nodes for audio codec and sound card, enable the audio serializer (McASP1) under use from SK-AM62 E2 [1] onwards and update pinmux. Keep all audio related nodes in the common dtsi as they are exactly the same between SK-AM62 and SK-AM62-LP [2]. Link: https://www.ti.com/lit/zip/sprr448 [1] Link: https://www.ti.com/lit/zip/sprr471 [2] Signed-off-by: Jai Luthra Reviewed-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20230313-mcasp_upstream-v10-2-94332149657a@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 + arch/arm64/boot/dts/ti/k3-am625-sk.dts | 15 ++++ .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 76 +++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index b2ca19e3042e..4b94f7a86316 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -225,3 +225,7 @@ }; }; }; + +&tlv320aic3106 { + DVDD-supply = <&buck2_reg>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index cdc0858dd1b2..2a1adda9bff6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -87,6 +87,17 @@ states = <1800000 0x0>, <3300000 0x1>; }; + + vcc_1v8: regulator-5 { + /* output of TPS6282518DMQ */ + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_sys>; + regulator-always-on; + regulator-boot-on; + }; }; &main_pmx0 { @@ -256,3 +267,7 @@ }; }; }; + +&tlv320aic3106 { + DVDD-supply = <&vcc_1v8>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 80e8b9b9a5f5..976f8303c84f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -81,6 +81,41 @@ default-state = "off"; }; }; + + tlv320_mclk: clk-0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12288000>; + }; + + codec_audio: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-SKEVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line In", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound_master>; + simple-audio-card,frame-master = <&sound_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp1>; + }; + + sound_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&tlv320_mclk>; + }; + }; }; &main_pmx0 { @@ -175,6 +210,15 @@ AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; + + main_mcasp1_pins_default: main-mcasp1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + >; + }; }; &wkup_uart0 { @@ -205,6 +249,18 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + + tlv320aic3106: audio-codec@1b { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x1b>; + ai3x-micbias-vg = <1>; /* 2.0V */ + + /* Regulators */ + AVDD-supply = <&vcc_3v3_sys>; + IOVDD-supply = <&vcc_3v3_sys>; + DRVDD-supply = <&vcc_3v3_sys>; + }; }; &sdhci0 { @@ -273,3 +329,23 @@ pinctrl-names = "default"; pinctrl-0 = <&main_usb1_pins_default>; }; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_mcasp1_pins_default>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; From dbf17e13f04ac04ef8d70158b002fd53f07ccc88 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Tue, 28 Mar 2023 11:04:47 +0200 Subject: [PATCH 0691/1040] arm64: dts: mediatek: add i2c support for mt8365 SoC There are four I2C master channels in MT8365 with a same HW architecture. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20221122-mt8365-i2c-support-v6-1-e1009c8afd53@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 48 ++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 351197c453c9..ff3154627914 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -282,6 +282,42 @@ clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi: spi@1100a000 { compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; reg = <0 0x1100a000 0 0x100>; @@ -295,6 +331,18 @@ status = "disabled"; }; + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ssusb: usb@11201000 { compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; From 988eff6543618d2cfd4690c30bfce68b69b88424 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Tue, 28 Mar 2023 11:04:48 +0200 Subject: [PATCH 0692/1040] arm64: dts: mediatek: enable i2c0 for mt8365-evk board Enable the I2C0 bus provides communication with: - The integrated RT9466 Switching Battery Charger. - The integrated MT6691 LP4X buck for VDDQ. - The integrated MT6691 LP4X buck for VDD2. - The pin header, to plug external I2C devices. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221122-mt8365-i2c-support-v6-2-e1009c8afd53@baylibre.com [mb: move bias-pull-up below pinmux] Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 4683704ea235..efbbdd0c74ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -87,6 +87,13 @@ }; }; +&i2c0 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pio { gpio_keys: gpio-keys-pins { pins { @@ -96,6 +103,14 @@ }; }; + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = , From 2d98d0d2d53720a365e0c1a2984215815337607c Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Wed, 29 Mar 2023 10:54:24 +0200 Subject: [PATCH 0693/1040] arm64: dts: mediatek: Increase the size BL31 reserved memory The reserved size for BL31 is too small. This has been highlighted by the MPU that now restrict access to BL31 memory to secure world only. This increase the size of the reserved memory. Signed-off-by: Alexandre Bailon Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-3-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index efbbdd0c74ae..ceb48eb1a6e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -65,10 +65,10 @@ #size-cells = <2>; ranges; - /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ bl31_secmon_reserved: secmon@43000000 { no-map; - reg = <0 0x43000000 0 0x20000>; + reg = <0 0x43000000 0 0x30000>; }; /* 12 MiB reserved for OP-TEE (BL32) From 55749bb478f8ea6e72c376f332e0bc01bdd9af15 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 29 Mar 2023 10:54:26 +0200 Subject: [PATCH 0694/1040] arm64: dts: mediatek: add mt6357 device-tree This new device-tree add the regulators, rtc and keys support for the MT6357 PMIC. Signed-off-by: Fabien Parent Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-5-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6357.dtsi | 282 +++++++++++++++++++++++ 1 file changed, 282 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6357.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6357.dtsi b/arch/arm64/boot/dts/mediatek/mt6357.dtsi new file mode 100644 index 000000000000..3330a03c2f74 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6357.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2023 BayLibre Inc. + */ + +#include + +&pwrap { + mt6357_pmic: pmic { + compatible = "mediatek,mt6357"; + + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name = "vproc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vcore_reg: buck-vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vmodem_reg: buck-vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <220>; + }; + + mt6357_vs1_reg: buck-vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2200000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <220>; + regulator-always-on; + }; + + mt6357_vpa_reg: buck-vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-ramp-delay = <50000>; + regulator-enable-ramp-delay = <220>; + }; + + mt6357_vfe28_reg: ldo-vfe28 { + compatible = "regulator-fixed"; + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vxo22_reg: ldo-vxo22 { + regulator-name = "vxo22"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2400000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vrf18_reg: ldo-vrf18 { + compatible = "regulator-fixed"; + regulator-name = "vrf18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vrf12_reg: ldo-vrf12 { + compatible = "regulator-fixed"; + regulator-name = "vrf12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <110>; + }; + + mt6357_vefuse_reg: ldo-vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn33_bt_reg: ldo-vcn33-bt { + regulator-name = "vcn33-bt"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn33_wifi_reg: ldo-vcn33-wifi { + regulator-name = "vcn33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn28_reg: ldo-vcn28 { + compatible = "regulator-fixed"; + regulator-name = "vcn28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcn18_reg: ldo-vcn18 { + compatible = "regulator-fixed"; + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcama_reg: ldo-vcama { + regulator-name = "vcama"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcamd_reg: ldo-vcamd { + regulator-name = "vcamd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vcamio_reg: ldo-vcamio18 { + compatible = "regulator-fixed"; + regulator-name = "vcamio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vldo28_reg: ldo-vldo28 { + regulator-name = "vldo28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vsram_others_reg: ldo-vsram-others { + regulator-name = "vsram-others"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + + mt6357_vsram_proc_reg: ldo-vsram-proc { + regulator-name = "vsram-proc"; + regulator-min-microvolt = <518750>; + regulator-max-microvolt = <1312500>; + regulator-ramp-delay = <6250>; + regulator-enable-ramp-delay = <110>; + regulator-always-on; + }; + + mt6357_vaux18_reg: ldo-vaux18 { + compatible = "regulator-fixed"; + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vaud28_reg: ldo-vaud28 { + compatible = "regulator-fixed"; + regulator-name = "vaud28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vio28_reg: ldo-vio28 { + compatible = "regulator-fixed"; + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vio18_reg: ldo-vio18 { + compatible = "regulator-fixed"; + regulator-name = "vio18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <264>; + regulator-always-on; + }; + + mt6357_vdram_reg: ldo-vdram { + regulator-name = "vdram"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <3300>; + }; + + mt6357_vmc_reg: ldo-vmc { + regulator-name = "vmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vmch_reg: ldo-vmch { + regulator-name = "vmch"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vemc_reg: ldo-vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + regulator-always-on; + }; + + mt6357_vsim1_reg: ldo-vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vsim2_reg: ldo-vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + + mt6357_vibr_reg: ldo-vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <44>; + }; + + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name = "vusb33"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <264>; + }; + }; + + rtc { + compatible = "mediatek,mt6357-rtc"; + }; + + keys { + compatible = "mediatek,mt6357-keys"; + + key-power { + linux,keycodes = ; + wakeup-source; + }; + + key-home { + linux,keycodes = ; + wakeup-source; + }; + + }; + }; +}; From a00d1c915df3db5e8f2ea8e06a1a63245fc5b861 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Wed, 29 Mar 2023 10:54:27 +0200 Subject: [PATCH 0695/1040] arm64: dts: mediatek: add pwrap support to mt8365 SoC In order to use the PMIC, the pwrap support should be added to allow communication between the SoC and the PMIC. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-6-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index ff3154627914..713c5609457f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -179,6 +179,18 @@ #clock-cells = <1>; }; + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8365-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWRAP_SPI>, + <&infracfg CLK_IFR_PMIC_AP>, + <&infracfg CLK_IFR_PWRAP_SYS>, + <&infracfg CLK_IFR_PWRAP_TMR>; + clock-names = "spi", "wrap", "sys", "tmr"; + }; + keypad: keypad@10010000 { compatible = "mediatek,mt6779-keypad"; reg = <0 0x10010000 0 0x1000>; From 8b5db516c9416d72d49c95656662fa1fbea446e1 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Wed, 29 Mar 2023 10:54:29 +0200 Subject: [PATCH 0696/1040] arm64: dts: mediatek: add mmc support for mt8365 SoC There are three ports of MSDC (MMC and SD Controller), which are: - MSDC0: EMMC5.1 - MSDC1: SD3.0/SDIO3.0 - MSDC2: SDIO3.0+ Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-8-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 713c5609457f..2a56997239b2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -388,6 +388,45 @@ }; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg CLK_IFR_MSDC0_HCLK>, + <&infracfg CLK_IFR_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&infracfg CLK_IFR_MSDC1_HCLK>, + <&infracfg CLK_IFR_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11c60000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, + <&infracfg CLK_IFR_MSDC2_HCLK>, + <&infracfg CLK_IFR_MSDC2_SRC>, + <&infracfg CLK_IFR_MSDC2_BK>, + <&infracfg CLK_IFR_AP_MSDC0>; + clock-names = "source", "hclk", "source_cg", + "bus_clk", "sys_cg"; + status = "disabled"; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; From 91e217d4b6ea3903f6052fa1fd5179037171b2a5 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Wed, 29 Mar 2023 10:54:33 +0200 Subject: [PATCH 0697/1040] arm64: dts: mediatek: add ethernet support for mt8365 SoC This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards. It supports power management with Energy Efficient Ethernet and Wake-on-LAN specification. Flow control is provided for half-duplex and full-duplex mode. For packet transmission and reception, the controller supports IPv4/UDP/TCP checksum offload and VLAN tag insertion. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230203-evk-board-support-v3-12-0003e80e0095@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 2a56997239b2..1f6b48359115 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -427,6 +427,18 @@ status = "disabled"; }; + ethernet: ethernet@112a0000 { + compatible = "mediatek,mt8365-eth"; + reg = <0 0x112a0000 0 0x1000>; + mediatek,pericfg = <&infracfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&infracfg CLK_IFR_NIC_AXI>, + <&infracfg CLK_IFR_NIC_SLV_AXI>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; From 891db0c48efb48c3af334006f9d7ea6a0aa49cb9 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Mon, 27 Mar 2023 14:01:00 +0530 Subject: [PATCH 0698/1040] arm64: dts: ti: k3-j784s4-evm: Add eMMC mmc0 support Add support for eMMC connected to main sdhci0 instance. Signed-off-by: Apurva Nandan Reviewed-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230327083100.12587-1-a-nandan@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 476ad8915c5b..f33815953e77 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -21,6 +21,7 @@ aliases { serial2 = &main_uart8; + mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; i2c0 = &main_i2c0; }; @@ -207,6 +208,14 @@ }; }; +&main_sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + &main_sdhci1 { /* SD card */ status = "okay"; From 417e58ea41abe4c7f8be22ab5034b5e11f952240 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 28 Mar 2023 10:15:14 +0000 Subject: [PATCH 0699/1040] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20230328101517.1595738-2-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index 83bcf9fe0152..4617805c7748 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -220,7 +220,8 @@ #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; m25p,fast-read; From 09ce8651229bb2d8e10ce0499e07da6f9bfaf5d8 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 28 Mar 2023 10:15:15 +0000 Subject: [PATCH 0700/1040] ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20230328101517.1595738-3-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index 8aa9e8dea337..95ecb7d040a8 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -43,7 +43,8 @@ #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From 46a8a137d8f60929923a609cdddde06e7007b0df Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 28 Mar 2023 10:15:16 +0000 Subject: [PATCH 0701/1040] ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus Tested-by: Nicolas Ferre # on sama5d2 ICP Link: https://lore.kernel.org/r/20230328101517.1595738-4-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index 1346b8f2b259..999adeca6f33 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -669,7 +669,8 @@ #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From 2c0a1faa4da5324a2ad6621b69fb7db26134b994 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Tue, 28 Mar 2023 10:15:17 +0000 Subject: [PATCH 0702/1040] ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~33%. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20230328101517.1595738-5-tudor.ambarus@linaro.org Signed-off-by: Nicolas Ferre --- arch/arm/boot/dts/at91-sam9x60ek.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 180e4b1aa2f6..5cd593028aff 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -578,7 +578,8 @@ #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = <7>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; m25p,fast-read; From fd1c6f13cfc3db3b7bb4ab10d4599e9ed374cd53 Mon Sep 17 00:00:00 2001 From: Balsam CHIHI Date: Thu, 9 Feb 2023 11:56:27 +0100 Subject: [PATCH 0703/1040] arm64: dts: mediatek: mt8195: Add thermal zones and thermal nodes Add thermal zones and thermal nodes for the mt8195. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230209105628.50294-6-bchihi@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 129 +++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c5248deaac99..39dc571e9fc0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8195"; @@ -1105,6 +1106,17 @@ status = "disabled"; }; + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8195-lvts-ap"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1357,6 +1369,17 @@ status = "disabled"; }; + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8195-lvts-mcu"; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + xhci1: usb@11290000 { compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; @@ -2976,4 +2999,110 @@ status = "disabled"; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; + trips { + cpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; + trips { + cpu1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; + trips { + cpu2_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; + trips { + cpu3_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; + trips { + cpu4_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; + trips { + cpu5_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; + trips { + cpu6_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; + trips { + cpu7_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; }; From 7f2fc184a966c0bc46fd2e2b23d049d6bdf0e20b Mon Sep 17 00:00:00 2001 From: Balsam CHIHI Date: Thu, 9 Feb 2023 11:56:28 +0100 Subject: [PATCH 0704/1040] arm64: dts: mediatek: mt8195: Add temperature mitigation threshold The mt8195 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold when to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230209105628.50294-7-bchihi@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 169 ++++++++++++++++++++--- 1 file changed, 153 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 39dc571e9fc0..aaef8936397e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include / { @@ -3002,107 +3003,243 @@ thermal_zones: thermal-zones { cpu0-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; + trips { + cpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; + trips { + cpu1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; + trips { + cpu2_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; + trips { + cpu3_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu4-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; + trips { + cpu4_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu4_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu4_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu5-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; + trips { + cpu5_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu5_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu5_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu6-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; + trips { + cpu6_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu6_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu6_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu7-thermal { - polling-delay = <0>; - polling-delay-passive = <0>; + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; + trips { + cpu7_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu7_crit: trip-crit { temperature = <100000>; hysteresis = <2000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu7_alert>; + cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; }; From b86b9464467de6687f58f6ef9a866696a69be5f3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 23 Feb 2023 15:54:25 +0100 Subject: [PATCH 0705/1040] arm64: dts: mediatek: mt8195: Add display pwm nodes Add the two hardware PWMs for display backlighting but keep them disabled by default, as usage is board-specific. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230223145426.193590-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index aaef8936397e..8652f41403ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1118,6 +1118,29 @@ #thermal-sensor-cells = <1>; }; + disp_pwm0: pwm@1100e000 { + compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM0>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + disp_pwm1: pwm@1100f000 { + compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM1>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; + clock-names = "main", "mm"; + status = "disabled"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; From ee508454fd555099d51f3c704fc2ff292c5e152f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 23 Feb 2023 15:54:26 +0100 Subject: [PATCH 0706/1040] arm64: dts: mediatek: cherry: Add configuration for display backlight Configure the hardware PWM for the integrated display's backlight: all Cherry devices enable the backlight with GPIO82 and manage the PWM via MediaTek disp-pwm on GPIO97. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230223145426.193590-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 24669093fbed..8ac80a136c37 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -22,6 +22,16 @@ serial0 = &uart0; }; + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <576>; + enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <1023>; + pwms = <&disp_pwm0 0 500000>; + power-supply = <&ppvar_sys>; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -212,6 +222,13 @@ }; }; +&disp_pwm0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pin_default>; +}; + &dp_tx { status = "okay"; @@ -653,6 +670,13 @@ }; }; + disp_pwm0_pin_default: disp-pwm0-default-pins { + pins-disp-pwm { + pinmux = , + ; + }; + }; + dptx_pin: dptx-default-pins { pins-cmd-dat { pinmux = ; From 59e9c5e2bdabf134b03229a6cd8b50e7c658b05f Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 9 Mar 2023 15:23:03 +0100 Subject: [PATCH 0707/1040] dt-bindings: soc: mediatek: specify which compatible requires clocks property According to the mtk-mutex.c driver and the SoC DTS, the clock isn't required to work properly for some of MTK SoC. Improve the clock requirement by adding a condition which is function to the compatible. Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230220-display-v1-14-45cbc68e188b@baylibre.com Signed-off-by: Matthias Brugger --- .../bindings/soc/mediatek/mediatek,mutex.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 74c1061d32f1..4bb4a5935398 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -71,12 +71,30 @@ properties: 4 arguments defined in this property. Each GCE subsys id is mapping to a client defined in the header include/dt-bindings/gce/-gce.h. +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-disp-mutex + - mediatek,mt2712-disp-mutex + - mediatek,mt6795-disp-mutex + - mediatek,mt8173-disp-mutex + - mediatek,mt8186-disp-mutex + - mediatek,mt8186-mdp3-mutex + - mediatek,mt8192-disp-mutex + - mediatek,mt8195-disp-mutex + then: + required: + - clocks + + required: - compatible - reg - interrupts - power-domains - - clocks additionalProperties: false From fa041c4d38fc309547fea525e970667fe91d6174 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Thu, 9 Mar 2023 15:23:04 +0100 Subject: [PATCH 0708/1040] dt-bindings: soc: mediatek: add display mutex for MT8365 SoC Add compatible for the MT8365 SoC. Signed-off-by: Alexandre Mergnat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230220-display-v1-15-45cbc68e188b@baylibre.com Signed-off-by: Matthias Brugger --- .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 4bb4a5935398..ba2014a8725c 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -36,6 +36,7 @@ properties: - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex - mediatek,mt8195-vpp-mutex + - mediatek,mt8365-disp-mutex reg: maxItems: 1 From 69d170c4c28ba0490bd42630cc09d7e1834bbb3d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 31 Mar 2023 13:21:18 -0500 Subject: [PATCH 0709/1040] dt-bindings: memory-controller: Drop unneeded quotes Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230331182119.1899919-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/renesas,dbsc.yaml | 4 ++-- .../bindings/memory-controllers/renesas,rpc-if.yaml | 2 +- .../bindings/memory-controllers/samsung,exynos5422-dmc.yaml | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml index 7056ccb7eb30..8e3822314b25 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas DDR Bus Controllers diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 30a403b1b79a..56e62cd0b36a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -20,7 +20,7 @@ description: | - if it contains "cfi-flash", then HyperFlash is used. allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 098348b2b815..783ac984d898 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -42,7 +42,7 @@ properties: maxItems: 8 devfreq-events: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 16 items: @@ -50,7 +50,7 @@ properties: description: phandles of the PPMU events used by the controller. device-handle: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | phandle of the connected DRAM memory device. For more information please refer to jedec,lpddr3.yaml. @@ -73,7 +73,7 @@ properties: - description: registers of DREX1 samsung,syscon-clk: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | Phandle of the clock register set used by the controller, these registers are used for enabling a 'pause' feature and are not exposed by clock From 1ef3e78ac207d5194c18d2b75cb2119273816cb5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:45 +0100 Subject: [PATCH 0710/1040] soc: mediatek: mtk-mmsys: Add .remove() callback Add a .remove() callback to correctly unregister the multimedia clocks and DRM drivers. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index fd2b37d451c8..6edada278a15 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -121,6 +121,8 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; + struct platform_device *clks_pdev; + struct platform_device *drm_pdev; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; struct cmdq_client_reg cmdq_base; @@ -386,6 +388,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) PLATFORM_DEVID_AUTO, NULL, 0); if (IS_ERR(clks)) return PTR_ERR(clks); + mmsys->clks_pdev = clks; if (mmsys->data->is_vppsys) goto out_probe_done; @@ -396,11 +399,22 @@ static int mtk_mmsys_probe(struct platform_device *pdev) platform_device_unregister(clks); return PTR_ERR(drm); } + mmsys->drm_pdev = drm; out_probe_done: return 0; } +static int mtk_mmsys_remove(struct platform_device *pdev) +{ + struct mtk_mmsys *mmsys = platform_get_drvdata(pdev); + + platform_device_unregister(mmsys->drm_pdev); + platform_device_unregister(mmsys->clks_pdev); + + return 0; +} + static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt2701-mmsys", @@ -475,6 +489,7 @@ static struct platform_driver mtk_mmsys_drv = { .of_match_table = of_match_mtk_mmsys, }, .probe = mtk_mmsys_probe, + .remove = mtk_mmsys_remove, }; static int __init mtk_mmsys_init(void) From 683c7d383fbd413cabe1203eb7df1cc8f39c70d5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:46 +0100 Subject: [PATCH 0711/1040] soc: mediatek: mtk-mmsys: Use module_platform_driver() macro Instead of open-coding init/exit calls, switch to using the module_platform_driver() macro instead, doing the exact same. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 6edada278a15..d698d7a3b985 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -491,19 +491,7 @@ static struct platform_driver mtk_mmsys_drv = { .probe = mtk_mmsys_probe, .remove = mtk_mmsys_remove, }; - -static int __init mtk_mmsys_init(void) -{ - return platform_driver_register(&mtk_mmsys_drv); -} - -static void __exit mtk_mmsys_exit(void) -{ - platform_driver_unregister(&mtk_mmsys_drv); -} - -module_init(mtk_mmsys_init); -module_exit(mtk_mmsys_exit); +module_platform_driver(mtk_mmsys_drv); MODULE_AUTHOR("Yongqiang Niu "); MODULE_DESCRIPTION("MediaTek SoC MMSYS driver"); From 0fe09bf32a79933c741118a7346711c2a7d05d05 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:47 +0100 Subject: [PATCH 0712/1040] soc: mediatek: mtk-mmsys: Compress of_device_id array entries Compress entries of the of_match_mtk_mmsys array to reduce the amount of lines and increase readability; this brings us to a maximum of 90 columns. While at it, also add a sentinel comment to the last entry for the sole purpose of consistency. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 83 +++++++------------------------- 1 file changed, 18 insertions(+), 65 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index d698d7a3b985..a6bd934b6e5c 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -416,71 +416,24 @@ static int mtk_mmsys_remove(struct platform_device *pdev) } static const struct of_device_id of_match_mtk_mmsys[] = { - { - .compatible = "mediatek,mt2701-mmsys", - .data = &mt2701_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt2712-mmsys", - .data = &mt2712_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6779-mmsys", - .data = &mt6779_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt6797-mmsys", - .data = &mt6797_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8167-mmsys", - .data = &mt8167_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8173-mmsys", - .data = &mt8173_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8183-mmsys", - .data = &mt8183_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8186-mmsys", - .data = &mt8186_mmsys_driver_data, - }, - { - .compatible = "mediatek,mt8188-vdosys0", - .data = &mt8188_vdosys0_driver_data, - }, - { - .compatible = "mediatek,mt8192-mmsys", - .data = &mt8192_mmsys_driver_data, - }, - { /* deprecated compatible */ - .compatible = "mediatek,mt8195-mmsys", - .data = &mt8195_vdosys0_driver_data, - }, - { - .compatible = "mediatek,mt8195-vdosys0", - .data = &mt8195_vdosys0_driver_data, - }, - { - .compatible = "mediatek,mt8195-vdosys1", - .data = &mt8195_vdosys1_driver_data, - }, - { - .compatible = "mediatek,mt8195-vppsys0", - .data = &mt8195_vppsys0_driver_data, - }, - { - .compatible = "mediatek,mt8195-vppsys1", - .data = &mt8195_vppsys1_driver_data, - }, - { - .compatible = "mediatek,mt8365-mmsys", - .data = &mt8365_mmsys_driver_data, - }, - { } + { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data }, + { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data }, + { .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data }, + { .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data }, + { .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data }, + { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data }, + { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data }, + { .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data }, + { .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data }, + { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data }, + /* "mediatek,mt8195-mmsys" compatible is deprecated */ + { .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data }, + { .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data }, + { .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data }, + { .compatible = "mediatek,mt8195-vppsys0", .data = &mt8195_vppsys0_driver_data }, + { .compatible = "mediatek,mt8195-vppsys1", .data = &mt8195_vppsys1_driver_data }, + { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data }, + { /* sentinel */ } }; static struct platform_driver mtk_mmsys_drv = { From 10687632307c08d9183b1859a01a5848e50e4334 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:48 +0100 Subject: [PATCH 0713/1040] soc: mediatek: mtk-mmsys: Add MODULE_DEVICE_TABLE() to allow auto-load Allow module auto-loading by adding a MODULE_DEVICE_TABLE for of_match_mmsys. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-5-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a6bd934b6e5c..0fa6c31f774c 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -435,6 +435,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, of_match_mtk_mmsys); static struct platform_driver mtk_mmsys_drv = { .driver = { From 00ee1db7016b73ecd3214d6dc2df4fa02beb694d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:49 +0100 Subject: [PATCH 0714/1040] soc: mediatek: mtk-mutex: Compress of_device_id array entries Compress entries of the of_match_mtk_mmsys array to reduce the amount of lines and increase readability; this brings us to a maximum of 95 columns. While at it, also add a sentinel comment to the last entry for the sole purpose of consistency. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230222094253.23678-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 41 +++++++++++--------------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 7751527fc30d..a59fde2bdcba 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -1040,33 +1040,20 @@ static int mtk_mutex_probe(struct platform_device *pdev) } static const struct of_device_id mutex_driver_dt_match[] = { - { .compatible = "mediatek,mt2701-disp-mutex", - .data = &mt2701_mutex_driver_data}, - { .compatible = "mediatek,mt2712-disp-mutex", - .data = &mt2712_mutex_driver_data}, - { .compatible = "mediatek,mt6795-disp-mutex", - .data = &mt6795_mutex_driver_data}, - { .compatible = "mediatek,mt8167-disp-mutex", - .data = &mt8167_mutex_driver_data}, - { .compatible = "mediatek,mt8173-disp-mutex", - .data = &mt8173_mutex_driver_data}, - { .compatible = "mediatek,mt8183-disp-mutex", - .data = &mt8183_mutex_driver_data}, - { .compatible = "mediatek,mt8186-disp-mutex", - .data = &mt8186_mutex_driver_data}, - { .compatible = "mediatek,mt8186-mdp3-mutex", - .data = &mt8186_mdp_mutex_driver_data}, - { .compatible = "mediatek,mt8188-disp-mutex", - .data = &mt8188_mutex_driver_data}, - { .compatible = "mediatek,mt8192-disp-mutex", - .data = &mt8192_mutex_driver_data}, - { .compatible = "mediatek,mt8195-disp-mutex", - .data = &mt8195_mutex_driver_data}, - { .compatible = "mediatek,mt8195-vpp-mutex", - .data = &mt8195_vpp_mutex_driver_data}, - { .compatible = "mediatek,mt8365-disp-mutex", - .data = &mt8365_mutex_driver_data}, - {}, + { .compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_mutex_driver_data }, + { .compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_mutex_driver_data }, + { .compatible = "mediatek,mt6795-disp-mutex", .data = &mt6795_mutex_driver_data }, + { .compatible = "mediatek,mt8167-disp-mutex", .data = &mt8167_mutex_driver_data }, + { .compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_mutex_driver_data }, + { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data }, + { .compatible = "mediatek,mt8186-disp-mutex", .data = &mt8186_mutex_driver_data }, + { .compatible = "mediatek,mt8186-mdp3-mutex", .data = &mt8186_mdp_mutex_driver_data }, + { .compatible = "mediatek,mt8188-disp-mutex", .data = &mt8188_mutex_driver_data }, + { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data }, + { .compatible = "mediatek,mt8195-disp-mutex", .data = &mt8195_mutex_driver_data }, + { .compatible = "mediatek,mt8195-vpp-mutex", .data = &mt8195_vpp_mutex_driver_data }, + { .compatible = "mediatek,mt8365-disp-mutex", .data = &mt8365_mutex_driver_data }, + { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); From dc36768d05bc877b1227b09af1bb304a28284ce3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:50 +0100 Subject: [PATCH 0715/1040] soc: mediatek: mtk-mutex: Replace max handles number with definition Replace the magic number "10", defining the maximum number of supported handles with a MTK_MUTEX_MAX_HANDLES definition. While at it, also change the type for `id` from a signed integer to a unsigned 8 bits integer to save some (small) memory footprint, as this number is never higher than 10. This cleanup brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index a59fde2bdcba..b68bb87bc365 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -14,6 +14,8 @@ #include #include +#define MTK_MUTEX_MAX_HANDLES 10 + #define MT2701_MUTEX0_MOD0 0x2c #define MT2701_MUTEX0_SOF0 0x30 #define MT8183_MUTEX0_MOD0 0x30 @@ -282,7 +284,7 @@ #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7) struct mtk_mutex { - int id; + u8 id; bool claimed; }; @@ -312,7 +314,7 @@ struct mtk_mutex_ctx { struct device *dev; struct clk *clk; void __iomem *regs; - struct mtk_mutex mutex[10]; + struct mtk_mutex mutex[MTK_MUTEX_MAX_HANDLES]; const struct mtk_mutex_data *data; phys_addr_t addr; struct cmdq_client_reg cmdq_reg; @@ -717,7 +719,7 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev) struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); int i; - for (i = 0; i < 10; i++) + for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) if (!mtx->mutex[i].claimed) { mtx->mutex[i].claimed = true; return &mtx->mutex[i]; @@ -1007,7 +1009,7 @@ static int mtk_mutex_probe(struct platform_device *pdev) if (!mtx) return -ENOMEM; - for (i = 0; i < 10; i++) + for (i = 0; i < MTK_MUTEX_MAX_HANDLES; i++) mtx->mutex[i].id = i; mtx->data = of_device_get_match_data(dev); From 1fccd1ef65b2b100b53b534894366f575b390e70 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:51 +0100 Subject: [PATCH 0716/1040] soc: mediatek: mtk-mutex: Use module_platform_driver() macro Replace open-coded init/exit calls with the module_platform_driver() macro being equivalent. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-8-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index b68bb87bc365..b106f3d23e0d 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -1067,19 +1067,7 @@ static struct platform_driver mtk_mutex_driver = { .of_match_table = mutex_driver_dt_match, }, }; - -static int __init mtk_mutex_init(void) -{ - return platform_driver_register(&mtk_mutex_driver); -} - -static void __exit mtk_mutex_exit(void) -{ - platform_driver_unregister(&mtk_mutex_driver); -} - -module_init(mtk_mutex_init); -module_exit(mtk_mutex_exit); +module_platform_driver(mtk_mutex_driver); MODULE_AUTHOR("Yongqiang Niu "); MODULE_DESCRIPTION("MediaTek SoC MUTEX driver"); From eb0d8623b9b805cbcab87620a363292552c19359 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:52 +0100 Subject: [PATCH 0717/1040] soc: mediatek: cmdq: Add inline functions for !CONFIG_MTK_CMDQ In preparation for a cleanup of ifdef instances of IS_REACHABLE() for the CONFIG_MTK_CMDQ configuration option, add inline functions that will either return a failure or, for void functions, do nothing. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-9-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- include/linux/soc/mediatek/mtk-cmdq.h | 114 ++++++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 2b498f4f3946..649955d2cf5c 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -27,6 +27,8 @@ struct cmdq_client { struct mbox_chan *chan; }; +#if IS_ENABLED(CONFIG_MTK_CMDQ) + /** * cmdq_dev_get_client_reg() - parse cmdq client reg from the device * node of CMDQ client @@ -277,4 +279,116 @@ int cmdq_pkt_finalize(struct cmdq_pkt *pkt); */ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt); +#else /* IS_ENABLED(CONFIG_MTK_CMDQ) */ + +static inline int cmdq_dev_get_client_reg(struct device *dev, + struct cmdq_client_reg *client_reg, int idx) +{ + return -ENODEV; +} + +static inline struct cmdq_client *cmdq_mbox_create(struct device *dev, int index) +{ + return ERR_PTR(-EINVAL); +} + +static inline void cmdq_mbox_destroy(struct cmdq_client *client) { } + +static inline struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client, size_t size) +{ + return ERR_PTR(-EINVAL); +} + +static inline void cmdq_pkt_destroy(struct cmdq_pkt *pkt) { } + +static inline int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value) +{ + return -ENOENT; +} + +static inline int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask) +{ + return -ENOENT; +} + +static inline int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, + u16 addr_low, u16 reg_idx) +{ + return -ENOENT; +} + +static inline int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, + u16 addr_low, u16 src_reg_idx) +{ + return -ENOENT; +} + +static inline int cmdq_pkt_write_s_mask(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, + u16 addr_low, u16 src_reg_idx, u32 mask) +{ + return -ENOENT; +} + +static inline int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, + u16 addr_low, u32 value) +{ + return -ENOENT; +} + +static inline int cmdq_pkt_write_s_mask_value(struct cmdq_pkt *pkt, u8 high_addr_reg_idx, + u16 addr_low, u32 value, u32 mask) +{ + return -ENOENT; +} + +static inline int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys, + u16 offset, u32 value, u32 mask) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_finalize(struct cmdq_pkt *pkt) +{ + return -EINVAL; +} + +static inline int cmdq_pkt_flush_async(struct cmdq_pkt *pkt) +{ + return -EINVAL; +} + +#endif /* IS_ENABLED(CONFIG_MTK_CMDQ) */ + #endif /* __MTK_CMDQ_H__ */ From b34884b4c878a6ad2a4f70d7c88ef60ac39ad408 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 22 Feb 2023 10:42:53 +0100 Subject: [PATCH 0718/1040] soc: mediatek: Cleanup ifdefs for IS_REACHABLE(CONFIG_MTK_CMDQ) Now that the mtk-cmdq.h header contains inline functions for cases in which the driver is not enabled (either module or built-in), we can safely go on with cleaning up ifdefs for CMDQ handling. This also shows in a clearer manner that writing through CMDQ HW is optional and used only for performance purposes when/where wanted, needed and/or required. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230222094253.23678-10-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 22 +++++++++------------- drivers/soc/mediatek/mtk-mutex.c | 15 +++------------ 2 files changed, 12 insertions(+), 25 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 0fa6c31f774c..b84485670f91 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -131,21 +131,18 @@ struct mtk_mmsys { static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val, struct cmdq_pkt *cmdq_pkt) { + int ret; u32 tmp; -#if IS_REACHABLE(CONFIG_MTK_CMDQ) - if (cmdq_pkt) { - if (mmsys->cmdq_base.size == 0) { - pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq"); + if (mmsys->cmdq_base.size && cmdq_pkt) { + ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, + mmsys->cmdq_base.offset + offset, val, + mask); + if (ret) + pr_debug("CMDQ unavailable: using CPU write\n"); + else return; - } - cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, - mmsys->cmdq_base.offset + offset, val, - mask); - return; } -#endif - tmp = readl_relaxed(mmsys->regs + offset); tmp = (tmp & ~mask) | (val & mask); writel_relaxed(tmp, mmsys->regs + offset); @@ -376,11 +373,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) } } -#if IS_REACHABLE(CONFIG_MTK_CMDQ) + /* CMDQ is optional */ ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); if (ret) dev_dbg(dev, "No mediatek,gce-client-reg!\n"); -#endif platform_set_drvdata(pdev, mmsys); diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index b106f3d23e0d..b92cffec7be7 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -871,23 +871,18 @@ int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt) { struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, mutex[mutex->id]); -#if IS_REACHABLE(CONFIG_MTK_CMDQ) struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt; WARN_ON(&mtx->mutex[mutex->id] != mutex); if (!mtx->cmdq_reg.size) { dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set"); - return -EINVAL; + return -ENODEV; } cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys, mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1); return 0; -#else - dev_err(mtx->dev, "Not support for enable MUTEX by CMDQ"); - return -ENODEV; -#endif } EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq); @@ -1000,10 +995,7 @@ static int mtk_mutex_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mtk_mutex_ctx *mtx; struct resource *regs; - int i; -#if IS_REACHABLE(CONFIG_MTK_CMDQ) - int ret; -#endif + int i, ret; mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL); if (!mtx) @@ -1030,11 +1022,10 @@ static int mtk_mutex_probe(struct platform_device *pdev) } mtx->addr = regs->start; -#if IS_REACHABLE(CONFIG_MTK_CMDQ) + /* CMDQ is optional */ ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0); if (ret) dev_dbg(dev, "No mediatek,gce-client-reg!\n"); -#endif platform_set_drvdata(pdev, mtx); From 2a0a8d8700ef4f75b1b3e87b3b314b07246b4c27 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Mar 2023 11:26:16 +0100 Subject: [PATCH 0719/1040] soc: mediatek: mtk-mmsys: Split out MT8173 mmsys DDP routing table MT2701, MT2712 and MT8173 were relying on a "default" DDP I/O routing table, describing all of the possible connections between display block components: while this is definitely working it's suboptimal for the actual routing description, as we may be enabling outputs and inputs that are not needed, possibly impacting on actual DDP performance other than slightly prolonging boot times by having to parse a table that is bigger than needed. Seen that all of the other supported SoCs have got their own table and seen that a comment in mtk-mmsys.h explicitly mentions that the wanted way is to have one table per SoC, create a new routing table that is specifically tailored to MT8173 and, while at it, remove mentions to said SoC from the comment in mtk-mmsys.h. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230309102618.114157-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8173-mmsys.h | 95 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 5 +- drivers/soc/mediatek/mtk-mmsys.h | 2 +- 3 files changed, 99 insertions(+), 3 deletions(-) create mode 100644 drivers/soc/mediatek/mt8173-mmsys.h diff --git a/drivers/soc/mediatek/mt8173-mmsys.h b/drivers/soc/mediatek/mt8173-mmsys.h new file mode 100644 index 000000000000..9d24e381271e --- /dev/null +++ b/drivers/soc/mediatek/mt8173-mmsys.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8173_MMSYS_H +#define __SOC_MEDIATEK_MT8173_MMSYS_H + +#define MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 +#define MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN 0x08c +#define MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x0a0 +#define MT8173_DISP_REG_CONFIG_DSI0_SEL_IN 0x0a4 +#define MT8173_DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x0b0 +#define MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN 0x0bc + +#define MT8173_AAL_SEL_IN_MERGE BIT(0) +#define MT8173_COLOR0_SEL_IN_OVL0 BIT(0) +#define MT8173_COLOR0_SOUT_MERGE BIT(0) +#define MT8173_DPI0_SEL_IN_MASK GENMASK(1, 0) +#define MT8173_DPI0_SEL_IN_RDMA1 BIT(0) +#define MT8173_DSI0_SEL_IN_UFOE BIT(0) +#define MT8173_GAMMA_MOUT_EN_RDMA1 BIT(0) +#define MT8173_OD0_MOUT_EN_RDMA0 BIT(0) +#define MT8173_OVL0_MOUT_EN_COLOR0 BIT(0) +#define MT8173_OVL1_MOUT_EN_COLOR1 BIT(0) +#define MT8173_UFOE_MOUT_EN_DSI0 BIT(0) +#define MT8173_UFOE_SEL_IN_RDMA0 BIT(0) +#define MT8173_RDMA0_SOUT_COLOR0 BIT(0) + +static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, + MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, + MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0 + }, { + DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, + MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, + MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0 + }, { + DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, + MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, + MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0 + }, { + DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0, + MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, + MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */ + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, + MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, + MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */ + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, + MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, + MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0 + }, { + DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0, + MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, + MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */ + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, + MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, + MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */ + }, { + DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, + MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, + MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */ + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, + MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, + MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1 + }, { + DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1, + MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, + MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1 + }, { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, + RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0 + }, { + DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, + MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, + COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1 + }, { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + MT8173_DISP_REG_CONFIG_DPI_SEL_IN, + MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1 + } +}; + +#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index b84485670f91..d5844aff0621 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -15,6 +15,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" +#include "mt8173-mmsys.h" #include "mt8183-mmsys.h" #include "mt8186-mmsys.h" #include "mt8188-mmsys.h" @@ -52,8 +53,8 @@ static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", - .routes = mmsys_default_routing_table, - .num_routes = ARRAY_SIZE(mmsys_default_routing_table), + .routes = mt8173_mmsys_routing_table, + .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, .num_resets = 32, }; diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 56f8cc3a97b7..6725403d2e3a 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -96,7 +96,7 @@ struct mtk_mmsys_driver_data { }; /* - * Routes in mt8173, mt2701, mt2712 are different. That means + * Routes in mt2701 and mt2712 are different. That means * in the same register address, it controls different input/output * selection for each SoC. But, right now, they use the same table as * default routes meet their requirements. But we don't have the complete From b427d857a8eae5cd2d22469371c4625c59dfbb2f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Mar 2023 11:26:17 +0100 Subject: [PATCH 0720/1040] soc: mediatek: mtk-mmsys: Change MT8173 num_resets to 64 The MT8173 SoC has 64 MMSYS resets, split in two contiguous 32-bits registers, MMSYS_SW0_RST_B (0x140) and MMSYS_SW1_RST_B (0x144), as also stated in the downstream kernel for the Amazon Fire TV 2 (Sloane) in the ddp_reg.h header. Please note that managing more than 32 reset bits is supported since commit 2004f8be8483 ("soc: mediatek: mmsys: add mmsys for support 64 reset bits") This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230309102618.114157-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index d5844aff0621..c4eeab99756b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -56,7 +56,7 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .routes = mt8173_mmsys_routing_table, .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, - .num_resets = 32, + .num_resets = 64, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { From e9a6f5bca5ea56f05d92a966034ed472408821b8 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Mar 2023 11:26:18 +0100 Subject: [PATCH 0721/1040] soc: mediatek: mtk-mmsys: Add support for MT6795 Helio X10 Add MMSYS support for the MT6795 SoC using the same mmsys routing table as MT8173 as, for the currently supported usecases (DSI0, DPI0 with no WDMA), these are identical. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230309102618.114157-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index c4eeab99756b..9619faa796e8 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -41,6 +41,14 @@ static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { .clk_driver = "clk-mt6779-mm", }; +static const struct mtk_mmsys_driver_data mt6795_mmsys_driver_data = { + .clk_driver = "clk-mt6795-mm", + .routes = mt8173_mmsys_routing_table, + .num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table), + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, + .num_resets = 64, +}; + static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = { .clk_driver = "clk-mt6797-mm", }; @@ -416,6 +424,7 @@ static const struct of_device_id of_match_mtk_mmsys[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data }, { .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data }, { .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data }, + { .compatible = "mediatek,mt6795-mmsys", .data = &mt6795_mmsys_driver_data }, { .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data }, { .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data }, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data }, From 03a750a7a7b5b278b82b0fcdeca0bba26ebecb7e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:31 +0200 Subject: [PATCH 0722/1040] arm64: dts: mediatek: mt6795: Add Frequency Hopping Controller node Add FHCTL node but keep it disabled as the PLL clocks that should be handled through FHCTL and the Spread Spectrum Clocking parameters are board specific. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index b3fc76d837a9..4d2119751572 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -310,6 +310,12 @@ clock-names = "clk13m"; }; + fhctl: clock-controller@10209f00 { + compatible = "mediatek,mt6795-fhctl"; + reg = <0 0x10209f00 0 0x100>; + status = "disabled"; + }; + gic: interrupt-controller@10221000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; From befae66a462bf42816394a23e3f710a068e8310c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:32 +0200 Subject: [PATCH 0723/1040] arm64: dts: mediatek: mt6795: Add apmixedsys syscon node Add the APMIXEDSYS node, providing a syscon to the APMIXED iospace and also providing PLLs. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-3-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 4d2119751572..26d640e1bfb6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -310,6 +310,12 @@ clock-names = "clk13m"; }; + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt6795-apmixedsys", "syscon"; + reg = <0 0x10209000 0 0x1000>; + #clock-cells = <1>; + }; + fhctl: clock-controller@10209f00 { compatible = "mediatek,mt6795-fhctl"; reg = <0 0x10209f00 0 0x100>; From c63e6a4640c7b7d0c800bc7c5c42565779eaa702 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:33 +0200 Subject: [PATCH 0724/1040] arm64: dts: mediatek: mt6795: xperia-m5: Enable Frequency Hopping Enable FHCTL with Spread Spectrum for MAINPLL, MPLL and MSDCPLL as found on the downstream kernel for this smartphone. Which one to enable, and at what SSC percentage, was found by dumping the debugging data from a running downstream kernel and checking the downstream code. /proc/freqhopping # cat status FH status: =============================================== id == fh_status == pll_status == setting_id == curr_freq == user_defined 0 0 1 0 1599000 0 1 0 1 0 1716000 0 2 1 1 2 1092000 0 3 1 1 2 2912000 0 4 1 0 2 1600000 0 5 0 0 0 0 0 6 0 1 0 1518002 0 7 0 0 0 0 0 8 0 0 0 0 0 Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index d3415527d389..52ce3284a46f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -48,6 +48,13 @@ }; }; +&fhctl { + clocks = <&apmixedsys CLK_APMIXED_MAINPLL>, <&apmixedsys CLK_APMIXED_MPLL>, + <&apmixedsys CLK_APMIXED_MSDCPLL>; + mediatek,hopping-ssc-percent = <8>, <5>, <8>; + status = "okay"; +}; + &pio { uart0_pins: uart0-pins { pins-rx { From 80d9c0734330729210b30a46bd28a40ad48e7256 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:35 +0200 Subject: [PATCH 0725/1040] arm64: dts: mediatek: mt6795: Add nodes for I2C controllers Add all four I2C controller nodes but keep them in disabled state as usage is board-dependant. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 60 ++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 26d640e1bfb6..ceb6fc948d8a 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -445,6 +445,66 @@ status = "disabled"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11010000 { + compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; + reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; + interrupts = ; + clock-div = <16>; + clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt6795-mmc"; reg = <0 0x11230000 0 0x1000>; From 80dd5ca523c5bbef082c31fad67825009bfb04d6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:36 +0200 Subject: [PATCH 0726/1040] arm64: dts: mediatek: mt6795: Add SoC power domains Add power domain tree for various hardware blocks on MT6795. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-7-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 79 ++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index ceb6fc948d8a..d63efb32e6bb 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include / { @@ -264,6 +265,84 @@ #reset-cells = <1>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt6795-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT6795_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT6795_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "mm", "venc"; + #power-domain-cells = <0>; + }; + power-domain@MT6795_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT6795_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT6795_POWER_DOMAIN_MJC { + reg = ; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MJC_SEL>; + clock-names = "mm", "mjc"; + #power-domain-cells = <0>; + }; + + power-domain@MT6795_POWER_DOMAIN_AUDIO { + reg = ; + #power-domain-cells = <0>; + }; + + mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&clk26m>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT6795_POWER_DOMAIN_MFG_2D { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT6795_POWER_DOMAIN_MFG { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + }; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt6795-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; From a73a7c41de593ea08f5a659b2b6ff4b5af493bbb Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Fri, 24 Mar 2023 10:17:29 +0800 Subject: [PATCH 0727/1040] soc: mediatek: mutex: Use dev_err_probe() Replace the open-code with dev_err_probe() to simplify the code. Signed-off-by: Ye Xingchen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/202303241017290414354@zte.com.cn Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index b92cffec7be7..26f3d9a41496 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -1008,11 +1008,8 @@ static int mtk_mutex_probe(struct platform_device *pdev) if (!mtx->data->no_clk) { mtx->clk = devm_clk_get(dev, NULL); - if (IS_ERR(mtx->clk)) { - if (PTR_ERR(mtx->clk) != -EPROBE_DEFER) - dev_err(dev, "Failed to get clock\n"); - return PTR_ERR(mtx->clk); - } + if (IS_ERR(mtx->clk)) + return dev_err_probe(dev, PTR_ERR(mtx->clk), "Failed to get clock\n"); } mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); From f3040daab8104ac68e2b241bc93288f63b88a3c7 Mon Sep 17 00:00:00 2001 From: Jeffrey Kardatzke Date: Fri, 31 Mar 2023 11:35:47 -0700 Subject: [PATCH 0728/1040] tee: optee: Add SMC for loading OP-TEE image Adds an SMC call that will pass an OP-TEE binary image to EL3 and instruct it to load it as the BL32 payload. This works in conjunction with a feature added to Trusted Firmware for ARMv8 and above architectures that supports this. The main purpose of this change is to facilitate updating the OP-TEE component on devices via a rootfs change rather than having to do a firmware update. Further details are linked to in the Kconfig file. Signed-off-by: Jeffrey Kardatzke Reviewed-by: Sumit Garg Signed-off-by: Jeffrey Kardatzke Signed-off-by: Jens Wiklander --- Documentation/staging/tee.rst | 53 +++++++++++++ drivers/tee/optee/Kconfig | 17 +++++ drivers/tee/optee/optee_msg.h | 12 +++ drivers/tee/optee/optee_smc.h | 24 ++++++ drivers/tee/optee/smc_abi.c | 137 ++++++++++++++++++++++++++++++++++ 5 files changed, 243 insertions(+) diff --git a/Documentation/staging/tee.rst b/Documentation/staging/tee.rst index 498343c7ab08..22baa077a3b9 100644 --- a/Documentation/staging/tee.rst +++ b/Documentation/staging/tee.rst @@ -214,6 +214,57 @@ call is done from the thread assisting the interrupt handler. This is a building block for OP-TEE OS in secure world to implement the top half and bottom half style of device drivers. +OPTEE_INSECURE_LOAD_IMAGE Kconfig option +---------------------------------------- + +The OPTEE_INSECURE_LOAD_IMAGE Kconfig option enables the ability to load the +BL32 OP-TEE image from the kernel after the kernel boots, rather than loading +it from the firmware before the kernel boots. This also requires enabling the +corresponding option in Trusted Firmware for Arm. The Trusted Firmware for Arm +documentation [8] explains the security threat associated with enabling this as +well as mitigations at the firmware and platform level. + +There are additional attack vectors/mitigations for the kernel that should be +addressed when using this option. + +1. Boot chain security. + + * Attack vector: Replace the OP-TEE OS image in the rootfs to gain control of + the system. + + * Mitigation: There must be boot chain security that verifies the kernel and + rootfs, otherwise an attacker can modify the loaded OP-TEE binary by + modifying it in the rootfs. + +2. Alternate boot modes. + + * Attack vector: Using an alternate boot mode (i.e. recovery mode), the + OP-TEE driver isn't loaded, leaving the SMC hole open. + + * Mitigation: If there are alternate methods of booting the device, such as a + recovery mode, it should be ensured that the same mitigations are applied + in that mode. + +3. Attacks prior to SMC invocation. + + * Attack vector: Code that is executed prior to issuing the SMC call to load + OP-TEE can be exploited to then load an alternate OS image. + + * Mitigation: The OP-TEE driver must be loaded before any potential attack + vectors are opened up. This should include mounting of any modifiable + filesystems, opening of network ports or communicating with external + devices (e.g. USB). + +4. Blocking SMC call to load OP-TEE. + + * Attack vector: Prevent the driver from being probed, so the SMC call to + load OP-TEE isn't executed when desired, leaving it open to being executed + later and loading a modified OS. + + * Mitigation: It is recommended to build the OP-TEE driver as builtin driver + rather than as a module to prevent exploits that may cause the module to + not be loaded. + AMD-TEE driver ============== @@ -309,3 +360,5 @@ References [6] include/linux/psp-tee.h [7] drivers/tee/amdtee/amdtee_if.h + +[8] https://trustedfirmware-a.readthedocs.io/en/latest/threat_model/threat_model.html diff --git a/drivers/tee/optee/Kconfig b/drivers/tee/optee/Kconfig index f121c224e682..70898bbd5809 100644 --- a/drivers/tee/optee/Kconfig +++ b/drivers/tee/optee/Kconfig @@ -7,3 +7,20 @@ config OPTEE help This implements the OP-TEE Trusted Execution Environment (TEE) driver. + +config OPTEE_INSECURE_LOAD_IMAGE + bool "Load OP-TEE image as firmware" + default n + depends on OPTEE && ARM64 + help + This loads the BL32 image for OP-TEE as firmware when the driver is + probed. This returns -EPROBE_DEFER until the firmware is loadable from + the filesystem which is determined by checking the system_state until + it is in SYSTEM_RUNNING. This also requires enabling the corresponding + option in Trusted Firmware for Arm. The documentation there explains + the security threat associated with enabling this as well as + mitigations at the firmware and platform level. + https://trustedfirmware-a.readthedocs.io/en/latest/threat_model/threat_model.html + + Additional documentation on kernel security risks are at + Documentation/staging/tee.rst. diff --git a/drivers/tee/optee/optee_msg.h b/drivers/tee/optee/optee_msg.h index 70e9cc2ee96b..e8840a82b983 100644 --- a/drivers/tee/optee/optee_msg.h +++ b/drivers/tee/optee/optee_msg.h @@ -241,11 +241,23 @@ struct optee_msg_arg { * 384fb3e0-e7f8-11e3-af63-0002a5d5c51b. * Represented in 4 32-bit words in OPTEE_MSG_UID_0, OPTEE_MSG_UID_1, * OPTEE_MSG_UID_2, OPTEE_MSG_UID_3. + * + * In the case where the OP-TEE image is loaded by the kernel, this will + * initially return an alternate UID to reflect that we are communicating with + * the TF-A image loading service at that time instead of OP-TEE. That UID is: + * a3fbeab1-1246-315d-c7c4-06b9c03cbea4. + * Represented in 4 32-bit words in OPTEE_MSG_IMAGE_LOAD_UID_0, + * OPTEE_MSG_IMAGE_LOAD_UID_1, OPTEE_MSG_IMAGE_LOAD_UID_2, + * OPTEE_MSG_IMAGE_LOAD_UID_3. */ #define OPTEE_MSG_UID_0 0x384fb3e0 #define OPTEE_MSG_UID_1 0xe7f811e3 #define OPTEE_MSG_UID_2 0xaf630002 #define OPTEE_MSG_UID_3 0xa5d5c51b +#define OPTEE_MSG_IMAGE_LOAD_UID_0 0xa3fbeab1 +#define OPTEE_MSG_IMAGE_LOAD_UID_1 0x1246315d +#define OPTEE_MSG_IMAGE_LOAD_UID_2 0xc7c406b9 +#define OPTEE_MSG_IMAGE_LOAD_UID_3 0xc03cbea4 #define OPTEE_MSG_FUNCID_CALLS_UID 0xFF01 /* diff --git a/drivers/tee/optee/optee_smc.h b/drivers/tee/optee/optee_smc.h index 73b5e7760d10..7d9fa426505b 100644 --- a/drivers/tee/optee/optee_smc.h +++ b/drivers/tee/optee/optee_smc.h @@ -104,6 +104,30 @@ struct optee_smc_call_get_os_revision_result { unsigned long reserved1; }; +/* + * Load Trusted OS from optee/tee.bin in the Linux firmware. + * + * WARNING: Use this cautiously as it could lead to insecure loading of the + * Trusted OS. + * This SMC instructs EL3 to load a binary and execute it as the Trusted OS. + * + * Call register usage: + * a0 SMC Function ID, OPTEE_SMC_CALL_LOAD_IMAGE + * a1 Upper 32bit of a 64bit size for the payload + * a2 Lower 32bit of a 64bit size for the payload + * a3 Upper 32bit of the physical address for the payload + * a4 Lower 32bit of the physical address for the payload + * + * The payload is in the OP-TEE image format. + * + * Returns result in a0, 0 on success and an error code otherwise. + */ +#define OPTEE_SMC_FUNCID_LOAD_IMAGE 2 +#define OPTEE_SMC_CALL_LOAD_IMAGE \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_32, \ + ARM_SMCCC_OWNER_TRUSTED_OS_END, \ + OPTEE_SMC_FUNCID_LOAD_IMAGE) + /* * Call with struct optee_msg_arg as argument * diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index a1c1fa1a9c28..6e1f023d50c6 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -7,10 +7,13 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include +#include #include #include #include +#include #include #include #include @@ -1149,6 +1152,22 @@ static bool optee_msg_api_uid_is_optee_api(optee_invoke_fn *invoke_fn) return false; } +#ifdef CONFIG_OPTEE_INSECURE_LOAD_IMAGE +static bool optee_msg_api_uid_is_optee_image_load(optee_invoke_fn *invoke_fn) +{ + struct arm_smccc_res res; + + invoke_fn(OPTEE_SMC_CALLS_UID, 0, 0, 0, 0, 0, 0, 0, &res); + + if (res.a0 == OPTEE_MSG_IMAGE_LOAD_UID_0 && + res.a1 == OPTEE_MSG_IMAGE_LOAD_UID_1 && + res.a2 == OPTEE_MSG_IMAGE_LOAD_UID_2 && + res.a3 == OPTEE_MSG_IMAGE_LOAD_UID_3) + return true; + return false; +} +#endif + static void optee_msg_get_os_revision(optee_invoke_fn *invoke_fn) { union { @@ -1354,6 +1373,120 @@ static void optee_shutdown(struct platform_device *pdev) optee_disable_shm_cache(optee); } +#ifdef CONFIG_OPTEE_INSECURE_LOAD_IMAGE + +#define OPTEE_FW_IMAGE "optee/tee.bin" + +static optee_invoke_fn *cpuhp_invoke_fn; + +static int optee_cpuhp_probe(unsigned int cpu) +{ + /* + * Invoking a call on a CPU will cause OP-TEE to perform the required + * setup for that CPU. Just invoke the call to get the UID since that + * has no side effects. + */ + if (optee_msg_api_uid_is_optee_api(cpuhp_invoke_fn)) + return 0; + else + return -EINVAL; +} + +static int optee_load_fw(struct platform_device *pdev, + optee_invoke_fn *invoke_fn) +{ + const struct firmware *fw = NULL; + struct arm_smccc_res res; + phys_addr_t data_pa; + u8 *data_buf = NULL; + u64 data_size; + u32 data_pa_high, data_pa_low; + u32 data_size_high, data_size_low; + int rc; + int hp_state; + + if (!optee_msg_api_uid_is_optee_image_load(invoke_fn)) + return 0; + + rc = request_firmware(&fw, OPTEE_FW_IMAGE, &pdev->dev); + if (rc) { + /* + * The firmware in the rootfs will not be accessible until we + * are in the SYSTEM_RUNNING state, so return EPROBE_DEFER until + * that point. + */ + if (system_state < SYSTEM_RUNNING) + return -EPROBE_DEFER; + goto fw_err; + } + + data_size = fw->size; + /* + * This uses the GFP_DMA flag to ensure we are allocated memory in the + * 32-bit space since TF-A cannot map memory beyond the 32-bit boundary. + */ + data_buf = kmalloc(fw->size, GFP_KERNEL | GFP_DMA); + if (!data_buf) { + rc = -ENOMEM; + goto fw_err; + } + memcpy(data_buf, fw->data, fw->size); + data_pa = virt_to_phys(data_buf); + reg_pair_from_64(&data_pa_high, &data_pa_low, data_pa); + reg_pair_from_64(&data_size_high, &data_size_low, data_size); + goto fw_load; + +fw_err: + pr_warn("image loading failed\n"); + data_pa_high = 0; + data_pa_low = 0; + data_size_high = 0; + data_size_low = 0; + +fw_load: + /* + * Always invoke the SMC, even if loading the image fails, to indicate + * to EL3 that we have passed the point where it should allow invoking + * this SMC. + */ + pr_warn("OP-TEE image loaded from kernel, this can be insecure"); + invoke_fn(OPTEE_SMC_CALL_LOAD_IMAGE, data_size_high, data_size_low, + data_pa_high, data_pa_low, 0, 0, 0, &res); + if (!rc) + rc = res.a0; + if (fw) + release_firmware(fw); + kfree(data_buf); + + if (!rc) { + /* + * We need to initialize OP-TEE on all other running cores as + * well. Any cores that aren't running yet will get initialized + * when they are brought up by the power management functions in + * TF-A which are registered by the OP-TEE SPD. Due to that we + * can un-register the callback right after registering it. + */ + cpuhp_invoke_fn = invoke_fn; + hp_state = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "optee:probe", + optee_cpuhp_probe, NULL); + if (hp_state < 0) { + pr_warn("Failed with CPU hotplug setup for OP-TEE"); + return -EINVAL; + } + cpuhp_remove_state(hp_state); + cpuhp_invoke_fn = NULL; + } + + return rc; +} +#else +static inline int optee_load_fw(struct platform_device *pdev, + optee_invoke_fn *invoke_fn) +{ + return 0; +} +#endif + static int optee_probe(struct platform_device *pdev) { optee_invoke_fn *invoke_fn; @@ -1372,6 +1505,10 @@ static int optee_probe(struct platform_device *pdev) if (IS_ERR(invoke_fn)) return PTR_ERR(invoke_fn); + rc = optee_load_fw(pdev, invoke_fn); + if (rc) + return rc; + if (!optee_msg_api_uid_is_optee_api(invoke_fn)) { pr_warn("api uid mismatch\n"); return -EINVAL; From 3c3e8a92ae57e5d5cc03abdf15970432d80ac4a5 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 3 Apr 2023 09:54:15 +0200 Subject: [PATCH 0729/1040] ARM: dts: stm32: YAML validation fails for STM32MP15 ST Boards "make dtbs_check" gives following output : stm32mp157x-xxx.dt.yaml: gpu@59000000: 'contiguous-area' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml Solve this trouble for STM32MPU Boards : - stm32mp157c-ed1 - stm32mp157x-dkx Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-ed1.dts | 9 --------- arch/arm/boot/dts/stm32mp15xx-dkx.dtsi | 9 --------- 2 files changed, 18 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 2dfde6292668..8beb901be506 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -69,11 +69,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@e8000000 { - reg = <0xe8000000 0x8000000>; - no-map; - }; }; sd_switch: regulator-sd_switch { @@ -140,10 +135,6 @@ status = "okay"; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index ded5ab9a4798..cefeeb00fc22 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -59,11 +59,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; }; led { @@ -157,10 +152,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; From 84a34e1862aae43e4dcdfb743a7dd3ade1fe4a3c Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 3 Apr 2023 09:58:31 +0200 Subject: [PATCH 0730/1040] ARM: dts: stm32: YAML validation fails for Odyssey Boards "make dtbs_check" gives following output : stm32mp157c-odyssey.dt.yaml: gpu@59000000: 'contiguous-area' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi index 2d9461006810..e22871dc580c 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -62,11 +62,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@d4000000 { - reg = <0xd4000000 0x4000000>; - no-map; - }; }; led { @@ -80,11 +75,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; - status = "okay"; -}; - &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; From fc8d2b21bc5d5d7a6eadaa8c2a5d2e6856689480 Mon Sep 17 00:00:00 2001 From: Pierre-Yves MORDRET Date: Mon, 3 Apr 2023 10:01:06 +0200 Subject: [PATCH 0731/1040] ARM: dts: stm32: YAML validation fails for Argon Boards "make dtbs_check" gives following output : stm32mp157c-emstamp-argon.dtb: gpu@59000000: 'contiguous-area' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpu/vivante,gc.yaml Signed-off-by: Pierre-Yves MORDRET Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi | 9 --------- 1 file changed, 9 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index 7d11c50b9e40..b01470a9a3d5 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -68,11 +68,6 @@ reg = <0x38000000 0x10000>; no-map; }; - - gpu_reserved: gpu@dc000000 { - reg = <0xdc000000 0x4000000>; - no-map; - }; }; led: gpio_leds { @@ -183,10 +178,6 @@ }; }; -&gpu { - contiguous-area = <&gpu_reserved>; -}; - &hash1 { status = "okay"; }; From 645a603783633a9d6e2bbaaa98d4cac847d97b2c Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Tue, 28 Mar 2023 19:07:11 +0200 Subject: [PATCH 0732/1040] ARM: dts: stm32: add FMC support on STM32MP13x SoC family Add FMC support on STM32MP13x SoC family. Signed-off-by: Christophe Kerello Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 9ea61687f023..7ea1fe0cd070 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -1232,6 +1232,39 @@ dma-requests = <48>; }; + fmc: memory-controller@58002000 { + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + #address-cells = <2>; + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + nand-controller@4,0 { + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, + <&mdma 24 0x2 0x12000a08 0x0 0x0>, + <&mdma 25 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x20253180>; From 8768487fc6cc5ed13705978057f1cfa3e1ce1e4c Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 31 Mar 2023 09:19:07 +0200 Subject: [PATCH 0733/1040] ARM: dts: stm32: Add QSPI support on STM32MP13x SoC family Add QSPI support on STM32MP13x SoC family Signed-off-by: Patrice Chotard Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 7ea1fe0cd070..d163c267e34c 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -1265,6 +1265,21 @@ }; }; + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, + <&mdma 26 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + sdmmc1: mmc@58005000 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x20253180>; From 60b3a99a3b50c94814b84795e38e2161767ea277 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 1 Mar 2023 15:47:55 +0200 Subject: [PATCH 0734/1040] firmware: tegra: bpmp: Fix error paths in debugfs Some error paths in mrq_debug_read and bpmp_debug_show would overwrite the return error code with a subsequent call to mrq_debug_close. Change the code to only change the error code if there was no prior error. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/firmware/tegra/bpmp-debugfs.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/tegra/bpmp-debugfs.c b/drivers/firmware/tegra/bpmp-debugfs.c index 3ca2b5d9e66f..6dfe3d34109e 100644 --- a/drivers/firmware/tegra/bpmp-debugfs.c +++ b/drivers/firmware/tegra/bpmp-debugfs.c @@ -193,7 +193,7 @@ static int mrq_debug_read(struct tegra_bpmp *bpmp, const char *name, }, }; u32 fd = 0, len = 0; - int remaining, err; + int remaining, err, close_err; mutex_lock(&bpmp_debug_lock); err = mrq_debug_open(bpmp, name, &fd, &len, 0); @@ -231,7 +231,9 @@ static int mrq_debug_read(struct tegra_bpmp *bpmp, const char *name, *nbytes = len; close: - err = mrq_debug_close(bpmp, fd); + close_err = mrq_debug_close(bpmp, fd); + if (!err) + err = close_err; out: mutex_unlock(&bpmp_debug_lock); return err; @@ -319,7 +321,7 @@ static int bpmp_debug_show(struct seq_file *m, void *p) }, }; u32 fd = 0, len = 0; - int remaining, err; + int remaining, err, close_err; filename = get_filename(bpmp, file, fnamebuf, sizeof(fnamebuf)); if (!filename) @@ -353,7 +355,9 @@ static int bpmp_debug_show(struct seq_file *m, void *p) } close: - err = mrq_debug_close(bpmp, fd); + close_err = mrq_debug_close(bpmp, fd); + if (!err) + err = close_err; out: mutex_unlock(&bpmp_debug_lock); return err; From 61228c9b240468dba55ef8a4ac93e777c810c68b Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 1 Mar 2023 15:47:56 +0200 Subject: [PATCH 0735/1040] soc/tegra: bpmp: Actually free memory on error path Within the error path, genpd->domains has not been set, so we need to pass the domains variable to kfree instead. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/soc/tegra/powergate-bpmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/tegra/powergate-bpmp.c b/drivers/soc/tegra/powergate-bpmp.c index 8eaf50d0b6af..179ed895c279 100644 --- a/drivers/soc/tegra/powergate-bpmp.c +++ b/drivers/soc/tegra/powergate-bpmp.c @@ -286,7 +286,7 @@ remove: tegra_powergate_remove(powergate); } - kfree(genpd->domains); + kfree(domains); return err; } From 161e0f78b396823e8596ae5e709d93acd914dad3 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 6 Mar 2023 15:09:00 +0000 Subject: [PATCH 0736/1040] soc/tegra: pmc: Add the PMIC wake event for Tegra234 Add the PMIC wake event for Tegra234 that is used to bring the device out of system suspend for events such as an RTC alarm. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index cf4cfbf9f7c5..e3e87d5da9f5 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -4225,6 +4225,7 @@ static const char * const tegra234_reset_sources[] = { }; static const struct tegra_wake_event tegra234_wake_events[] = { + TEGRA_WAKE_IRQ("pmu", 24, 209), TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), TEGRA_WAKE_IRQ("rtc", 73, 10), }; From cc026ccdd502c3709f06aadfde14d1eac6cc3763 Mon Sep 17 00:00:00 2001 From: Sushil Singh Date: Thu, 23 Mar 2023 18:43:24 +0530 Subject: [PATCH 0737/1040] soc/tegra: pmc: Add wake source interrupt for MGBE Add the GPIO wake interrupt for MGBE ethernet controller on Tegra234 SoC. Signed-off-by: Sushil Singh Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index e3e87d5da9f5..d478be88d580 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3,7 +3,7 @@ * drivers/soc/tegra/pmc.c * * Copyright (c) 2010 Google, Inc - * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * * Author: * Colin Cross @@ -4227,6 +4227,7 @@ static const char * const tegra234_reset_sources[] = { static const struct tegra_wake_event tegra234_wake_events[] = { TEGRA_WAKE_IRQ("pmu", 24, 209), TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), + TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)), TEGRA_WAKE_IRQ("rtc", 73, 10), }; From a0941221c5c6d4574af69b40ac026c22c24965fc Mon Sep 17 00:00:00 2001 From: Petlozu Pravareshwar Date: Thu, 30 Mar 2023 17:06:21 +0000 Subject: [PATCH 0738/1040] soc/tegra: pmc: Support software wake-up for SPE The Sensor Processing Engine(SPE) can trigger a software wake-up of the device. To support this wake-up for the SPE, set SR_CAPTURE_EN bit in WAKE_AOWAKE_CNTRL register associated with the wake-up for the SPE. This SR capturing logic is expected to be enabled for wakes with short pulse signalling requirements. Signed-off-by: Viswanath L Signed-off-by: Petlozu Pravareshwar Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index d478be88d580..5d17799524c9 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -177,6 +177,7 @@ /* Tegra186 and later */ #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2)) #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3) +#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1) #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2)) #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2)) #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2)) @@ -191,6 +192,8 @@ #define WAKE_AOWAKE_CTRL 0x4f4 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) +#define SW_WAKE_ID 83 /* wake83 */ + /* for secure PMC */ #define TEGRA_SMC_PMC 0xc2fffe00 #define TEGRA_SMC_PMC_READ 0xaa @@ -355,6 +358,7 @@ struct tegra_pmc_soc { void (*setup_irq_polarity)(struct tegra_pmc *pmc, struct device_node *np, bool invert); + void (*set_wake_filters)(struct tegra_pmc *pmc); int (*irq_set_wake)(struct irq_data *data, unsigned int on); int (*irq_set_type)(struct irq_data *data, unsigned int type); int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id, @@ -2416,6 +2420,17 @@ static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type) return 0; } +static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc) +{ + u32 value; + + /* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */ + value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); + value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN; + writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID)); + dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value); +} + static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on) { struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); @@ -3042,6 +3057,10 @@ static int tegra_pmc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pmc); tegra_pm_init_suspend(); + /* Some wakes require specific filter configuration */ + if (pmc->soc->set_wake_filters) + pmc->soc->set_wake_filters(pmc); + return 0; cleanup_powergates: @@ -3938,6 +3957,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = { .regs = &tegra186_pmc_regs, .init = tegra186_pmc_init, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .set_wake_filters = tegra186_pmc_set_wake_filters, .irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_type = tegra186_pmc_irq_set_type, .reset_sources = tegra186_reset_sources, @@ -4122,6 +4142,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = { .regs = &tegra194_pmc_regs, .init = tegra186_pmc_init, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .set_wake_filters = tegra186_pmc_set_wake_filters, .irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_type = tegra186_pmc_irq_set_type, .reset_sources = tegra194_reset_sources, @@ -4249,6 +4270,7 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { .regs = &tegra234_pmc_regs, .init = tegra186_pmc_init, .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, + .set_wake_filters = tegra186_pmc_set_wake_filters, .irq_set_wake = tegra186_pmc_irq_set_wake, .irq_set_type = tegra186_pmc_irq_set_type, .reset_sources = tegra234_reset_sources, From 71de0a054d0ee1f9d0b13401330069cdb8f3e50a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 23 Jan 2023 16:15:43 +0100 Subject: [PATCH 0739/1040] arm64: tegra: Drop serial clock-names and reset-names The serial node does not use clock-names and reset-names: tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected) Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 8 -------- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 -- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ---- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 8 -------- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 -- 5 files changed, 24 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index c017764bc27e..8b78be8f4f9d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -338,9 +338,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTA>; - clock-names = "serial"; resets = <&tegra_car 6>; - reset-names = "serial"; dmas = <&apbdma 8>, <&apbdma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -352,9 +350,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTB>; - clock-names = "serial"; resets = <&tegra_car 7>; - reset-names = "serial"; dmas = <&apbdma 9>, <&apbdma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -366,9 +362,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTC>; - clock-names = "serial"; resets = <&tegra_car 55>; - reset-names = "serial"; dmas = <&apbdma 10>, <&apbdma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -380,9 +374,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA124_CLK_UARTD>; - clock-names = "serial"; resets = <&tegra_car 65>; - reset-names = "serial"; dmas = <&apbdma 19>, <&apbdma 19>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index efc450821398..7e4c496fd91c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -610,9 +610,7 @@ reg-shift = <2>; interrupts = ; clocks = <&bpmp TEGRA186_CLK_UARTA>; - clock-names = "serial"; resets = <&bpmp TEGRA186_RESET_UARTA>; - reset-names = "serial"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 133dbe5b429d..2ddade14fe4b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -745,9 +745,7 @@ reg-shift = <2>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_UARTA>; - clock-names = "serial"; resets = <&bpmp TEGRA194_RESET_UARTA>; - reset-names = "serial"; status = "disabled"; }; @@ -757,9 +755,7 @@ reg-shift = <2>; interrupts = ; clocks = <&bpmp TEGRA194_CLK_UARTB>; - clock-names = "serial"; resets = <&bpmp TEGRA194_RESET_UARTB>; - reset-names = "serial"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 980565bf02c9..0e463b3cbe01 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -618,9 +618,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTA>; - clock-names = "serial"; resets = <&tegra_car 6>; - reset-names = "serial"; dmas = <&apbdma 8>, <&apbdma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -632,9 +630,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTB>; - clock-names = "serial"; resets = <&tegra_car 7>; - reset-names = "serial"; dmas = <&apbdma 9>, <&apbdma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -646,9 +642,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTC>; - clock-names = "serial"; resets = <&tegra_car 55>; - reset-names = "serial"; dmas = <&apbdma 10>, <&apbdma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -660,9 +654,7 @@ reg-shift = <2>; interrupts = ; clocks = <&tegra_car TEGRA210_CLK_UARTD>; - clock-names = "serial"; resets = <&tegra_car 65>; - reset-names = "serial"; dmas = <&apbdma 19>, <&apbdma 19>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8fe8eda7654d..b9caf6d2d975 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -676,9 +676,7 @@ reg = <0x0 0x03100000 0x0 0x10000>; interrupts = ; clocks = <&bpmp TEGRA234_CLK_UARTA>; - clock-names = "serial"; resets = <&bpmp TEGRA234_RESET_UARTA>; - reset-names = "serial"; status = "disabled"; }; From 8e0ae0fb4b91655bcdca2a4d7d16ebb81fc5d786 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Mon, 6 Mar 2023 15:01:57 +0000 Subject: [PATCH 0740/1040] arm64: tegra: Add DSU PMUs for Tegra234 Populate the DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) devices for Tegra234 which has one DSU PMU per CPU cluster. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index b9caf6d2d975..01504ede6334 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3400,6 +3400,24 @@ }; }; + dsu-pmu0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; + }; + + dsu-pmu1 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; + }; + + dsu-pmu2 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; + }; + pmu { compatible = "arm,cortex-a78-pmu"; interrupts = ; From 37f9514e618f3b95125d7eda8991a7ae3b17da96 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Sun, 2 Apr 2023 16:47:23 +0200 Subject: [PATCH 0741/1040] ARM: dts: exynos: replace mshc0 alias with mmc-ddr-1_8v property Previously, the mshc0 alias has been necessary so that MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA are set for mshc_0/mmc_0. However, these capabilities should be described in the device tree so that we do not have to rely on the alias. The property mmc-ddr-1_8v replaces MMC_CAP_1_8V_DDR, while bus_width = <8>, which is already set for all the mshc0/mmc0 nodes, replaces MMC_CAP_8_BIT_DATA. Also drop other mshc aliases as they are not needed. Signed-off-by: Henrik Grimler Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230402144724.17839-2-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 1 + arch/arm/boot/dts/exynos3250-monk.dts | 1 + arch/arm/boot/dts/exynos3250-rinato.dts | 1 + arch/arm/boot/dts/exynos3250.dtsi | 3 --- arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 1 + arch/arm/boot/dts/exynos4412-midas.dtsi | 1 + arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 1 + arch/arm/boot/dts/exynos4412-origen.dts | 1 + arch/arm/boot/dts/exynos4412-p4note.dtsi | 1 + arch/arm/boot/dts/exynos4412.dtsi | 1 - arch/arm/boot/dts/exynos5250-arndale.dts | 1 + arch/arm/boot/dts/exynos5250-smdk5250.dts | 1 + arch/arm/boot/dts/exynos5250-snow-common.dtsi | 1 + arch/arm/boot/dts/exynos5250-spring.dts | 1 + arch/arm/boot/dts/exynos5250.dtsi | 4 ---- arch/arm/boot/dts/exynos5260-xyref5260.dts | 1 + arch/arm/boot/dts/exynos5410-odroidxu.dts | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 1 + arch/arm/boot/dts/exynos5420-arndale-octa.dts | 1 + arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi | 1 + arch/arm/boot/dts/exynos5420-peach-pit.dts | 1 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 1 + arch/arm/boot/dts/exynos5420.dtsi | 3 --- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 + arch/arm/boot/dts/exynos5422-samsung-k3g.dts | 1 + arch/arm/boot/dts/exynos5800-peach-pi.dts | 1 + 26 files changed, 22 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 0ac3f284fbb8..b81e1a9df126 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -321,6 +321,7 @@ vmmc-supply = <&ldo12_reg>; clock-frequency = <100000000>; max-frequency = <100000000>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 80d90fe7fad1..861c26824d4f 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -443,6 +443,7 @@ vmmc-supply = <&vemmc_reg>; clock-frequency = <100000000>; max-frequency = <100000000>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 1f9cba0607e1..a252a5f667eb 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -624,6 +624,7 @@ vmmc-supply = <&ldo12_reg>; clock-frequency = <100000000>; max-frequency = <100000000>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <1>; samsung,dw-mshc-sdr-timing = <0 1>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index cb2c59c98c4a..bd37f1b587f0 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -28,9 +28,6 @@ aliases { pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; - mshc0 = &mshc_0; - mshc1 = &mshc_1; - mshc2 = &mshc_2; spi0 = &spi_0; spi1 = &spi_1; i2c0 = &i2c_0; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index e42e39dc0e40..ca8d42b2ce3b 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -476,6 +476,7 @@ vmmc-supply = <&buck9_reg>; broken-cd; card-detect-delay = <200>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 3be48de5c130..82aed59cba7c 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -977,6 +977,7 @@ samsung,dw-mshc-ciu-div = <0>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; + mmc-ddr-1_8v; pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 7c2780d3e37c..25e082fda955 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -533,6 +533,7 @@ broken-cd; card-detect-delay = <200>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index ea9fd284386d..f6cebf73b839 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -498,6 +498,7 @@ broken-cd; card-detect-delay = <200>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 317e248f354b..9052b3ebb3e8 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -693,6 +693,7 @@ samsung,dw-mshc-ciu-div = <0>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; + mmc-ddr-1_8v; pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; bus-width = <4>; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 7fa3e5fd6801..82a36fb5ee8b 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -28,7 +28,6 @@ pinctrl3 = &pinctrl_3; fimc-lite0 = &fimc_lite_0; fimc-lite1 = &fimc_lite_1; - mshc0 = &mshc_0; }; bus_acp: bus-acp { diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index c03bb436bfed..8f01337bb291 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -589,6 +589,7 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-1_8v; }; &mmc_2 { diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 831b3494bd46..f7d4017e1ede 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -350,6 +350,7 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-1_8v; }; &mmc_2 { diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 3d84b9c6dea3..dea2dc818578 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -549,6 +549,7 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-1_8v; }; /* uSD card */ diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 5eca10ecd550..8980cdbdcb3b 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -431,6 +431,7 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-1_8v; }; /* diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 89c8665ac9aa..1a4c6c028d03 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -30,10 +30,6 @@ gsc1 = &gsc_1; gsc2 = &gsc_2; gsc3 = &gsc_3; - mshc0 = &mmc_0; - mshc1 = &mmc_1; - mshc2 = &mmc_2; - mshc3 = &mmc_3; i2c4 = &i2c_4; i2c5 = &i2c_5; i2c6 = &i2c_6; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 387b8494f18f..0fd728bc0b75 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -89,6 +89,7 @@ cap-mmc-highspeed; mmc-hs200-1_8v; card-detect-delay = <200>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 6ddd1dd2fb0b..1ed73f3b4ac0 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -513,6 +513,7 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>; bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-1_8v; mmc-hs200-1_8v; vmmc-supply = <&ldo20_reg>; vqmmc-supply = <&ldo11_reg>; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index b8f953c41c73..b4a74f9cf319 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -61,6 +61,7 @@ cap-mmc-highspeed; broken-cd; card-detect-delay = <200>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 55b7759682a9..5ed55a5b0c67 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -778,6 +778,7 @@ status = "okay"; non-removable; card-detect-delay = <200>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi index 63675fe189cd..6a51cb14b58a 100644 --- a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi +++ b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi @@ -604,6 +604,7 @@ bus-width = <8>; cap-mmc-highspeed; card-detect-delay = <200>; + mmc-ddr-1_8v; mmc-hs200-1_8v; non-removable; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 9e2123470cad..df863b909ff7 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -722,6 +722,7 @@ /* eMMC flash */ &mmc_0 { status = "okay"; + mmc-ddr-1_8v; mmc-hs200-1_8v; cap-mmc-highspeed; non-removable; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 4d7b6d9008a7..0a9371bec3e0 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -355,6 +355,7 @@ status = "okay"; broken-cd; card-detect-delay = <200>; + mmc-ddr-1_8v; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 17dec11fb773..dd291f1199f2 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -19,9 +19,6 @@ compatible = "samsung,exynos5420", "samsung,exynos5"; aliases { - mshc0 = &mmc_0; - mshc1 = &mmc_1; - mshc2 = &mmc_2; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index e6e7e2ff2a26..d1b8e59e2daf 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -472,6 +472,7 @@ pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd &sd0_rclk>; bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; max-frequency = <200000000>; diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts index df41723d56d4..13134592c199 100644 --- a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts +++ b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts @@ -597,6 +597,7 @@ /* eMMC flash */ &mmc_0 { status = "okay"; + mmc-ddr-1_8v; mmc-hs200-1_8v; cap-mmc-highspeed; non-removable; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 0ebcb66c6319..37af8fbd215c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -703,6 +703,7 @@ /* eMMC flash */ &mmc_0 { status = "okay"; + mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; cap-mmc-highspeed; From 3ddba33dc270209868de79f695e5b27afa49e230 Mon Sep 17 00:00:00 2001 From: Henrik Grimler Date: Sun, 2 Apr 2023 16:47:24 +0200 Subject: [PATCH 0742/1040] ARM: dts: exynos: add mmc aliases Add aliases for eMMC, SD card and WiFi where applicable, so that assigned mmc indeces are always the same. Co-developed-by: Anton Bambura Signed-off-by: Anton Bambura [ Tested on exynos5800-peach-pi ] Tested-by: Valentine Iourine Signed-off-by: Henrik Grimler Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20230402144724.17839-3-henrik@grimler.se Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5-eval.dts | 4 ++++ arch/arm/boot/dts/exynos3250-artik5.dtsi | 5 +++++ arch/arm/boot/dts/exynos3250-monk.dts | 1 + arch/arm/boot/dts/exynos3250-rinato.dts | 2 ++ arch/arm/boot/dts/exynos4210-i9100.dts | 6 ++++++ arch/arm/boot/dts/exynos4210-origen.dts | 5 +++++ arch/arm/boot/dts/exynos4210-smdkv310.dts | 4 ++++ arch/arm/boot/dts/exynos4210-trats.dts | 6 ++++++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 6 ++++++ arch/arm/boot/dts/exynos4412-itop-elite.dts | 4 ++++ arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 4 ++++ arch/arm/boot/dts/exynos4412-midas.dtsi | 3 +++ arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 5 +++++ arch/arm/boot/dts/exynos4412-origen.dts | 5 +++++ arch/arm/boot/dts/exynos4412-p4note.dtsi | 6 ++++++ arch/arm/boot/dts/exynos4412-smdk4412.dts | 4 ++++ arch/arm/boot/dts/exynos4412-tiny4412.dts | 4 ++++ arch/arm/boot/dts/exynos5250-arndale.dts | 5 +++++ arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 ++ arch/arm/boot/dts/exynos5250-snow-common.dtsi | 3 +++ arch/arm/boot/dts/exynos5250-spring.dts | 5 +++++ arch/arm/boot/dts/exynos5260-xyref5260.dts | 5 +++++ arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 ++ arch/arm/boot/dts/exynos5410-smdk5410.dts | 5 +++++ arch/arm/boot/dts/exynos5420-arndale-octa.dts | 5 +++++ arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi | 5 +++++ arch/arm/boot/dts/exynos5420-peach-pit.dts | 3 +++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 5 +++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 ++++ arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 4 ++++ arch/arm/boot/dts/exynos5422-samsung-k3g.dts | 4 ++++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 3 +++ 32 files changed, 134 insertions(+) diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts index a1e22f630638..660cc7fac4db 100644 --- a/arch/arm/boot/dts/exynos3250-artik5-eval.dts +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -16,6 +16,10 @@ model = "Samsung ARTIK5 evaluation board"; compatible = "samsung,artik5-eval", "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; + + aliases { + mmc0 = &mshc_2; + }; }; &mshc_2 { diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index b81e1a9df126..3fdd922e635c 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -17,6 +17,11 @@ / { compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; + aliases { + mmc0 = &mshc_0; + mmc1 = &mshc_1; + }; + chosen { stdout-path = &serial_2; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 861c26824d4f..2de877d4ccc5 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -22,6 +22,7 @@ aliases { i2c7 = &i2c_max77836; + mmc0 = &mshc_0; }; memory@40000000 { diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index a252a5f667eb..88fb3e68ff02 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -23,6 +23,8 @@ aliases { i2c7 = &i2c_max77836; + mmc0 = &mshc_0; + mmc1 = &mshc_1; }; chosen { diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index bba85011ecc9..37cd4dde53e4 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -25,6 +25,12 @@ reg = <0x40000000 0x40000000>; }; + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + mmc2 = &sdhci_3; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 1103e7f92b57..f1927ca15e08 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -30,6 +30,11 @@ 0x70000000 0x10000000>; }; + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + }; + chosen { bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; stdout-path = "serial2:115200n8"; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 181c99eca675..b566f878ed84 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -25,6 +25,10 @@ reg = <0x40000000 0x80000000>; }; + aliases { + mmc0 = &sdhci_2; + }; + chosen { bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; stdout-path = "serial1:115200n8"; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index b8e9dd23fc51..ff6ee4b2c31b 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -26,6 +26,12 @@ 0x70000000 0x10000000>; }; + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + mmc2 = &sdhci_3; + }; + chosen { bootargs = "root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; stdout-path = "serial2:115200n8"; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 140abfb38e1d..8fe0d5d2be2d 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -24,6 +24,12 @@ 0x50000000 0x10000000>; }; + aliases { + mmc0 = &sdhci_0; + mmc1 = &sdhci_2; + mmc2 = &sdhci_3; + }; + chosen { bootargs = "root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; stdout-path = "serial2:115200n8"; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 6260da187e92..ded232b04e0d 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -20,6 +20,10 @@ model = "TOPEET iTop 4412 Elite board based on Exynos4412"; compatible = "topeet,itop4412-elite", "samsung,exynos4412", "samsung,exynos4"; + aliases { + mmc1 = &sdhci_2; + }; + chosen { bootargs = "root=/dev/mmcblk0p2 rw rootfstype=ext4 rootdelay=1 rootwait"; stdout-path = "serial2:115200n8"; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index ca8d42b2ce3b..7bc6968af9c3 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -23,6 +23,10 @@ reg = <0x40000000 0x40000000>; }; + aliases { + mmc0 = &mshc_0; + }; + firmware@203f000 { compatible = "samsung,secure-firmware"; reg = <0x0203f000 0x1000>; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 82aed59cba7c..e6b949c1a00f 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -25,6 +25,9 @@ aliases { i2c11 = &i2c_max77693; i2c12 = &i2c_max77693_fuel; + mmc0 = &mshc_0; + mmc2 = &sdhci_2; + mmc3 = &sdhci_3; }; chosen { diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 25e082fda955..45ef7b7ba7e0 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -13,6 +13,11 @@ #include "exynos-mfc-reserved-memory.dtsi" / { + aliases { + mmc0 = &mshc_0; + mmc2 = &sdhci_2; + }; + chosen { stdout-path = &serial_1; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index f6cebf73b839..23b151645d66 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -25,6 +25,11 @@ reg = <0x40000000 0x40000000>; }; + aliases { + mmc0 = &mshc_0; + mmc1 = &sdhci_2; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 9052b3ebb3e8..0b89d5682f85 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -26,6 +26,12 @@ reg = <0x40000000 0x80000000>; }; + aliases { + mmc0 = &mshc_0; + mmc2 = &sdhci_2; + mmc3 = &sdhci_3; + }; + chosen { stdout-path = &serial_2; }; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index a40ff394977c..715dfcba1417 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -22,6 +22,10 @@ reg = <0x40000000 0x40000000>; }; + aliases { + mmc0 = &sdhci_2; + }; + chosen { bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M init=/linuxrc"; stdout-path = "serial1:115200n8"; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index e0b6162d2e2a..5a2dcdc5c28b 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -17,6 +17,10 @@ model = "FriendlyARM TINY4412 board based on Exynos4412"; compatible = "friendlyarm,tiny4412", "samsung,exynos4412", "samsung,exynos4"; + aliases { + mmc0 = &sdhci_2; + }; + chosen { stdout-path = &serial_0; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 8f01337bb291..d586189966da 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -23,6 +23,11 @@ reg = <0x40000000 0x80000000>; }; + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index f7d4017e1ede..bb623726ef1e 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -17,6 +17,8 @@ compatible = "samsung,smdk5250", "samsung,exynos5250", "samsung,exynos5"; aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; }; memory@40000000 { diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index dea2dc818578..59b2cc35c37b 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -15,6 +15,9 @@ / { aliases { i2c104 = &i2c_104; + mmc0 = &mmc_0; /* eMMC */ + mmc1 = &mmc_2; /* SD */ + mmc2 = &mmc_3; /* WiFi */ }; memory@40000000 { diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 8980cdbdcb3b..c12bb17631b7 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -23,6 +23,11 @@ reg = <0x40000000 0x80000000>; }; + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_1; + }; + chosen { bootargs = "console=tty1"; stdout-path = "serial3:115200n8"; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 0fd728bc0b75..d072a7398866 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -18,6 +18,11 @@ reg = <0x20000000 0x80000000>; }; + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 1ed73f3b4ac0..882fc77c4bc4 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -21,6 +21,8 @@ aliases { ethernet = ðernet; + mmc0 = &mmc_0; + mmc1 = &mmc_2; }; memory@40000000 { diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index b4a74f9cf319..bb29b76f6f6a 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -18,6 +18,11 @@ reg = <0x40000000 0x80000000>; }; + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 5ed55a5b0c67..809ddda02e53 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -23,6 +23,11 @@ reg = <0x20000000 0x80000000>; }; + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + chosen { stdout-path = "serial3:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi index 6a51cb14b58a..f525b2f5e4e0 100644 --- a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi +++ b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi @@ -28,6 +28,11 @@ * for more details. */ + aliases { + mmc0 = &mmc_0; + mmc2 = &mmc_2; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index df863b909ff7..7a48f2b32819 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -31,6 +31,9 @@ aliases { /* Assign 20 so we don't get confused w/ builtin ones */ i2c20 = &i2c_tunnel; + mmc0 = &mmc_0; /* eMMC */ + mmc1 = &mmc_2; /* uSD */ + mmc2 = &mmc_1; /* WiFi */ }; backlight: backlight { diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 0a9371bec3e0..e299344e427a 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -21,6 +21,11 @@ reg = <0x20000000 0x80000000>; }; + aliases { + mmc0 = &mmc_0; + mmc1 = &mmc_2; + }; + chosen { bootargs = "init=/linuxrc"; stdout-path = "serial2:115200n8"; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 30fc677d8bac..2f5b8602e020 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -19,6 +19,10 @@ reg = <0x40000000 0x7ea00000>; }; + aliases { + mmc2 = &mmc_2; + }; + chosen { stdout-path = "serial2:115200n8"; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d1b8e59e2daf..b4a851aa8881 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -13,6 +13,10 @@ #include "exynos5422-odroid-core.dtsi" / { + aliases { + mmc0 = &mmc_0; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts index 13134592c199..c35261a338ff 100644 --- a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts +++ b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts @@ -19,6 +19,10 @@ chassis-type = "handset"; + aliases { + mmc0 = &mmc_0; + }; + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x80000000>; /* 2 GiB */ diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 37af8fbd215c..1f544f12da6c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -29,6 +29,9 @@ aliases { /* Assign 20 so we don't get confused w/ builtin ones */ i2c20 = &i2c_tunnel; + mmc0 = &mmc_0; /* eMMC */ + mmc1 = &mmc_2; /* SD */ + mmc2 = &mmc_1; /* WiFi */ }; backlight: backlight { From 75dfbcbfd781f826c73ebe42b78d49c23179d082 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:51 +0000 Subject: [PATCH 0743/1040] mailbox: mpfs: fix an incorrect mask width The system controller registers on PolarFire SoC are 32 bits wide, so 16 + 16 as the first input to GENMASK_ULL() gives a 33 bit wide mask. It probably should have been immediately obvious when it was pointed out during review that the width required using GENMASK_ULL() - but I scarcely knew what I was doing at the time and missed it. The mistake ends up being moot as it is a mask after all, but it is incorrect and should be fixed. No functional change intended. Acked-by: Jassi Brar Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/mailbox/mailbox-mpfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 853901acaeec..d37560e91116 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -39,7 +39,7 @@ #define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY) #define SCB_CTRL_POS (16) -#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS) +#define SCB_CTRL_MASK GENMASK(SCB_CTRL_POS + SCB_MASK_WIDTH - 1, SCB_CTRL_POS) /* SCBCTRL service status register */ @@ -118,6 +118,7 @@ static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data) } opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu)); + tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK; tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK; writel_relaxed(tx_trigger, mbox->ctrl_base + SERVICES_CR_OFFSET); From b5984a9844fc45cd301a28fb56f3de95f7e20f3c Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:52 +0000 Subject: [PATCH 0744/1040] mailbox: mpfs: switch to txdone_poll The system controller on PolarFire SoC has no interrupt to signify that the TX has been completed. The interrupt instead signals that a service requested by the mailbox client has succeeded. If a service fails, there will be no interrupt delivered. Switch to polling the busy register to determine whether transmission has completed. Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Acked-by: Jassi Brar Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/mailbox/mailbox-mpfs.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index d37560e91116..e0e825bdbad9 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -79,6 +79,13 @@ static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) return status & SCB_STATUS_BUSY_MASK; } +static bool mpfs_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; + + return !mpfs_mbox_busy(mbox); +} + static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data) { struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; @@ -183,7 +190,6 @@ static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data) mpfs_mbox_rx_data(chan); - mbox_chan_txdone(chan, 0); return IRQ_HANDLED; } @@ -213,6 +219,7 @@ static const struct mbox_chan_ops mpfs_mbox_ops = { .send_data = mpfs_mbox_send_data, .startup = mpfs_mbox_startup, .shutdown = mpfs_mbox_shutdown, + .last_tx_done = mpfs_mbox_last_tx_done, }; static int mpfs_mbox_probe(struct platform_device *pdev) @@ -248,7 +255,8 @@ static int mpfs_mbox_probe(struct platform_device *pdev) mbox->controller.num_chans = 1; mbox->controller.chans = mbox->chans; mbox->controller.ops = &mpfs_mbox_ops; - mbox->controller.txdone_irq = true; + mbox->controller.txdone_poll = true; + mbox->controller.txpoll_period = 10u; ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller); if (ret) { From da82f95f7c0752f36cdb8ff99d543004e4e3acdf Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:53 +0000 Subject: [PATCH 0745/1040] mailbox: mpfs: ditch a useless busy check mpfs_mbox_rx_data() already checks if the system controller is busy before attempting to do anything, so drop the second check before reading any data. No functional change intended. Acked-by: Jassi Brar Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/mailbox/mailbox-mpfs.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index e0e825bdbad9..0d176aba3462 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -170,12 +170,10 @@ static void mpfs_mbox_rx_data(struct mbox_chan *chan) if (response->resp_status) return; - if (!mpfs_mbox_busy(mbox)) { - for (i = 0; i < num_words; i++) { - response->resp_msg[i] = - readl_relaxed(mbox->mbox_base - + mbox->resp_offset + i * 0x4); - } + for (i = 0; i < num_words; i++) { + response->resp_msg[i] = + readl_relaxed(mbox->mbox_base + + mbox->resp_offset + i * 0x4); } mbox_chan_received_data(chan, response); From 37e3430176ff333afb013314a6c949660d75cc92 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:54 +0000 Subject: [PATCH 0746/1040] mailbox: mpfs: check the service status in .tx_done() Services are supposed to generate an interrupt once completed, whether or not they have do so successfully. What appears to be a bug in the system controller means that interrupts are only generated for *successful* services. Currently, the status of a service is only checked in the mpfs_mbox_rx_data() once an interrupt is received. As it turns out, this is not really helpful where the potentially buggy behaviour is present, as we'll only see the status for successes where it is moot anyway. Jassi suggested moving the check to the .tx_done() callback instead. This makes sense, as the busy bit that tx_done() is polling will be lowered on completion, regardless of whether the service passed or failed. That allows us to check the status bits for all services, whether they generate an interrupt or not & pass something more informative than -EBADMSG back to the drivers implementing individual services. Suggested-by: Jassi Brar Acked-by: Jassi Brar Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/mailbox/mailbox-mpfs.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c index 0d176aba3462..162df49654fb 100644 --- a/drivers/mailbox/mailbox-mpfs.c +++ b/drivers/mailbox/mailbox-mpfs.c @@ -82,8 +82,22 @@ static bool mpfs_mbox_busy(struct mpfs_mbox *mbox) static bool mpfs_mbox_last_tx_done(struct mbox_chan *chan) { struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; + struct mpfs_mss_response *response = mbox->response; + u32 val; - return !mpfs_mbox_busy(mbox); + if (mpfs_mbox_busy(mbox)) + return false; + + /* + * The service status is stored in bits 31:16 of the SERVICES_SR + * register & is only valid when the system controller is not busy. + * Failed services are intended to generated interrupts, but in reality + * this does not happen, so the status must be checked here. + */ + val = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); + response->resp_status = (val & SCB_STATUS_MASK) >> SCB_STATUS_POS; + + return true; } static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data) @@ -138,7 +152,7 @@ static void mpfs_mbox_rx_data(struct mbox_chan *chan) struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv; struct mpfs_mss_response *response = mbox->response; u16 num_words = ALIGN((response->resp_size), (4)) / 4U; - u32 i, status; + u32 i; if (!response->resp_msg) { dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM); @@ -146,8 +160,6 @@ static void mpfs_mbox_rx_data(struct mbox_chan *chan) } /* - * The status is stored in bits 31:16 of the SERVICES_SR register. - * It is only valid when BUSY == 0. * We should *never* get an interrupt while the controller is * still in the busy state. If we do, something has gone badly * wrong & the content of the mailbox would not be valid. @@ -158,18 +170,6 @@ static void mpfs_mbox_rx_data(struct mbox_chan *chan) return; } - status = readl_relaxed(mbox->ctrl_base + SERVICES_SR_OFFSET); - - /* - * If the status of the individual servers is non-zero, the service has - * failed. The contents of the mailbox at this point are not be valid, - * so don't bother reading them. Set the status so that the driver - * implementing the service can handle the result. - */ - response->resp_status = (status & SCB_STATUS_MASK) >> SCB_STATUS_POS; - if (response->resp_status) - return; - for (i = 0; i < num_words; i++) { response->resp_msg[i] = readl_relaxed(mbox->mbox_base From 5ca631ec757bed5843e39c91c8f52d1789991756 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:55 +0000 Subject: [PATCH 0747/1040] soc: microchip: mpfs: fix some horrible alignment mpfs_sys_controller_delete() has some horrible alignment that upsets my OCD... Move the RHS of the assignment to a new line for greater satifaction. Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/soc/microchip/mpfs-sys-controller.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index 6e20207b5756..12039cb38b33 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -66,8 +66,8 @@ static void rx_callback(struct mbox_client *client, void *msg) static void mpfs_sys_controller_delete(struct kref *kref) { - struct mpfs_sys_controller *sys_controller = container_of(kref, struct mpfs_sys_controller, - consumers); + struct mpfs_sys_controller *sys_controller = + container_of(kref, struct mpfs_sys_controller, consumers); mbox_free_channel(sys_controller->chan); kfree(sys_controller); From 4f739af1934ad7195db35f74cfbdca264668d8fc Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:56 +0000 Subject: [PATCH 0748/1040] soc: microchip: mpfs: use a consistent completion timeout Completion timeouts use jiffies, so passing a number directly will produce inconsistent timeouts depending on config. Define the timeout in ms and convert it to jiffies instead. Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/soc/microchip/mpfs-sys-controller.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index 12039cb38b33..738ecd624d64 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -11,12 +11,15 @@ #include #include #include +#include #include #include #include #include #include +#define MPFS_SYS_CTRL_TIMEOUT_MS 100 + static DEFINE_MUTEX(transaction_lock); struct mpfs_sys_controller { @@ -28,6 +31,7 @@ struct mpfs_sys_controller { int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct mpfs_mss_msg *msg) { + unsigned long timeout = msecs_to_jiffies(MPFS_SYS_CTRL_TIMEOUT_MS); int ret, err; err = mutex_lock_interruptible(&transaction_lock); @@ -38,7 +42,7 @@ int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct ret = mbox_send_message(sys_controller->chan, msg); if (ret >= 0) { - if (wait_for_completion_timeout(&sys_controller->c, HZ)) { + if (wait_for_completion_timeout(&sys_controller->c, timeout)) { ret = 0; } else { ret = -ETIMEDOUT; From 7606f4dfffa7a4e4aadd8aef918cc8ac1f1e2196 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:57 +0000 Subject: [PATCH 0749/1040] soc: microchip: mpfs: simplify error handling in mpfs_blocking_transaction() The error handling has a kinda weird nested-if setup that is not really adding anything. Switch it to more of an early return arrangement as a predatory step for adding different handing for timeouts and failed services. Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/soc/microchip/mpfs-sys-controller.c | 27 ++++++++++----------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index 738ecd624d64..e61ba9b7aae3 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -32,28 +32,27 @@ struct mpfs_sys_controller { int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct mpfs_mss_msg *msg) { unsigned long timeout = msecs_to_jiffies(MPFS_SYS_CTRL_TIMEOUT_MS); - int ret, err; + int ret; - err = mutex_lock_interruptible(&transaction_lock); - if (err) - return err; + ret = mutex_lock_interruptible(&transaction_lock); + if (ret) + return ret; reinit_completion(&sys_controller->c); ret = mbox_send_message(sys_controller->chan, msg); - if (ret >= 0) { - if (wait_for_completion_timeout(&sys_controller->c, timeout)) { - ret = 0; - } else { - ret = -ETIMEDOUT; - dev_warn(sys_controller->client.dev, - "MPFS sys controller transaction timeout\n"); - } + if (ret < 0) + goto out; + + if (!wait_for_completion_timeout(&sys_controller->c, timeout)) { + ret = -ETIMEDOUT; + dev_warn(sys_controller->client.dev, "MPFS sys controller transaction timeout\n"); } else { - dev_err(sys_controller->client.dev, - "mpfs sys controller transaction returned %d\n", ret); + /* mbox_send_message() returns positive integers on success */ + ret = 0; } +out: mutex_unlock(&transaction_lock); return ret; From 8f943dd12eeff71857b9a1ca45adbaaba379bf30 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 20:22:58 +0000 Subject: [PATCH 0750/1040] soc: microchip: mpfs: handle timeouts and failed services differently The system controller will only deliver an interrupt if a service succeeds. This leaves us in the unfortunate position with current code where there is no way to differentiate between a legitimate timeout where the service has not completed & where it has completed, but failed. mbox_send_message() has its own completion, and it will time out of the system controller does not lower the busy flag. In this case, a timeout has occurred and the error can be propagated back to the caller. If the busy flag is lowered, but no interrupt has arrived to trigger the rx callback, the service can be deemed to have failed. Report -EBADMSG in this case so that callers can differentiate. Tested-by: Valentina Fernandez Signed-off-by: Conor Dooley --- drivers/soc/microchip/mpfs-sys-controller.c | 27 +++++++++++++++++---- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index e61ba9b7aae3..ceaeebc1fc6b 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -18,7 +18,11 @@ #include #include -#define MPFS_SYS_CTRL_TIMEOUT_MS 100 +/* + * This timeout must be long, as some services (example: image authentication) + * take significant time to complete + */ +#define MPFS_SYS_CTRL_TIMEOUT_MS 30000 static DEFINE_MUTEX(transaction_lock); @@ -41,14 +45,26 @@ int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct reinit_completion(&sys_controller->c); ret = mbox_send_message(sys_controller->chan, msg); - if (ret < 0) + if (ret < 0) { + dev_warn(sys_controller->client.dev, "MPFS sys controller service timeout\n"); goto out; + } + /* + * Unfortunately, the system controller will only deliver an interrupt + * if a service succeeds. mbox_send_message() will block until the busy + * flag is gone. If the busy flag is gone but no interrupt has arrived + * to trigger the rx callback then the service can be deemed to have + * failed. + * The caller can then interrogate msg::response::resp_status to + * determine the cause of the failure. + * mbox_send_message() returns positive integers in the success path, so + * ret needs to be cleared if we do get an interrupt. + */ if (!wait_for_completion_timeout(&sys_controller->c, timeout)) { - ret = -ETIMEDOUT; - dev_warn(sys_controller->client.dev, "MPFS sys controller transaction timeout\n"); + ret = -EBADMSG; + dev_warn(sys_controller->client.dev, "MPFS sys controller service failed\n"); } else { - /* mbox_send_message() returns positive integers on success */ ret = 0; } @@ -107,6 +123,7 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev) sys_controller->client.dev = dev; sys_controller->client.rx_callback = rx_callback; sys_controller->client.tx_block = 1U; + sys_controller->client.tx_tout = msecs_to_jiffies(MPFS_SYS_CTRL_TIMEOUT_MS); sys_controller->chan = mbox_request_channel(&sys_controller->client, 0); if (IS_ERR(sys_controller->chan)) { From 4dd472bdafcb660bea17bc63a97d06e24fcb36ed Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 31 Mar 2023 08:18:17 +0100 Subject: [PATCH 0751/1040] soc: microchip: mpfs: add a prefix to rx_callback() Add a prefix to the function name to match the rest of the file. Signed-off-by: Conor Dooley --- drivers/soc/microchip/mpfs-sys-controller.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c index ceaeebc1fc6b..216d9f4ea0ce 100644 --- a/drivers/soc/microchip/mpfs-sys-controller.c +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -75,7 +75,7 @@ out: } EXPORT_SYMBOL(mpfs_blocking_transaction); -static void rx_callback(struct mbox_client *client, void *msg) +static void mpfs_sys_controller_rx_callback(struct mbox_client *client, void *msg) { struct mpfs_sys_controller *sys_controller = container_of(client, struct mpfs_sys_controller, client); @@ -121,7 +121,7 @@ static int mpfs_sys_controller_probe(struct platform_device *pdev) return -ENOMEM; sys_controller->client.dev = dev; - sys_controller->client.rx_callback = rx_callback; + sys_controller->client.rx_callback = mpfs_sys_controller_rx_callback; sys_controller->client.tx_block = 1U; sys_controller->client.tx_tout = msecs_to_jiffies(MPFS_SYS_CTRL_TIMEOUT_MS); From c3fbced9af885a6f217fd95509a613d6590916ce Mon Sep 17 00:00:00 2001 From: Zhaoyang Li Date: Mon, 27 Mar 2023 19:54:22 +0800 Subject: [PATCH 0752/1040] soc: bcm: brcmstb: biuctrl: fix of_iomap leak Smatch reports: drivers/soc/bcm/brcmstb/biuctrl.c:291 setup_hifcpubiuctrl_regs() warn: 'cpubiuctrl_base' from of_iomap() not released on lines: 291. This is because in setup_hifcpubiuctrl_regs(), cpubiuctrl_base is not released when handle error, which may cause a leak. To fix this, iounmap is added when handle error. Fixes: 22f7a9116eba ("soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs") Signed-off-by: Zhaoyang Li Reviewed-by: Dan Carpenter Reviewed-by: Dongliang Mu Link: https://lore.kernel.org/r/20230327115422.1536615-1-lizhaoyang04@hust.edu.cn Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index e1d7b4543248..364ddbe365c2 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -288,6 +288,10 @@ static int __init setup_hifcpubiuctrl_regs(struct device_node *np) if (BRCM_ID(family_id) == 0x7260 && BRCM_REV(family_id) == 0) cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs; out: + if (ret && cpubiuctrl_base) { + iounmap(cpubiuctrl_base); + cpubiuctrl_base = NULL; + } return ret; } From a1c11b345943ddebcc493bc18b7dc6e968834904 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 23 Jan 2023 10:34:44 +0900 Subject: [PATCH 0753/1040] arm64: dts: renesas: r8a779f0: Revise renesas,ipmmu-main Since IMSSTR register was undocumented on the latest datasheet and dt-bindings of renesas,ipmmu-vmsa was updated about the renesas,ipmmu-main property, revise the property on each cache IPMMU node. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20230123013448.1250991-2-yoshihiro.shimoda.uh@renesas.com [geert: Drop indices from renesas,ipmmu-main properties] Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index dc4d23daa8e8..1d5426e6293c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1059,7 +1059,7 @@ compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee480000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -1068,7 +1068,7 @@ compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee4c0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 19>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -1077,7 +1077,7 @@ compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -1086,7 +1086,7 @@ compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 2>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; From 432d5fedafe686c9894f303107473938856b0a4b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 23 Jan 2023 10:34:46 +0900 Subject: [PATCH 0754/1040] arm64: dts: renesas: r8a779g0: Add IPMMU nodes Add IPMMU nodes for r8a779g0. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20230123013448.1250991-4-yoshihiro.shimoda.uh@renesas.com [geert: Drop indices from renesas,ipmmu-main properties] [geert: s/hsc/hc/, s/vc0/vc/] Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 109 ++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 281f98fc3f16..bd078df28bc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1761,6 +1761,115 @@ }; }; + ipmmu_rt0: iommu@ee480000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee480000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_rt1: iommu@ee4c0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xee4c0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds0: iommu@eed00000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@eed40000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ir: iommu@eed80000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeed80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_A3IR>; + #iommu-cells = <1>; + }; + + ipmmu_vc: iommu@eedc0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeedc0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_3dg: iommu@eee00000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@eee80000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeee80000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: iommu@eeec0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeeec0000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip0: iommu@eef00000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeef00000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vip1: iommu@eef40000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeef40000 0 0x20000>; + renesas,ipmmu-main = <&ipmmu_mm>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@eefc0000 { + compatible = "renesas,ipmmu-r8a779g0", + "renesas,rcar-gen4-ipmmu-vmsa"; + reg = <0 0xeefc0000 0 0x20000>; + interrupts = , + ; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + mmc0: mmc@ee140000 { compatible = "renesas,sdhi-r8a779g0", "renesas,rcar-gen4-sdhi"; From 00a9526b218edeb51bd5ee5b49c257e2214a1a26 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 23 Jan 2023 10:34:47 +0900 Subject: [PATCH 0755/1040] arm64: dts: renesas: r8a779g0: Add iommus to DMAC nodes Add iommus properties to the DMAC nodes for r8a779g0. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230123013448.1250991-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index bd078df28bc4..039db06f668e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1655,6 +1655,14 @@ resets = <&cpg 709>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; }; dmac1: dma-controller@e7351000 { @@ -1690,6 +1698,14 @@ resets = <&cpg 710>; #dma-cells = <1>; dma-channels = <16>; + iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, + <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, + <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, + <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, + <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, + <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, + <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, + <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; }; rcar_sound: sound@ec5a0000 { From 166e023478696be40af1dd639af7ac89fea09003 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 23 Jan 2023 10:34:48 +0900 Subject: [PATCH 0756/1040] arm64: dts: renesas: r8a779g0: Add iommus to MMC node Add iommus property to the MMC node for r8a779g0. Signed-off-by: Yoshihiro Shimoda Tested-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230123013448.1250991-6-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 039db06f668e..d3d25e077c5d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1897,6 +1897,7 @@ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; resets = <&cpg 706>; max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; status = "disabled"; }; From 741f99c7ff7c508cfc0ede760ea089993b2327c3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Fri, 31 Mar 2023 16:14:31 +0200 Subject: [PATCH 0757/1040] arm64: dts: renesas: falcon-csi-dsi: Set bus-type for MAX96712 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Specify the bus-type property for all three connected MAX96712. The default behavior when parsing a node without this property is to default to D-PHY. Making this explicit plays it safe and future proofs things as the default parsing comes from the V4L2 core and not the driver itself. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230331141431.3820311-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi index e06b8eda85e1..dbc8dcab109d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -5,6 +5,8 @@ * Copyright (C) 2021 Glider bv */ +#include + &csi40 { status = "okay"; @@ -105,6 +107,7 @@ port@4 { reg = <4>; max96712_out0: endpoint { + bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3 4>; remote-endpoint = <&csi40_in>; @@ -125,6 +128,7 @@ port@4 { reg = <4>; max96712_out1: endpoint { + bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; @@ -146,6 +150,7 @@ port@4 { reg = <4>; max96712_out2: endpoint { + bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3 4>; lane-polarities = <0 0 0 0 1>; From 2f04079bf5920b5120407421478dff1d5692d959 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 4 Apr 2023 09:10:08 +0200 Subject: [PATCH 0758/1040] arm64: dts: renesas: r8a779a0: Revise renesas,ipmmu-main Since IMSSTR register was undocumented on the latest datasheet and dt-bindings of renesas,ipmmu-vmsa was updated about the renesas,ipmmu-main property, revise the property on each cache IPMMU node. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/ed4c21150e42dd23412a8f4af7976f81edc1c9c2.1680592069.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 7925341a69c8..bf587a14ec19 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2098,7 +2098,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee480000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 10>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2107,7 +2107,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee4c0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 19>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2116,7 +2116,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 0>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2125,7 +2125,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 1>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2134,7 +2134,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 3>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_A3IR>; #iommu-cells = <1>; }; @@ -2143,7 +2143,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeedc0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 12>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2152,7 +2152,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee80000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 14>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2161,7 +2161,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeeec0000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 15>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2170,7 +2170,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 6>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2179,7 +2179,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef00000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 5>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; @@ -2188,7 +2188,7 @@ compatible = "renesas,ipmmu-r8a779a0", "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef40000 0 0x20000>; - renesas,ipmmu-main = <&ipmmu_mm 11>; + renesas,ipmmu-main = <&ipmmu_mm>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; #iommu-cells = <1>; }; From fc187a46a8e682f0f1167b230792b88de01ceaa0 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Fri, 31 Mar 2023 17:55:44 +0800 Subject: [PATCH 0759/1040] soc: renesas: renesas-soc: Release 'chipid' from ioremap() Smatch reports: drivers/soc/renesas/renesas-soc.c:536 renesas_soc_init() warn: 'chipid' from ioremap() not released on lines: 475. If soc_dev_atrr allocation is failed, function renesas_soc_init() will return without releasing 'chipid' from ioremap(). Fix this by adding function iounmap(). Fixes: cb5508e47e60 ("soc: renesas: Add support for reading product revision for RZ/G2L family") Signed-off-by: Li Yang Reviewed-by: Dan Carpenter Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230331095545.31823-1-lidaxian@hust.edu.cn Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/renesas-soc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 4ba893e45427..42af7c09f743 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -469,8 +469,11 @@ static int __init renesas_soc_init(void) } soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) + if (!soc_dev_attr) { + if (chipid) + iounmap(chipid); return -ENOMEM; + } np = of_find_node_by_path("/"); of_property_read_string(np, "model", &soc_dev_attr->machine); From 062dfd995e8cbaf47f6cbf8bcdf5525439ebaa5e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 31 Mar 2023 18:29:11 +0200 Subject: [PATCH 0760/1040] dt-bindings: tegra: Document Jetson Orin NX The Jetson Orin NX is the latest iteration in the NX family of Jetson products. Document the compatible strings used for these devices. Acked-by: Rob Herring Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 1f62253f9410..c1a62eb1b925 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -167,5 +167,9 @@ properties: - const: nvidia,p3737-0000+p3701-0000 - const: nvidia,p3701-0000 - const: nvidia,tegra234 + - description: Jetson Orin NX + items: + - const: nvidia,p3767-0000 + - const: nvidia,tegra234 additionalProperties: true From d89baa52929f00e9052f61b4eef838ccc8ebf180 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 31 Mar 2023 18:29:12 +0200 Subject: [PATCH 0761/1040] dt-bindings: tegra: Document Jetson Orin NX reference platform Document the combination of the P3768 carrier board with the P3767 (Jetson Orin NX) module. Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/arm/tegra.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index c1a62eb1b925..0df41f5b7e2a 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -171,5 +171,10 @@ properties: items: - const: nvidia,p3767-0000 - const: nvidia,tegra234 + - description: Jetson Orin NX Engineering Reference Developer Kit + items: + - const: nvidia,p3768-0000+p3767-0000 + - const: nvidia,p3767-0000 + - const: nvidia,tegra234 additionalProperties: true From 13b0aca303e97500e6aa6fa7965c620394c67775 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 31 Mar 2023 18:29:13 +0200 Subject: [PATCH 0762/1040] arm64: tegra: Support Jetson Orin NX This adds a device tree for the Jetson Orin NX module, which is Jetson AGX Orin's little sibling with 6 or 8 ARM Cortex-A78AE cores, an Ampere GPU (1024 GPU and 32 tensor cores) and a number of accelerators for machine learning, image processing and more. The Jetson Orin NX comes with either 8 or 16 GiB of 128-bit LPDDR5 and supports NVME for mass storage. Signed-off-by: Thierry Reding --- .../boot/dts/nvidia/tegra234-p3767-0000.dtsi | 14 ++ .../arm64/boot/dts/nvidia/tegra234-p3767.dtsi | 172 ++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi new file mode 100644 index 000000000000..baf4f69e410d --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767-0000.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234-p3767.dtsi" + +/ { + compatible = "nvidia,p3767-0000", "nvidia,tegra234"; + model = "NVIDIA Jetson Orin NX"; + + bus@0 { + hda@3510000 { + nvidia,model = "NVIDIA Jetson Orin NX HDA"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi new file mode 100644 index 000000000000..bd60478fa75e --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "tegra234.dtsi" + +/ { + compatible = "nvidia,p3767", "nvidia,tegra234"; + + bus@0 { + i2c@3160000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + label = "module"; + vcc-supply = <&vdd_1v8_hs>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <136000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + + /* + * This only exists on Jetson Orin Nano Developer Kit (SKU 5) + * but UEFI needs this and will remove it on devices where it + * doesn't exist. + */ + mmc@3400000 { + status = "okay"; + bus-width = <4>; + cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_HIGH>; + disable-wp; + }; + + hda@3510000 { + status = "okay"; + }; + + padctl@3520000 { + vclamp-usb-supply = <&vdd_1v8_ao>; + avdd-usb-supply = <&vdd_3v3_ao>; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; + + vdd_5v0_sys: regulator-vdd-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_5V0_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vdd_1v8_hs: regulator-vdd-1v8-hs { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_HS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v8_ao: regulator-vdd-1v8-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_AO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_ao: regulator-vdd-3v3-ao { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_AO"; + regulator-min-microvolt = <33000000>; + regulator-max-microvolt = <33000000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; + + thermal-zones { + /* + * This monitoring is far from optimal, but it's good enough + * at this stage. + */ + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <1000>; + status = "okay"; + + trips { + critical { + temperature = <104500>; + hysteresis = <0>; + type = "critical"; + }; + + hot { + temperature = <99000>; + hysteresis = <1000>; + type = "hot"; + }; + + board_trip_passive: passive { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + board_trip_active2: active-2 { + temperature = <80000>; + hysteresis = <4000>; + type = "active"; + }; + + board_trip_active1: active-1 { + temperature = <65000>; + hysteresis = <4000>; + type = "active"; + }; + + board_trip_active0: active-0 { + temperature = <50000>; + hysteresis = <4000>; + type = "active"; + }; + }; + + cooling-maps { + passive { + cooling-device = <&fan 3 3>; + trip = <&board_trip_passive>; + }; + + active2 { + cooling-device = <&fan 2 3>; + trip = <&board_trip_active2>; + }; + + active1 { + cooling-device = <&fan 1 2>; + trip = <&board_trip_active1>; + }; + + active0 { + cooling-device = <&fan 0 1>; + trip = <&board_trip_active0>; + }; + }; + }; + }; +}; From e63472eda5ea84424e4bff2b809389b0ba266613 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 31 Mar 2023 18:29:14 +0200 Subject: [PATCH 0763/1040] arm64: tegra: Support Jetson Orin NX reference platform Add support for the combination of the NVIDIA Jetson Orin NX (P3767, SKU 0) module and the P3768 carrier board. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 2 + .../nvidia/tegra234-p3768-0000+p3767-0000.dts | 134 ++++++++++ .../boot/dts/nvidia/tegra234-p3768-0000.dtsi | 245 ++++++++++++++++++ 3 files changed, 381 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index bc34c9d8846a..1406d5d40b8f 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -9,6 +9,7 @@ DTC_FLAGS_tegra194-p2972-0000 := -@ DTC_FLAGS_tegra194-p3509-0000+p3668-0000 := -@ DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@ DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@ +DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@ dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb @@ -24,3 +25,4 @@ dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0001.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts new file mode 100644 index 000000000000..7dfbc38eb3c4 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include + +#include "tegra234-p3767-0000.dtsi" +#include "tegra234-p3768-0000.dtsi" + +/ { + compatible = "nvidia,p3768-0000+p3767-0000", "nvidia,p3767-0000", "nvidia,tegra234"; + model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit"; + + aliases { + serial0 = &tcu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bus@0 { + serial@31d0000 { + current-speed = <115200>; + status = "okay"; + }; + + pwm@32a0000 { + assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + status = "okay"; + }; + + hda@3510000 { + nvidia,model = "NVIDIA Jetson Orin NX HDA"; + status = "okay"; + }; + + padctl@3520000 { + status = "okay"; + }; + + /* C1 - M.2 Key-E */ + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + /* C4 - M.2 Key-M */ + pcie@14160000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + /* C8 - Ethernet */ + pcie@140a0000 { + status = "okay"; + + num-lanes = <2>; + + phys = <&p2u_gbe_2>, <&p2u_gbe_3>; + phy-names = "p2u-0", "p2u-1"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + }; + + /* C7 - M.2 Key-M */ + pcie@141e0000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_gbe_0>, <&p2u_gbe_1>; + phy-names = "p2u-0", "p2u-1"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + key-suspend { + label = "Suspend"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + cooling-levels = <0 95 178 255>; + #cooling-cells = <2>; + }; + + vdd_3v3_pcie: regulator-vdd-3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_PCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + serial { + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi new file mode 100644 index 000000000000..aee21428e1a5 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + compatible = "nvidia,p3768-0000"; + + aliases { + serial0 = &tcu; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bus@0 { + i2c@3160000 { + status = "okay"; + + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + + label = "system"; + vcc-supply = <&vdd_1v8_sys>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + + serial@31d0000 { + current-speed = <115200>; + status = "okay"; + }; + + pwm@32a0000 { + assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + status = "okay"; + }; + + padctl@3520000 { + status = "okay"; + + pads { + usb2 { + lanes { + usb2-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb2-2 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + + usb3 { + lanes { + usb3-0 { + nvidia,function = "xusb"; + status = "okay"; + }; + + usb3-1 { + nvidia,function = "xusb"; + status = "okay"; + }; + }; + }; + }; + + ports { + /* recovery port */ + usb2-0 { + mode = "otg"; + vbus-supply = <&vdd_5v0_sys>; + status = "okay"; + usb-role-switch; + }; + + /* hub */ + usb2-1 { + mode = "host"; + vbus-supply = <&vdd_1v1_hub>; + status = "okay"; + }; + + /* M.2 Key-E */ + usb2-2 { + mode = "host"; + vbus-supply = <&vdd_5v0_sys>; + status = "okay"; + }; + + /* hub */ + usb3-0 { + nvidia,usb2-companion = <1>; + status = "okay"; + }; + + /* J5 */ + usb3-1 { + nvidia,usb2-companion = <0>; + status = "okay"; + }; + }; + }; + + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb3-1"; + }; + + usb@3610000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>, + <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>, + <&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>; + phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", + "usb3-1"; + }; + + /* C1 - M.2 Key-E */ + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + /* C4 - M.2 Key-M */ + pcie@14160000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + /* C8 - Ethernet */ + pcie@140a0000 { + status = "okay"; + + num-lanes = <2>; + + phys = <&p2u_gbe_2>, <&p2u_gbe_3>; + phy-names = "p2u-0", "p2u-1"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + }; + + /* C7 - M.2 Key-M */ + pcie@141e0000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_gbe_0>, <&p2u_gbe_1>; + phy-names = "p2u-0", "p2u-1"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + key-suspend { + label = "Suspend"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm3 0 45334>; + cooling-levels = <0 95 178 255>; + #cooling-cells = <2>; + }; + + vdd_1v8_sys: regulator-vdd-1v8-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8_SYS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vdd_1v1_hub: regulator-vdd-1v1-hub { + compatible = "regulator-fixed"; + regulator-name = "VDD_AV10_HUB"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vdd_5v0_sys>; + regulator-always-on; + }; + + vdd_3v3_pcie: regulator-vdd-3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_PCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + serial { + status = "okay"; + }; +}; From 62a4276877d21fe8f42085b25db8351de9406643 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 29 Mar 2023 12:04:02 +0300 Subject: [PATCH 0764/1040] ARM: tegra: asus-tf101: Fix accelerometer mount matrix Accelerometer mount matrix used in tf101 downstream is inverted. This new matrix was generated on actual device using calibration script, like on other transformers. Tested-by: Robert Eckelmann Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-asus-tf101.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index 3f1da75a2736..c2a9c3fb5b33 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -577,9 +577,9 @@ vdd-supply = <&vdd_1v8_sys>; vddio-supply = <&vdd_1v8_sys>; - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "1"; + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; }; }; }; From b3f65f45303f2453f477044cd02f8285a4c65bf0 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 29 Mar 2023 12:04:03 +0300 Subject: [PATCH 0765/1040] ARM: tegra30: peripherals: Add 266.5MHz nodes LG Optimus Vu (p895) and Optimus 4X HD (p880) have 266.5MHz RAM clock and require this entry to work with it correctly. Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- .../arm/boot/dts/tegra30-peripherals-opp.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi index d100a1a8b705..a2d557155114 100644 --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi +++ b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi @@ -210,6 +210,20 @@ opp-suspend; }; + opp-266500000-1000 { + opp-microvolt = <1000000 1000000 1350000>; + opp-hz = /bits/ 64 <266500000>; + opp-supported-hw = <0x0007>; + required-opps = <&core_opp_1000>; + }; + + opp-266500000-1250 { + opp-microvolt = <1250000 1250000 1350000>; + opp-hz = /bits/ 64 <266500000>; + opp-supported-hw = <0x0008>; + required-opps = <&core_opp_1250>; + }; + opp-333500000-1000 { opp-microvolt = <1000000 1000000 1350000>; opp-hz = /bits/ 64 <333500000>; @@ -424,6 +438,12 @@ opp-suspend; }; + opp-266500000 { + opp-hz = /bits/ 64 <266500000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <2132000>; + }; + opp-333500000 { opp-hz = /bits/ 64 <333500000>; opp-supported-hw = <0x000F>; From 13a53ebc229996f424bbf7db466f1ff96f73e8a5 Mon Sep 17 00:00:00 2001 From: Maxim Schwalm Date: Wed, 29 Mar 2023 12:04:01 +0300 Subject: [PATCH 0766/1040] ARM: tegra30: Use cpu* labels Replace cpu paths with labels since those already exist in tree. Signed-off-by: Maxim Schwalm Signed-off-by: Svyatoslav Ryhel Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index b6fcac6016e0..9cba67b54111 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1283,10 +1283,7 @@ , , ; - interrupt-affinity = <&{/cpus/cpu@0}>, - <&{/cpus/cpu@1}>, - <&{/cpus/cpu@2}>, - <&{/cpus/cpu@3}>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; thermal-zones { From c94673e80377d67ba36ee4059d7814b2ab98fa71 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 31 Mar 2023 13:21:59 -0500 Subject: [PATCH 0767/1040] dt-bindings: arm: nvidia: Drop unneeded quotes Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml | 6 +++--- .../bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml | 6 +++--- .../bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml | 4 ++-- .../bindings/arm/tegra/nvidia,tegra194-cbb.yaml | 8 ++++---- .../bindings/arm/tegra/nvidia,tegra234-cbb.yaml | 4 ++-- .../bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml | 4 ++-- .../bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml | 4 ++-- .../bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml | 4 ++-- .../bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml | 4 ++-- 9 files changed, 22 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml index b6f57d79a753..84dc6b7512af 100644 --- a/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml +++ b/Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra194 CPU Complex @@ -25,7 +25,7 @@ properties: - nvidia,tegra194-ccplex nvidia,bpmp: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | Specifies the bpmp node that needs to be queried to get operating point data for all CPUs. diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml index 6089a96eae4f..36dbd0838f2d 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra CPU COMPLEX CLUSTER area @@ -29,7 +29,7 @@ properties: maxItems: 1 nvidia,bpmp: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | Specifies the BPMP node that needs to be queried to get operating point data for all CPUs. diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml index 788a13f8aa93..5e0f1dc542b0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra194 AXI2APB bridge diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml index dd3a4770c6a1..d9c54c32c6b9 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra194 CBB 1.0 @@ -64,13 +64,13 @@ properties: - description: secure interrupt nvidia,axi2apb: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: Specifies the node having all axi2apb bridges which need to be checked for any error logged in their status register. nvidia,apbmisc: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: Specifies the apbmisc node which need to be used for reading the ERD register. diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml index 44184ee01449..fcdf03131323 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra CBB 2.0 diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml index ed9554c837ef..ba4c6473ff92 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra NVDEC diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml index 8199e5fa8211..c23dae713eb8 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra NVENC diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml index 895fb346ac72..99a33a5eac3f 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra NVJPG diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml index 4bdc19a2bccf..0b7561c8b9bb 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra234 NVDEC From fc746270c2a5cc6eecaec9d81d000aaaa02b2f86 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 3 Apr 2023 09:42:20 +0200 Subject: [PATCH 0768/1040] ARM: configs: remove oxnas_v6_defconfig Due to lack of maintainance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX820 specific defconfig. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Signed-off-by: Arnd Bergmann --- arch/arm/configs/oxnas_v6_defconfig | 92 ----------------------------- 1 file changed, 92 deletions(-) delete mode 100644 arch/arm/configs/oxnas_v6_defconfig diff --git a/arch/arm/configs/oxnas_v6_defconfig b/arch/arm/configs/oxnas_v6_defconfig deleted file mode 100644 index 70a67b3fc91b..000000000000 --- a/arch/arm/configs/oxnas_v6_defconfig +++ /dev/null @@ -1,92 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_CGROUPS=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EMBEDDED=y -CONFIG_PERF_EVENTS=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_MULTI_V6=y -CONFIG_ARCH_OXNAS=y -CONFIG_MACH_OX820=y -CONFIG_SMP=y -CONFIG_NR_CPUS=16 -CONFIG_ARCH_FORCE_MAX_ORDER=12 -CONFIG_SECCOMP=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_KEXEC=y -CONFIG_EFI=y -CONFIG_CPU_IDLE=y -CONFIG_ARM_CPUIDLE=y -CONFIG_VFP=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_CMDLINE_PARTITION=y -CONFIG_CMA=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_OXNAS=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_NETDEVICES=y -CONFIG_STMMAC_ETH=y -CONFIG_REALTEK_PHY=y -CONFIG_INPUT_EVDEV=y -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_GPIO_GENERIC_PLATFORM=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_CLASS_FLASH=m -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_ARM_TIMER_SP804=y -CONFIG_EXT4_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_UBIFS_FS=y -CONFIG_PSTORE=y -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=y -CONFIG_DMA_CMA=y -CONFIG_CMA_SIZE_MBYTES=64 -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y From a9414bef866c575bf33465f55b1a3e7951eb2e4a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 3 Apr 2023 09:42:18 +0200 Subject: [PATCH 0769/1040] ARM: dts: oxnas: remove obsolete device tree files Due to lack of maintainance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 devices. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/Makefile | 3 - arch/arm/boot/dts/ox810se-wd-mbwe.dts | 115 ------ arch/arm/boot/dts/ox810se.dtsi | 357 ------------------ .../ox820-cloudengines-pogoplug-series-3.dts | 93 ----- arch/arm/boot/dts/ox820.dtsi | 299 --------------- 5 files changed, 867 deletions(-) delete mode 100644 arch/arm/boot/dts/ox810se-wd-mbwe.dts delete mode 100644 arch/arm/boot/dts/ox810se.dtsi delete mode 100644 arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts delete mode 100644 arch/arm/boot/dts/ox820.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ad06ab3c62af..d092993864f3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1041,9 +1041,6 @@ dtb-$(CONFIG_ARCH_PXA) += \ pxa300-raumfeld-speaker-m.dtb \ pxa300-raumfeld-speaker-one.dtb \ pxa300-raumfeld-speaker-s.dtb -dtb-$(CONFIG_ARCH_OXNAS) += \ - ox810se-wd-mbwe.dtb \ - ox820-cloudengines-pogoplug-series-3.dtb dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8016-sbc.dtb \ qcom-apq8026-asus-sparrow.dtb \ diff --git a/arch/arm/boot/dts/ox810se-wd-mbwe.dts b/arch/arm/boot/dts/ox810se-wd-mbwe.dts deleted file mode 100644 index c59e06ff2423..000000000000 --- a/arch/arm/boot/dts/ox810se-wd-mbwe.dts +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition - * - * Copyright (C) 2016 Neil Armstrong - */ - -/dts-v1/; -#include "ox810se.dtsi" - -/ { - model = "Western Digital My Book World Edition"; - - compatible = "wd,mbwe", "oxsemi,ox810se"; - - chosen { - bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; - }; - - memory { - /* 128Mbytes DDR */ - reg = <0x48000000 0x8000000>; - }; - - aliases { - serial1 = &uart1; - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - gpio-keys-polled { - compatible = "gpio-keys-polled"; - #address-cells = <1>; - #size-cells = <0>; - poll-interval = <100>; - - power { - label = "power"; - gpios = <&gpio0 0 1>; - linux,code = <0x198>; - }; - - recovery { - label = "recovery"; - gpios = <&gpio0 4 1>; - linux,code = <0xab>; - }; - }; - - leds { - compatible = "gpio-leds"; - - a0 { - label = "activity0"; - gpios = <&gpio0 25 0>; - default-state = "keep"; - }; - - a1 { - label = "activity1"; - gpios = <&gpio0 26 0>; - default-state = "keep"; - }; - - a2 { - label = "activity2"; - gpios = <&gpio0 5 0>; - default-state = "keep"; - }; - - a3 { - label = "activity3"; - gpios = <&gpio0 6 0>; - default-state = "keep"; - }; - - a4 { - label = "activity4"; - gpios = <&gpio0 7 0>; - default-state = "keep"; - }; - - a5 { - label = "activity5"; - gpios = <&gpio1 2 0>; - default-state = "keep"; - }; - }; - - i2c-gpio { - compatible = "i2c-gpio"; - gpios = <&gpio0 3 0 /* sda */ - &gpio0 2 0 /* scl */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - #address-cells = <1>; - #size-cells = <0>; - - rtc0: rtc@48 { - compatible = "st,m41t00"; - reg = <0x68>; - }; - }; -}; - -ða { - status = "okay"; -}; - -&uart1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -}; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi deleted file mode 100644 index 96c0745f7b70..000000000000 --- a/arch/arm/boot/dts/ox810se.dtsi +++ /dev/null @@ -1,357 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC - * - * Copyright (C) 2016 Neil Armstrong - */ - -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "oxsemi,ox810se"; - - cpus { - #address-cells = <0>; - #size-cells = <0>; - - cpu { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - clocks = <&armclk>; - }; - }; - - memory { - device_type = "memory"; - /* Max 256MB @ 0x48000000 */ - reg = <0x48000000 0x10000000>; - }; - - clocks { - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - gmacclk: gmacclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - rpsclk: rpsclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc>; - }; - - pll400: pll400 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <733333333>; - }; - - sysclk: sysclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&pll400>; - }; - - armclk: armclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clocks = <&pll400>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&intc>; - - etha: ethernet@40400000 { - compatible = "oxsemi,ox810se-dwmac", "snps,dwmac"; - reg = <0x40400000 0x2000>; - interrupts = <8>; - interrupt-names = "macirq"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - phy-mode = "rgmii"; - - clocks = <&stdclk 6>, <&gmacclk>; - clock-names = "gmac", "stmmaceth"; - resets = <&reset 6>; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - status = "disabled"; - }; - - apb-bridge@44000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x44000000 0x1000000>; - - pinctrl: pinctrl { - compatible = "oxsemi,ox810se-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart0: uart0 { - uart0a { - pins = "gpio31"; - function = "fct3"; - }; - uart0b { - pins = "gpio32"; - function = "fct3"; - }; - }; - - pinctrl_uart0_modem: uart0_modem { - uart0c { - pins = "gpio27"; - function = "fct3"; - }; - uart0d { - pins = "gpio28"; - function = "fct3"; - }; - uart0e { - pins = "gpio29"; - function = "fct3"; - }; - uart0f { - pins = "gpio30"; - function = "fct3"; - }; - uart0g { - pins = "gpio33"; - function = "fct3"; - }; - uart0h { - pins = "gpio34"; - function = "fct3"; - }; - }; - - pinctrl_uart1: uart1 { - uart1a { - pins = "gpio20"; - function = "fct3"; - }; - uart1b { - pins = "gpio22"; - function = "fct3"; - }; - }; - - pinctrl_uart1_modem: uart1_modem { - uart1c { - pins = "gpio8"; - function = "fct3"; - }; - uart1d { - pins = "gpio9"; - function = "fct3"; - }; - uart1e { - pins = "gpio23"; - function = "fct3"; - }; - uart1f { - pins = "gpio24"; - function = "fct3"; - }; - uart1g { - pins = "gpio25"; - function = "fct3"; - }; - uart1h { - pins = "gpio26"; - function = "fct3"; - }; - }; - - pinctrl_uart2: uart2 { - uart2a { - pins = "gpio6"; - function = "fct3"; - }; - uart2b { - pins = "gpio7"; - function = "fct3"; - }; - }; - - pinctrl_uart2_modem: uart2_modem { - uart2c { - pins = "gpio0"; - function = "fct3"; - }; - uart2d { - pins = "gpio1"; - function = "fct3"; - }; - uart2e { - pins = "gpio2"; - function = "fct3"; - }; - uart2f { - pins = "gpio3"; - function = "fct3"; - }; - uart2g { - pins = "gpio4"; - function = "fct3"; - }; - uart2h { - pins = "gpio5"; - function = "fct3"; - }; - }; - }; - - gpio0: gpio@0 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x000000 0x100000>; - interrupts = <21>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <32>; - oxsemi,gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - gpio1: gpio@100000 { - compatible = "oxsemi,ox810se-gpio"; - reg = <0x100000 0x100000>; - interrupts = <22>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <3>; - oxsemi,gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 3>; - }; - - uart0: serial@200000 { - compatible = "ns16550a"; - reg = <0x200000 0x100000>; - clocks = <&sysclk>; - interrupts = <23>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART1>; - }; - - uart1: serial@300000 { - compatible = "ns16550a"; - reg = <0x300000 0x100000>; - clocks = <&sysclk>; - interrupts = <24>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART2>; - }; - - uart2: serial@900000 { - compatible = "ns16550a"; - reg = <0x900000 0x100000>; - clocks = <&sysclk>; - interrupts = <29>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART3>; - }; - - uart3: serial@a00000 { - compatible = "ns16550a"; - reg = <0xa00000 0x100000>; - clocks = <&sysclk>; - interrupts = <30>; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - resets = <&reset RESET_UART4>; - }; - }; - - apb-bridge@45000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x45000000 0x1000000>; - - sys: sys-ctrl@0 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; - - stdclk: stdclk { - compatible = "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; - }; - - rps@300000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x300000 0x100000>; - - intc: interrupt-controller@0 { - compatible = "oxsemi,ox810se-rps-irq"; - interrupt-controller; - reg = <0 0x200>; - #interrupt-cells = <1>; - valid-mask = <0xffffffff>; - clear-mask = <0xffffffff>; - }; - - timer0: timer@200 { - compatible = "oxsemi,ox810se-rps-timer"; - reg = <0x200 0x40>; - clocks = <&rpsclk>; - interrupts = <4 5>; - }; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts deleted file mode 100644 index c3daceccde55..000000000000 --- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3 - * - * Copyright (C) 2016 Neil Armstrong - */ - -/dts-v1/; -#include "ox820.dtsi" - -/ { - model = "Cloud Engines PogoPlug Series 3"; - - compatible = "cloudengines,pogoplugv3", "oxsemi,ox820"; - - chosen { - bootargs = "earlyprintk"; - stdout-path = "serial0:115200n8"; - }; - - memory { - /* 128Mbytes DDR */ - reg = <0x60000000 0x8000000>; - }; - - aliases { - serial0 = &uart0; - gpio0 = &gpio0; - gpio1 = &gpio1; - }; - - leds { - compatible = "gpio-leds"; - - blue { - label = "pogoplug:blue"; - gpios = <&gpio0 2 0>; - default-state = "keep"; - }; - - orange { - label = "pogoplug:orange"; - gpios = <&gpio1 16 1>; - default-state = "keep"; - }; - - green { - label = "pogoplug:green"; - gpios = <&gpio1 17 1>; - default-state = "keep"; - }; - }; -}; - -&uart0 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; -}; - -&nandc { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nand>; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-ecc-mode = "soft"; - nand-ecc-algo = "hamming"; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00e00000>; - read-only; - }; - - partition@e00000 { - label = "ubi"; - reg = <0x00e00000 0x07200000>; - }; - }; -}; - -ða { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etha_mdio>; -}; diff --git a/arch/arm/boot/dts/ox820.dtsi b/arch/arm/boot/dts/ox820.dtsi deleted file mode 100644 index dde4364892bf..000000000000 --- a/arch/arm/boot/dts/ox820.dtsi +++ /dev/null @@ -1,299 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC - * - * Copyright (C) 2016 Neil Armstrong - */ - -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "oxsemi,ox820"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "oxsemi,ox820-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - clocks = <&armclk>; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,arm11mpcore"; - clocks = <&armclk>; - reg = <1>; - }; - }; - - memory { - device_type = "memory"; - /* Max 512MB @ 0x60000000 */ - reg = <0x60000000 0x20000000>; - }; - - clocks { - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - gmacclk: gmacclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - }; - - sysclk: sysclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - clocks = <&osc>; - }; - - plla: plla { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <850000000>; - }; - - armclk: armclk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - clocks = <&plla>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges; - interrupt-parent = <&gic>; - - nandc: nand-controller@41000000 { - compatible = "oxsemi,ox820-nand"; - reg = <0x41000000 0x100000>; - clocks = <&stdclk CLK_820_NAND>; - resets = <&reset RESET_NAND>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - etha: ethernet@40400000 { - compatible = "oxsemi,ox820-dwmac", "snps,dwmac"; - reg = <0x40400000 0x2000>; - interrupts = , - ; - interrupt-names = "macirq", "eth_wake_irq"; - mac-address = [000000000000]; /* Filled in by U-Boot */ - phy-mode = "rgmii"; - - clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; - clock-names = "gmac", "stmmaceth"; - resets = <&reset RESET_MAC>; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - status = "disabled"; - }; - - apb-bridge@44000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x44000000 0x1000000>; - - pinctrl: pinctrl { - compatible = "oxsemi,ox820-pinctrl"; - - /* Regmap for sys registers */ - oxsemi,sys-ctrl = <&sys>; - - pinctrl_uart0: uart0 { - uart0 { - pins = "gpio30", "gpio31"; - function = "fct5"; - }; - }; - - pinctrl_uart0_modem: uart0_modem { - uart0_modem_a { - pins = "gpio24", "gpio24", "gpio26", "gpio27"; - function = "fct4"; - }; - uart0_modem_b { - pins = "gpio28", "gpio29"; - function = "fct5"; - }; - }; - - pinctrl_uart1: uart1 { - uart1 { - pins = "gpio7", "gpio8"; - function = "fct4"; - }; - }; - - pinctrl_uart1_modem: uart1_modem { - uart1_modem { - pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43"; - function = "fct4"; - }; - }; - - pinctrl_etha_mdio: etha_mdio { - etha_mdio { - pins = "gpio3", "gpio4"; - function = "fct1"; - }; - }; - - pinctrl_nand: nand { - nand { - pins = "gpio12", "gpio13", "gpio14", "gpio15", - "gpio16", "gpio17", "gpio18", "gpio19", - "gpio20", "gpio21", "gpio22", "gpio23", - "gpio24"; - function = "fct1"; - }; - }; - }; - - gpio0: gpio@0 { - compatible = "oxsemi,ox820-gpio"; - reg = <0x000000 0x100000>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <32>; - oxsemi,gpio-bank = <0>; - gpio-ranges = <&pinctrl 0 0 32>; - }; - - gpio1: gpio@100000 { - compatible = "oxsemi,ox820-gpio"; - reg = <0x100000 0x100000>; - interrupts = ; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - ngpios = <18>; - oxsemi,gpio-bank = <1>; - gpio-ranges = <&pinctrl 0 32 18>; - }; - - uart0: serial@200000 { - compatible = "ns16550a"; - reg = <0x200000 0x100000>; - interrupts = ; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - clocks = <&sysclk>; - resets = <&reset RESET_UART1>; - }; - - uart1: serial@300000 { - compatible = "ns16550a"; - reg = <0x200000 0x100000>; - interrupts = ; - reg-shift = <0>; - fifo-size = <16>; - reg-io-width = <1>; - current-speed = <115200>; - no-loopback-test; - status = "disabled"; - clocks = <&sysclk>; - resets = <&reset RESET_UART2>; - }; - - rps@400000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x400000 0x100000>; - - intc: interrupt-controller@0 { - compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq"; - interrupt-controller; - reg = <0 0x200>; - interrupts = ; - #interrupt-cells = <1>; - valid-mask = <0xffffffff>; - clear-mask = <0xffffffff>; - }; - - timer0: timer@200 { - compatible = "oxsemi,ox820-rps-timer"; - reg = <0x200 0x40>; - clocks = <&sysclk>; - interrupt-parent = <&intc>; - interrupts = <4>; - }; - }; - - sys: sys-ctrl@e00000 { - compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"; - reg = <0xe00000 0x200000>; - - reset: reset-controller { - compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; - - stdclk: stdclk { - compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk"; - #clock-cells = <1>; - }; - }; - }; - - apb-bridge@47000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0 0x47000000 0x1000000>; - - scu: scu@0 { - compatible = "arm,arm11mp-scu"; - reg = <0x0 0x100>; - }; - - local-timer@600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x600 0x20>; - interrupts = ; - clocks = <&armclk>; - }; - - gic: interrupt-controller@1000 { - compatible = "arm,arm11mp-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x1000 0x1000>, - <0x100 0x500>; - }; - }; - }; -}; From 03216cdbd7df38aabf5fffac588a366177f5434a Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 3 Apr 2023 09:42:21 +0200 Subject: [PATCH 0770/1040] dt-bindings: arm: oxnas: remove obsolete bindings Due to lack of maintainance and stall of development for a few years now, and since no new features will ever be added upstream, remove the OX810 and OX820 SoC and boards bindings. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Signed-off-by: Neil Armstrong Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/oxnas.txt | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt deleted file mode 100644 index ac64e60f99f1..000000000000 --- a/Documentation/devicetree/bindings/arm/oxnas.txt +++ /dev/null @@ -1,14 +0,0 @@ -Oxford Semiconductor OXNAS SoCs Family device tree bindings -------------------------------------------- - -Boards with the OX810SE SoC shall have the following properties: - Required root node property: - compatible: "oxsemi,ox810se" - -Boards with the OX820 SoC shall have the following properties: - Required root node property: - compatible: "oxsemi,ox820" - -Board compatible values: - - "wd,mbwe" (OX810SE) - - "cloudengines,pogoplugv3" (OX820) From b903a6c5aaa862f8b88f4be4431ccca3b6fbc187 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Mon, 13 Feb 2023 10:14:34 +0530 Subject: [PATCH 0771/1040] arm64: tegra: Audio codec support on Jetson AGX Orin Jetson AGX Orin has onboard RT5640 audio codec. This patch adds the codec device node and the bindings to I2S1 interface. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 8a9747855d6b..ddc057f01f24 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -3,6 +3,7 @@ #include #include +#include #include "tegra234-p3701-0000.dtsi" #include "tegra234-p3737-0000.dtsi" @@ -49,7 +50,7 @@ i2s1_dap: endpoint { dai-format = "i2s"; - /* placeholder for external codec */ + remote-endpoint = <&rt5640_ep>; }; }; }; @@ -2017,6 +2018,30 @@ status = "okay"; }; + i2c@31e0000 { + status = "okay"; + + audio-codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>; + clock-names = "mclk"; + realtek,dmic1-data-pin = ; + realtek,dmic2-data-pin = ; + realtek,jack-detect-source = ; + sound-name-prefix = "CVB-RT"; + + port { + rt5640_ep: endpoint { + remote-endpoint = <&i2s1_dap>; + mclk-fs = <256>; + }; + }; + }; + }; + pwm@32a0000 { assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; @@ -2293,5 +2318,23 @@ <&dmic3_port>; label = "NVIDIA Jetson AGX Orin APE"; + + widgets = "Microphone", "CVB-RT MIC Jack", + "Microphone", "CVB-RT MIC", + "Headphone", "CVB-RT HP Jack", + "Speaker", "CVB-RT SPK"; + + routing = /* I2S1 <-> RT5640 */ + "CVB-RT AIF1 Playback", "I2S1 DAP-Playback", + "I2S1 DAP-Capture", "CVB-RT AIF1 Capture", + /* RT5640 codec controls */ + "CVB-RT HP Jack", "CVB-RT HPOL", + "CVB-RT HP Jack", "CVB-RT HPOR", + "CVB-RT IN1P", "CVB-RT MIC Jack", + "CVB-RT IN2P", "CVB-RT MIC Jack", + "CVB-RT SPK", "CVB-RT SPOLP", + "CVB-RT SPK", "CVB-RT SPORP", + "CVB-RT DMIC1", "CVB-RT MIC", + "CVB-RT DMIC2", "CVB-RT MIC"; }; }; From 3244442406ff49e8f75a1f2def211c497710570f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 9 Mar 2023 10:14:52 +0100 Subject: [PATCH 0772/1040] arm64: dts: qcom: msm8916: Move WCN compatible to boards On MSM8916 the wireless connectivity functionality (WiFi/Bluetooth) is split into the digital part inside the SoC and the analog RF part inside a supplementary WCN36xx chip. For MSM8916, three different options exist: - WCN3620 (WLAN 802.11 b/g/n 2.4 GHz + Bluetooth) - WCN3660B (WLAN 802.11 a/b/g/n 2.4/5 GHz + Bluetooth) - WCN3680B (WLAN 802.11ac 2.4/5 GHz + Bluetooth) Choosing one of these is up to the board vendor. This means that the compatible belongs into the board-specific DT part so people porting new boards pay attention to set the correct compatible. Right now msm8916.dtsi sets "qcom,wcn3620" as default compatible, which does not work at all for boards that have WCN3660B or WCN3680B. Remove the default compatible from msm8196.dtsi and move it to the board DT as follows: - Boards with only &pronto { status = "okay"; } used the default "qcom,wcn3620" so far. They now set this explicitly for &wcnss_iris. - Boards with &pronto { ... iris { compatible = "qcom,wcn3660b"; }}; already had an override that just moves to &wcnss_iris now. - For msm8916-samsung-a2015-common.dtsi the WCN compatible differs for boards making use of it (a3u: wcn3620, a5u: wcn3660b, e2015: wcn3620) so the definitions move to the board-specific DT part. Since this requires touching all the board DTs, use this as a chance to name the WCNSS-related labels consistently, so everything is grouped properly when sorted alphabetically. No functional change, just clean-up for more clarity & easier porting. Aside from ordering the generated DTBs are identical. Signed-off-by: Stephan Gerhold Reviewed-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230309091452.1011776-1-stephan.gerhold@kernkonzept.com --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 15 ++++++++----- .../boot/dts/qcom/msm8916-acer-a1-724.dts | 12 ++++++---- .../boot/dts/qcom/msm8916-alcatel-idol347.dts | 12 ++++++---- .../arm64/boot/dts/qcom/msm8916-asus-z00l.dts | 12 ++++++---- .../boot/dts/qcom/msm8916-gplus-fl8005a.dts | 12 ++++++---- .../arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 12 ++++++---- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 12 ++++++---- .../boot/dts/qcom/msm8916-longcheer-l8910.dts | 12 ++++++---- arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi | 22 +++++++++---------- .../qcom/msm8916-samsung-a2015-common.dtsi | 4 ---- .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 8 +++++++ .../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 14 +++++++----- .../qcom/msm8916-samsung-e2015-common.dtsi | 8 +++++++ .../dts/qcom/msm8916-samsung-gt5-common.dtsi | 16 +++++++------- .../dts/qcom/msm8916-samsung-j5-common.dtsi | 12 ++++++---- .../dts/qcom/msm8916-samsung-serranove.dts | 16 +++++++------- arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi | 12 ++++++---- .../dts/qcom/msm8916-wingtech-wt88047.dts | 12 ++++++---- arch/arm64/boot/dts/qcom/msm8916.dtsi | 13 +++++------ 19 files changed, 146 insertions(+), 90 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index c52d79a55d80..27ceaa94c8bd 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -325,12 +325,6 @@ linux,code = ; }; -&pronto { - status = "okay"; - - firmware-name = "qcom/apq8016/wcnss.mbn"; -}; - &sdhc_1 { status = "okay"; @@ -411,10 +405,19 @@ qcom,mbhc-vthreshold-high = <75 150 237 450 500>; }; +&wcnss { + status = "okay"; + firmware-name = "qcom/apq8016/wcnss.mbn"; +}; + &wcnss_ctrl { firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; }; +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + /* Enable CoreSight */ &cti0 { status = "okay"; }; &cti1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index ed3fa7b3575b..13cd9ad167df 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -118,10 +118,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; @@ -149,6 +145,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 701a5585d77e..fecb69944cfa 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -160,10 +160,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -191,6 +187,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts index 3618704a5330..91284a1d0966 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts @@ -128,10 +128,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -159,6 +155,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index a0e520edde02..525ec76efeeb 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -118,10 +118,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -149,6 +145,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 8c07eca900d3..5b1bac8f5122 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -227,10 +227,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -312,6 +308,14 @@ qcom,hphl-jack-type-normally-open; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index d1e8cf2f50c0..f1dd625e1822 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -231,10 +231,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -263,6 +259,14 @@ extcon = <&pm8916_usbin>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 3899e11b9843..b79e80913af9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -99,10 +99,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -130,6 +126,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi index 8cac23b5240c..6eb5e0a39510 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi @@ -20,17 +20,6 @@ pll-supply = <&pm8916_l7>; }; -&pronto { - vddpx-supply = <&pm8916_l7>; - - iris { - vddxo-supply = <&pm8916_l7>; - vddrfa-supply = <&pm8916_s3>; - vddpa-supply = <&pm8916_l9>; - vdddig-supply = <&pm8916_l5>; - }; -}; - &sdhc_1 { vmmc-supply = <&pm8916_l8>; vqmmc-supply = <&pm8916_l5>; @@ -46,6 +35,17 @@ v3p3-supply = <&pm8916_l13>; }; +&wcnss { + vddpx-supply = <&pm8916_l7>; +}; + +&wcnss_iris { + vddxo-supply = <&pm8916_l7>; + vddrfa-supply = <&pm8916_s3>; + vddpa-supply = <&pm8916_l9>; + vdddig-supply = <&pm8916_l5>; +}; + &rpm_requests { smd_rpm_regulators: regulators { compatible = "qcom,rpm-pm8916-regulators"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi index a2ed7bdbf528..16d67749960e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi @@ -252,10 +252,6 @@ linux,code = ; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts index c691cca2eb45..a1ca4d883420 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts @@ -112,6 +112,14 @@ status = "okay"; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &msmgpio { panel_vdd3_default: panel-vdd3-default-state { pins = "gpio9"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts index 3dd819458785..4e10b8a5e9f9 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts @@ -54,12 +54,6 @@ status = "okay"; }; -&pronto { - iris { - compatible = "qcom,wcn3660b"; - }; -}; - &touchkey { vcc-supply = <®_touch_key>; vdd-supply = <®_touch_key>; @@ -69,6 +63,14 @@ status = "okay"; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + &msmgpio { tkey_en_default: tkey-en-default-state { pins = "gpio97"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index c95f0b4bc61f..f6c4a011fdfd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -58,6 +58,14 @@ vdd-supply = <®_touch_key>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &msmgpio { tkey_en_default: tkey-en-default-state { pins = "gpio97"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index d920b7247d82..74ffd04db8d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -125,14 +125,6 @@ status = "okay"; }; -&pronto { - status = "okay"; - - iris { - compatible = "qcom,wcn3660b"; - }; -}; - &sdhc_1 { pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -162,6 +154,14 @@ extcon = <&pm8916_usbin>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index f3b81b6f0a2f..adeee0830e76 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -93,10 +93,6 @@ linux,code = ; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -124,6 +120,14 @@ extcon = <&muic>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index d4984b3af802..1a41a4db874d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -272,14 +272,6 @@ status = "okay"; }; -&pronto { - status = "okay"; - - iris { - compatible = "qcom,wcn3660b"; - }; -}; - &sdhc_1 { status = "okay"; @@ -320,6 +312,14 @@ extcon = <&muic>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi index cdf34b74fa8f..50bae6f214f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi @@ -99,10 +99,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>; @@ -122,6 +118,14 @@ extcon = <&pm8916_usbin>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index a87be1d95b14..ac56c7595f78 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -153,10 +153,6 @@ status = "okay"; }; -&pronto { - status = "okay"; -}; - &sdhc_1 { status = "okay"; @@ -184,6 +180,14 @@ extcon = <&usb_id>; }; +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 639b158b4fbe..7e0fa37a3adf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1870,7 +1870,7 @@ }; }; - pronto: remoteproc@a21b000 { + wcnss: remoteproc@a21b000 { compatible = "qcom,pronto-v2-pil", "qcom,pronto"; reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; reg-names = "ccu", "dxe", "pmu"; @@ -1896,9 +1896,8 @@ status = "disabled"; - iris { - compatible = "qcom,wcn3620"; - + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ clocks = <&rpmcc RPM_SMD_RF_CLK2>; clock-names = "xo"; }; @@ -1916,13 +1915,13 @@ compatible = "qcom,wcnss"; qcom,smd-channels = "WCNSS_CTRL"; - qcom,mmio = <&pronto>; + qcom,mmio = <&wcnss>; - bluetooth { + wcnss_bt: bluetooth { compatible = "qcom,wcnss-bt"; }; - wifi { + wcnss_wifi: wifi { compatible = "qcom,wcnss-wlan"; interrupts = , From d27580366db0fb6fa1f6b6ca94bc89dcbf9fd496 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Fri, 10 Mar 2023 22:33:28 +0800 Subject: [PATCH 0773/1040] dt-bindings: vendor-prefixes: Add Henan Yiming Technology Co., Ltd. Henan Yiming Technology Co., Ltd. was established in 2021. The business scope of the company includes: communication equipment (excluding radio control equipment). Link: https://gw.yimingkeji.net Signed-off-by: Yang Xiwen Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/tencent_27DD0718C3FD9C5F7D6E2FBA225CAA760405@qq.com --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..d6ec61904d6b 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1528,6 +1528,8 @@ patternProperties: description: Yes Optoelectronics Co.,Ltd. "^yic,.*": description: YIC System Co., Ltd. + "^yiming,.*": + description: Henan Yiming Technology Co., Ltd. "^ylm,.*": description: Shenzhen Yangliming Electronic Technology Co., Ltd. "^yna,.*": From 26c56dbddc304cf7304346df4b25b3be0c086e36 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Fri, 10 Mar 2023 22:33:29 +0800 Subject: [PATCH 0774/1040] dt-bindings: arm: qcom: Add Yiming LTE dongle uz801-v3.0 (yiming-uz801v3) Add a compatible for Yiming LTE dongle uz801-v3.0 Signed-off-by: Yang Xiwen Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/tencent_61B4697855AD14BA2930AC7B21FFC75C4406@qq.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 05badce5fedc..f8d29b65f28b 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -230,6 +230,7 @@ properties: - thwc,uf896 - thwc,ufi001c - wingtech,wt88047 + - yiming,uz801-v3 - const: qcom,msm8916 - items: From 7a888e143f0c87017d91490ea9d0ecc2dc21f2a9 Mon Sep 17 00:00:00 2001 From: Yang Xiwen Date: Fri, 10 Mar 2023 22:33:30 +0800 Subject: [PATCH 0775/1040] arm64: dts: qcom: msm8916-yiming-uz801v3: Add initial device tree This commit adds support for the uz801 v3.0 WiFi/LTE dongle made by Henan Yiming Technology Co., Ltd. based on MSM8916. Note: The original firmware does not support 64-bit OS. It is necessary to flash 64-bit TZ firmware to boot arm64. Currently supported: - All CPU cores - Buttons - LEDs - Modem - SDHC - USB Device Mode - UART Signed-off-by: Yang Xiwen Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/tencent_62395CA0D608DD0078DD3D889F6E4E22BA05@qq.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/msm8916-yiming-uz801v3.dts | 35 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1a29403400b7..f6ff4024a60e 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts new file mode 100644 index 000000000000..74ce6563be18 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8916-ufi.dtsi" + +/ { + model = "uz801 v3.0 4G Modem Stick"; + compatible = "yiming,uz801-v3", "qcom,msm8916"; +}; + +&button_restart { + gpios = <&msmgpio 23 GPIO_ACTIVE_LOW>; +}; + +&led_r { + gpios = <&msmgpio 7 GPIO_ACTIVE_HIGH>; +}; + +&led_g { + gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>; +}; + +&led_b { + gpios = <&msmgpio 6 GPIO_ACTIVE_HIGH>; +}; + +&button_default { + pins = "gpio23"; + bias-pull-up; +}; + +&gpio_leds_default { + pins = "gpio6", "gpio7", "gpio8"; +}; From 0d8d77228aa1efec69f92ef92e1cd9270c1151c4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:15 +0100 Subject: [PATCH 0776/1040] arm64: dts: qcom: sda660-inforce: correct key node name gpio-key bindings expect children to be named with generic prefix: sda660-inforce-ifc6560.dtb: gpio-keys: 'volup' does not match any of the regexes: ... Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 7c81918eee66..7459525d9982 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -29,7 +29,7 @@ gpio-keys { compatible = "gpio-keys"; - volup { + key-volup { label = "Volume Up"; gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; linux,code = ; From de88b1759b35086d5e63736fb604ea2d06486b1a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:16 +0100 Subject: [PATCH 0777/1040] arm64: dts: qcom: sc7280-herobrine-villager: correct trackpad supply The hid-over-i2c takes VDD, not VCC supply. Fix copy-pasta from other Herobrine boards which use elan,ekth3000 with valid VCC: sc7280-herobrine-villager-r1-lte.dtb: trackpad@2c: 'vcc-supply' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: ee2a62116015 ("arm64: dts: qcom: sc7280: Add device tree for herobrine villager") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi index 818d4046d2c7..38c8a3679fcb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi @@ -33,7 +33,7 @@ ap_tp_i2c: &i2c0 { interrupts = <7 IRQ_TYPE_EDGE_FALLING>; hid-descr-addr = <0x20>; - vcc-supply = <&pp3300_z1>; + vdd-supply = <&pp3300_z1>; wakeup-source; }; From 52e2996f253d82520011340d40dbc1c76ea79208 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:17 +0100 Subject: [PATCH 0778/1040] arm64: dts: qcom: sc7180-trogdor-lazor: correct trackpad supply The hid-over-i2c takes VDD, not VCC supply. Fix copy-pasta from other boards which use elan,ekth3000 with valid VCC: sc7180-trogdor-lazor-limozeen-nots-r4.dtb: trackpad@2c: 'vcc-supply' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: 2c26adb8dbab ("arm64: dts: qcom: Add sc7180-lazor-limozeen skus") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-3-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts index 850776c5323d..70d5a7aa8873 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts @@ -26,7 +26,7 @@ interrupt-parent = <&tlmm>; interrupts = <58 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <&pp3300_fp_tp>; + vdd-supply = <&pp3300_fp_tp>; hid-descr-addr = <0x20>; wakeup-source; From 24f39eec6a70768e7c2eb2f3d8158f45050ff75a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:18 +0100 Subject: [PATCH 0779/1040] arm64: dts: qcom: sc7180-trogdor-pazquel: correct trackpad supply The hid-over-i2c takes VDD, not VCC supply. Fix copy-pasta from other boards which use elan,ekth3000 with valid VCC: sc7180-trogdor-pazquel360-lte.dtb: trackpad@15: 'vcc-supply' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: fb69f6adaf88 ("arm64: dts: qcom: sc7180: Add pazquel dts files") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi index d06cc4ea3375..8823edbb4d6e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi @@ -39,7 +39,7 @@ interrupt-parent = <&tlmm>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - vcc-supply = <&pp3300_fp_tp>; + vdd-supply = <&pp3300_fp_tp>; post-power-on-delay-ms = <100>; hid-descr-addr = <0x0001>; From 97b4fdc6b82d6d5cfb92a9b164540278720fb700 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:19 +0100 Subject: [PATCH 0780/1040] arm64: dts: qcom: msm8998-oneplus-cheeseburger: revert "fix backlight pin function" This reverts commit 46546f28825cf3a5ef6873b9cf947cd85c8a7258 because it mistakenly took PMIC pinctrl/GPIO as TLMM. The TLMM pinctrl uses "gpio" function, but PMIC uses "normal", so original code was correct: msm8998-oneplus-cheeseburger.dtb: pmic@2: gpio@c000:button-backlight-state: 'oneOf' conditional failed, one must be fixed: 'gpio' is not one of ['normal', 'paired', 'func1', 'func2', 'dtest1', 'dtest2', 'dtest3', 'dtest4', 'func3', 'func4'] Fixes: 46546f28825c ("arm64: dts: qcom: msm8998-oneplus-cheeseburger: fix backlight pin function") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts index d36b36af49d0..fac8b3510cd3 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts @@ -34,7 +34,7 @@ &pmi8998_gpios { button_backlight_default: button-backlight-state { pins = "gpio5"; - function = "gpio"; + function = "normal"; bias-pull-down; qcom,drive-strength = ; }; From 3555dd528ba9c08d6ccd56239c695dbeac3b63e3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:20 +0100 Subject: [PATCH 0781/1040] arm64: dts: qcom: msm8994-kitakami: drop unit address from PMI8994 regulator The PMIC regulators are not supposed to have unit addresses. Fixes: e9783584c9b7 ("arm64: dts: qcom: msm8994-kitakami: Add VDD_GFX regulator") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 3ceb86b06209..26059f861250 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -173,8 +173,7 @@ * power domain.. which still isn't enough and forces us to bind * OXILI_CX and OXILI_GX together! */ - vdd_gfx: s2@1700 { - reg = <0x1700 0x100>; + vdd_gfx: s2 { regulator-name = "VDD_GFX"; regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; From 7a202df0f3eed006e4a9e7c06d62cf67be56c14c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:21 +0100 Subject: [PATCH 0782/1040] arm64: dts: qcom: msm8994-msft-lumia-octagon: drop unit address from PMI8994 regulator The PMIC regulators are not supposed to have unit addresses. Fixes: 60b214effb80 ("arm64: dts: qcom: msm8994-octagon: Configure regulators") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index e9480c4208f6..2861bcdf87b7 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -540,8 +540,7 @@ }; &pmi8994_spmi_regulators { - vdd_gfx: s2@1700 { - reg = <0x1700 0x100>; + vdd_gfx: s2 { regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; }; From ec57cbce1a6d9384f8ac1ff966b204dc262f4927 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 19:36:22 +0100 Subject: [PATCH 0783/1040] arm64: dts: qcom: apq8096-db820c: drop unit address from PMI8994 regulator The PMIC regulators are not supposed to have unit addresses. Fixes: 2317b87a2a6f ("arm64: dts: qcom: db820c: Add vdd_gfx and tie it into mmcc") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230312183622.460488-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 3 +-- arch/arm64/boot/dts/qcom/pmi8994.dtsi | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index c965a8c81d9b..b599909c4463 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -703,8 +703,7 @@ &pmi8994_spmi_regulators { vdd_s2-supply = <&vph_pwr>; - vdd_gfx: s2@1700 { - reg = <0x1700 0x100>; + vdd_gfx: s2 { regulator-name = "VDD_GFX"; regulator-min-microvolt = <980000>; regulator-max-microvolt = <980000>; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index a0af91698d49..0192968f4d9b 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -49,8 +49,6 @@ pmi8994_spmi_regulators: regulators { compatible = "qcom,pmi8994-regulators"; - #address-cells = <1>; - #size-cells = <1>; }; pmi8994_wled: wled@d800 { From 6209038f131fee84ff1536dc59864f54d06740f2 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Mon, 13 Mar 2023 18:27:31 +0530 Subject: [PATCH 0784/1040] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on QDU1000 and QRU1000 SoCs. Signed-off-by: Komal Bajaj Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313125731.17745-1-quic_kbajaj@quicinc.com --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 99d784085fb3..734438113bba 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1321,6 +1321,18 @@ qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; + + system-cache-controller@19200000 { + compatible = "qcom,qdu1000-llcc"; + reg = <0 0x19200000 0 0xd80000>, + <0 0x1a200000 0 0x80000>, + <0 0x221c8128 0 0x4>; + reg-names = "llcc_base", + "llcc_broadcast_base", + "multi_channel_register"; + interrupts = ; + multi-ch-bit-off = <24 2>; + }; }; timer { From d20ad168b7d024d8cbe6b54e9c029537aa412576 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Mon, 13 Mar 2023 10:42:26 -0500 Subject: [PATCH 0785/1040] arm64: dts: qcom: sdm845-xiaomi-beryllium: add notification LED The Poco F1 has a single color white notification LED. Enable the Qualcomm Light Pulse Generator (LPG) driver based notification LED. Signed-off-by: Joel Selvaraj Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313154226.136726-1-joelselvaraj.oss@gmail.com --- .../boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index e444ef1cd742..5ed975cc6ecb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -2,6 +2,7 @@ /dts-v1/; +#include #include #include #include @@ -319,6 +320,16 @@ }; }; +&pmi8998_lpg { + status = "okay"; + + led@5 { + reg = <5>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + &pmi8998_wled { status = "okay"; qcom,current-boost-limit = <970>; From 900007f26aa82e28ac4f494cd0121a75673d39ff Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 14 Mar 2023 14:28:34 +0100 Subject: [PATCH 0786/1040] arm64: dts: qcom: msm8998-yoshino: Use SONY GPIO names Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Yoshino devices DTs to better document the hardware. Lilac and Poplar have identical pin assignments. Diff between these two and maple: TLMM: - "NC", + "TS_VDDIO_EN", PMI8998: - "NC" + "USB_SWITCH_SEL" - "NC" + "4K_DISP_DCDC_EN" PM8005: - "NC" + "EAR_EN" Which is probably due to Maple being designed and released quite a bit earlier than the other two and it having a super high tech true-4K display. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-yoshino_gpio-v2-1-4cb80e187e38@linaro.org --- .../msm8998-sony-xperia-yoshino-maple.dts | 175 +++++++++++++++ .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 199 ++++++++++++++++++ 2 files changed, 374 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 1868ad649415..8b6a718835c7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -37,7 +37,29 @@ qcom,soft-start-us = <200>; }; +&pm8005_gpios { + gpio-line-names = "EAR_EN", /* GPIO_1 */ + "NC", + "SLB", + "OPTION_1_PM8005"; +}; + &pmi8998_gpios { + gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */ + "NC", + "NC", + "TYPEC_UUSB_SEL", + "VIB_LDO_EN", + "NC", + "DISPLAY_TYPE_SEL", + "USB_SWITCH_SEL", + "NC", + "4K_DISP_DCDC_EN", /* GPIO_10 */ + "NC", + "DIV_CLK3", + "SPMI_I2C_SEL", + "NC"; + disp_dvdd_en: disp-dvdd-en-active-state { pins = "gpio10"; function = "normal"; @@ -49,6 +71,159 @@ }; }; +&tlmm { + gpio-line-names = "", /* GPIO_0 */ + "", + "", + "", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "NC", + "NC", + "MDP_VSYNC_P", /* GPIO_10 */ + "RGBC_IR_INT", + "NFC_VEN", + "CAM_MCLK0", + "CAM_MCLK1", + "NC", + "NC", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "MAIN_CAM_PWR_EN", + "TOF_INT_N", + "NC", + "NC", + "CHAT_CAM_PWR_EN", + "NC", + "TOF_RESET_N", + "CAM2_RSTN", + "NC", + "CAM1_RSTN", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "CC_DIR", + "UIM2_DETECT_EN", + "FP_RESET_N", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "BT_HCI_UART_TXD", + "BT_HCI_UART_RXD", + "BT_HCI_UART_CTS_N", + "BT_HCI_UART_RFR_N", + "NC", + "NC", /* GPIO_50 */ + "NC", + "NC", + "CODEC_INT2_N", + "CODEC_INT1_N", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "FORCED_USB_BOOT", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "NC", + "TRAY2_DET_DS", + "CODEC_RST_N", + "WSA_L_EN", + "WSA_R_EN", + "NC", + "NC", + "NC", + "LPASS_SLIMBUS_CLK", /* GPIO_70 */ + "LPASS_SLIMBUS_DATA0", + "LPASS_SLIMBUS_DATA1", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "NC", + "NC", /* GPIO_80 */ + "SW_SERVICE", + "TX_GTR_THRES_IN", + "HW_ID0", + "HW_ID1", + "NC", + "NC", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_RESET_N", + "NC", /* GPIO_90 */ + "NC", + "NFC_IRQ", + "NFC_DWLD_EN", + "DISP_RESET_N", + "TRAY2_DET", + "CAM_SOF", + "RFFE6_CLK", + "RFFE6_DATA", + "DEBUG_GPIO0", + "DEBUG_GPIO1", /* GPIO_100 */ + "GRFC4", + "NC", + "NC", + "RSVD", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RST", + "UIM1_PRESENT", + "UIM_BATT_ALARM", + "RSVD", + "NC", + "NC", + "ACCEL_INT", + "GYRO_INT", + "COMPASS_INT", + "ALS_PROX_INT_N", /* GPIO_120 */ + "FP_INT_N", + "NC", + "BAROMETER_INT", + "ACC_COVER_OPEN", + "TS_INT_N", + "NC", + "NC", + "USB_DETECT_EN", + "NC", + "QLINK_REQUEST", /* GPIO_130 */ + "QLINK_ENABLE", + "NC", + "TS_VDDIO_EN", + "WMSS_RESET_N", + "PA_INDICATOR_OR", + "NC", + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "RFFE4_CLK", /* GPIO_140 */ + "RFFE5_DATA", + "RFFE5_CLK", + "GNSS_EN", + "MSS_LTE_COXM_TXD", + "MSS_LTE_COXM_RXD", + "RFFE2_DATA", + "RFFE2_CLK", + "RFFE1_DATA", + "RFFE1_CLK"; +}; + &vreg_l22a_2p85 { regulator-min-microvolt = <2704000>; regulator-max-microvolt = <2704000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index fa02e45f1c24..bb1c1e86ac2a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -292,6 +292,13 @@ regulator-soft-start; }; +&pm8005_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "SLB", + "OPTION_1_PM8005"; +}; + &pm8005_regulators { /* VDD_GFX supply */ pm8005_s1: s1 { @@ -304,6 +311,33 @@ }; &pm8998_gpios { + gpio-line-names = "UIM_BATT_ALARM", /* GPIO_1 */ + "NC", + "WLAN_SW_CTRL (DISALLOWED)", + "SSC_PWR_EN", + "VOL_DOWN_N", + "VOL_UP_N", + "SNAPSHOT_N", + "FOCUS_N", + "FLASH_THERM", + "", /* GPIO_10 */ + "", + "", + "DIV_CLK1", + "NC", + "NC (DISALLOWED)", + "DIV_CLK3", + "NC", + "NC", + "NC", + "NC (DISALLOWED)", /* GPIO_20 */ + "NFC_CLK_REQ", + "NC (DISALLOWED)", + "WCSS_PWR_REQ", + "OPTION_1 (DISALLOWED)", + "OPTION_2 (DISALLOWED)", + "PM_SLB (DISALLOWED)"; + vol_down_pin_a: vol-down-active-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; @@ -336,6 +370,21 @@ }; &pmi8998_gpios { + gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */ + "NC", + "NC", + "TYPEC_UUSB_SEL", + "VIB_LDO_EN", + "NC", + "DISPLAY_TYPE_SEL", + "NC", + "NC", + "NC", /* GPIO_10 */ + "NC", + "DIV_CLK3", + "SPMI_I2C_SEL", + "NC"; + cam_vio_default: cam-vio-active-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; @@ -590,6 +639,156 @@ &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; + gpio-line-names = "", /* GPIO_0 */ + "", + "", + "", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "NC", + "NC", + "MDP_VSYNC_P", /* GPIO_10 */ + "RGBC_IR_INT", + "NFC_VEN", + "CAM_MCLK0", + "CAM_MCLK1", + "NC", + "NC", + "CCI_I2C_SDA0", + "CCI_I2C_SCL0", + "CCI_I2C_SDA1", + "CCI_I2C_SCL1", /* GPIO_20 */ + "MAIN_CAM_PWR_EN", + "TOF_INT_N", + "NC", + "NC", + "CHAT_CAM_PWR_EN", + "NC", + "TOF_RESET_N", + "CAM2_RSTN", + "NC", + "CAM1_RSTN", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "CC_DIR", + "UIM2_DETECT_EN", + "FP_RESET_N", /* GPIO_40 */ + "NC", + "NC", + "NC", + "NC", + "BT_HCI_UART_TXD", + "BT_HCI_UART_RXD", + "BT_HCI_UART_CTS_N", + "BT_HCI_UART_RFR_N", + "NC", + "NC", /* GPIO_50 */ + "NC", + "NC", + "CODEC_INT2_N", + "CODEC_INT1_N", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "FORCED_USB_BOOT", + "NC", + "NC", + "NC", /* GPIO_60 */ + "NC", + "NC", + "TRAY2_DET_DS", + "CODEC_RST_N", + "WSA_L_EN", + "WSA_R_EN", + "NC", + "NC", + "NC", + "LPASS_SLIMBUS_CLK", /* GPIO_70 */ + "LPASS_SLIMBUS_DATA0", + "LPASS_SLIMBUS_DATA1", + "BT_FM_SLIMBUS_DATA", + "BT_FM_SLIMBUS_CLK", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "NC", + "NC", /* GPIO_80 */ + "SW_SERVICE", + "TX_GTR_THRES_IN", + "HW_ID0", + "HW_ID1", + "NC", + "NC", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_RESET_N", + "NC", /* GPIO_90 */ + "NC", + "NFC_IRQ", + "NFC_DWLD_EN", + "DISP_RESET_N", + "TRAY2_DET", + "CAM_SOF", + "RFFE6_CLK", + "RFFE6_DATA", + "DEBUG_GPIO0", + "DEBUG_GPIO1", /* GPIO_100 */ + "GRFC4", + "NC", + "NC", + "RSVD", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RST", + "UIM1_PRESENT", + "UIM_BATT_ALARM", + "RSVD", + "NC", + "NC", + "ACCEL_INT", + "GYRO_INT", + "COMPASS_INT", + "ALS_PROX_INT_N", /* GPIO_120 */ + "FP_INT_N", + "NC", + "BAROMETER_INT", + "ACC_COVER_OPEN", + "TS_INT_N", + "NC", + "NC", + "USB_DETECT_EN", + "NC", + "QLINK_REQUEST", /* GPIO_130 */ + "QLINK_ENABLE", + "NC", + "NC", + "WMSS_RESET_N", + "PA_INDICATOR_OR", + "NC", + "RFFE3_DATA", + "RFFE3_CLK", + "RFFE4_DATA", + "RFFE4_CLK", /* GPIO_140 */ + "RFFE5_DATA", + "RFFE5_CLK", + "GNSS_EN", + "MSS_LTE_COXM_TXD", + "MSS_LTE_COXM_RXD", + "RFFE2_DATA", + "RFFE2_CLK", + "RFFE1_DATA", + "RFFE1_CLK"; mdp_vsync_n: mdp-vsync-n-state { pins = "gpio10"; From a9eaa4798473fd3cfe39210c64e403d6cbc31984 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 14 Mar 2023 14:28:35 +0100 Subject: [PATCH 0787/1040] arm64: dts: qcom: msm8998-yoshino: Use actual pin names for pin nodes With the gpio-line-names in place coming from SONY themselves, we can now make the pin nodes and their labels to more closely resemble the actual thing. 4k has been renamed to four_k due to dtc limitations. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230314-topic-yoshino_gpio-v2-2-4cb80e187e38@linaro.org --- .../msm8998-sony-xperia-yoshino-maple.dts | 4 +- .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 61 +++++++++---------- 2 files changed, 32 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 8b6a718835c7..055b6a643d82 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -22,7 +22,7 @@ enable-active-high; gpio = <&pmi8998_gpios 10 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&disp_dvdd_en>; + pinctrl-0 = <&four_k_disp_dcdc_en>; }; }; @@ -60,7 +60,7 @@ "SPMI_I2C_SEL", "NC"; - disp_dvdd_en: disp-dvdd-en-active-state { + four_k_disp_dcdc_en: 4k-disp-dcdc-en-state { pins = "gpio10"; function = "normal"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index bb1c1e86ac2a..8e1c25b15f57 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -21,7 +21,7 @@ clocks { div1_mclk: divclk1 { compatible = "gpio-gate-clock"; - pinctrl-0 = <&audio_mclk_pin>; + pinctrl-0 = <&div_clk1>; pinctrl-names = "default"; clocks = <&rpmcc RPM_SMD_DIV_CLK1>; #clock-cells = <0>; @@ -46,7 +46,7 @@ enable-active-high; gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&cam0_vdig_default>; + pinctrl-0 = <&main_cam_pwr_en>; }; cam1_vdig_vreg: cam1-vdig { @@ -56,7 +56,7 @@ enable-active-high; gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&cam1_vdig_default>; + pinctrl-0 = <&chat_cam_pwr_en>; vin-supply = <&vreg_s3a_1p35>; }; @@ -67,7 +67,7 @@ enable-active-high; gpio = <&pmi8998_gpios 1 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&cam_vio_default>; + pinctrl-0 = <&main_cam_pwr_io_en>; vin-supply = <&vreg_lvs1a_1p8>; }; @@ -92,15 +92,14 @@ id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&usb_extcon_active &usb_vbus_active>; + pinctrl-0 = <&cc_dir_default &usb_detect_en>; }; gpio-keys { compatible = "gpio-keys"; label = "Side buttons"; pinctrl-names = "default"; - pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, - <&cam_snapshot_pin_a>; + pinctrl-0 = <&vol_down_n &focus_n &snapshot_n>; button-vol-down { label = "Volume Down"; gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>; @@ -131,7 +130,7 @@ compatible = "gpio-keys"; label = "Hall sensors"; pinctrl-names = "default"; - pinctrl-0 = <&hall_sensor0_default>; + pinctrl-0 = <&acc_cover_open>; event-hall-sensor0 { label = "Cover Hall Sensor"; @@ -189,7 +188,7 @@ compatible = "gpio-vibrator"; enable-gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&vib_default>; + pinctrl-0 = <&vib_ldo_en>; }; }; @@ -263,7 +262,7 @@ vdd-supply = <&cam_vio_vreg>; pinctrl-names = "default"; - pinctrl-0 = <&tof_int &tof_reset>; + pinctrl-0 = <&tof_int_n &tof_reset>; }; }; @@ -338,7 +337,7 @@ "OPTION_2 (DISALLOWED)", "PM_SLB (DISALLOWED)"; - vol_down_pin_a: vol-down-active-state { + vol_down_n: vol-down-n-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -346,7 +345,7 @@ qcom,drive-strength = ; }; - cam_focus_pin_a: cam-focus-btn-active-state { + focus_n: focus-n-state { pins = "gpio7"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -354,7 +353,7 @@ qcom,drive-strength = ; }; - cam_snapshot_pin_a: cam-snapshot-btn-active-state { + snapshot_n: snapshot-n-state { pins = "gpio8"; function = PMIC_GPIO_FUNC_NORMAL; bias-pull-up; @@ -362,7 +361,7 @@ qcom,drive-strength = ; }; - audio_mclk_pin: audio-mclk-pin-active-state { + div_clk1: div-clk1-state { pins = "gpio13"; function = "func2"; power-source = <0>; @@ -385,7 +384,7 @@ "SPMI_I2C_SEL", "NC"; - cam_vio_default: cam-vio-active-state { + main_cam_pwr_io_en: main-cam-pwr-io-en-state { pins = "gpio1"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -395,7 +394,7 @@ power-source = <1>; }; - vib_default: vib-en-state { + vib_ldo_en: vib-ldo-en-state { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; bias-disable; @@ -790,7 +789,7 @@ "RFFE1_DATA", "RFFE1_CLK"; - mdp_vsync_n: mdp-vsync-n-state { + mdp_vsync_p: mdp-vsync-p-state { pins = "gpio10"; function = "mdp_vsync_a"; drive-strength = <2>; @@ -805,14 +804,14 @@ output-low; }; - msm_mclk0_default: msm-mclk0-active-state { + cam_mclk0_active: cam-mclk0-active-state { pins = "gpio13"; function = "cam_mclk"; drive-strength = <2>; bias-disable; }; - msm_mclk1_default: msm-mclk1-active-state { + cam_mclk1_active: cam-mclk1-active-state { pins = "gpio14"; function = "cam_mclk"; drive-strength = <2>; @@ -833,14 +832,14 @@ drive-strength = <2>; }; - cam0_vdig_default: cam0-vdig-default-state { + main_cam_pwr_en: main-cam-pwr-en-default-state { pins = "gpio21"; function = "gpio"; bias-disable; drive-strength = <2>; }; - tof_int: tof-int-state { + tof_int_n: tof-int-n-state { pins = "gpio22"; function = "gpio"; bias-pull-up; @@ -848,20 +847,13 @@ input-enable; }; - cam1_vdig_default: cam1-vdig-default-state { + chat_cam_pwr_en: chat-cam-pwr-en-default-state { pins = "gpio25"; function = "gpio"; bias-disable; drive-strength = <2>; }; - usb_extcon_active: usb-extcon-active-state { - pins = "gpio38"; - function = "gpio"; - bias-disable; - drive-strength = <16>; - }; - tof_reset: tof-reset-state { pins = "gpio27"; function = "gpio"; @@ -869,7 +861,14 @@ drive-strength = <2>; }; - hall_sensor0_default: acc-cover-open-state { + cc_dir_default: cc-dir-active-state { + pins = "gpio38"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + + acc_cover_open: acc-cover-open-state { pins = "gpio124"; function = "gpio"; bias-disable; @@ -884,7 +883,7 @@ bias-pull-up; }; - usb_vbus_active: usb-vbus-active-state { + usb_detect_en: usb-detect-en-active-state { pins = "gpio128"; function = "gpio"; bias-disable; From 452c165e3597691a953e3f4c4c0442c41c8e02f4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:20 +0100 Subject: [PATCH 0788/1040] soc: qcom: icc-bwmon: Remove unused struct member bwmon->regmap was never used, as the regmap for bwmon is registered through devres and accessed through bwmon's regmap_field members. Remove it Fixes: ec63dcd3c863 ("soc: qcom: icc-bwmon: use regmap and prepare for BWMON v5") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-2-77a050c2fbda@linaro.org --- drivers/soc/qcom/icc-bwmon.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d07be3700db6..d45caf512e2d 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -164,7 +164,6 @@ struct icc_bwmon { const struct icc_bwmon_data *data; int irq; - struct regmap *regmap; struct regmap_field *regs[F_NUM_FIELDS]; unsigned int max_bw_kbps; From b6e9fb7ac236bc48cc2c667e0b51153d2daa5268 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:21 +0100 Subject: [PATCH 0789/1040] soc: qcom: icc-bwmon: Handle global registers correctly The BWMON hardware has two sets of registers: one for the monitor itself and one called "global". It has what seems to be some kind of a head switch and an interrupt control register. It's usually 0x200 in size. On fairly recent SoCs (with the starting point seemingly being moving the OSM programming to the firmware) these two register sets are contiguous and overlapping, like this (on sm8450): /* notice how base.start == global_base.start+0x100 */ reg = <0x90b6400 0x300>, <0x90b6300 0x200>; reg-names = "base", "global_base"; Which led to some confusion and the assumption that since the "interesting" global registers begin right after global_base+0x100, there's no need to map two separate regions and one can simply subtract 0x100 from the offsets. This is however not the case for anything older than SDM845, as the global region can appear in seemingly random spots on the register map. Handle the case where the global registers are mapped separately to allow proper functioning of BWMONv4 on MSM8998 and older. Add specific compatibles for 845, 8280xp, 7280 and 8550 (all of which use the single reg space scheme) to keep backwards compatibility with old DTs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-3-77a050c2fbda@linaro.org --- drivers/soc/qcom/icc-bwmon.c | 230 +++++++++++++++++++++++++++++++---- 1 file changed, 209 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d45caf512e2d..fd58c5b69897 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -34,14 +34,27 @@ /* Internal sampling clock frequency */ #define HW_TIMER_HZ 19200000 -#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x008 -#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x00c +#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x108 +#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x10c /* * All values here and further are matching regmap fields, so without absolute * register offsets. */ #define BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE BIT(0) +/* + * Starting with SDM845, the BWMON4 register space has changed a bit: + * the global registers were jammed into the beginning of the monitor region. + * To keep the proper offsets, one would have to map and + * , which is straight up wrong. + * To facilitate for that, while allowing the older, arguably more proper + * implementations to work, offset the global registers by -0x100 to avoid + * having to map half of the global registers twice. + */ +#define BWMON_V4_845_OFFSET 0x100 +#define BWMON_V4_GLOBAL_IRQ_CLEAR_845 (BWMON_V4_GLOBAL_IRQ_CLEAR - BWMON_V4_845_OFFSET) +#define BWMON_V4_GLOBAL_IRQ_ENABLE_845 (BWMON_V4_GLOBAL_IRQ_ENABLE - BWMON_V4_845_OFFSET) + #define BWMON_V4_IRQ_STATUS 0x100 #define BWMON_V4_IRQ_CLEAR 0x108 @@ -118,9 +131,13 @@ #define BWMON_NEEDS_FORCE_CLEAR BIT(1) enum bwmon_fields { + /* Global region fields, keep them at the top */ F_GLOBAL_IRQ_CLEAR, F_GLOBAL_IRQ_ENABLE, - F_IRQ_STATUS, + F_NUM_GLOBAL_FIELDS, + + /* Monitor region fields */ + F_IRQ_STATUS = F_NUM_GLOBAL_FIELDS, F_IRQ_CLEAR, F_IRQ_ENABLE, F_ENABLE, @@ -157,6 +174,9 @@ struct icc_bwmon_data { const struct regmap_config *regmap_cfg; const struct reg_field *regmap_fields; + + const struct regmap_config *global_regmap_cfg; + const struct reg_field *global_regmap_fields; }; struct icc_bwmon { @@ -165,6 +185,7 @@ struct icc_bwmon { int irq; struct regmap_field *regs[F_NUM_FIELDS]; + struct regmap_field *global_regs[F_NUM_GLOBAL_FIELDS]; unsigned int max_bw_kbps; unsigned int min_bw_kbps; @@ -174,8 +195,8 @@ struct icc_bwmon { /* BWMON v4 */ static const struct reg_field msm8998_bwmon_reg_fields[] = { - [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), - [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), + [F_GLOBAL_IRQ_CLEAR] = {}, + [F_GLOBAL_IRQ_ENABLE] = {}, [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), @@ -201,7 +222,6 @@ static const struct reg_field msm8998_bwmon_reg_fields[] = { }; static const struct regmap_range msm8998_bwmon_reg_noread_ranges[] = { - regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), }; @@ -221,16 +241,33 @@ static const struct regmap_access_table msm8998_bwmon_reg_volatile_table = { .n_yes_ranges = ARRAY_SIZE(msm8998_bwmon_reg_volatile_ranges), }; +static const struct reg_field msm8998_bwmon_global_reg_fields[] = { + [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), + [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), +}; + +static const struct regmap_range msm8998_bwmon_global_reg_noread_ranges[] = { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), +}; + +static const struct regmap_access_table msm8998_bwmon_global_reg_read_table = { + .no_ranges = msm8998_bwmon_global_reg_noread_ranges, + .n_no_ranges = ARRAY_SIZE(msm8998_bwmon_global_reg_noread_ranges), +}; + /* * Fill the cache for non-readable registers only as rest does not really * matter and can be read from the device. */ static const struct reg_default msm8998_bwmon_reg_defaults[] = { - { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, { BWMON_V4_IRQ_CLEAR, 0x0 }, { BWMON_V4_CLEAR, 0x0 }, }; +static const struct reg_default msm8998_bwmon_global_reg_defaults[] = { + { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, +}; + static const struct regmap_config msm8998_bwmon_regmap_cfg = { .reg_bits = 32, .reg_stride = 4, @@ -251,6 +288,93 @@ static const struct regmap_config msm8998_bwmon_regmap_cfg = { .cache_type = REGCACHE_RBTREE, }; +static const struct regmap_config msm8998_bwmon_global_regmap_cfg = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking = true, + .rd_table = &msm8998_bwmon_global_reg_read_table, + .reg_defaults = msm8998_bwmon_global_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(msm8998_bwmon_global_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type = REGCACHE_RBTREE, +}; + +static const struct reg_field sdm845_cpu_bwmon_reg_fields[] = { + [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0, 0), + [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE_845, 0, 0), + [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), + [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), + [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), + /* F_ENABLE covers entire register to disable other features */ + [F_ENABLE] = REG_FIELD(BWMON_V4_ENABLE, 0, 31), + [F_CLEAR] = REG_FIELD(BWMON_V4_CLEAR, 0, 1), + [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23), + [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11), + [F_THRESHOLD_MED] = REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11), + [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11), + [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7), + [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15), + [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23), + [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31), + [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7), + [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15), + [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23), + [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31), + [F_ZONE0_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11), + [F_ZONE1_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11), + [F_ZONE2_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11), + [F_ZONE3_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11), +}; + +static const struct regmap_range sdm845_cpu_bwmon_reg_noread_ranges[] = { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR_845, BWMON_V4_GLOBAL_IRQ_CLEAR_845), + regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), + regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), +}; + +static const struct regmap_access_table sdm845_cpu_bwmon_reg_read_table = { + .no_ranges = sdm845_cpu_bwmon_reg_noread_ranges, + .n_no_ranges = ARRAY_SIZE(sdm845_cpu_bwmon_reg_noread_ranges), +}; + +/* + * Fill the cache for non-readable registers only as rest does not really + * matter and can be read from the device. + */ +static const struct reg_default sdm845_cpu_bwmon_reg_defaults[] = { + { BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0x0 }, + { BWMON_V4_IRQ_CLEAR, 0x0 }, + { BWMON_V4_CLEAR, 0x0 }, +}; + +static const struct regmap_config sdm845_cpu_bwmon_regmap_cfg = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking = true, + .rd_table = &sdm845_cpu_bwmon_reg_read_table, + .volatile_table = &msm8998_bwmon_reg_volatile_table, + .reg_defaults = sdm845_cpu_bwmon_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(sdm845_cpu_bwmon_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type = REGCACHE_RBTREE, +}; + /* BWMON v5 */ static const struct reg_field sdm845_llcc_bwmon_reg_fields[] = { [F_GLOBAL_IRQ_CLEAR] = {}, @@ -349,6 +473,13 @@ static void bwmon_clear_counters(struct icc_bwmon *bwmon, bool clear_all) static void bwmon_clear_irq(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_clr; + + if (bwmon->data->global_regmap_fields) + global_irq_clr = bwmon->global_regs[F_GLOBAL_IRQ_CLEAR]; + else + global_irq_clr = bwmon->regs[F_GLOBAL_IRQ_CLEAR]; + /* * Clear zone and global interrupts. The order and barriers are * important. Quoting downstream Qualcomm msm-4.9 tree: @@ -369,15 +500,22 @@ static void bwmon_clear_irq(struct icc_bwmon *bwmon) if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR) regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], 0); if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR], + regmap_field_force_write(global_irq_clr, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); } static void bwmon_disable(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0); + regmap_field_write(global_irq_en, 0x0); regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0); /* @@ -389,10 +527,18 @@ static void bwmon_disable(struct icc_bwmon *bwmon) static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Enable interrupts */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], + regmap_field_write(global_irq_en, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); + regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable); /* Enable bwmon */ @@ -555,7 +701,9 @@ static int bwmon_init_regmap(struct platform_device *pdev, struct device *dev = &pdev->dev; void __iomem *base; struct regmap *map; + int ret; + /* Map the monitor base */ base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return dev_err_probe(dev, PTR_ERR(base), @@ -566,12 +714,35 @@ static int bwmon_init_regmap(struct platform_device *pdev, return dev_err_probe(dev, PTR_ERR(map), "failed to initialize regmap\n"); + BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_global_reg_fields) != F_NUM_GLOBAL_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_reg_fields) != F_NUM_FIELDS); + BUILD_BUG_ON(ARRAY_SIZE(sdm845_cpu_bwmon_reg_fields) != F_NUM_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(sdm845_llcc_bwmon_reg_fields) != F_NUM_FIELDS); - return devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, + ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, bwmon->data->regmap_fields, F_NUM_FIELDS); + if (ret) + return ret; + + if (bwmon->data->global_regmap_cfg) { + /* Map the global base, if separate */ + base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to map bwmon global registers\n"); + + map = devm_regmap_init_mmio(dev, base, bwmon->data->global_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "failed to initialize global regmap\n"); + + ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->global_regs, + bwmon->data->global_regmap_fields, + F_NUM_GLOBAL_FIELDS); + } + + return ret; } static int bwmon_probe(struct platform_device *pdev) @@ -644,6 +815,21 @@ static const struct icc_bwmon_data msm8998_bwmon_data = { .quirks = BWMON_HAS_GLOBAL_IRQ, .regmap_fields = msm8998_bwmon_reg_fields, .regmap_cfg = &msm8998_bwmon_regmap_cfg, + .global_regmap_fields = msm8998_bwmon_global_reg_fields, + .global_regmap_cfg = &msm8998_bwmon_global_regmap_cfg, +}; + +static const struct icc_bwmon_data sdm845_cpu_bwmon_data = { + .sample_ms = 4, + .count_unit_kb = 64, + .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ + .default_medbw_kbps = 512 * 1024, /* 512 MBps */ + .default_lowbw_kbps = 0, + .zone1_thres_count = 16, + .zone3_thres_count = 1, + .quirks = BWMON_HAS_GLOBAL_IRQ, + .regmap_fields = sdm845_cpu_bwmon_reg_fields, + .regmap_cfg = &sdm845_cpu_bwmon_regmap_cfg, }; static const struct icc_bwmon_data sdm845_llcc_bwmon_data = { @@ -672,16 +858,18 @@ static const struct icc_bwmon_data sc7280_llcc_bwmon_data = { }; static const struct of_device_id bwmon_of_match[] = { - { - .compatible = "qcom,msm8998-bwmon", - .data = &msm8998_bwmon_data - }, { - .compatible = "qcom,sdm845-llcc-bwmon", - .data = &sdm845_llcc_bwmon_data - }, { - .compatible = "qcom,sc7280-llcc-bwmon", - .data = &sc7280_llcc_bwmon_data - }, + /* BWMONv4, separate monitor and global register spaces */ + { .compatible = "qcom,msm8998-bwmon", .data = &msm8998_bwmon_data }, + /* BWMONv4, unified register space */ + { .compatible = "qcom,sdm845-bwmon", .data = &sdm845_cpu_bwmon_data }, + /* BWMONv5 */ + { .compatible = "qcom,sdm845-llcc-bwmon", .data = &sdm845_llcc_bwmon_data }, + { .compatible = "qcom,sc7280-llcc-bwmon", .data = &sc7280_llcc_bwmon_data }, + + /* Compatibles kept for legacy reasons */ + { .compatible = "qcom,sc7280-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, + { .compatible = "qcom,sc8280xp-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, + { .compatible = "qcom,sm8550-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, {} }; MODULE_DEVICE_TABLE(of, bwmon_of_match); From 8c47b8253f4cfd8b4dbda8c9adc1d0b1d7f3009d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:04 -0600 Subject: [PATCH 0790/1040] firmware: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Signed-off-by: Rob Herring Acked-by: Sudeep Holla Signed-off-by: Thierry Reding --- drivers/firmware/arm_scmi/optee.c | 2 +- drivers/firmware/tegra/bpmp.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/arm_scmi/optee.c b/drivers/firmware/arm_scmi/optee.c index 929720387102..e123de6e8c67 100644 --- a/drivers/firmware/arm_scmi/optee.c +++ b/drivers/firmware/arm_scmi/optee.c @@ -403,7 +403,7 @@ out: static int setup_shmem(struct device *dev, struct scmi_chan_info *cinfo, struct scmi_optee_channel *channel) { - if (of_find_property(cinfo->dev->of_node, "shmem", NULL)) + if (of_property_present(cinfo->dev->of_node, "shmem")) return setup_static_shmem(dev, cinfo, channel); else return setup_dynamic_shmem(dev, channel); diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c index 042c2043929d..8b5e5daa9fae 100644 --- a/drivers/firmware/tegra/bpmp.c +++ b/drivers/firmware/tegra/bpmp.c @@ -764,19 +764,19 @@ static int tegra_bpmp_probe(struct platform_device *pdev) if (err < 0) goto free_mrq; - if (of_find_property(pdev->dev.of_node, "#clock-cells", NULL)) { + if (of_property_present(pdev->dev.of_node, "#clock-cells")) { err = tegra_bpmp_init_clocks(bpmp); if (err < 0) goto free_mrq; } - if (of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) { + if (of_property_present(pdev->dev.of_node, "#reset-cells")) { err = tegra_bpmp_init_resets(bpmp); if (err < 0) goto free_mrq; } - if (of_find_property(pdev->dev.of_node, "#power-domain-cells", NULL)) { + if (of_property_present(pdev->dev.of_node, "#power-domain-cells")) { err = tegra_bpmp_init_powergates(bpmp); if (err < 0) goto free_mrq; From df90ded69043400c01c552d672f198a99bd531e6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:52 +0100 Subject: [PATCH 0791/1040] dt-bindings: sram: qcom,imem: document SM6375 IMEM Add a compatible for SM6375 IMEM. Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-3-708b8191f7eb@linaro.org --- Documentation/devicetree/bindings/sram/qcom,imem.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index ba694ce4a037..0548e8e0d30b 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm845-imem - qcom,sdx55-imem - qcom,sdx65-imem + - qcom,sm6375-imem - qcom,sm8450-imem - const: syscon - const: simple-mfd From fc7c39d61cf8cd03e197ac492241fa5a007dd2c0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 11:52:09 +0100 Subject: [PATCH 0792/1040] arm64: dts: qcom: sm6115: Add GPUCC and Adreno SMMU Add GPUCC and Adreno SMMU nodes in preparation for adding the GPU itself. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230315-topic-kamorta_adrsmmu-v1-2-d1c0dea90bd9@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 38 ++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 2a51c938bbcb..2505c815c65a 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1111,6 +1112,43 @@ }; }; + gpucc: clock-controller@5990000 { + compatible = "qcom,sm6115-gpucc"; + reg = <0x0 0x05990000 0x0 0x9000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@59a0000 { + compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x059a0000 0x0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + power-domains = <&gpucc GPU_CX_GDSC>; + + #global-interrupts = <1>; + #iommu-cells = <2>; + }; + mdss: display-subsystem@5e00000 { compatible = "qcom,sm6115-mdss"; reg = <0x0 0x05e00000 0x0 0x1000>; From bad26511c4cb5469545834886e8df1d2b4c117d8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:22 +0100 Subject: [PATCH 0793/1040] arm64: dts: qcom: sc7280: Use the correct BWMON fallback compatible Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-4-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5e6f9f441f1a..0cdb16316021 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3540,7 +3540,7 @@ }; pmu@90b6400 { - compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = ; From 5e1b11c00ffc0a2d105af5a92053fa10ca15fcd0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:23 +0100 Subject: [PATCH 0794/1040] arm64: dts: qcom: sc8280xp: Use the correct BWMON fallback compatible Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-5-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index af7bee14fa06..cc7be432ec3c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2953,7 +2953,7 @@ }; pmu@90b6400 { - compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = ; From e95b60f1207dee16e0d3d66254ece655fd4e73c0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:24 +0100 Subject: [PATCH 0795/1040] arm64: dts: qcom: sdm845: Use the correct BWMON compatible Drop the incorrect msm8998 fallback and use the new qcom,sdm845-cpu-bwmon compatible to distinguish the CPU BWMON found on this platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-6-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 2f32179c7d1b..589b3470c3e1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2252,7 +2252,7 @@ }; pmu@1436400 { - compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x01436400 0 0x600>; interrupts = ; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; From feffd767971e25f43ba47bf2ab23a660f3a3758c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:25 +0100 Subject: [PATCH 0796/1040] arm64: dts: qcom: sm8550: Use the correct BWMON fallback compatible Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230304-topic-ddr_bwmon-v3-7-77a050c2fbda@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ed2554be467f..7a1994bf4086 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3406,7 +3406,7 @@ }; pmu@240b6400 { - compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b6400 0 0x600>; interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; From 2cecb9c2419f78e939e6e902895591ce3e3a7cc7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:53 +0100 Subject: [PATCH 0797/1040] arm64: dts: qcom: sm6375: Add RPM sleep stats Add a node for RPM sleep stats to enable sleep monitoring. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-4-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 86d733ca9b4f..a47cd80d0e1c 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -735,6 +735,11 @@ reg = <0 0x045f0000 0 0x7000>; }; + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0 0x04690000 0 0x400>; + }; + sdhc_2: mmc@4784000 { compatible = "qcom,sm6375-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x04784000 0 0x1000>; From 528630df2fa6d34eca0268a293fe354c71e48556 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:54 +0100 Subject: [PATCH 0798/1040] arm64: dts: qcom: sm6375: Add IMEM Add a node for the IMEM block on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-5-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index a47cd80d0e1c..46b39fa8d5b8 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1251,6 +1251,20 @@ }; }; + sram@c125000 { + compatible = "qcom,sm6375-imem", "syscon", "simple-mfd"; + reg = <0 0x0c125000 0 0x1000>; + ranges = <0 0 0x0c125000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6375-smmu-500", "arm,mmu-500"; reg = <0 0x0c600000 0 0x100000>; From 149d179d1408bc67b6af10af160ac13b48fa3399 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:56 +0100 Subject: [PATCH 0799/1040] arm64: dts: qcom: sm6375: Add wifi node Add a node for ATH10K_SNoC wifi on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-7-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 46b39fa8d5b8..37f4b726959a 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1341,6 +1341,28 @@ #iommu-cells = <2>; }; + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x0c800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&pil_wlan_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x80 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0 0x0f200000 0x0 0x10000>, /* GICD */ From 31cc61104f6894f686491dbbb5c8ece97b06e75d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:57 +0100 Subject: [PATCH 0800/1040] arm64: dts: qcom: sm6375: Add modem nodes Add required nodes to make the embedded 5G modem boot up on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-8-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 82 ++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 37f4b726959a..b768b767604f 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -572,6 +572,47 @@ }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wlan_smp2p_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -1177,6 +1218,47 @@ }; }; + remoteproc_mss: remoteproc@6000000 { + compatible = "qcom,sm6375-mpss-pas"; + reg = <0 0x06000000 0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd SM6375_VDDCX>; + power-domain-names = "cx"; + + memory-region = <&pil_mpss_wlan_mem>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + remoteproc_adsp: remoteproc@a400000 { compatible = "qcom,sm6375-adsp-pas"; reg = <0 0x0a400000 0 0x100>; From 2f51d9231485250c0e4cf4d7326c30109c553382 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:58 +0100 Subject: [PATCH 0801/1040] arm64: dts: qcom: sm6375: Add CPUCP L3 node Configure the L3 cache DVFS scaler within the CPUCP block to allow for dynamic frequency switching. Reviewed-by: Sibi Sankar Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-9-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index b768b767604f..a5dde682ede0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1513,6 +1513,15 @@ }; }; + cpucp_l3: interconnect@fd90000 { + compatible = "qcom,sm6375-cpucp-l3", "qcom,epss-l3"; + reg = <0 0x0fd90000 0 0x1000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@fd91000 { compatible = "qcom,sm6375-cpufreq-epss", "qcom,cpufreq-epss"; reg = <0 0x0fd91000 0 0x1000>, <0 0x0fd92000 0 0x1000>; From 3f54391526b407a419d2dfd4055fdc9e6e223551 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:12:59 +0100 Subject: [PATCH 0802/1040] arm64: dts: qcom: sm6375: Add TSENS Add nodes for the two TSENS v2.8.0 controllers present on the SoC. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-10-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index a5dde682ede0..bf95608e1116 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -771,6 +771,28 @@ #interrupt-cells = <4>; }; + tsens0: thermal-sensor@4411000 { + compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; + reg = <0 0x04411000 0 0x140>, /* TM */ + <0 0x04410000 0 0x20>; /* SROT */ + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <15>; + }; + + tsens1: thermal-sensor@4413000 { + compatible = "qcom,sm6375-tsens", "qcom,tsens-v2"; + reg = <0 0x04413000 0 0x140>, /* TM */ + <0 0x04412000 0 0x20>; /* SROT */ + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + #qcom,sensors = <11>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0 0x045f0000 0 0x7000>; From 33555cdae863984c7840ba742cfffe839a0f71e4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:00 +0100 Subject: [PATCH 0803/1040] arm64: dts: qcom: sm6375: Configure TSENS thermal zones Add a thermal zones configuration for all 15+11 TSENS sensors. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-11-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 704 +++++++++++++++++++++++++++ 1 file changed, 704 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index bf95608e1116..036e36ceebb5 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -1559,6 +1559,710 @@ }; }; + thermal-zones { + mapss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + mapss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss0_crit: mapss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + cpu5_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + cluster0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cluster1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + cluster1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cluster1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 10>; + + trips { + cpu7_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-unk0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 11>; + + trips { + cpu_unk0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk0_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-unk1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 12>; + + trips { + cpu_unk1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_unk1_crit: cpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 13>; + + trips { + gpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss0_crit: gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 14>; + + trips { + gpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpuss1_crit: gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mapss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 0>; + + trips { + mapss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss1_crit: mapss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cwlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 1>; + + trips { + cwlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cwlan_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cwlan_crit: cwlan-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + audio-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 2>; + + trips { + audio_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + audio_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + audio_crit: audio-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 3>; + + trips { + ddr_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + ddr_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + ddr_crit: ddr-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + q6hvx-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 4>; + + trips { + q6hvx_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + q6hvx_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + q6hvx_crit: q6hvx-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 5>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_crit: camera-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-core0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 6>; + + trips { + mdm_core0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core0_crit: mdm-core0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-core1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 7>; + + trips { + mdm_core1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_core1_crit: mdm-core1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm-vec-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 8>; + + trips { + mdm_vec_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_vec_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm_vec_crit: mdm-vec-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + msm-scl-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 9>; + + trips { + msm_scl_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + msm_scl_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + msm_scl_crit: msm-scl-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens1 10>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From 097d6525af378f4be768c05cc1d77183a4e742e3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:01 +0100 Subject: [PATCH 0804/1040] arm64: dts: qcom: sm6375: Bump CPU rail power collapse index In preparation for supporting a less-deep sleep state, rename the existing rail power off from _0 to _1. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-12-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 036e36ceebb5..6b75d8611077 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -214,7 +214,7 @@ idle-states { entry-method = "psci"; - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -224,7 +224,7 @@ local-timer-stop; }; - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -275,49 +275,49 @@ CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + domain-idle-states = <&LITTLE_CPU_SLEEP_1>; }; CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; + domain-idle-states = <&BIG_CPU_SLEEP_1>; }; CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; + domain-idle-states = <&BIG_CPU_SLEEP_1>; }; CLUSTER_PD: power-domain-cpu-cluster0 { From dbe38b9cba6d0de56ca186151f3f54f9c776f9d9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:02 +0100 Subject: [PATCH 0805/1040] arm64: dts: qcom: sm6375: Introduce C3 power state for both ARM clusters Introduce the C3 power state, which - to the best of my understanding - gates the CPU clock, but does not shut off the power rail. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-13-708b8191f7eb@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 36 +++++++++++++++++++++------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 6b75d8611077..f66f7ec66387 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -214,6 +214,16 @@ idle-states { entry-method = "psci"; + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; @@ -224,6 +234,16 @@ local-timer-stop; }; + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + local-timer-stop; + }; + BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; @@ -275,49 +295,49 @@ CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_1>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; }; CPU_PD6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_1>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; }; CPU_PD7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_1>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; }; CLUSTER_PD: power-domain-cpu-cluster0 { From 795ee50e55f4e869ad1d56f0262d0baa401f6c3d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 16 Mar 2023 15:13:03 +0100 Subject: [PATCH 0806/1040] arm64: dts: qcom: sm6375-pdx225: Add volume down GPIO key Add the required nodes to enable the volume down key on the Sony Xperia 10 IV. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230303-topic-sm6375_features0_dts-v2-14-708b8191f7eb@linaro.org --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index b691c3834b6b..8220e6f44117 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -46,6 +46,23 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&vol_down_n>; + pinctrl-names = "default"; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&pmr735a_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + reserved-memory { cont_splash_mem: memory@85200000 { reg = <0 0x85200000 0 0xc00000>; @@ -133,6 +150,16 @@ status = "okay"; }; +&pmr735a_gpios { + vol_down_n: vol-down-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + &pon_pwrkey { status = "okay"; }; From dffc4b5c086cf1d3dae4761427122a56b9d1253a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:08 +0100 Subject: [PATCH 0807/1040] arm64: dts: qcom: sm8250: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8250-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Ulf Hansson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7b78761f2041..69becde511c4 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -362,12 +362,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-llcc-off"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3264>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; From 1766e9155d086cd238c24113a7be9740d35c2ebe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:09 +0100 Subject: [PATCH 0808/1040] arm64: dts: qcom: sdm845: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sdm845-shift-axolotl.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 589b3470c3e1..47cd1ff46a91 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -339,12 +339,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; From ac7944f01b771af7718a81793ca5b38b0e3a0c21 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:10 +0100 Subject: [PATCH 0809/1040] arm64: dts: qcom: sm6375: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm6375-sony-xperia-murray-pdx225.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index f66f7ec66387..ae9b6bc446cb 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -258,12 +258,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <2752>; exit-latency-us = <3048>; min-residency-us = <6118>; - local-timer-stop; }; }; }; From 770f85c19536fde3591f4f2f70ac32f33d86b975 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:11 +0100 Subject: [PATCH 0810/1040] arm64: dts: qcom: sm8150: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8150-hdk.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 9491be4a6bf0..c9c04ac9bfcd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -295,12 +295,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c244>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; From 7983224c6a6cea77aa0b9b4e23bb7651241df961 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:12 +0100 Subject: [PATCH 0811/1040] arm64: dts: qcom: sm8350: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name' and 'local-timer-stop': sm8350-mtp.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7fbc288eca58..8985a59602f9 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -257,12 +257,10 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; - local-timer-stop; }; }; }; From ea1811e2614cd66608961ae3c5a9ee6038fc424b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 08:38:13 +0100 Subject: [PATCH 0812/1040] arm64: dts: qcom: sc8280xp: drop incorrect domain idle states properties Domain idle states do not use 'idle-state-name': sc8280xp-crd.dtb: domain-idle-states: cluster-sleep-0: 'idle-state-name' does not match any of the regexes: 'pinctrl-[0-9]+' Reported-by: Neil Armstrong Link: https://lore.kernel.org/all/20230323-topic-sm8450-upstream-dt-bindings-fixes-v1-4-3ead1e418fe4@linaro.org/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324073813.22158-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index cc7be432ec3c..451cd85cbac8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -276,7 +276,6 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <3263>; exit-latency-us = <6562>; From 35fa9a7fc577a4d1ed541ff37d9dda83b0635e4b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 24 Mar 2023 10:28:47 +0100 Subject: [PATCH 0813/1040] arm64: dts: qcom: sm8450: remove invalid properties in cluster-sleep nodes Fixes the following DT bindings check error: domain-idle-states: cluster-sleep-0: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' domain-idle-states: cluster-sleep-1: 'idle-state-name', 'local-timer-stop' do not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323-topic-sm8450-upstream-dt-bindings-fixes-v2-2-0ca1bea1a843@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 31877f18dce2..c59a922ce9f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -256,22 +256,18 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - idle-state-name = "cluster-l3-off"; arm,psci-suspend-param = <0x41000044>; entry-latency-us = <1050>; exit-latency-us = <2500>; min-residency-us = <5309>; - local-timer-stop; }; CLUSTER_SLEEP_1: cluster-sleep-1 { compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <2700>; exit-latency-us = <3500>; min-residency-us = <13959>; - local-timer-stop; }; }; }; From 7b4c00e9cc36e24e60d9907e6c3161791b11695c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 24 Mar 2023 10:37:54 +0100 Subject: [PATCH 0814/1040] arm64: defconfig: remove duplicate TYPEC_UCSI & QCOM_PMIC_GLINK Both configs were already applied by 2 separate changes, fix this to avoid: arch/arm64/configs/defconfig:989:warning: override: reassigning to symbol TYPEC_UCSI arch/arm64/configs/defconfig:1232:warning: override: reassigning to symbol QCOM_PMIC_GLINK Fixes: 4ffd0b001956 ("arm64: defconfig: add PMIC GLINK modules") Signed-off-by: Neil Armstrong Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324-topic-sm8450-upstream-defconfig-fixup-v1-1-2d75cc9b3c3d@linaro.org --- arch/arm64/configs/defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 2d9325a2163d..5c191a3058b5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -274,8 +274,6 @@ CONFIG_BLK_DEV_NVME=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_FASTRPC=m CONFIG_BATTERY_QCOM_BATTMGR=m -CONFIG_QCOM_PMIC_GLINK=m -CONFIG_TYPEC_UCSI=m CONFIG_UCSI_PMIC_GLINK=m CONFIG_SRAM=y CONFIG_PCI_ENDPOINT_TEST=m From 3042fb4b61c8a6ce692a4914b1970daa56e6f04e Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:49 +0100 Subject: [PATCH 0815/1040] arm64: dts: msm8953: Replace xo_board with rpmcc sourced xo Assign RPM_SMD_XO_CLK_SRC from rpmcc in place of fixed-clock where possible. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-1-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index da00c2f04cda..438a70eb6152 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ #include +#include #include #include #include @@ -637,7 +638,7 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clocks = <&xo_board>, + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, <0>, <0>, @@ -801,7 +802,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; @@ -868,7 +869,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>; + clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; status = "disabled"; @@ -992,7 +993,7 @@ clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; power-domains = <&rpmpd MSM8953_VDDCX>; @@ -1052,7 +1053,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; power-domains = <&rpmpd MSM8953_VDDCX>; From 635abd877516f6d5e35343d3c3eb233ab195ebc5 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:50 +0100 Subject: [PATCH 0816/1040] arm64: dts: msm8953: Provide dsi_phy clocks to gcc Provide clocks from dsi_phy to gcc, this will make sure we don't fallback to global name lookup. Signed-off-by: Adam Skladowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-2-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 438a70eb6152..5dd10c35ee0d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -640,10 +640,10 @@ #power-domain-cells = <1>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>; + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>; clock-names = "xo", "sleep", "dsi0pll", From c0494df2cdac723f4c7df834c05d548ea3a804e9 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:51 +0100 Subject: [PATCH 0817/1040] arm64: dts: msm8953: Drop unsupported dwc3 flag Property phy_mode according to binding checker does not exist, drop it. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-3-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 5dd10c35ee0d..0a1bf1058cbf 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -977,7 +977,6 @@ snps,hird-threshold = /bits/ 8 <0x00>; maximum-speed = "high-speed"; - phy_mode = "utmi"; }; }; From 26aae2310fd7375a5ca0dd772cd3bc57cf5e02bb Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Sat, 25 Mar 2023 12:28:52 +0100 Subject: [PATCH 0818/1040] arm64: dts: msm8953: Pad regs to 8 digits Follow other dtses and pad regs to 8 digits. Signed-off-by: Adam Skladowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325112852.18841-4-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 98 +++++++++++++-------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 0a1bf1058cbf..684668170353 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -350,12 +350,12 @@ rpm_msg_ram: sram@60000 { compatible = "qcom,rpm-msg-ram"; - reg = <0x60000 0x8000>; + reg = <0x00060000 0x8000>; }; hsusb_phy: phy@79000 { compatible = "qcom,msm8953-qusb2-phy"; - reg = <0x79000 0x180>; + reg = <0x00079000 0x180>; #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, @@ -378,8 +378,8 @@ tsens0: thermal-sensor@4a9000 { compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; - reg = <0x4a9000 0x1000>, /* TM */ - <0x4a8000 0x1000>; /* SROT */ + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ #qcom,sensors = <16>; interrupts = , ; @@ -389,12 +389,12 @@ restart@4ab000 { compatible = "qcom,pshold"; - reg = <0x4ab000 0x4>; + reg = <0x004ab000 0x4>; }; tlmm: pinctrl@1000000 { compatible = "qcom,msm8953-pinctrl"; - reg = <0x1000000 0x300000>; + reg = <0x01000000 0x300000>; interrupts = ; gpio-controller; gpio-ranges = <&tlmm 0 0 142>; @@ -634,7 +634,7 @@ gcc: clock-controller@1800000 { compatible = "qcom,gcc-msm8953"; - reg = <0x1800000 0x80000>; + reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -654,25 +654,25 @@ tcsr_mutex: hwlock@1905000 { compatible = "qcom,tcsr-mutex"; - reg = <0x1905000 0x20000>; + reg = <0x01905000 0x20000>; #hwlock-cells = <1>; }; tcsr: syscon@1937000 { compatible = "qcom,tcsr-msm8953", "syscon"; - reg = <0x1937000 0x30000>; + reg = <0x01937000 0x30000>; }; tcsr_phy_clk_scheme_sel: syscon@193f044 { compatible = "qcom,tcsr-msm8953", "syscon"; - reg = <0x193f044 0x4>; + reg = <0x0193f044 0x4>; }; mdss: display-subsystem@1a00000 { compatible = "qcom,mdss"; - reg = <0x1a00000 0x1000>, - <0x1ab0000 0x1040>; + reg = <0x01a00000 0x1000>, + <0x01ab0000 0x1040>; reg-names = "mdss_phys", "vbif_phys"; @@ -699,7 +699,7 @@ mdp: display-controller@1a01000 { compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; - reg = <0x1a01000 0x89000>; + reg = <0x01a01000 0x89000>; reg-names = "mdp_phys"; interrupt-parent = <&mdss>; @@ -740,7 +740,7 @@ dsi0: dsi@1a94000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0x1a94000 0x400>; + reg = <0x01a94000 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -792,9 +792,9 @@ dsi0_phy: phy@1a94400 { compatible = "qcom,dsi-phy-14nm-8953"; - reg = <0x1a94400 0x100>, - <0x1a94500 0x300>, - <0x1a94800 0x188>; + reg = <0x01a94400 0x100>, + <0x01a94500 0x300>, + <0x01a94800 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -810,7 +810,7 @@ dsi1: dsi@1a96000 { compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; - reg = <0x1a96000 0x400>; + reg = <0x01a96000 0x400>; reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; @@ -859,9 +859,9 @@ dsi1_phy: phy@1a96400 { compatible = "qcom,dsi-phy-14nm-8953"; - reg = <0x1a96400 0x100>, - <0x1a96500 0x300>, - <0x1a96800 0x188>; + reg = <0x01a96400 0x100>, + <0x01a96500 0x300>, + <0x01a96800 0x188>; reg-names = "dsi_phy", "dsi_phy_lane", "dsi_pll"; @@ -878,7 +878,7 @@ apps_iommu: iommu@1e00000 { compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; - ranges = <0 0x1e20000 0x20000>; + ranges = <0 0x01e20000 0x20000>; clocks = <&gcc GCC_SMMU_CFG_CLK>, <&gcc GCC_APSS_TCU_ASYNC_CLK>; @@ -914,11 +914,11 @@ spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x200f000 0x1000>, - <0x2400000 0x800000>, - <0x2c00000 0x800000>, - <0x3800000 0x200000>, - <0x200a000 0x2100>; + reg = <0x0200f000 0x1000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x2100>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; @@ -933,7 +933,7 @@ usb3: usb@70f8800 { compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; - reg = <0x70f8800 0x400>; + reg = <0x070f8800 0x400>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -983,7 +983,7 @@ sdhc_1: mmc@7824900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x7824900 0x500>, <0x7824000 0x800>; + reg = <0x07824900 0x500>, <0x07824000 0x800>; reg-names = "hc", "core"; interrupts = , @@ -1043,7 +1043,7 @@ sdhc_2: mmc@7864900 { compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; - reg = <0x7864900 0x500>, <0x7864000 0x800>; + reg = <0x07864900 0x500>, <0x07864000 0x800>; reg-names = "hc", "core"; interrupts = , @@ -1098,7 +1098,7 @@ uart_0: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; - reg = <0x78af000 0x200>; + reg = <0x078af000 0x200>; interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; @@ -1109,7 +1109,7 @@ i2c_1: i2c@78b5000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b5000 0x600>; + reg = <0x078b5000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, @@ -1127,7 +1127,7 @@ i2c_2: i2c@78b6000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b6000 0x600>; + reg = <0x078b6000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, @@ -1145,7 +1145,7 @@ i2c_3: i2c@78b7000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b7000 0x600>; + reg = <0x078b7000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, @@ -1162,7 +1162,7 @@ i2c_4: i2c@78b8000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x78b8000 0x600>; + reg = <0x078b8000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, @@ -1179,7 +1179,7 @@ i2c_5: i2c@7af5000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af5000 0x600>; + reg = <0x07af5000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, @@ -1196,7 +1196,7 @@ i2c_6: i2c@7af6000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af6000 0x600>; + reg = <0x07af6000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, @@ -1213,7 +1213,7 @@ i2c_7: i2c@7af7000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af7000 0x600>; + reg = <0x07af7000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, @@ -1230,7 +1230,7 @@ i2c_8: i2c@7af8000 { compatible = "qcom,i2c-qup-v2.2.1"; - reg = <0x7af8000 0x600>; + reg = <0x07af8000 0x600>; interrupts = ; clock-names = "core", "iface"; clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, @@ -1254,13 +1254,13 @@ apcs: mailbox@b011000 { compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; - reg = <0xb011000 0x1000>; + reg = <0x0b011000 0x1000>; #mbox-cells = <1>; }; timer@b120000 { compatible = "arm,armv7-timer-mem"; - reg = <0xb120000 0x1000>; + reg = <0x0b120000 0x1000>; #address-cells = <0x01>; #size-cells = <0x01>; ranges; @@ -1269,49 +1269,49 @@ frame-number = <0>; interrupts = , ; - reg = <0xb121000 0x1000>, - <0xb122000 0x1000>; + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; }; frame@b123000 { frame-number = <1>; interrupts = ; - reg = <0xb123000 0x1000>; + reg = <0x0b123000 0x1000>; status = "disabled"; }; frame@b124000 { frame-number = <2>; interrupts = ; - reg = <0xb124000 0x1000>; + reg = <0x0b124000 0x1000>; status = "disabled"; }; frame@b125000 { frame-number = <3>; interrupts = ; - reg = <0xb125000 0x1000>; + reg = <0x0b125000 0x1000>; status = "disabled"; }; frame@b126000 { frame-number = <4>; interrupts = ; - reg = <0xb126000 0x1000>; + reg = <0x0b126000 0x1000>; status = "disabled"; }; frame@b127000 { frame-number = <5>; interrupts = ; - reg = <0xb127000 0x1000>; + reg = <0x0b127000 0x1000>; status = "disabled"; }; frame@b128000 { frame-number = <6>; interrupts = ; - reg = <0xb128000 0x1000>; + reg = <0x0b128000 0x1000>; status = "disabled"; }; }; From c78ad8597ed961e822bf86ce7f1916dbfba255ef Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Sat, 25 Mar 2023 17:54:33 +0530 Subject: [PATCH 0819/1040] dt-bindings: firmware: document Qualcomm SC8180X SCM Document the compatible for Qualcomm sc8180x SCM. Acked-by: Krzysztof Kozlowski Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230325122444.249507-2-vkoul@kernel.org --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 543feb3b6c58..c3851b13cd5a 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -44,6 +44,7 @@ properties: - qcom,scm-sa8775p - qcom,scm-sc7180 - qcom,scm-sc7280 + - qcom,scm-sc8180x - qcom,scm-sc8280xp - qcom,scm-sdm670 - qcom,scm-sdm845 From 5dcc6587fde26fa03fe6993278d9bd01daed09b1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:18 +0200 Subject: [PATCH 0820/1040] arm64: dts: qcom: sdm845-tama: Add display nodes Add required nodes to support display on XZ2/XZ2c. XZ3 has a different power rail setup and needs to be handled separately. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-1-2b1567c039d7@linaro.org --- .../qcom/sdm845-sony-xperia-tama-akari.dts | 4 + .../qcom/sdm845-sony-xperia-tama-akatsuki.dts | 44 ++++++++- .../qcom/sdm845-sony-xperia-tama-apollo.dts | 6 ++ .../dts/qcom/sdm845-sony-xperia-tama.dtsi | 93 +++++++++++++++++++ 4 files changed, 146 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts index 34f84f1f1eb4..d97b7f1e7140 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akari.dts @@ -11,3 +11,7 @@ model = "Sony Xperia XZ2"; compatible = "sony,akari-row", "qcom,sdm845"; }; + +&panel { + compatible = "sony,td4353-jdi-tama"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts index 2f5e12deaada..81cbf535cb76 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -10,9 +10,51 @@ / { model = "Sony Xperia XZ3"; compatible = "sony,akatsuki-row", "qcom,sdm845"; + + /* Fixed DCDC for the OLED panel */ + ts_vddio_supply: ts-vddio-regulator { + compatible = "regulator-fixed"; + regulator-name = "ts_vddio"; + + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <1840000>; + + gpio = <&tlmm 133 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ibb { + status = "disabled"; +}; + +&lab { + status = "disabled"; +}; + +&panel { + /* Akatsuki uses an OLED panel. */ + /delete-property/ backlight; + /delete-property/ vsp-supply; + /delete-property/ vsn-supply; + /delete-property/ touch-reset-gpios; +}; + +&pmi8998_wled { + status = "disabled"; +}; + +&tlmm { + ts_vddio_en: ts-vddio-en-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; }; -/* For the future: WLED + LAB/IBB/OLEDB are not used on Akatsuki */ &vreg_l14a_1p8 { regulator-min-microvolt = <1840000>; regulator-max-microvolt = <1840000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts index c9e62c72f60e..cd056f78070f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-apollo.dts @@ -11,3 +11,9 @@ model = "Sony Xperia XZ2 Compact"; compatible = "sony,apollo-row", "qcom,sdm845"; }; + +&panel { + compatible = "sony,td4353-jdi-tama"; + height-mm = <112>; + width-mm = <56>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 4984c7496c31..3c7d129d9d8e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -356,6 +356,43 @@ }; }; +&dsi0 { + vdda-supply = <&vreg_l26a_1p2>; + status = "okay"; + + panel: panel@0 { + /* The compatible is assigned in device DTs. */ + reg = <0>; + + backlight = <&pmi8998_wled>; + vddio-supply = <&vreg_l14a_1p8>; + vsp-supply = <&lab>; + vsn-supply = <&ibb>; + panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>; + pinctrl-1 = <&sde_dsi_sleep &sde_te_active_sleep>; + pinctrl-names = "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + vdds-supply = <&vreg_l1a_0p9>; + status = "okay"; +}; + &gcc { protected-clocks = , , @@ -388,6 +425,31 @@ /* AMS TCS3490 RGB+IR color sensor @ 72 */ }; +&ibb { + qcom,discharge-resistor-kohms = <300>; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5700000>; + regulator-min-microamp = <0>; + regulator-max-microamp = <800000>; + regulator-over-current-protection; + regulator-soft-start; + regulator-pull-down; +}; + +&lab { + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5700000>; + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-over-current-protection; + regulator-soft-start; + regulator-pull-down; +}; + +&mdss { + status = "okay"; +}; + &pm8998_gpios { focus_n: focus-n-state { pins = "gpio2"; @@ -422,6 +484,16 @@ }; }; +&pmi8998_wled { + default-brightness = <800>; + qcom,switching-freq = <800>; + qcom,ovp-millivolt = <29600>; + qcom,current-boost-limit = <970>; + qcom,current-limit-microamp = <20000>; + qcom,enabled-strings = <0 1 2 3>; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -465,6 +537,27 @@ bias-pull-up; }; }; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_sleep: sde-dsi-sleep-state { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active_sleep: sde-te-active-sleep-state { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart6 { From 3ab8216de2fab6a6efeb5b22d8d61676b67964dc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:19 +0200 Subject: [PATCH 0821/1040] arm64: dts: qcom: sdm845-tama: Add Synaptics Touchscreen Add required pins and RMI4 node to the common DT and remove it from Akatsuki, as it uses a different touch. Since the panels are super high tech proprietary incell, they need to be handled with very precise timings. As such the panel driver sets up the power rails and GPIOs and the touchscreen driver *has to* probe afterwards. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-2-2b1567c039d7@linaro.org --- .../qcom/sdm845-sony-xperia-tama-akatsuki.dts | 3 + .../dts/qcom/sdm845-sony-xperia-tama.dtsi | 68 ++++++++++++++++++- 2 files changed, 69 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts index 81cbf535cb76..5d2052a0ff69 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama-akatsuki.dts @@ -7,6 +7,9 @@ #include "sdm845-sony-xperia-tama.dtsi" +/* XZ3 uses an Atmel touchscreen instead. */ +/delete-node/ &touchscreen; + / { model = "Sony Xperia XZ3"; compatible = "sony,akatsuki-row", "qcom,sdm845"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 3c7d129d9d8e..8172d0c9c1a3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -402,10 +402,42 @@ }; &i2c5 { - status = "okay"; clock-frequency = <400000>; + status = "okay"; - /* Synaptics touchscreen @ 2c, 3c */ + touchscreen: touchscreen@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vreg_l14a_1p8>; + /* + * This is a blatant abuse of OF, but the panel driver *needs* + * to probe first, as the power/gpio switching needs to be precisely + * timed in order for both the display and touch panel to function properly. + */ + incell-supply = <&panel>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <1000>; + + pinctrl-0 = <&ts_default>; + pinctrl-1 = <&ts_sleep>; + pinctrl-names = "default", "sleep"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; }; &i2c10 { @@ -558,6 +590,38 @@ drive-strength = <2>; bias-pull-down; }; + + ts_default: ts-default-state { + reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + int-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + ts_sleep: ts-sleep-state { + reset-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + int-pins { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; &uart6 { From 1d99fee382a6ada0cd05ae8afaea2dd1884c58a3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:20 +0200 Subject: [PATCH 0822/1040] arm64: dts: qcom: sdm845-tama: Add regulator-system-load to l14a/l28a Add the properties to ensure the ever so delicate touchscreen setup matches downstream. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-3-2b1567c039d7@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 8172d0c9c1a3..208ed466081d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -228,6 +228,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-system-load = <62000>; }; vreg_l15a_1p8: ldo15 { @@ -314,6 +315,7 @@ regulator-min-microvolt = <2856000>; regulator-max-microvolt = <3008000>; regulator-initial-mode = ; + regulator-system-load = <100000>; }; vreg_lvs1a_1p8: lvs1 { From 39e0f8076f6fc5022902c62f5046ad91cf2b7a59 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:21 +0200 Subject: [PATCH 0823/1040] arm64: dts: qcom: sdm845-tama: Enable remoteprocs Enable ADSP, CDSP and Venus. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-4-2b1567c039d7@linaro.org --- .../boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 208ed466081d..48916a3216e5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -98,6 +98,11 @@ }; }; +&adsp_pas { + firmware-name = "qcom/sdm845/Sony/tama/adsp.mbn"; + status = "okay"; +}; + &apps_rsc { regulators-0 { compatible = "qcom,pm8998-rpmh-regulators"; @@ -358,6 +363,11 @@ }; }; +&cdsp_pas { + firmware-name = "qcom/sdm845/Sony/tama/cdsp.mbn"; + status = "okay"; +}; + &dsi0 { vdda-supply = <&vreg_l26a_1p2>; status = "okay"; @@ -659,3 +669,8 @@ vdda-pll-supply = <&vreg_l12a_1p8>; vdda-phy-dpdm-supply = <&vreg_l24a_3p1>; }; + +&venus { + firmware-name = "qcom/sdm845/Sony/tama/venus.mbn"; + status = "okay"; +}; From ff9108ea69adc0b38e5bbc8575434355f0e20579 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:22 +0200 Subject: [PATCH 0824/1040] arm64: dts: qcom: sdm845-tama: Enable GPU Enable the A630 GPU and its GMU. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-5-2b1567c039d7@linaro.org --- .../boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 48916a3216e5..df8dd6e45a38 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -413,6 +413,19 @@ ; }; +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/Sony/tama/a630_zap.mbn"; + }; +}; + &i2c5 { clock-frequency = <400000>; status = "okay"; From da51e2ceedc2df7248bad6bec45ae3280de9ada2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:41:23 +0200 Subject: [PATCH 0825/1040] arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1 Enable both GPI DMAs. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230313-topic-tama_disp-v3-6-2b1567c039d7@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index df8dd6e45a38..420ffede3e80 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -417,6 +417,14 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; From 894e258b6a38922f9860a20ca07cf2f745e3b090 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 3 Apr 2023 15:23:28 +0200 Subject: [PATCH 0826/1040] arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name The bindings expect second Soundwire interrupt to be "wakeup" (Linux driver takes by index): sc8280xp-crd.dtb: soundwire-controller@3330000: interrupt-names:1: 'wakeup' was expected Fixes: c18773d162a6 ("arm64: dts: qcom: sc8280xp: add SoundWire and LPASS") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230403132328.61414-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 451cd85cbac8..a33df7a1adea 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2605,7 +2605,7 @@ reg = <0 0x03330000 0 0x2000>; interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "core", "wake"; + interrupt-names = "core", "wakeup"; clocks = <&txmacro>; clock-names = "iface"; From 3fd7e2eec8f4fedbe3b252cf436be8527f7a5f82 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:52:59 +0200 Subject: [PATCH 0827/1040] arm64: dts: qcom: sa8775p: pad reg properties to 8 digits The file has inconsistent padding of the address part of soc node children's reg properties. Fix it. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-2-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index c5b73c591e0f..5aa28a3b12ae 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -440,7 +440,7 @@ gcc: clock-controller@100000 { compatible = "qcom,sa8775p-gcc"; - reg = <0x0 0x100000 0x0 0xc7018>; + reg = <0x0 0x00100000 0x0 0xc7018>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; @@ -464,7 +464,7 @@ ipcc: mailbox@408000 { compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; - reg = <0x0 0x408000 0x0 0x1000>; + reg = <0x0 0x00408000 0x0 0x1000>; interrupts = ; interrupt-controller; #interrupt-cells = <3>; @@ -473,7 +473,7 @@ qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; - reg = <0x0 0xac0000 0x0 0x6000>; + reg = <0x0 0x00ac0000 0x0 0x6000>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -485,7 +485,7 @@ uart10: serial@a8c000 { compatible = "qcom,geni-uart"; - reg = <0x0 0xa8c000 0x0 0x4000>; + reg = <0x0 0x00a8c000 0x0 0x4000>; interrupts = ; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; @@ -735,7 +735,7 @@ tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x1f40000 0x0 0x20000>; + reg = <0x0 0x01f40000 0x0 0x20000>; #hwlock-cells = <1>; }; @@ -754,7 +754,7 @@ tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; - reg = <0x0 0xf000000 0x0 0x1000000>; + reg = <0x0 0x0f000000 0x0 0x1000000>; interrupts = ; gpio-controller; #gpio-cells = <2>; From f95f988cf7b609157630dd1f2f7e8d297aadbe2b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:00 +0200 Subject: [PATCH 0828/1040] arm64: dts: qcom: sa8775p: sort soc nodes by reg property Sort all children of the soc node by the first address in their reg property. This was mostly already the case but there were some nodes that didn't follow it so fix it now for consistency. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-3-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 394 +++++++++++++------------- 1 file changed, 197 insertions(+), 197 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 5aa28a3b12ae..296ba69b81ab 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -471,50 +471,6 @@ #mbox-cells = <2>; }; - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - iommus = <&apps_smmu 0x443 0x0>; - status = "disabled"; - - uart10: serial@a8c000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a8c000 0x0 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 - &clk_virt SLAVE_QUP_CORE_1 0>, - <&gem_noc MASTER_APPSS_PROC 0 - &config_noc SLAVE_QUP_1 0>; - power-domains = <&rpmhpd SA8775P_CX>; - operating-points-v2 = <&qup_opp_table_100mhz>; - status = "disabled"; - }; - - uart12: serial@a94000 { - compatible = "qcom,geni-uart"; - reg = <0x0 0x00a94000 0x0 0x4000>; - interrupts = ; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - clock-names = "se"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS - &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, - <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS - &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; - interconnect-names = "qup-core", "qup-config"; - power-domains = <&rpmhpd SA8775P_CX>; - status = "disabled"; - }; - }; - qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -585,152 +541,48 @@ }; }; - intc: interrupt-controller@17a00000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x20000>; - }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; - memtimer: timer@17c20000 { - compatible = "arm,armv7-timer-mem"; - reg = <0x0 0x17c20000 0x0 0x1000>; - ranges = <0x0 0x0 0x0 0x20000000>; - #address-cells = <1>; - #size-cells = <1>; - - frame@17c21000 { - reg = <0x17c21000 0x1000>, - <0x17c22000 0x1000>; - interrupts = , - ; - frame-number = <0>; - }; - - frame@17c23000 { - reg = <0x17c23000 0x1000>; - interrupts = ; - frame-number = <1>; + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; - frame@17c25000 { - reg = <0x17c25000 0x1000>; - interrupts = ; - frame-number = <2>; + uart12: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; - - frame@17c27000 { - reg = <0x17c27000 0x1000>; - interrupts = ; - frame-number = <3>; - status = "disabled"; - }; - - frame@17c29000 { - reg = <0x17c29000 0x1000>; - interrupts = ; - frame-number = <4>; - status = "disabled"; - }; - - frame@17c2b000 { - reg = <0x17c2b000 0x1000>; - interrupts = ; - frame-number = <5>; - status = "disabled"; - }; - - frame@17c2d000 { - reg = <0x17c2d000 0x1000>; - interrupts = ; - frame-number = <6>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@18200000 { - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x18200000 0x0 0x10000>, - <0x0 0x18210000 0x0 0x10000>, - <0x0 0x18220000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - label = "apps_rsc"; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sa8775p-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board_clk>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sa8775p-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp-0 { - opp-level = ; - }; - - rpmhpd_opp_min_svs: opp-1 { - opp-level = ; - }; - - rpmhpd_opp_low_svs: opp2 { - opp-level = ; - }; - - rpmhpd_opp_svs: opp3 { - opp-level = ; - }; - - rpmhpd_opp_svs_l1: opp-4 { - opp-level = ; - }; - - rpmhpd_opp_nom: opp-5 { - opp-level = ; - }; - - rpmhpd_opp_nom_l1: opp-6 { - opp-level = ; - }; - - rpmhpd_opp_nom_l2: opp-7 { - opp-level = ; - }; - - rpmhpd_opp_turbo: opp-8 { - opp-level = ; - }; - - rpmhpd_opp_turbo_l1: opp-9 { - opp-level = ; - }; - }; - }; }; tcsr_mutex: hwlock@1f40000 { @@ -739,19 +591,6 @@ #hwlock-cells = <1>; }; - cpufreq_hw: cpufreq@18591000 { - compatible = "qcom,sa8775p-cpufreq-epss", - "qcom,cpufreq-epss"; - reg = <0x0 0x18591000 0x0 0x1000>, - <0x0 0x18593000 0x0 0x1000>; - reg-names = "freq-domain0", "freq-domain1"; - - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - - #freq-domain-cells = <1>; - }; - tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>; @@ -900,6 +739,167 @@ , ; }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sa8775p-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sa8775p-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible = "qcom,sa8775p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg = <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; arch_timer: timer { From 8696cd072e955bd6f5df757774e47f0b9dd29920 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:02 +0200 Subject: [PATCH 0829/1040] arm64: dts: qcom: sa8775p: add the pdc node Add the Power Domain Controller node for SA8775p. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-5-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 47 +++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 296ba69b81ab..6bb1db1839cc 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -591,6 +591,53 @@ #hwlock-cells = <1>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sa8775p-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges = <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>; From fdd55b3babedce5abd1c1f90afc3ab2199a772ad Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:03 +0200 Subject: [PATCH 0830/1040] arm64: dts: qcom: sa8775p: add the spmi node Add the SPMI PMIC Arbiter node for SA8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-6-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 6bb1db1839cc..2343df7e0ea4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -638,6 +638,28 @@ interrupt-controller; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + qcom,channel = <0>; + qcom,ee = <0>; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sa8775p-tlmm"; reg = <0x0 0x0f000000 0x0 0x1000000>; From 634a3de323fc5c67c144919e298259d8d9d44a4b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:05 +0200 Subject: [PATCH 0831/1040] arm64: dts: qcom: sa8775p: add support for the on-board PMICs Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced to the SoC via SPMI. Enable the PMICs for sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 37 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 1 + 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi new file mode 100644 index 000000000000..afe220b374c2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include + +&spmi_bus { + pmm8654au_0: pmic@0 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_1: pmic@2 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x2 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_2: pmic@4 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x4 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; + + pmm8654au_3: pmic@6 { + compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 1020dfd21da2..b7ee4cc676b5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sa8775p.dtsi" +#include "sa8775p-pmics.dtsi" / { model = "Qualcomm SA8775P Ride"; From d2d9a592746cd454bd5b8f72193f2d3db2e62a44 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:06 +0200 Subject: [PATCH 0832/1040] arm64: dts: qcom: sa8775p: add the Power On device node Add the PON node to PMIC #0 for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-9-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index afe220b374c2..dbc596e32253 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -12,6 +12,14 @@ reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_0_pon: pon@1200 { + compatible = "qcom,pmk8350-pon"; + reg = <0x1200>, <0x800>; + reg-names = "hlos", "pbs"; + mode-recovery = <0x1>; + mode-bootloader = <0x2>; + }; }; pmm8654au_1: pmic@2 { From b3a755ba16e6f61d93c811b827edacc9946b0500 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:07 +0200 Subject: [PATCH 0833/1040] arm64: dts: qcom: sa8775p: pmic: add the power key Add the power key node under the PON node for PMIC #0 on sa8775p. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-10-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index dbc596e32253..f421d4d64c8e 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -19,6 +19,13 @@ reg-names = "hlos", "pbs"; mode-recovery = <0x1>; mode-bootloader = <0x2>; + + pmm8654au_0_pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts-extended = <&spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + debounce = <15625>; + }; }; }; From cecff1f5429d975df9649376e2bd5a2fb004f988 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:08 +0200 Subject: [PATCH 0834/1040] arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input Add the RESIN input for sa8775p platforms' PMIC. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-11-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index f421d4d64c8e..8616ead3daf5 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -26,6 +26,13 @@ linux,code = ; debounce = <15625>; }; + + pmm8654au_0_pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts-extended = <&spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + status = "disabled"; + }; }; }; From fa40ca07e943333a14d247988ef5008a59949153 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:09 +0200 Subject: [PATCH 0835/1040] arm64: dts: qcom: sa8775p: pmic: add thermal zones Add the thermal zones and associated alarm nodes for the PMICs that have them hooked up on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-12-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 112 ++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index 8616ead3daf5..be12997a080c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -6,6 +6,90 @@ #include #include +/ { + thermal-zones { + pmm8654au_0_thermal: pm8775-0-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_0_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8775-1-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_1_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8775-2-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_2_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8775-3-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmm8654au_3_temp_alarm>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmm8654au_0: pmic@0 { compatible = "qcom,pmm8654au", "qcom,spmi-pmic"; @@ -13,6 +97,13 @@ #address-cells = <1>; #size-cells = <0>; + pmm8654au_0_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmm8654au_0_pon: pon@1200 { compatible = "qcom,pmk8350-pon"; reg = <0x1200>, <0x800>; @@ -41,6 +132,13 @@ reg = <0x2 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_1_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_2: pmic@4 { @@ -48,6 +146,13 @@ reg = <0x4 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_2_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; pmm8654au_3: pmic@6 { @@ -55,5 +160,12 @@ reg = <0x6 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pmm8654au_3_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; }; }; From e5a893a7cec5776e10c25d7fa80b5ad1edf88c17 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:12 +0200 Subject: [PATCH 0836/1040] arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes Add GPIO controller nodes to PMICs that have the GPIO hooked up on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-15-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi | 40 +++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi index be12997a080c..7602cca47bae 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi @@ -125,6 +125,16 @@ status = "disabled"; }; }; + + pmm8654au_0_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_0_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_1: pmic@2 { @@ -139,6 +149,16 @@ interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_1_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_2: pmic@4 { @@ -153,6 +173,16 @@ interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_2_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_2_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmm8654au_3: pmic@6 { @@ -167,5 +197,15 @@ interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; + + pmm8654au_3_gpios: gpio@8800 { + compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmm8654au_3_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; }; From 81767c1591dcb711f1f78a80e510b667b1fb5718 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 27 Mar 2023 14:53:13 +0200 Subject: [PATCH 0837/1040] arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs Set line names for GPIO lines exposed by PMICs on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 51 +++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index b7ee4cc676b5..a0d2024a69df 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -32,6 +32,57 @@ status = "okay"; }; +&pmm8654au_0_gpios { + gpio-line-names = "DS_EN", + "POFF_COMPLETE", + "UFS0_VER_ID", + "FAST_POFF", + "DBU1_PON_DONE", + "AOSS_SLEEP", + "CAM_DES0_EN", + "CAM_DES1_EN", + "CAM_DES2_EN", + "CAM_DES3_EN", + "UEFI", + "ANALOG_PON_OPT"; +}; + +&pmm8654au_1_gpios { + gpio-line-names = "PMIC_C_ID0", + "PMIC_C_ID1", + "UFS1_VER_ID", + "IPA_PWR", + "", + "WLAN_DBU4_EN", + "WLAN_EN", + "BT_EN", + "USB2_PWR_EN", + "USB2_FAULT"; +}; + +&pmm8654au_2_gpios { + gpio-line-names = "PMIC_E_ID0", + "PMIC_E_ID1", + "USB0_PWR_EN", + "USB0_FAULT", + "SENSOR_IRQ_1", + "SENSOR_IRQ_2", + "SENSOR_RST", + "SGMIIO0_RST", + "SGMIIO1_RST", + "USB1_PWR_ENABLE", + "USB1_FAULT", + "VMON_SPX8"; +}; + +&pmm8654au_3_gpios { + gpio-line-names = "PMIC_G_ID0", + "PMIC_G_ID1", + "GNSS_RST", + "GNSS_EN", + "GNSS_BOOT_MODE"; +}; + &qupv3_id_1 { status = "okay"; }; From b8e0ed06d1a569694c8976c3563bbd0aae728e1d Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 16 Mar 2023 13:41:14 +0530 Subject: [PATCH 0838/1040] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316081117.14288-17-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 47cd1ff46a91..da4b200281d8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2291,8 +2291,9 @@ reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01c07000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; @@ -2396,8 +2397,9 @@ reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; + <0 0x40100000 0 0x100000>, + <0 0x01c0c000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; From 89210342406b91954c514d171baeabb91f85f0a5 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 16 Mar 2023 13:41:15 +0530 Subject: [PATCH 0839/1040] arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316081117.14288-18-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 69becde511c4..4e7875f8786f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1829,8 +1829,9 @@ <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; @@ -1938,8 +1939,9 @@ <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x40100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; @@ -2046,8 +2048,9 @@ <0 0x64000000 0 0xf1d>, <0 0x64000f20 0 0xa8>, <0 0x64001000 0 0x1000>, - <0 0x64100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x64100000 0 0x100000>, + <0 0x01c13000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <2>; bus-range = <0x00 0xff>; From de7d3d2f9ddef9a3305decccdd3b95b09fd2bd46 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 16 Mar 2023 13:41:16 +0530 Subject: [PATCH 0840/1040] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316081117.14288-19-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a33df7a1adea..2b76be6a5f1c 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1660,8 +1660,9 @@ <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, - <0x0 0x30100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x30100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, @@ -1759,8 +1760,9 @@ <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, - <0x0 0x32100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x32100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, @@ -1856,8 +1858,9 @@ <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, - <0x0 0x34100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x34100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, @@ -1956,8 +1959,9 @@ <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, - <0x0 0x38100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x38100000 0x0 0x100000>, + <0x0 0x01c1b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, @@ -2053,8 +2057,9 @@ <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, - <0x0 0x3c100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, From 9db28f297526f17c6575ec0eefc93a8b1642cff7 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Sun, 26 Mar 2023 18:38:11 -0500 Subject: [PATCH 0841/1040] arm64: dts: qcom: sc8280xp: Define uart2 Add the definition for uart2 for sc8280xp devices. Signed-off-by: Bjorn Andersson Signed-off-by: Steev Klimaszewski Reviewed-by: Brian Masney Reviewed-by: Johan Hovold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326233812.28058-4-steev@kali.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 2b76be6a5f1c..4c75da1bac2d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1214,6 +1214,20 @@ status = "disabled"; }; + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00988000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interrupts = ; + operating-points-v2 = <&qup_opp_table_100mhz>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>; From 105560b4fca4df0d42dba6656105b5e4131d8ad3 Mon Sep 17 00:00:00 2001 From: Steev Klimaszewski Date: Sun, 26 Mar 2023 18:38:12 -0500 Subject: [PATCH 0842/1040] arm64: dts: qcom: sc8280xp-x13s: Add bluetooth The Lenovo Thinkpad X13s has a WCN6855 Bluetooth controller on uart2, add this. Signed-off-by: Steev Klimaszewski Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230326233812.28058-5-steev@kali.org --- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 4884e22ccca1..a1db3cf80c47 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -24,6 +24,7 @@ aliases { i2c4 = &i2c4; i2c21 = &i2c21; + serial1 = &uart2; }; wcd938x: audio-codec { @@ -1067,6 +1068,32 @@ status = "okay"; }; +&uart2 { + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn6855-bt"; + + vddio-supply = <&vreg_s10b>; + vddbtcxmx-supply = <&vreg_s12b>; + vddrfacmn-supply = <&vreg_s12b>; + vddrfa0p8-supply = <&vreg_s12b>; + vddrfa1p2-supply = <&vreg_s11b>; + vddrfa1p7-supply = <&vreg_s1c>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; +}; + &usb_0 { status = "okay"; }; @@ -1187,6 +1214,21 @@ &tlmm { gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + bt_default: bt-default-state { + hstp-bt-en-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + hstp-sw-ctrl-pins { + pins = "gpio132"; + function = "gpio"; + bias-pull-down; + }; + }; + edp_reg_en: edp-reg-en-state { pins = "gpio25"; function = "gpio"; @@ -1353,6 +1395,34 @@ }; }; + uart2_default: uart2-default-state { + cts-pins { + pins = "gpio121"; + function = "qup2"; + bias-bus-hold; + }; + + rts-pins { + pins = "gpio122"; + function = "qup2"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio124"; + function = "qup2"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio123"; + function = "qup2"; + drive-strength = <2>; + bias-disable; + }; + }; + usb0_sbu_default: usb0-sbu-state { oe-n-pins { pins = "gpio101"; From e154a338e16cc3b3bbd54c891253319d22383746 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Feb 2023 20:28:49 +0100 Subject: [PATCH 0843/1040] dt-bindings: soc: samsung: exynos-pmu: allow phys as child on Exynos3 and Exynos4 Just like on Exynos5250, Exynos5420 and Exynos5433 the MIPI phy is actually part of the Power Management Unit system controller thus allow it as PMU's child. Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230207192851.549242-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/soc/samsung/exynos-pmu.yaml | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index f7c141dd11ec..5d8d9497f18e 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -48,6 +48,9 @@ properties: - const: syscon - items: - enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5420-pmu - samsung,exynos5433-pmu @@ -133,6 +136,24 @@ allOf: - clock-names - clocks + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + then: + properties: + mipi-phy: true + else: + properties: + mipi-phy: false + - if: properties: compatible: @@ -144,11 +165,9 @@ allOf: then: properties: dp-phy: true - mipi-phy: true else: properties: dp-phy: false - mipi-phy: false examples: - | From 92ac94f7e176bb9f5a9735bc1be6d69e96d4d5c1 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Tue, 4 Apr 2023 12:50:25 +0100 Subject: [PATCH 0844/1040] dt-bindings: firmware: arm,scmi: Support mailboxes unidirectional channels SCMI defines two kinds of communication channels between the agent and the platform: one bidirectional 'a2p' channel used by the agent to send SCMI commands and synchronously receive the related replies, and an optional 'p2a' unidirectional channel used to asynchronously receive delayed responses and notifications emitted from the platform. When configuring an SCMI transport based on mailboxes, the current binding supports only mailboxes providing bidirectional channels: in such a case one mailbox channel can be easily assigned to each SCMI channel as above described. In case, instead, to have to deal with mailboxes providing only distinct unidirectional channels, it becomes necessary to extend the binding in order to be able to bind 2 distinct unidirectional mailbox channels to the same SCMI 'a2p' channel. Bidirectional and unidirectional channels support for the SCMI mailbox transport can coexist by carefully considering the effective combination of defined 'mboxes' and 'shmem' descriptors. Signed-off-by: Cristian Marussi Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20230404115026.2828149-2-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- .../bindings/firmware/arm,scmi.yaml | 48 +++++++++++++++---- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 2f7c51c75e85..5824c43e9893 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -56,17 +56,38 @@ properties: description: Specifies the mailboxes used to communicate with SCMI compliant firmware. - items: - - const: tx - - const: rx + oneOf: + - items: + - const: tx + - const: rx + minItems: 1 + - items: + - const: tx + - const: tx_reply + - const: rx + minItems: 2 mboxes: description: List of phandle and mailbox channel specifiers. It should contain - exactly one or two mailboxes, one for transmitting messages("tx") - and another optional for receiving the notifications("rx") if supported. + exactly one, two or three mailboxes; the first one or two for transmitting + messages ("tx") and another optional ("rx") for receiving notifications + and delayed responses, if supported by the platform. + The number of mailboxes needed for transmitting messages depends on the + type of channels exposed by the specific underlying mailbox controller; + one single channel descriptor is enough if such channel is bidirectional, + while two channel descriptors are needed to represent the SCMI ("tx") + channel if the underlying mailbox channels are of unidirectional type. + The effective combination in numbers of mboxes and shmem descriptors let + the SCMI subsystem determine unambiguosly which type of SCMI channels are + made available by the underlying mailbox controller and how to use them. + 1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel + 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels + 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels + 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels + Any other combination of mboxes and shmem is invalid. minItems: 1 - maxItems: 2 + maxItems: 3 shmem: description: @@ -228,13 +249,20 @@ $defs: maxItems: 1 mbox-names: - items: - - const: tx - - const: rx + oneOf: + - items: + - const: tx + - const: rx + minItems: 1 + - items: + - const: tx + - const: tx_reply + - const: rx + minItems: 2 mboxes: minItems: 1 - maxItems: 2 + maxItems: 3 shmem: minItems: 1 From 9f68ff79ec2cb303f360a35eef5dd8f1f0f817e1 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Tue, 4 Apr 2023 12:50:26 +0100 Subject: [PATCH 0845/1040] firmware: arm_scmi: Add support for unidirectional mailbox channels Extend the SCMI transport layer to support mailbox controllers that expose communication channels that are unidirectional by nature. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230404115026.2828149-3-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/mailbox.c | 95 +++++++++++++++++++++++++---- 1 file changed, 84 insertions(+), 11 deletions(-) diff --git a/drivers/firmware/arm_scmi/mailbox.c b/drivers/firmware/arm_scmi/mailbox.c index 112c285deb97..1efa5e9392c4 100644 --- a/drivers/firmware/arm_scmi/mailbox.c +++ b/drivers/firmware/arm_scmi/mailbox.c @@ -19,13 +19,15 @@ * struct scmi_mailbox - Structure representing a SCMI mailbox transport * * @cl: Mailbox Client - * @chan: Transmit/Receive mailbox channel + * @chan: Transmit/Receive mailbox uni/bi-directional channel + * @chan_receiver: Optional Receiver mailbox unidirectional channel * @cinfo: SCMI channel info * @shmem: Transmit/Receive shared memory area */ struct scmi_mailbox { struct mbox_client cl; struct mbox_chan *chan; + struct mbox_chan *chan_receiver; struct scmi_chan_info *cinfo; struct scmi_shared_mem __iomem *shmem; }; @@ -48,30 +50,62 @@ static void rx_callback(struct mbox_client *cl, void *m) static bool mailbox_chan_available(struct device_node *of_node, int idx) { + int num_mb; + + /* + * Just check if bidirrectional channels are involved, and check the + * index accordingly; proper full validation will be made later + * in mailbox_chan_setup(). + */ + num_mb = of_count_phandle_with_args(of_node, "mboxes", "#mbox-cells"); + if (num_mb == 3 && idx == 1) + idx = 2; + return !of_parse_phandle_with_args(of_node, "mboxes", "#mbox-cells", idx, NULL); } -static int mailbox_chan_validate(struct device *cdev) +/** + * mailbox_chan_validate - Validate transport configuration and map channels + * + * @cdev: Reference to the underlying transport device carrying the + * of_node descriptor to analyze. + * @a2p_rx_chan: A reference to an optional unidirectional channel to use + * for replies on the a2p channel. Set as zero if not present. + * @p2a_chan: A reference to the optional p2a channel. + * Set as zero if not present. + * + * At first, validate the transport configuration as described in terms of + * 'mboxes' and 'shmem', then determin which mailbox channel indexes are + * appropriate to be use in the current configuration. + * + * Return: 0 on Success or error + */ +static int mailbox_chan_validate(struct device *cdev, + int *a2p_rx_chan, int *p2a_chan) { int num_mb, num_sh, ret = 0; struct device_node *np = cdev->of_node; num_mb = of_count_phandle_with_args(np, "mboxes", "#mbox-cells"); num_sh = of_count_phandle_with_args(np, "shmem", NULL); + dev_dbg(cdev, "Found %d mboxes and %d shmems !\n", num_mb, num_sh); + /* Bail out if mboxes and shmem descriptors are inconsistent */ - if (num_mb <= 0 || num_sh > 2 || num_mb != num_sh) { - dev_warn(cdev, "Invalid channel descriptor for '%s'\n", - of_node_full_name(np)); + if (num_mb <= 0 || num_sh <= 0 || num_sh > 2 || num_mb > 3 || + (num_mb == 1 && num_sh != 1) || (num_mb == 3 && num_sh != 2)) { + dev_warn(cdev, + "Invalid channel descriptor for '%s' - mbs:%d shm:%d\n", + of_node_full_name(np), num_mb, num_sh); return -EINVAL; } + /* Bail out if provided shmem descriptors do not refer distinct areas */ if (num_sh > 1) { struct device_node *np_tx, *np_rx; np_tx = of_parse_phandle(np, "shmem", 0); np_rx = of_parse_phandle(np, "shmem", 1); - /* SCMI Tx and Rx shared mem areas have to be distinct */ if (!np_tx || !np_rx || np_tx == np_rx) { dev_warn(cdev, "Invalid shmem descriptor for '%s'\n", of_node_full_name(np)); @@ -82,6 +116,29 @@ static int mailbox_chan_validate(struct device *cdev) of_node_put(np_rx); } + /* Calculate channels IDs to use depending on mboxes/shmem layout */ + if (!ret) { + switch (num_mb) { + case 1: + *a2p_rx_chan = 0; + *p2a_chan = 0; + break; + case 2: + if (num_sh == 2) { + *a2p_rx_chan = 0; + *p2a_chan = 1; + } else { + *a2p_rx_chan = 1; + *p2a_chan = 0; + } + break; + case 3: + *a2p_rx_chan = 1; + *p2a_chan = 2; + break; + } + } + return ret; } @@ -92,15 +149,18 @@ static int mailbox_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, struct device *cdev = cinfo->dev; struct scmi_mailbox *smbox; struct device_node *shmem; - int ret, idx = tx ? 0 : 1; + int ret, a2p_rx_chan, p2a_chan, idx = tx ? 0 : 1; struct mbox_client *cl; resource_size_t size; struct resource res; - ret = mailbox_chan_validate(cdev); + ret = mailbox_chan_validate(cdev, &a2p_rx_chan, &p2a_chan); if (ret) return ret; + if (!tx && !p2a_chan) + return -ENODEV; + smbox = devm_kzalloc(dev, sizeof(*smbox), GFP_KERNEL); if (!smbox) return -ENOMEM; @@ -130,15 +190,26 @@ static int mailbox_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, cl->tx_block = false; cl->knows_txdone = tx; - smbox->chan = mbox_request_channel(cl, tx ? 0 : 1); + smbox->chan = mbox_request_channel(cl, tx ? 0 : p2a_chan); if (IS_ERR(smbox->chan)) { ret = PTR_ERR(smbox->chan); if (ret != -EPROBE_DEFER) - dev_err(cdev, "failed to request SCMI %s mailbox\n", - tx ? "Tx" : "Rx"); + dev_err(cdev, + "failed to request SCMI %s mailbox\n", desc); return ret; } + /* Additional unidirectional channel for TX if needed */ + if (tx && a2p_rx_chan) { + smbox->chan_receiver = mbox_request_channel(cl, a2p_rx_chan); + if (IS_ERR(smbox->chan_receiver)) { + ret = PTR_ERR(smbox->chan_receiver); + if (ret != -EPROBE_DEFER) + dev_err(cdev, "failed to request SCMI Tx Receiver mailbox\n"); + return ret; + } + } + cinfo->transport_info = smbox; smbox->cinfo = cinfo; @@ -152,8 +223,10 @@ static int mailbox_chan_free(int id, void *p, void *data) if (smbox && !IS_ERR(smbox->chan)) { mbox_free_channel(smbox->chan); + mbox_free_channel(smbox->chan_receiver); cinfo->transport_info = NULL; smbox->chan = NULL; + smbox->chan_receiver = NULL; smbox->cinfo = NULL; } From 16744314ee57928c24aca95aa15f1381657edcfe Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 31 Jan 2023 17:57:47 +0000 Subject: [PATCH 0846/1040] arm64: tegra: Populate USB Type-C Controller for Jetson AGX Orin Add the USB Type-C controller that is present on the Jetson AGX Orin board. The ports for the Type-C controller are not populated yet, but will be added later once the USB host and device support for Jetson AGX Orin is enabled. This is based upon a patch from Wayne Chang . Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../nvidia/tegra234-p3737-0000+p3701-0000.dts | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index ddc057f01f24..caa9e952a149 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -2098,11 +2098,21 @@ usb2-0 { mode = "host"; status = "okay"; + port { + hs_typec_p1: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p1>; + }; + }; }; usb2-1 { mode = "host"; status = "okay"; + port { + hs_typec_p0: endpoint { + remote-endpoint = <&hs_ucsi_ccg_p0>; + }; + }; }; usb2-2 { @@ -2118,11 +2128,21 @@ usb3-0 { nvidia,usb2-companion = <1>; status = "okay"; + port { + ss_typec_p0: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p0>; + }; + }; }; usb3-1 { nvidia,usb2-companion = <0>; status = "okay"; + port { + ss_typec_p1: endpoint { + remote-endpoint = <&ss_ucsi_ccg_p1>; + }; + }; }; usb3-2 { @@ -2215,6 +2235,64 @@ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", "p2u-5", "p2u-6", "p2u-7"; }; + + i2c@c240000 { + status = "okay"; + typec@8 { + compatible = "cypress,cypd4226"; + reg = <0x08>; + interrupt-parent = <&gpio>; + interrupts = ; + firmware-name = "nvidia,jetson-agx-xavier"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "host"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ucsi_ccg_p0: endpoint { + remote-endpoint = <&hs_typec_p0>; + }; + }; + port@1 { + reg = <1>; + ss_ucsi_ccg_p0: endpoint { + remote-endpoint = <&ss_typec_p0>; + }; + }; + }; + }; + ccg_typec_con1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "USB-C"; + data-role = "dual"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hs_ucsi_ccg_p1: endpoint { + remote-endpoint = <&hs_typec_p1>; + }; + }; + port@1 { + reg = <1>; + ss_ucsi_ccg_p1: endpoint { + remote-endpoint = <&ss_typec_p1>; + }; + }; + }; + }; + }; + }; }; gpio-keys { From c299a2e6bf944b4218acc194a1cdf500b34e80aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 12 Dec 2022 23:25:49 +0100 Subject: [PATCH 0847/1040] soc: tegra: cbb: Drop empty platform remove function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A remove callback just returning 0 is equivalent to no remove callback at all. So drop the useless function. Signed-off-by: Uwe Kleine-König Reviewed-by: Sumit Gupta Signed-off-by: Thierry Reding --- drivers/soc/tegra/cbb/tegra234-cbb.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c index e23e8acfd7c7..cee87c92e53c 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -1173,11 +1173,6 @@ static int tegra234_cbb_probe(struct platform_device *pdev) return tegra_cbb_register(&cbb->base); } -static int tegra234_cbb_remove(struct platform_device *pdev) -{ - return 0; -} - static int __maybe_unused tegra234_cbb_resume_noirq(struct device *dev) { struct tegra234_cbb *cbb = dev_get_drvdata(dev); @@ -1195,7 +1190,6 @@ static const struct dev_pm_ops tegra234_cbb_pm = { static struct platform_driver tegra234_cbb_driver = { .probe = tegra234_cbb_probe, - .remove = tegra234_cbb_remove, .driver = { .name = "tegra234-cbb", .of_match_table = tegra234_cbb_dt_ids, From 5c0ddb4e715d89e4ea94821cd85bcac220bd7ea4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Fri, 27 Jan 2023 09:39:10 +0000 Subject: [PATCH 0848/1040] arm64: tegra: Add vccmq on Jetson TX2 The TX2 SoM's SDIO WiFI card is connected via mmc@3440000 however it does not look like the upstream kernel is even bothering to power this (and the regulator framework shuts down this power rail post kernel init). The issue seems to be a missing link for vccq from the MAX77620 PMIC's LDO5 which is labeled vddio_sdmmc3 (and not used anywhere else) to the mmc@3440000 node to ensure there is at leasr bus power. Note this does not fix the WiFi issue on upstream kernels, there is still something else missing that gets the BCM WiFi device to detect properly. Signed-off-by: Ben Dooks Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index a4264ea41728..e2d6857a3709 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -145,6 +145,7 @@ /* SDMMC3 (SDIO) */ mmc@3440000 { status = "okay"; + vqmmc-supply = <&vddio_sdmmc3>; }; /* SDMMC4 (eMMC) */ From 42c67aa26271fd3c12947dc3983051ff5c0d3a73 Mon Sep 17 00:00:00 2001 From: Ye Xingchen Date: Wed, 15 Feb 2023 17:18:03 +0800 Subject: [PATCH 0849/1040] soc/tegra: flowctrl: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Ye Xingchen Signed-off-by: Thierry Reding --- drivers/soc/tegra/flowctrl.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/tegra/flowctrl.c b/drivers/soc/tegra/flowctrl.c index 5db919d96aba..221202db3313 100644 --- a/drivers/soc/tegra/flowctrl.c +++ b/drivers/soc/tegra/flowctrl.c @@ -156,10 +156,8 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) static int tegra_flowctrl_probe(struct platform_device *pdev) { void __iomem *base = tegra_flowctrl_base; - struct resource *res; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - tegra_flowctrl_base = devm_ioremap_resource(&pdev->dev, res); + tegra_flowctrl_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(tegra_flowctrl_base)) return PTR_ERR(tegra_flowctrl_base); From e8476011f04b1ee4360f755ed19cbbddf12dc83e Mon Sep 17 00:00:00 2001 From: Nick Alcock Date: Fri, 17 Feb 2023 14:10:44 +0000 Subject: [PATCH 0850/1040] ARM: tegra: Remove MODULE_LICENSE in non-modules Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Luis Chamberlain Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding --- drivers/amba/tegra-ahb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/amba/tegra-ahb.c b/drivers/amba/tegra-ahb.c index 0b2c20fddb7c..c0e8b765522d 100644 --- a/drivers/amba/tegra-ahb.c +++ b/drivers/amba/tegra-ahb.c @@ -285,5 +285,4 @@ module_platform_driver(tegra_ahb_driver); MODULE_AUTHOR("Hiroshi DOYU "); MODULE_DESCRIPTION("Tegra AHB driver"); -MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:" DRV_NAME); From 6854f2759842baf94c8970b52f443aaee18af1bf Mon Sep 17 00:00:00 2001 From: Nick Alcock Date: Tue, 28 Feb 2023 13:02:15 +0000 Subject: [PATCH 0851/1040] soc/tegra: cbb: Remove MODULE_LICENSE in non-modules Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in the files in this commit, none of which can be built as modules. Signed-off-by: Nick Alcock Suggested-by: Luis Chamberlain Cc: Luis Chamberlain Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding --- drivers/soc/tegra/cbb/tegra194-cbb.c | 1 - drivers/soc/tegra/cbb/tegra234-cbb.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra194-cbb.c b/drivers/soc/tegra/cbb/tegra194-cbb.c index a05fc2caff3b..64574da3ced0 100644 --- a/drivers/soc/tegra/cbb/tegra194-cbb.c +++ b/drivers/soc/tegra/cbb/tegra194-cbb.c @@ -2358,4 +2358,3 @@ module_exit(tegra194_cbb_exit); MODULE_AUTHOR("Sumit Gupta "); MODULE_DESCRIPTION("Control Backbone error handling driver for Tegra194"); -MODULE_LICENSE("GPL"); diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c index cee87c92e53c..5d16161b2566 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -1211,4 +1211,3 @@ static void __exit tegra234_cbb_exit(void) module_exit(tegra234_cbb_exit); MODULE_DESCRIPTION("Control Backbone 2.0 error handling driver for Tegra234"); -MODULE_LICENSE("GPL"); From f462eb1d0df39499eff2407b2581ddf2fe89e744 Mon Sep 17 00:00:00 2001 From: Besar Wicaksono Date: Tue, 21 Mar 2023 15:05:35 -0500 Subject: [PATCH 0852/1040] arm64: defconfig: Enable ARM CoreSight PMU driver Enable driver for Coresight PMU arch device. Signed-off-by: Besar Wicaksono Signed-off-by: Thierry Reding --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 7790ee42c68a..6df526ce5c5d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1329,6 +1329,7 @@ CONFIG_PHY_J721E_WIZ=m CONFIG_ARM_CCI_PMU=m CONFIG_ARM_CCN=m CONFIG_ARM_CMN=m +CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m CONFIG_ARM_SMMU_V3_PMU=m CONFIG_ARM_DSU_PMU=m CONFIG_FSL_IMX8_DDR_PMU=m From 056a6e1db2f1cd6faa8c62c508c84850fe300f05 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 27 Oct 2022 14:56:25 +0800 Subject: [PATCH 0853/1040] soc/tegra: cbb: tegra194: Use of_address_count() helper After commit 16988c742968 ("of/address: introduce of_address_count() helper"), We can use of_address_count() to instead of open-coding it. Signed-off-by: Yang Yingliang Signed-off-by: Thierry Reding --- drivers/soc/tegra/cbb/tegra194-cbb.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra194-cbb.c b/drivers/soc/tegra/cbb/tegra194-cbb.c index 64574da3ced0..54d7ce05c636 100644 --- a/drivers/soc/tegra/cbb/tegra194-cbb.c +++ b/drivers/soc/tegra/cbb/tegra194-cbb.c @@ -2190,7 +2190,6 @@ MODULE_DEVICE_TABLE(of, tegra194_cbb_match); static int tegra194_cbb_get_bridges(struct tegra194_cbb *cbb, struct device_node *np) { struct tegra_cbb *entry; - struct resource res; unsigned long flags; unsigned int i; int err; @@ -2210,8 +2209,7 @@ static int tegra194_cbb_get_bridges(struct tegra194_cbb *cbb, struct device_node spin_unlock_irqrestore(&cbb_lock, flags); if (!cbb->bridges) { - while (of_address_to_resource(np, cbb->num_bridges, &res) == 0) - cbb->num_bridges++; + cbb->num_bridges = of_address_count(np); cbb->bridges = devm_kcalloc(cbb->base.dev, cbb->num_bridges, sizeof(*cbb->bridges), GFP_KERNEL); From 7fce1e39f01900a294cd2c456c77f3e2512e0634 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 1 Apr 2023 19:19:13 +0800 Subject: [PATCH 0854/1040] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Add bindings for the system clock and reset generator (SYSCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Reviewed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Signed-off-by: Conor Dooley --- .../clock/starfive,jh7110-syscrg.yaml | 104 +++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 203 ++++++++++++++++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 142 ++++++++++++ 3 files changed, 449 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml new file mode 100644 index 000000000000..84373ae31644 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 System Clock and Reset Generator + +maintainers: + - Emil Renner Berthing + +properties: + compatible: + const: starfive,jh7110-syscrg + + reg: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC1 RMII reference or GMAC1 RGMII RX + - description: External I2S TX bit clock + - description: External I2S TX left/right channel clock + - description: External I2S RX bit clock + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC1 RMII reference + - description: GMAC1 RGMII RX + - description: External I2S TX bit clock + - description: External I2S TX left/right channel clock + - description: External I2S RX bit clock + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock + + clock-names: + oneOf: + - items: + - const: osc + - enum: + - gmac1_rmii_refin + - gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + + - items: + - const: osc + - const: gmac1_rmii_refin + - const: gmac1_rgmii_rxin + - const: i2stx_bclk_ext + - const: i2stx_lrck_ext + - const: i2srx_bclk_ext + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13020000 { + compatible = "starfive,jh7110-syscrg"; + reg = <0x13020000 0x10000>; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h new file mode 100644 index 000000000000..fdd1852e34cc --- /dev/null +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2022 Emil Renner Berthing + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ + +/* SYSCRG clocks */ +#define JH7110_SYSCLK_CPU_ROOT 0 +#define JH7110_SYSCLK_CPU_CORE 1 +#define JH7110_SYSCLK_CPU_BUS 2 +#define JH7110_SYSCLK_GPU_ROOT 3 +#define JH7110_SYSCLK_PERH_ROOT 4 +#define JH7110_SYSCLK_BUS_ROOT 5 +#define JH7110_SYSCLK_NOCSTG_BUS 6 +#define JH7110_SYSCLK_AXI_CFG0 7 +#define JH7110_SYSCLK_STG_AXIAHB 8 +#define JH7110_SYSCLK_AHB0 9 +#define JH7110_SYSCLK_AHB1 10 +#define JH7110_SYSCLK_APB_BUS 11 +#define JH7110_SYSCLK_APB0 12 +#define JH7110_SYSCLK_PLL0_DIV2 13 +#define JH7110_SYSCLK_PLL1_DIV2 14 +#define JH7110_SYSCLK_PLL2_DIV2 15 +#define JH7110_SYSCLK_AUDIO_ROOT 16 +#define JH7110_SYSCLK_MCLK_INNER 17 +#define JH7110_SYSCLK_MCLK 18 +#define JH7110_SYSCLK_MCLK_OUT 19 +#define JH7110_SYSCLK_ISP_2X 20 +#define JH7110_SYSCLK_ISP_AXI 21 +#define JH7110_SYSCLK_GCLK0 22 +#define JH7110_SYSCLK_GCLK1 23 +#define JH7110_SYSCLK_GCLK2 24 +#define JH7110_SYSCLK_CORE 25 +#define JH7110_SYSCLK_CORE1 26 +#define JH7110_SYSCLK_CORE2 27 +#define JH7110_SYSCLK_CORE3 28 +#define JH7110_SYSCLK_CORE4 29 +#define JH7110_SYSCLK_DEBUG 30 +#define JH7110_SYSCLK_RTC_TOGGLE 31 +#define JH7110_SYSCLK_TRACE0 32 +#define JH7110_SYSCLK_TRACE1 33 +#define JH7110_SYSCLK_TRACE2 34 +#define JH7110_SYSCLK_TRACE3 35 +#define JH7110_SYSCLK_TRACE4 36 +#define JH7110_SYSCLK_TRACE_COM 37 +#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 +#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 +#define JH7110_SYSCLK_OSC_DIV2 40 +#define JH7110_SYSCLK_PLL1_DIV4 41 +#define JH7110_SYSCLK_PLL1_DIV8 42 +#define JH7110_SYSCLK_DDR_BUS 43 +#define JH7110_SYSCLK_DDR_AXI 44 +#define JH7110_SYSCLK_GPU_CORE 45 +#define JH7110_SYSCLK_GPU_CORE_CLK 46 +#define JH7110_SYSCLK_GPU_SYS_CLK 47 +#define JH7110_SYSCLK_GPU_APB 48 +#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 +#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 +#define JH7110_SYSCLK_ISP_TOP_CORE 51 +#define JH7110_SYSCLK_ISP_TOP_AXI 52 +#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 +#define JH7110_SYSCLK_HIFI4_CORE 54 +#define JH7110_SYSCLK_HIFI4_AXI 55 +#define JH7110_SYSCLK_AXI_CFG1_MAIN 56 +#define JH7110_SYSCLK_AXI_CFG1_AHB 57 +#define JH7110_SYSCLK_VOUT_SRC 58 +#define JH7110_SYSCLK_VOUT_AXI 59 +#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 +#define JH7110_SYSCLK_VOUT_TOP_AHB 61 +#define JH7110_SYSCLK_VOUT_TOP_AXI 62 +#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63 +#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64 +#define JH7110_SYSCLK_JPEGC_AXI 65 +#define JH7110_SYSCLK_CODAJ12_AXI 66 +#define JH7110_SYSCLK_CODAJ12_CORE 67 +#define JH7110_SYSCLK_CODAJ12_APB 68 +#define JH7110_SYSCLK_VDEC_AXI 69 +#define JH7110_SYSCLK_WAVE511_AXI 70 +#define JH7110_SYSCLK_WAVE511_BPU 71 +#define JH7110_SYSCLK_WAVE511_VCE 72 +#define JH7110_SYSCLK_WAVE511_APB 73 +#define JH7110_SYSCLK_VDEC_JPG 74 +#define JH7110_SYSCLK_VDEC_MAIN 75 +#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 +#define JH7110_SYSCLK_VENC_AXI 77 +#define JH7110_SYSCLK_WAVE420L_AXI 78 +#define JH7110_SYSCLK_WAVE420L_BPU 79 +#define JH7110_SYSCLK_WAVE420L_VCE 80 +#define JH7110_SYSCLK_WAVE420L_APB 81 +#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 +#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 +#define JH7110_SYSCLK_AXI_CFG0_MAIN 84 +#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85 +#define JH7110_SYSCLK_AXIMEM2_AXI 86 +#define JH7110_SYSCLK_QSPI_AHB 87 +#define JH7110_SYSCLK_QSPI_APB 88 +#define JH7110_SYSCLK_QSPI_REF_SRC 89 +#define JH7110_SYSCLK_QSPI_REF 90 +#define JH7110_SYSCLK_SDIO0_AHB 91 +#define JH7110_SYSCLK_SDIO1_AHB 92 +#define JH7110_SYSCLK_SDIO0_SDCARD 93 +#define JH7110_SYSCLK_SDIO1_SDCARD 94 +#define JH7110_SYSCLK_USB_125M 95 +#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 +#define JH7110_SYSCLK_GMAC1_AHB 97 +#define JH7110_SYSCLK_GMAC1_AXI 98 +#define JH7110_SYSCLK_GMAC_SRC 99 +#define JH7110_SYSCLK_GMAC1_GTXCLK 100 +#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 +#define JH7110_SYSCLK_GMAC1_PTP 102 +#define JH7110_SYSCLK_GMAC1_RX 103 +#define JH7110_SYSCLK_GMAC1_RX_INV 104 +#define JH7110_SYSCLK_GMAC1_TX 105 +#define JH7110_SYSCLK_GMAC1_TX_INV 106 +#define JH7110_SYSCLK_GMAC1_GTXC 107 +#define JH7110_SYSCLK_GMAC0_GTXCLK 108 +#define JH7110_SYSCLK_GMAC0_PTP 109 +#define JH7110_SYSCLK_GMAC_PHY 110 +#define JH7110_SYSCLK_GMAC0_GTXC 111 +#define JH7110_SYSCLK_IOMUX_APB 112 +#define JH7110_SYSCLK_MAILBOX_APB 113 +#define JH7110_SYSCLK_INT_CTRL_APB 114 +#define JH7110_SYSCLK_CAN0_APB 115 +#define JH7110_SYSCLK_CAN0_TIMER 116 +#define JH7110_SYSCLK_CAN0_CAN 117 +#define JH7110_SYSCLK_CAN1_APB 118 +#define JH7110_SYSCLK_CAN1_TIMER 119 +#define JH7110_SYSCLK_CAN1_CAN 120 +#define JH7110_SYSCLK_PWM_APB 121 +#define JH7110_SYSCLK_WDT_APB 122 +#define JH7110_SYSCLK_WDT_CORE 123 +#define JH7110_SYSCLK_TIMER_APB 124 +#define JH7110_SYSCLK_TIMER0 125 +#define JH7110_SYSCLK_TIMER1 126 +#define JH7110_SYSCLK_TIMER2 127 +#define JH7110_SYSCLK_TIMER3 128 +#define JH7110_SYSCLK_TEMP_APB 129 +#define JH7110_SYSCLK_TEMP_CORE 130 +#define JH7110_SYSCLK_SPI0_APB 131 +#define JH7110_SYSCLK_SPI1_APB 132 +#define JH7110_SYSCLK_SPI2_APB 133 +#define JH7110_SYSCLK_SPI3_APB 134 +#define JH7110_SYSCLK_SPI4_APB 135 +#define JH7110_SYSCLK_SPI5_APB 136 +#define JH7110_SYSCLK_SPI6_APB 137 +#define JH7110_SYSCLK_I2C0_APB 138 +#define JH7110_SYSCLK_I2C1_APB 139 +#define JH7110_SYSCLK_I2C2_APB 140 +#define JH7110_SYSCLK_I2C3_APB 141 +#define JH7110_SYSCLK_I2C4_APB 142 +#define JH7110_SYSCLK_I2C5_APB 143 +#define JH7110_SYSCLK_I2C6_APB 144 +#define JH7110_SYSCLK_UART0_APB 145 +#define JH7110_SYSCLK_UART0_CORE 146 +#define JH7110_SYSCLK_UART1_APB 147 +#define JH7110_SYSCLK_UART1_CORE 148 +#define JH7110_SYSCLK_UART2_APB 149 +#define JH7110_SYSCLK_UART2_CORE 150 +#define JH7110_SYSCLK_UART3_APB 151 +#define JH7110_SYSCLK_UART3_CORE 152 +#define JH7110_SYSCLK_UART4_APB 153 +#define JH7110_SYSCLK_UART4_CORE 154 +#define JH7110_SYSCLK_UART5_APB 155 +#define JH7110_SYSCLK_UART5_CORE 156 +#define JH7110_SYSCLK_PWMDAC_APB 157 +#define JH7110_SYSCLK_PWMDAC_CORE 158 +#define JH7110_SYSCLK_SPDIF_APB 159 +#define JH7110_SYSCLK_SPDIF_CORE 160 +#define JH7110_SYSCLK_I2STX0_APB 161 +#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 +#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 +#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 +#define JH7110_SYSCLK_I2STX0_BCLK 165 +#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 +#define JH7110_SYSCLK_I2STX0_LRCK 167 +#define JH7110_SYSCLK_I2STX1_APB 168 +#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 +#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 +#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 +#define JH7110_SYSCLK_I2STX1_BCLK 172 +#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 +#define JH7110_SYSCLK_I2STX1_LRCK 174 +#define JH7110_SYSCLK_I2SRX_APB 175 +#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 +#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 +#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 +#define JH7110_SYSCLK_I2SRX_BCLK 179 +#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 +#define JH7110_SYSCLK_I2SRX_LRCK 181 +#define JH7110_SYSCLK_PDM_DMIC 182 +#define JH7110_SYSCLK_PDM_APB 183 +#define JH7110_SYSCLK_TDM_AHB 184 +#define JH7110_SYSCLK_TDM_APB 185 +#define JH7110_SYSCLK_TDM_INTERNAL 186 +#define JH7110_SYSCLK_TDM_TDM 187 +#define JH7110_SYSCLK_TDM_TDM_INV 188 +#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 + +#define JH7110_SYSCLK_END 190 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h new file mode 100644 index 000000000000..b88216a4fe40 --- /dev/null +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ + +/* SYSCRG resets */ +#define JH7110_SYSRST_JTAG_APB 0 +#define JH7110_SYSRST_SYSCON_APB 1 +#define JH7110_SYSRST_IOMUX_APB 2 +#define JH7110_SYSRST_BUS 3 +#define JH7110_SYSRST_DEBUG 4 +#define JH7110_SYSRST_CORE0 5 +#define JH7110_SYSRST_CORE1 6 +#define JH7110_SYSRST_CORE2 7 +#define JH7110_SYSRST_CORE3 8 +#define JH7110_SYSRST_CORE4 9 +#define JH7110_SYSRST_CORE0_ST 10 +#define JH7110_SYSRST_CORE1_ST 11 +#define JH7110_SYSRST_CORE2_ST 12 +#define JH7110_SYSRST_CORE3_ST 13 +#define JH7110_SYSRST_CORE4_ST 14 +#define JH7110_SYSRST_TRACE0 15 +#define JH7110_SYSRST_TRACE1 16 +#define JH7110_SYSRST_TRACE2 17 +#define JH7110_SYSRST_TRACE3 18 +#define JH7110_SYSRST_TRACE4 19 +#define JH7110_SYSRST_TRACE_COM 20 +#define JH7110_SYSRST_GPU_APB 21 +#define JH7110_SYSRST_GPU_DOMA 22 +#define JH7110_SYSRST_NOC_BUS_APB 23 +#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 +#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 +#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 +#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 +#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 +#define JH7110_SYSRST_NOC_BUS_DDRC 29 +#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 +#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 + +#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 +#define JH7110_SYSRST_AXI_CFG1_AHB 33 +#define JH7110_SYSRST_AXI_CFG1_MAIN 34 +#define JH7110_SYSRST_AXI_CFG0_MAIN 35 +#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36 +#define JH7110_SYSRST_AXI_CFG0_HIFI4 37 +#define JH7110_SYSRST_DDR_AXI 38 +#define JH7110_SYSRST_DDR_OSC 39 +#define JH7110_SYSRST_DDR_APB 40 +#define JH7110_SYSRST_ISP_TOP 41 +#define JH7110_SYSRST_ISP_TOP_AXI 42 +#define JH7110_SYSRST_VOUT_TOP_SRC 43 +#define JH7110_SYSRST_CODAJ12_AXI 44 +#define JH7110_SYSRST_CODAJ12_CORE 45 +#define JH7110_SYSRST_CODAJ12_APB 46 +#define JH7110_SYSRST_WAVE511_AXI 47 +#define JH7110_SYSRST_WAVE511_BPU 48 +#define JH7110_SYSRST_WAVE511_VCE 49 +#define JH7110_SYSRST_WAVE511_APB 50 +#define JH7110_SYSRST_VDEC_JPG 51 +#define JH7110_SYSRST_VDEC_MAIN 52 +#define JH7110_SYSRST_AXIMEM0_AXI 53 +#define JH7110_SYSRST_WAVE420L_AXI 54 +#define JH7110_SYSRST_WAVE420L_BPU 55 +#define JH7110_SYSRST_WAVE420L_VCE 56 +#define JH7110_SYSRST_WAVE420L_APB 57 +#define JH7110_SYSRST_AXIMEM1_AXI 58 +#define JH7110_SYSRST_AXIMEM2_AXI 59 +#define JH7110_SYSRST_INTMEM 60 +#define JH7110_SYSRST_QSPI_AHB 61 +#define JH7110_SYSRST_QSPI_APB 62 +#define JH7110_SYSRST_QSPI_REF 63 + +#define JH7110_SYSRST_SDIO0_AHB 64 +#define JH7110_SYSRST_SDIO1_AHB 65 +#define JH7110_SYSRST_GMAC1_AXI 66 +#define JH7110_SYSRST_GMAC1_AHB 67 +#define JH7110_SYSRST_MAILBOX_APB 68 +#define JH7110_SYSRST_SPI0_APB 69 +#define JH7110_SYSRST_SPI1_APB 70 +#define JH7110_SYSRST_SPI2_APB 71 +#define JH7110_SYSRST_SPI3_APB 72 +#define JH7110_SYSRST_SPI4_APB 73 +#define JH7110_SYSRST_SPI5_APB 74 +#define JH7110_SYSRST_SPI6_APB 75 +#define JH7110_SYSRST_I2C0_APB 76 +#define JH7110_SYSRST_I2C1_APB 77 +#define JH7110_SYSRST_I2C2_APB 78 +#define JH7110_SYSRST_I2C3_APB 79 +#define JH7110_SYSRST_I2C4_APB 80 +#define JH7110_SYSRST_I2C5_APB 81 +#define JH7110_SYSRST_I2C6_APB 82 +#define JH7110_SYSRST_UART0_APB 83 +#define JH7110_SYSRST_UART0_CORE 84 +#define JH7110_SYSRST_UART1_APB 85 +#define JH7110_SYSRST_UART1_CORE 86 +#define JH7110_SYSRST_UART2_APB 87 +#define JH7110_SYSRST_UART2_CORE 88 +#define JH7110_SYSRST_UART3_APB 89 +#define JH7110_SYSRST_UART3_CORE 90 +#define JH7110_SYSRST_UART4_APB 91 +#define JH7110_SYSRST_UART4_CORE 92 +#define JH7110_SYSRST_UART5_APB 93 +#define JH7110_SYSRST_UART5_CORE 94 +#define JH7110_SYSRST_SPDIF_APB 95 + +#define JH7110_SYSRST_PWMDAC_APB 96 +#define JH7110_SYSRST_PDM_DMIC 97 +#define JH7110_SYSRST_PDM_APB 98 +#define JH7110_SYSRST_I2SRX_APB 99 +#define JH7110_SYSRST_I2SRX_BCLK 100 +#define JH7110_SYSRST_I2STX0_APB 101 +#define JH7110_SYSRST_I2STX0_BCLK 102 +#define JH7110_SYSRST_I2STX1_APB 103 +#define JH7110_SYSRST_I2STX1_BCLK 104 +#define JH7110_SYSRST_TDM_AHB 105 +#define JH7110_SYSRST_TDM_CORE 106 +#define JH7110_SYSRST_TDM_APB 107 +#define JH7110_SYSRST_PWM_APB 108 +#define JH7110_SYSRST_WDT_APB 109 +#define JH7110_SYSRST_WDT_CORE 110 +#define JH7110_SYSRST_CAN0_APB 111 +#define JH7110_SYSRST_CAN0_CORE 112 +#define JH7110_SYSRST_CAN0_TIMER 113 +#define JH7110_SYSRST_CAN1_APB 114 +#define JH7110_SYSRST_CAN1_CORE 115 +#define JH7110_SYSRST_CAN1_TIMER 116 +#define JH7110_SYSRST_TIMER_APB 117 +#define JH7110_SYSRST_TIMER0 118 +#define JH7110_SYSRST_TIMER1 119 +#define JH7110_SYSRST_TIMER2 120 +#define JH7110_SYSRST_TIMER3 121 +#define JH7110_SYSRST_INT_CTRL_APB 122 +#define JH7110_SYSRST_TEMP_APB 123 +#define JH7110_SYSRST_TEMP_CORE 124 +#define JH7110_SYSRST_JTAG_CERTIFICATION 125 + +#define JH7110_SYSRST_END 126 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ From 3de0c91032580d4923624fe6ee773eddd1b574bc Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 1 Apr 2023 19:19:14 +0800 Subject: [PATCH 0855/1040] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator Add bindings for the always-on clock and reset generator (AONCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Reviewed-by: Conor Dooley Reviewed-by: Rob Herring Reviewed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Signed-off-by: Conor Dooley --- .../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++ .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++ .../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++ 3 files changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml new file mode 100644 index 000000000000..923680a44aef --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Always-On Clock and Reset Generator + +maintainers: + - Emil Renner Berthing + +properties: + compatible: + const: starfive,jh7110-aoncrg + + reg: + maxItems: 1 + + clocks: + oneOf: + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference or GMAC0 RGMII RX + - description: STG AXI/AHB or GMAC0 RGMII RX + - description: APB Bus or STG AXI/AHB + - description: GMAC0 GTX or APB Bus + - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX + + - items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII reference + - description: GMAC0 RGMII RX + - description: STG AXI/AHB + - description: APB Bus + - description: GMAC0 GTX + - description: RTC Oscillator (32.768 kHz) + + clock-names: + oneOf: + - minItems: 5 + items: + - const: osc + - enum: + - gmac0_rmii_refin + - gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + - minItems: 6 + items: + - const: osc + - const: gmac0_rmii_refin + - const: gmac0_rgmii_rxin + - const: stg_axiahb + - const: apb_bus + - const: gmac0_gtxclk + - const: rtc_osc + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x17000000 0x10000>; + clocks = <&osc>, <&gmac0_rmii_refin>, + <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, + <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk", + "rtc_osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index fdd1852e34cc..06257bfd9ac1 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -200,4 +200,22 @@ #define JH7110_SYSCLK_END 190 +/* AONCRG clocks */ +#define JH7110_AONCLK_OSC_DIV4 0 +#define JH7110_AONCLK_APB_FUNC 1 +#define JH7110_AONCLK_GMAC0_AHB 2 +#define JH7110_AONCLK_GMAC0_AXI 3 +#define JH7110_AONCLK_GMAC0_RMII_RTX 4 +#define JH7110_AONCLK_GMAC0_TX 5 +#define JH7110_AONCLK_GMAC0_TX_INV 6 +#define JH7110_AONCLK_GMAC0_RX 7 +#define JH7110_AONCLK_GMAC0_RX_INV 8 +#define JH7110_AONCLK_OTPC_APB 9 +#define JH7110_AONCLK_RTC_APB 10 +#define JH7110_AONCLK_RTC_INTERNAL 11 +#define JH7110_AONCLK_RTC_32K 12 +#define JH7110_AONCLK_RTC_CAL 13 + +#define JH7110_AONCLK_END 14 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index b88216a4fe40..d78e38690ceb 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -139,4 +139,16 @@ #define JH7110_SYSRST_END 126 +/* AONCRG resets */ +#define JH7110_AONRST_GMAC0_AXI 0 +#define JH7110_AONRST_GMAC0_AHB 1 +#define JH7110_AONRST_IOMUX 2 +#define JH7110_AONRST_PMU_APB 3 +#define JH7110_AONRST_PMU_WKUP 4 +#define JH7110_AONRST_RTC_APB 5 +#define JH7110_AONRST_RTC_CAL 6 +#define JH7110_AONRST_RTC_32K 7 + +#define JH7110_AONRST_END 8 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ From 1ff5482ab9a5565a56b15626a6bc5bf20dab3465 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 1 Apr 2023 19:19:28 +0800 Subject: [PATCH 0856/1040] dt-bindings: timer: Add StarFive JH7110 clint Add compatible string for the StarFive JH7110 clint. Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski Reviewed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index aada6957216c..94bef9424df1 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -31,6 +31,7 @@ properties: - enum: - sifive,fu540-c000-clint - starfive,jh7100-clint + - starfive,jh7110-clint - canaan,k210-clint - const: sifive,clint0 - items: From 8406d19ca0493aa8b4b83314efe57219c8bb92b6 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 1 Apr 2023 19:19:29 +0800 Subject: [PATCH 0857/1040] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Add compatible string for StarFive JH7110 plic. Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski Reviewed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Hal Feng Signed-off-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 63bc89e13480..4e98261f2948 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -59,6 +59,7 @@ properties: - enum: - sifive,fu540-c000-plic - starfive,jh7100-plic + - starfive,jh7110-plic - canaan,k210-plic - const: sifive,plic-1.0.0 - items: From 8868caa2a073cdac8a3c28e4e30cf72fe6b44f22 Mon Sep 17 00:00:00 2001 From: Hal Feng Date: Sat, 1 Apr 2023 19:19:30 +0800 Subject: [PATCH 0858/1040] dt-bindings: riscv: Add SiFive S7 compatible Add a new compatible string in cpu.yaml for SiFive S7 CPU core which is used on SiFive U74-MC core complex etc. Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski Reviewed-by: Emil Renner Berthing Signed-off-by: Hal Feng Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 001931d526ec..14b5b7ea0ce0 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -35,6 +35,7 @@ properties: - sifive,e7 - sifive,e71 - sifive,rocket0 + - sifive,s7 - sifive,u5 - sifive,u54 - sifive,u7 From 60bf0a39842eb042bbdc4539285c7e524011fc2d Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 1 Apr 2023 19:19:31 +0800 Subject: [PATCH 0859/1040] riscv: dts: starfive: Add initial StarFive JH7110 device tree Add initial device tree for the JH7110 RISC-V SoC by StarFive Technology Ltd. Tested-by: Tommaso Merciai Reviewed-by: Conor Dooley Signed-off-by: Emil Renner Berthing Co-developed-by: Jianlong Huang Signed-off-by: Jianlong Huang Co-developed-by: Hal Feng Signed-off-by: Hal Feng [conor: squashed in the removal of the S7's non-existent mmu] Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 500 +++++++++++++++++++++++ 1 file changed, 500 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi new file mode 100644 index 000000000000..4c5fdb905da8 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing + */ + +/dts-v1/; +#include +#include + +/ { + compatible = "starfive,jh7110"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + S7_0: cpu@0 { + compatible = "sifive,s7", "riscv"; + reg = <0>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <16384>; + next-level-cache = <&ccache>; + riscv,isa = "rv64imac_zba_zbb"; + status = "disabled"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_1: cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_2: cpu@2 { + compatible = "sifive,u74-mc", "riscv"; + reg = <2>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_3: cpu@3 { + compatible = "sifive,u74-mc", "riscv"; + reg = <3>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_4: cpu@4 { + compatible = "sifive,u74-mc", "riscv"; + reg = <4>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&S7_0>; + }; + + core1 { + cpu = <&U74_1>; + }; + + core2 { + cpu = <&U74_2>; + }; + + core3 { + cpu = <&U74_3>; + }; + + core4 { + cpu = <&U74_4>; + }; + }; + }; + }; + + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rgmii_rxin"; + #clock-cells = <0>; + }; + + gmac0_rmii_refin: gmac0-rmii-refin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rmii_refin"; + #clock-cells = <0>; + }; + + gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac1_rgmii_rxin"; + #clock-cells = <0>; + }; + + gmac1_rmii_refin: gmac1-rmii-refin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac1_rmii_refin"; + #clock-cells = <0>; + }; + + i2srx_bclk_ext: i2srx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_bclk_ext"; + #clock-cells = <0>; + }; + + i2srx_lrck_ext: i2srx-lrck-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_lrck_ext"; + #clock-cells = <0>; + }; + + i2stx_bclk_ext: i2stx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2stx_bclk_ext"; + #clock-cells = <0>; + }; + + i2stx_lrck_ext: i2stx-lrck-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2stx_lrck_ext"; + #clock-cells = <0>; + }; + + mclk_ext: mclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "mclk_ext"; + #clock-cells = <0>; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc"; + #clock-cells = <0>; + }; + + rtc_osc: rtc-oscillator { + compatible = "fixed-clock"; + clock-output-names = "rtc_osc"; + #clock-cells = <0>; + }; + + tdm_ext: tdm-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "tdm_ext"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: timer@2000000 { + compatible = "starfive,jh7110-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + ccache: cache-controller@2010000 { + compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; + reg = <0x0 0x2010000 0x0 0x4000>; + interrupts = <1>, <3>, <4>, <2>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + }; + + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <136>; + }; + + uart0: serial@10000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, + <&syscrg JH7110_SYSCLK_UART0_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART0_APB>; + interrupts = <32>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@10010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, + <&syscrg JH7110_SYSCLK_UART1_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART1_APB>; + interrupts = <33>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@10020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, + <&syscrg JH7110_SYSCLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART2_APB>; + interrupts = <34>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c0: i2c@10030000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10030000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C0_APB>; + interrupts = <35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@10040000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C1_APB>; + interrupts = <36>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@10050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10050000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C2_APB>; + interrupts = <37>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, + <&syscrg JH7110_SYSCLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART3_APB>; + interrupts = <45>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@12010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, + <&syscrg JH7110_SYSCLK_UART4_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART4_APB>; + interrupts = <46>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@12020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, + <&syscrg JH7110_SYSCLK_UART5_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART5_APB>; + interrupts = <47>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c3: i2c@12030000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12030000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C3_APB>; + interrupts = <48>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@12040000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C4_APB>; + interrupts = <49>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@12050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12050000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C5_APB>; + interrupts = <50>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@12060000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12060000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C6_APB>; + interrupts = <51>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + syscrg: clock-controller@13020000 { + compatible = "starfive,jh7110-syscrg"; + reg = <0x0 0x13020000 0x0 0x10000>; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sysgpio: pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; + resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; + interrupts = <86>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + aoncrg: clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x0 0x17000000 0x0 0x10000>; + clocks = <&osc>, <&gmac0_rmii_refin>, + <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, + <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk", + "rtc_osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + aongpio: pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x0 0x17020000 0x0 0x10000>; + resets = <&aoncrg JH7110_AONRST_IOMUX>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; From e22f09e598d12e46e7c96df3c10271d037e1fd39 Mon Sep 17 00:00:00 2001 From: Jianlong Huang Date: Sat, 1 Apr 2023 19:19:32 +0800 Subject: [PATCH 0860/1040] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Add pin function definitions for StarFive JH7110 SoC. Tested-by: Tommaso Merciai Co-developed-by: Emil Renner Berthing Signed-off-by: Emil Renner Berthing Signed-off-by: Jianlong Huang Signed-off-by: Hal Feng Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++++++++++++ 1 file changed, 308 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h diff --git a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h new file mode 100644 index 000000000000..fb0139b56723 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h @@ -0,0 +1,308 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +#ifndef __JH7110_PINFUNC_H__ +#define __JH7110_PINFUNC_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: function selector + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux dout */ +#define GPOUT_LOW 0 +#define GPOUT_HIGH 1 +#define GPOUT_SYS_WAVE511_UART_TX 2 +#define GPOUT_SYS_CAN0_STBY 3 +#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4 +#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5 +#define GPOUT_SYS_CAN0_TXD 6 +#define GPOUT_SYS_USB_DRIVE_VBUS 7 +#define GPOUT_SYS_QSPI_CS1 8 +#define GPOUT_SYS_SPDIF 9 +#define GPOUT_SYS_HDMI_CEC_SDA 10 +#define GPOUT_SYS_HDMI_DDC_SCL 11 +#define GPOUT_SYS_HDMI_DDC_SDA 12 +#define GPOUT_SYS_WATCHDOG 13 +#define GPOUT_SYS_I2C0_CLK 14 +#define GPOUT_SYS_I2C0_DATA 15 +#define GPOUT_SYS_SDIO0_BACK_END_POWER 16 +#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17 +#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18 +#define GPOUT_SYS_SDIO0_RST 19 +#define GPOUT_SYS_UART0_TX 20 +#define GPOUT_SYS_HIFI4_JTAG_TDO 21 +#define GPOUT_SYS_JTAG_TDO 22 +#define GPOUT_SYS_PDM_MCLK 23 +#define GPOUT_SYS_PWM_CHANNEL0 24 +#define GPOUT_SYS_PWM_CHANNEL1 25 +#define GPOUT_SYS_PWM_CHANNEL2 26 +#define GPOUT_SYS_PWM_CHANNEL3 27 +#define GPOUT_SYS_PWMDAC_LEFT 28 +#define GPOUT_SYS_PWMDAC_RIGHT 29 +#define GPOUT_SYS_SPI0_CLK 30 +#define GPOUT_SYS_SPI0_FSS 31 +#define GPOUT_SYS_SPI0_TXD 32 +#define GPOUT_SYS_GMAC_PHYCLK 33 +#define GPOUT_SYS_I2SRX_BCLK 34 +#define GPOUT_SYS_I2SRX_LRCK 35 +#define GPOUT_SYS_I2STX0_BCLK 36 +#define GPOUT_SYS_I2STX0_LRCK 37 +#define GPOUT_SYS_MCLK 38 +#define GPOUT_SYS_TDM_CLK 39 +#define GPOUT_SYS_TDM_SYNC 40 +#define GPOUT_SYS_TDM_TXD 41 +#define GPOUT_SYS_TRACE_DATA0 42 +#define GPOUT_SYS_TRACE_DATA1 43 +#define GPOUT_SYS_TRACE_DATA2 44 +#define GPOUT_SYS_TRACE_DATA3 45 +#define GPOUT_SYS_TRACE_REF 46 +#define GPOUT_SYS_CAN1_STBY 47 +#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48 +#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49 +#define GPOUT_SYS_CAN1_TXD 50 +#define GPOUT_SYS_I2C1_CLK 51 +#define GPOUT_SYS_I2C1_DATA 52 +#define GPOUT_SYS_SDIO1_BACK_END_POWER 53 +#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54 +#define GPOUT_SYS_SDIO1_CLK 55 +#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56 +#define GPOUT_SYS_SDIO1_CMD 57 +#define GPOUT_SYS_SDIO1_DATA0 58 +#define GPOUT_SYS_SDIO1_DATA1 59 +#define GPOUT_SYS_SDIO1_DATA2 60 +#define GPOUT_SYS_SDIO1_DATA3 61 +#define GPOUT_SYS_SDIO1_DATA4 63 +#define GPOUT_SYS_SDIO1_DATA5 63 +#define GPOUT_SYS_SDIO1_DATA6 64 +#define GPOUT_SYS_SDIO1_DATA7 65 +#define GPOUT_SYS_SDIO1_RST 66 +#define GPOUT_SYS_UART1_RTS 67 +#define GPOUT_SYS_UART1_TX 68 +#define GPOUT_SYS_I2STX1_SDO0 69 +#define GPOUT_SYS_I2STX1_SDO1 70 +#define GPOUT_SYS_I2STX1_SDO2 71 +#define GPOUT_SYS_I2STX1_SDO3 72 +#define GPOUT_SYS_SPI1_CLK 73 +#define GPOUT_SYS_SPI1_FSS 74 +#define GPOUT_SYS_SPI1_TXD 75 +#define GPOUT_SYS_I2C2_CLK 76 +#define GPOUT_SYS_I2C2_DATA 77 +#define GPOUT_SYS_UART2_RTS 78 +#define GPOUT_SYS_UART2_TX 79 +#define GPOUT_SYS_SPI2_CLK 80 +#define GPOUT_SYS_SPI2_FSS 81 +#define GPOUT_SYS_SPI2_TXD 82 +#define GPOUT_SYS_I2C3_CLK 83 +#define GPOUT_SYS_I2C3_DATA 84 +#define GPOUT_SYS_UART3_TX 85 +#define GPOUT_SYS_SPI3_CLK 86 +#define GPOUT_SYS_SPI3_FSS 87 +#define GPOUT_SYS_SPI3_TXD 88 +#define GPOUT_SYS_I2C4_CLK 89 +#define GPOUT_SYS_I2C4_DATA 90 +#define GPOUT_SYS_UART4_RTS 91 +#define GPOUT_SYS_UART4_TX 92 +#define GPOUT_SYS_SPI4_CLK 93 +#define GPOUT_SYS_SPI4_FSS 94 +#define GPOUT_SYS_SPI4_TXD 95 +#define GPOUT_SYS_I2C5_CLK 96 +#define GPOUT_SYS_I2C5_DATA 97 +#define GPOUT_SYS_UART5_RTS 98 +#define GPOUT_SYS_UART5_TX 99 +#define GPOUT_SYS_SPI5_CLK 100 +#define GPOUT_SYS_SPI5_FSS 101 +#define GPOUT_SYS_SPI5_TXD 102 +#define GPOUT_SYS_I2C6_CLK 103 +#define GPOUT_SYS_I2C6_DATA 104 +#define GPOUT_SYS_SPI6_CLK 105 +#define GPOUT_SYS_SPI6_FSS 106 +#define GPOUT_SYS_SPI6_TXD 107 + +/* aon_iomux dout */ +#define GPOUT_AON_CLK_32K_OUT 2 +#define GPOUT_AON_PTC0_PWM4 3 +#define GPOUT_AON_PTC0_PWM5 4 +#define GPOUT_AON_PTC0_PWM6 5 +#define GPOUT_AON_PTC0_PWM7 6 +#define GPOUT_AON_CLK_GCLK0 7 +#define GPOUT_AON_CLK_GCLK1 8 +#define GPOUT_AON_CLK_GCLK2 9 + +/* sys_iomux doen */ +#define GPOEN_ENABLE 0 +#define GPOEN_DISABLE 1 +#define GPOEN_SYS_HDMI_CEC_SDA 2 +#define GPOEN_SYS_HDMI_DDC_SCL 3 +#define GPOEN_SYS_HDMI_DDC_SDA 4 +#define GPOEN_SYS_I2C0_CLK 5 +#define GPOEN_SYS_I2C0_DATA 6 +#define GPOEN_SYS_HIFI4_JTAG_TDO 7 +#define GPOEN_SYS_JTAG_TDO 8 +#define GPOEN_SYS_PWM0_CHANNEL0 9 +#define GPOEN_SYS_PWM0_CHANNEL1 10 +#define GPOEN_SYS_PWM0_CHANNEL2 11 +#define GPOEN_SYS_PWM0_CHANNEL3 12 +#define GPOEN_SYS_SPI0_NSSPCTL 13 +#define GPOEN_SYS_SPI0_NSSP 14 +#define GPOEN_SYS_TDM_SYNC 15 +#define GPOEN_SYS_TDM_TXD 16 +#define GPOEN_SYS_I2C1_CLK 17 +#define GPOEN_SYS_I2C1_DATA 18 +#define GPOEN_SYS_SDIO1_CMD 19 +#define GPOEN_SYS_SDIO1_DATA0 20 +#define GPOEN_SYS_SDIO1_DATA1 21 +#define GPOEN_SYS_SDIO1_DATA2 22 +#define GPOEN_SYS_SDIO1_DATA3 23 +#define GPOEN_SYS_SDIO1_DATA4 24 +#define GPOEN_SYS_SDIO1_DATA5 25 +#define GPOEN_SYS_SDIO1_DATA6 26 +#define GPOEN_SYS_SDIO1_DATA7 27 +#define GPOEN_SYS_SPI1_NSSPCTL 28 +#define GPOEN_SYS_SPI1_NSSP 29 +#define GPOEN_SYS_I2C2_CLK 30 +#define GPOEN_SYS_I2C2_DATA 31 +#define GPOEN_SYS_SPI2_NSSPCTL 32 +#define GPOEN_SYS_SPI2_NSSP 33 +#define GPOEN_SYS_I2C3_CLK 34 +#define GPOEN_SYS_I2C3_DATA 35 +#define GPOEN_SYS_SPI3_NSSPCTL 36 +#define GPOEN_SYS_SPI3_NSSP 37 +#define GPOEN_SYS_I2C4_CLK 38 +#define GPOEN_SYS_I2C4_DATA 39 +#define GPOEN_SYS_SPI4_NSSPCTL 40 +#define GPOEN_SYS_SPI4_NSSP 41 +#define GPOEN_SYS_I2C5_CLK 42 +#define GPOEN_SYS_I2C5_DATA 43 +#define GPOEN_SYS_SPI5_NSSPCTL 44 +#define GPOEN_SYS_SPI5_NSSP 45 +#define GPOEN_SYS_I2C6_CLK 46 +#define GPOEN_SYS_I2C6_DATA 47 +#define GPOEN_SYS_SPI6_NSSPCTL 48 +#define GPOEN_SYS_SPI6_NSSP 49 + +/* aon_iomux doen */ +#define GPOEN_AON_PTC0_OE_N_4 2 +#define GPOEN_AON_PTC0_OE_N_5 3 +#define GPOEN_AON_PTC0_OE_N_6 4 +#define GPOEN_AON_PTC0_OE_N_7 5 + +/* sys_iomux gin */ +#define GPI_NONE 255 + +#define GPI_SYS_WAVE511_UART_RX 0 +#define GPI_SYS_CAN0_RXD 1 +#define GPI_SYS_USB_OVERCURRENT 2 +#define GPI_SYS_SPDIF 3 +#define GPI_SYS_JTAG_RST 4 +#define GPI_SYS_HDMI_CEC_SDA 5 +#define GPI_SYS_HDMI_DDC_SCL 6 +#define GPI_SYS_HDMI_DDC_SDA 7 +#define GPI_SYS_HDMI_HPD 8 +#define GPI_SYS_I2C0_CLK 9 +#define GPI_SYS_I2C0_DATA 10 +#define GPI_SYS_SDIO0_CD 11 +#define GPI_SYS_SDIO0_INT 12 +#define GPI_SYS_SDIO0_WP 13 +#define GPI_SYS_UART0_RX 14 +#define GPI_SYS_HIFI4_JTAG_TCK 15 +#define GPI_SYS_HIFI4_JTAG_TDI 16 +#define GPI_SYS_HIFI4_JTAG_TMS 17 +#define GPI_SYS_HIFI4_JTAG_RST 18 +#define GPI_SYS_JTAG_TDI 19 +#define GPI_SYS_JTAG_TMS 20 +#define GPI_SYS_PDM_DMIC0 21 +#define GPI_SYS_PDM_DMIC1 22 +#define GPI_SYS_I2SRX_SDIN0 23 +#define GPI_SYS_I2SRX_SDIN1 24 +#define GPI_SYS_I2SRX_SDIN2 25 +#define GPI_SYS_SPI0_CLK 26 +#define GPI_SYS_SPI0_FSS 27 +#define GPI_SYS_SPI0_RXD 28 +#define GPI_SYS_JTAG_TCK 29 +#define GPI_SYS_MCLK_EXT 30 +#define GPI_SYS_I2SRX_BCLK 31 +#define GPI_SYS_I2SRX_LRCK 32 +#define GPI_SYS_I2STX0_BCLK 33 +#define GPI_SYS_I2STX0_LRCK 34 +#define GPI_SYS_TDM_CLK 35 +#define GPI_SYS_TDM_RXD 36 +#define GPI_SYS_TDM_SYNC 37 +#define GPI_SYS_CAN1_RXD 38 +#define GPI_SYS_I2C1_CLK 39 +#define GPI_SYS_I2C1_DATA 40 +#define GPI_SYS_SDIO1_CD 41 +#define GPI_SYS_SDIO1_INT 42 +#define GPI_SYS_SDIO1_WP 43 +#define GPI_SYS_SDIO1_CMD 44 +#define GPI_SYS_SDIO1_DATA0 45 +#define GPI_SYS_SDIO1_DATA1 46 +#define GPI_SYS_SDIO1_DATA2 47 +#define GPI_SYS_SDIO1_DATA3 48 +#define GPI_SYS_SDIO1_DATA4 49 +#define GPI_SYS_SDIO1_DATA5 50 +#define GPI_SYS_SDIO1_DATA6 51 +#define GPI_SYS_SDIO1_DATA7 52 +#define GPI_SYS_SDIO1_STRB 53 +#define GPI_SYS_UART1_CTS 54 +#define GPI_SYS_UART1_RX 55 +#define GPI_SYS_SPI1_CLK 56 +#define GPI_SYS_SPI1_FSS 57 +#define GPI_SYS_SPI1_RXD 58 +#define GPI_SYS_I2C2_CLK 59 +#define GPI_SYS_I2C2_DATA 60 +#define GPI_SYS_UART2_CTS 61 +#define GPI_SYS_UART2_RX 62 +#define GPI_SYS_SPI2_CLK 63 +#define GPI_SYS_SPI2_FSS 64 +#define GPI_SYS_SPI2_RXD 65 +#define GPI_SYS_I2C3_CLK 66 +#define GPI_SYS_I2C3_DATA 67 +#define GPI_SYS_UART3_RX 68 +#define GPI_SYS_SPI3_CLK 69 +#define GPI_SYS_SPI3_FSS 70 +#define GPI_SYS_SPI3_RXD 71 +#define GPI_SYS_I2C4_CLK 72 +#define GPI_SYS_I2C4_DATA 73 +#define GPI_SYS_UART4_CTS 74 +#define GPI_SYS_UART4_RX 75 +#define GPI_SYS_SPI4_CLK 76 +#define GPI_SYS_SPI4_FSS 77 +#define GPI_SYS_SPI4_RXD 78 +#define GPI_SYS_I2C5_CLK 79 +#define GPI_SYS_I2C5_DATA 80 +#define GPI_SYS_UART5_CTS 81 +#define GPI_SYS_UART5_RX 82 +#define GPI_SYS_SPI5_CLK 83 +#define GPI_SYS_SPI5_FSS 84 +#define GPI_SYS_SPI5_RXD 85 +#define GPI_SYS_I2C6_CLK 86 +#define GPI_SYS_I2C6_DATA 87 +#define GPI_SYS_SPI6_CLK 88 +#define GPI_SYS_SPI6_FSS 89 +#define GPI_SYS_SPI6_RXD 90 + +/* aon_iomux gin */ +#define GPI_AON_PMU_GPIO_WAKEUP_0 0 +#define GPI_AON_PMU_GPIO_WAKEUP_1 1 +#define GPI_AON_PMU_GPIO_WAKEUP_2 2 +#define GPI_AON_PMU_GPIO_WAKEUP_3 3 + +#endif From 54baba33392d428a8be4942441a92a9b05cf537e Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Sat, 1 Apr 2023 19:19:33 +0800 Subject: [PATCH 0861/1040] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Add a minimal device tree for StarFive JH7110 VisionFive 2 board which has version A and version B. Support booting and basic clock/reset/pinctrl/uart drivers. Tested-by: Tommaso Merciai Reviewed-by: Conor Dooley Acked-by: Conor Dooley Signed-off-by: Emil Renner Berthing Co-developed-by: Jianlong Huang Signed-off-by: Jianlong Huang Co-developed-by: Hal Feng Signed-off-by: Hal Feng Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/Makefile | 6 +- .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++ .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++ .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++ 4 files changed, 246 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 7b00a48580ca..170956846d49 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -1,2 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb + +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts new file mode 100644 index 000000000000..4af3300f3cf3 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing + */ + +/dts-v1/; +#include "jh7110-starfive-visionfive-2.dtsi" + +/ { + model = "StarFive VisionFive 2 v1.2A"; + compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts new file mode 100644 index 000000000000..9230cc3d8946 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing + */ + +/dts-v1/; +#include "jh7110-starfive-visionfive-2.dtsi" + +/ { + model = "StarFive VisionFive 2 v1.3B"; + compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi new file mode 100644 index 000000000000..2a6d81609284 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing + */ + +/dts-v1/; +#include "jh7110.dtsi" +#include "jh7110-pinfunc.h" +#include + +/ { + aliases { + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c5 = &i2c5; + i2c6 = &i2c6; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = <4000000>; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x1 0x0>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; + priority = <224>; + }; +}; + +&gmac0_rgmii_rxin { + clock-frequency = <125000000>; +}; + +&gmac0_rmii_refin { + clock-frequency = <50000000>; +}; + +&gmac1_rgmii_rxin { + clock-frequency = <125000000>; +}; + +&gmac1_rmii_refin { + clock-frequency = <50000000>; +}; + +&i2srx_bclk_ext { + clock-frequency = <12288000>; +}; + +&i2srx_lrck_ext { + clock-frequency = <192000>; +}; + +&i2stx_bclk_ext { + clock-frequency = <12288000>; +}; + +&i2stx_lrck_ext { + clock-frequency = <192000>; +}; + +&mclk_ext { + clock-frequency = <12288000>; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&rtc_osc { + clock-frequency = <32768>; +}; + +&tdm_ext { + clock-frequency = <49152000>; +}; + +&i2c0 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; + i2c-sda-falling-time-ns = <510>; + i2c-scl-falling-time-ns = <510>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + status = "okay"; +}; + +&sysgpio { + i2c0_pins: i2c0-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c2_pins: i2c2-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c5_pins: i2c5-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + i2c6_pins: i2c6-0 { + i2c-pins { + pinmux = , + ; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + uart0_pins: uart0-0 { + tx-pins { + pinmux = ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = ; + bias-disable; /* external pull-up */ + drive-strength = <2>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; From 821d96e3a006d09ca9aa3d982c50f3d86fa55500 Mon Sep 17 00:00:00 2001 From: Kartik Date: Tue, 17 Jan 2023 14:00:55 +0530 Subject: [PATCH 0862/1040] soc/tegra: fuse: Remove nvmem root only access To read fuse values, various "non-root" userspace applications require access to nvmem binary interface. Remove root only access for nvmem userspace binary interface. Signed-off-by: Kartik Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index f02953f793e9..d7a37f5d4527 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved. */ #include @@ -166,7 +166,7 @@ static int tegra_fuse_probe(struct platform_device *pdev) nvmem.nkeepout = fuse->soc->num_keepouts; nvmem.type = NVMEM_TYPE_OTP; nvmem.read_only = true; - nvmem.root_only = true; + nvmem.root_only = false; nvmem.reg_read = tegra_fuse_read; nvmem.size = fuse->soc->info->size; nvmem.word_size = 4; From 1e6e0c1c971e5e02047a05c015510cc203530dc2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 18 Mar 2023 14:42:55 +0100 Subject: [PATCH 0863/1040] arm64: dts: qcom: sm6115: Use the correct DSI compatible Use the non-deprecated, SoC-specific DSI compatible. Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230307-topic-dsi_qcm-v6-9-70e13b1214fa@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 2505c815c65a..3426a36053ea 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1241,7 +1241,7 @@ }; mdss_dsi0: dsi@5e94000 { - compatible = "qcom,dsi-ctrl-6g-qcm2290"; + compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0 0x05e94000 0x0 0x400>; reg-names = "dsi_ctrl"; From 1e9c2404d8870ec08bfc338ae7113c3f7fe0b171 Mon Sep 17 00:00:00 2001 From: Shreeya Patel Date: Wed, 5 Apr 2023 13:57:11 +0530 Subject: [PATCH 0864/1040] arm64: dts: rockchip: Enable RTC support for Rock 5B Add DT node to enable RTC support for Rock 5B board. Signed-off-by: Shreeya Patel Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/r/20230405082711.46303-1-shreeya.patel@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 95805cb0adfa..e63138eb7e8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -27,6 +27,31 @@ }; }; +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + &sdhci { bus-width = <8>; no-sdio; From f36bb17653e4b9e26bbdb1224027d20614e77636 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 4 Apr 2023 20:38:07 +0300 Subject: [PATCH 0865/1040] arm64: dts: rockchip: Add pwm-fan to rk3588-rock-5b Add the necessary DT changes for the Rock 5B board to enable support for the PWM controlled heat sink fan. Signed-off-by: Cristian Ciocaltea Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/r/20230404173807.490520-3-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index e63138eb7e8d..24fb5340e981 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -17,6 +17,14 @@ stdout-path = "serial2:1500000n8"; }; + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -52,6 +60,10 @@ }; }; +&pwm1 { + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; From 32641b8ab1a5bd08e898cec3d46a8ecb4b4e895e Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 4 Apr 2023 17:44:29 +0200 Subject: [PATCH 0866/1040] arm64: dts: rockchip: add rk3588 thermal sensor Add thermal sensor IP, which allows monitoring temperatures at seven different places in the SoC: * Chip Center * CPU Cluster 1 (Dual A76 "Big" Cores) * CPU Cluster 2 (Dual A76 "Big" Cores) * CPU Cluster 0 (Quad A55 "Little" Cores) * Power Domain Center * Graphics Processing Unit * Neural Processing Unit Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230404154429.51601-1-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 4bd8697c6b48..b83b3ae9ca27 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -1580,6 +1580,26 @@ status = "disabled"; }; + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>; From 87810bda8a8472a9a106c6de34a032fb6a4b425b Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sun, 2 Apr 2023 12:50:50 +0300 Subject: [PATCH 0867/1040] arm64: dts: rockchip: Fix SCMI assigned clocks on rk3588s Since commit df4fdd0db475 ("dt-bindings: firmware: arm,scmi: Restrict protocol child node properties") the following dtbs_check warning is shown: rk3588-rock-5b.dtb: scmi: protocol@14: Unevaluated properties are not allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected) Because adding the missing properties to firmware/arm,scmi.yaml binding document was not an acceptable solution, move SCMI_CLK_CPUB01 and SCMI_CLK_CPUB23 assigned clocks to the related CPU nodes and also add the missing SCMI_CLK_CPUL. Additionally, adjust frequency to 816 MHz for all the above mentioned assigned clocks, in order to match the firmware defaults. Suggested-by: Sebastian Reichel Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230402095054.384739-2-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index b83b3ae9ca27..37d03330a37e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -60,6 +60,8 @@ enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -136,6 +138,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -174,6 +178,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -304,10 +310,6 @@ scmi_clk: protocol@14 { reg = <0x14>; - assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>, - <&scmi_clk SCMI_CLK_CPUB23>; - assigned-clock-rates = <1200000000>, - <1200000000>; #clock-cells = <1>; }; From b46a22dea7530cf530a45c6b84c03300083b813d Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sun, 2 Apr 2023 12:50:51 +0300 Subject: [PATCH 0868/1040] arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz instead of 1.1 GHz. Fix it. Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC") Reported-by: Sebastian Reichel Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 37d03330a37e..5e27905b9d6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -416,7 +416,7 @@ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates = - <100000000>, <786432000>, + <1100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>, From 8ae112a5554fb1580fc5564f8610cef85f2e3f7b Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sun, 2 Apr 2023 12:50:52 +0300 Subject: [PATCH 0869/1040] arm64: dts: rockchip: Add rk3588s I2S nodes There are five I2S/PCM/TDM controllers and two I2S/PCM controllers embedded in the RK3588 and RK3588S SoCs. Add the DT nodes corresponding to the above mentioned Rockchip controllers. Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers, which are handled via a separate patch. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230402095054.384739-4-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 148 ++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 5e27905b9d6a..9d524dcb7b25 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -812,6 +812,57 @@ }; }; + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>; @@ -1134,6 +1185,103 @@ status = "disabled"; }; + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ From 6f48c6f5859296eaf54a55f436db3a248f772e4d Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sun, 2 Apr 2023 12:50:53 +0300 Subject: [PATCH 0870/1040] arm64: dts: rockchip: Add I2S rk3588 nodes In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides another group of four I2S/PCM/TDM controllers. Add the DT nodes corresponding to the additional controllers. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230402095054.384739-5-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index d085e57fbc4c..8be75556af8f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,74 @@ #include "rk3588-pinctrl.dtsi" / { + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; From 55529fe3f32d8c2fdb70981f2e151735e090a1e0 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Sun, 2 Apr 2023 12:50:54 +0300 Subject: [PATCH 0871/1040] arm64: dts: rockchip: Add rk3588-rock-5b analog audio Add the necessary DT nodes for the Rock 5B board to enable the analog audio support provided by the Everest Semi ES8316 codec. Signed-off-by: Cristian Ciocaltea Reviewed-by: Christopher Obbard Link: https://lore.kernel.org/r/20230402095054.384739-6-cristian.ciocaltea@collabora.com [adapted to the fan addition I applied slightly earlier] Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 24fb5340e981..88b9f7ddf291 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -2,6 +2,7 @@ /dts-v1/; +#include #include "rk3588.dtsi" / { @@ -25,6 +26,23 @@ #cooling-cells = <2>; }; + sound { + compatible = "audio-graph-card"; + label = "Analog"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -52,12 +70,54 @@ }; }; +&i2c7 { + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { From 07099a551803e05d3ee42fae152bf404f8dc21f9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 22:45:18 +0200 Subject: [PATCH 0872/1040] arm64: dts: rockchip: correct panel supplies on Odroid Go Super The Anbernic and Odroid Go have different panels and take differently named supplies, so move all the supplies to DTS defining actual panel to fix warnings like: rk3326-odroid-go3.dtb: panel@0: 'IOVCC-supply' is a required property rk3326-odroid-go3.dtb: panel@0: 'iovcc-supply', 'vdd-supply' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230326204520.80859-1-krzysztof.kozlowski@linaro.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts index 1b9769ccfdeb..35bbaf559ca3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts @@ -144,6 +144,7 @@ &internal_display { compatible = "elida,kd50t048a", "sitronix,st7701"; reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + IOVCC-supply = <&vcc_lcd>; VCC-supply = <&vcc_lcd>; }; From fcbfe8121a45152a3cfbe1c28c96a3b611b7347d Mon Sep 17 00:00:00 2001 From: Niklas Schnelle Date: Thu, 23 Mar 2023 17:33:52 +0100 Subject: [PATCH 0873/1040] Kconfig: introduce HAS_IOPORT option and select it as necessary We introduce a new HAS_IOPORT Kconfig option to indicate support for I/O Port access. In a future patch HAS_IOPORT=n will disable compilation of the I/O accessor functions inb()/outb() and friends on architectures which can not meaningfully support legacy I/O spaces such as s390. The following architectures do not select HAS_IOPORT: * ARC * C-SKY * Hexagon * Nios II * OpenRISC * s390 * User-Mode Linux * Xtensa All other architectures select HAS_IOPORT at least conditionally. The "depends on" relations on HAS_IOPORT in drivers as well as ifdefs for HAS_IOPORT specific sections will be added in subsequent patches on a per subsystem basis. Co-developed-by: Arnd Bergmann Signed-off-by: Arnd Bergmann Acked-by: Johannes Berg # for ARCH=um Acked-by: Geert Uytterhoeven Signed-off-by: Niklas Schnelle Signed-off-by: Arnd Bergmann --- arch/alpha/Kconfig | 1 + arch/arm/Kconfig | 1 + arch/arm64/Kconfig | 1 + arch/ia64/Kconfig | 1 + arch/loongarch/Kconfig | 1 + arch/m68k/Kconfig | 1 + arch/microblaze/Kconfig | 1 + arch/mips/Kconfig | 1 + arch/parisc/Kconfig | 1 + arch/powerpc/Kconfig | 1 + arch/riscv/Kconfig | 1 + arch/sh/Kconfig | 1 + arch/sparc/Kconfig | 1 + arch/x86/Kconfig | 1 + drivers/bus/Kconfig | 2 +- drivers/parisc/Kconfig | 1 + lib/Kconfig | 4 ++++ 17 files changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 780d4673c3ca..a5c2b1aa46b0 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -27,6 +27,7 @@ config ALPHA select AUDIT_ARCH select GENERIC_CPU_VULNERABILITIES select GENERIC_SMP_IDLE_THREAD + select HAS_IOPORT select HAVE_ARCH_AUDITSYSCALL select HAVE_MOD_ARCH_SPECIFIC select MODULES_USE_ELF_RELA diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e24a9820e12f..4acb5bc4b52a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -70,6 +70,7 @@ config ARM select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD select HARDIRQS_SW_RESEND + select HAS_IOPORT select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1023e896d46b..b740019c4aee 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -145,6 +145,7 @@ config ARM64 select GENERIC_GETTIMEOFDAY select GENERIC_VDSO_TIME_NS select HARDIRQS_SW_RESEND + select HAS_IOPORT select HAVE_MOVE_PMD select HAVE_MOVE_PUD select HAVE_PCI diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index d7e4a24e8644..2e13ec8263b9 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -25,6 +25,7 @@ config IA64 select PCI_DOMAINS if PCI select PCI_MSI select PCI_SYSCALL if PCI + select HAS_IOPORT select HAVE_ASM_MODVERSIONS select HAVE_UNSTABLE_SCHED_CLOCK select HAVE_EXIT_THREAD diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 7fd51257e0ed..e1615dfb5437 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -80,6 +80,7 @@ config LOONGARCH select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL select GPIOLIB + select HAS_IOPORT select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_MMAP_RND_BITS if MMU select HAVE_ARCH_SECCOMP_FILTER diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 82154952e574..40198a1ebe27 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -18,6 +18,7 @@ config M68K select GENERIC_CPU_DEVICES select GENERIC_IOMAP select GENERIC_IRQ_SHOW + select HAS_IOPORT if PCI || ISA || ATARI_ROM_ISA select HAVE_ARCH_SECCOMP select HAVE_ARCH_SECCOMP_FILTER select HAVE_ASM_MODVERSIONS diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index cc88af6fa7a4..211f338d6235 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -21,6 +21,7 @@ config MICROBLAZE select GENERIC_IRQ_SHOW select GENERIC_PCI_IOMAP select GENERIC_SCHED_CLOCK + select HAS_IOPORT if PCI select HAVE_ARCH_HASH select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e2f3ca73f40d..2ea3539a07ad 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -47,6 +47,7 @@ config MIPS select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT + select HAS_IOPORT if !NO_IOPORT_MAP || ISA select HAVE_ARCH_COMPILER_H select HAVE_ARCH_JUMP_LABEL select HAVE_ARCH_KGDB if MIPS_FP_SUPPORT diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index a98940e64243..466a25525364 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -47,6 +47,7 @@ config PARISC select MODULES_USE_ELF_RELA select CLONE_BACKWARDS select TTY # Needed for pdc_cons.c + select HAS_IOPORT if PCI || EISA select HAVE_DEBUG_STACKOVERFLOW select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_HASH diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index a6c4407d3ec8..02fd9bcd9215 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -188,6 +188,7 @@ config PPC select GENERIC_SMP_IDLE_THREAD select GENERIC_TIME_VSYSCALL select GENERIC_VDSO_TIME_NS + select HAS_IOPORT if PCI select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP select HAVE_ARCH_HUGE_VMAP if PPC_RADIX_MMU || PPC_8xx diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c5e42cc37604..b957d12a171b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -74,6 +74,7 @@ config RISCV select GENERIC_TIME_VSYSCALL if MMU && 64BIT select GENERIC_VDSO_TIME_NS if HAVE_GENERIC_VDSO select HARDIRQS_SW_RESEND + select HAS_IOPORT if MMU select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT && !XIP_KERNEL diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 0665ac0add0b..cfb797bc4200 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -25,6 +25,7 @@ config SUPERH select GENERIC_SCHED_CLOCK select GENERIC_SMP_IDLE_THREAD select GUP_GET_PXX_LOW_HIGH if X2TLB + select HAS_IOPORT if HAS_IOPORT_MAP select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_KGDB select HAVE_ARCH_SECCOMP_FILTER diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 84437a4c6545..d4c1d96f85cd 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -32,6 +32,7 @@ config SPARC select GENERIC_IRQ_SHOW select ARCH_WANT_IPC_PARSE_VERSION select GENERIC_PCI_IOMAP + select HAS_IOPORT select HAVE_NMI_WATCHDOG if SPARC64 select HAVE_CBPF_JIT if SPARC32 select HAVE_EBPF_JIT if SPARC64 diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a825bf031f49..44514c63a476 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -162,6 +162,7 @@ config X86 select GUP_GET_PXX_LOW_HIGH if X86_PAE select HARDIRQS_SW_RESEND select HARDLOCKUP_CHECK_TIMESTAMP if X86_64 + select HAS_IOPORT select HAVE_ACPI_APEI if ACPI select HAVE_ACPI_APEI_NMI if ACPI select HAVE_ALIGNED_STRUCT_PAGE if SLUB diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 7bfe998f3514..fcfa280df98a 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -81,7 +81,7 @@ config MOXTET config HISILICON_LPC bool "Support for ISA I/O space on HiSilicon Hip06/7" depends on (ARM64 && ARCH_HISI) || (COMPILE_TEST && !ALPHA && !HEXAGON && !PARISC) - depends on HAS_IOMEM + depends on HAS_IOPORT select INDIRECT_PIO if ARM64 help Driver to enable I/O access to devices attached to the Low Pin diff --git a/drivers/parisc/Kconfig b/drivers/parisc/Kconfig index 9eb2c1b5de7d..2fc3222d2634 100644 --- a/drivers/parisc/Kconfig +++ b/drivers/parisc/Kconfig @@ -4,6 +4,7 @@ menu "Bus options (PCI, PCMCIA, EISA, GSC, ISA)" config GSC bool "VSC/GSC/HSC bus support" select HAVE_EISA + select HAS_IOPORT default y help The VSC, GSC and HSC busses were used from the earliest 700-series diff --git a/lib/Kconfig b/lib/Kconfig index ce2abffb9ed8..5c2da561c516 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -92,6 +92,7 @@ config ARCH_USE_SYM_ANNOTATIONS config INDIRECT_PIO bool "Access I/O in non-MMIO mode" depends on ARM64 + depends on HAS_IOPORT help On some platforms where no separate I/O space exists, there are I/O hosts which can not be accessed in MMIO mode. Using the logical PIO @@ -509,6 +510,9 @@ config HAS_IOMEM depends on !NO_IOMEM default y +config HAS_IOPORT + bool + config HAS_IOPORT_MAP bool depends on HAS_IOMEM && !NO_IOPORT_MAP From 30c6a9a64211300c93cb261f1f8509983e273100 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 22 Mar 2023 13:25:03 +0800 Subject: [PATCH 0874/1040] arm64: dts: imx8-apalis-v1.1: drop ci-disable-lpm This is an NXP downstream property. And no binding doc, and no driver use this property. So drop it Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 486adf849452..bd5d771637ca 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -726,7 +726,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg1>; adp-disable; - ci-disable-lpm; hnp-disable; over-current-active-low; power-active-high; From 7c0277ab8c209ec9fb5d5c112577958a6236b57b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Mon, 27 Mar 2023 19:35:26 +0200 Subject: [PATCH 0875/1040] arm64: dts: imx8mp: Add GPT blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The i.MX8MP includes the same GPT blocks as the i.MX6DL. Add all 6 instances. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 48 +++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 1b6757148516..8b4a3397b417 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -409,6 +409,30 @@ status = "disabled"; }; + gpt1: timer@302d0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302d0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@302e0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302e0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; + clock-names = "ipg", "per"; + }; + + gpt3: timer@302f0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x302f0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; + clock-names = "ipg", "per"; + }; + iomuxc: pinctrl@30330000 { compatible = "fsl,imx8mp-iomuxc"; reg = <0x30330000 0x10000>; @@ -722,6 +746,30 @@ clocks = <&osc_24m>; clock-names = "per"; }; + + gpt6: timer@306e0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x306e0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; + clock-names = "ipg", "per"; + }; + + gpt5: timer@306f0000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x306f0000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; + clock-names = "ipg", "per"; + }; + + gpt4: timer@30700000 { + compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; + reg = <0x30700000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; + clock-names = "ipg", "per"; + }; }; aips3: bus@30800000 { From 788fd97b244627347519c392f30b63850f6667a4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Mar 2023 11:36:35 +0800 Subject: [PATCH 0876/1040] arm64: dts: imx8mn-evk: update i2c pinctrl to match dtschema The dtschema requires 'grp' in the end, so update the name. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 8fef980c4ab2..1443857bfa5f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -389,7 +389,7 @@ >; }; - pinctrl_i2c2_gpio: i2c2grp-gpio { + pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 @@ -403,7 +403,7 @@ >; }; - pinctrl_i2c3_gpio: i2c3grp-gpio { + pinctrl_i2c3_gpio: i2c3gpiogrp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 From 523306b6608c49a39aff772039e96510f2ebc0bf Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Mar 2023 11:36:36 +0800 Subject: [PATCH 0877/1040] arm64: dts: imx8mm-ddr4-evk: update gpmi pinctrl to match dtschema The dtschema requires 'grp' in the end, so update the name. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts index 6c079c0a3a48..010e836ebe5c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts @@ -28,7 +28,7 @@ }; &iomuxc { - pinctrl_gpmi_nand: gpmi-nand { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 From 72783d652005d6732903c35a323170d57f5dab8f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Mar 2023 11:36:37 +0800 Subject: [PATCH 0878/1040] arm64: dts: imx8mq-librem5: update pinctrl to match dtschema The dtschema requires 'grp' in the end, so update the name. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 7605802f294d..ce7ce2ba855c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -667,7 +667,7 @@ >; }; - pinctrl_spkamp: spkamp { + pinctrl_spkamp: spkampgrp { fsl,pins = < MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x81 /* MUTE */ >; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index ceced6bc4e89..48d96183f3d1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -686,7 +686,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd @@ -703,7 +703,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf @@ -733,7 +733,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d @@ -746,7 +746,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x80 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f From 6de2a9e20f7450150206d785efcb209b848e1aba Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Mar 2023 11:36:38 +0800 Subject: [PATCH 0879/1040] arm64: dts: imx8mm-emcon: update pinctrl to match dtschema The dtschema requires 'grp' in the end, so update the name Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi index 3d859a350bd5..4e9e58acd262 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi @@ -124,7 +124,7 @@ >; }; - pinctrl_ecspi1_cs: ecspi1-cs { + pinctrl_ecspi1_cs: ecspi1cs-grp { fsl,pins = < MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 @@ -215,7 +215,7 @@ >; }; - pinctrl_pmic: pmic-irq { + pinctrl_pmic: pmicirq-grp { fsl,pins = < MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41 >; From 4629e559d95ef811bb28bc799828d6225a68749b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Mar 2023 11:36:39 +0800 Subject: [PATCH 0880/1040] arm64: dts: imx8mn-bsh-smm: update pinctrl to match dtschema The dtschema requires 'grp' in the end, so update the name Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index c11895d9d582..8e100e71b8d2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -341,7 +341,7 @@ >; }; - pinctrl_pmic: pmicirq { + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040 >; @@ -381,7 +381,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4 @@ -392,7 +392,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts index 33f98582eace..7acc5a960dd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts @@ -26,7 +26,7 @@ }; &iomuxc { - pinctrl_gpmi_nand: gpmi-nand { + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts index fbbb3367037b..c6ad65becc97 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -136,7 +136,7 @@ >; }; - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4 @@ -152,7 +152,7 @@ >; }; - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6 From cb562edda04242b9b37d27e26175c562d798e54c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Mar 2023 11:36:40 +0800 Subject: [PATCH 0881/1040] arm64: dts: imx8mm-prt8mm: update pinctrl to match dtschema The dtschema requires 'grp' in the end, so update the name Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts index 9fbbbb556c0b..1eb1fe7ebde8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts @@ -264,7 +264,7 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 @@ -280,7 +280,7 @@ >; }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 From 2858e62e5d192e7579ce9152457705ff98c62387 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 28 Mar 2023 14:11:23 +0800 Subject: [PATCH 0882/1040] arm64: dts: imx8mq-librem5: add missing #clock-cells '#clock-cells' is a dependency of 'clock-output-names', following binding doc, add it. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 48d96183f3d1..38732579d13e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -830,6 +830,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>, <&pinctrl_camera_pwr>; clocks = <&pmic_osc>; + #clock-cells = <0>; clock-names = "osc"; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; From a8bd7f155126912e39568e3cfa59a4699d985583 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 27 Mar 2023 10:55:22 -0400 Subject: [PATCH 0883/1040] arm64: dts: imx8qxp: add cadence usb3 support There are cadence usb3.0 controller in 8qxp and 8qm. Add usb3 node at common connect subsystem. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 4852760adeee..b32c2e199c16 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -138,6 +138,53 @@ conn_subsys: bus@5b000000 { status = "disabled"; }; + usbotg3: usb@5b110000 { + compatible = "fsl,imx8qm-usb3"; + reg = <0x5b110000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&usb3_lpcg IMX_LPCG_CLK_1>, + <&usb3_lpcg IMX_LPCG_CLK_0>, + <&usb3_lpcg IMX_LPCG_CLK_7>, + <&usb3_lpcg IMX_LPCG_CLK_4>, + <&usb3_lpcg IMX_LPCG_CLK_5>; + clock-names = "lpm", "bus", "aclk", "ipg", "core"; + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + assigned-clock-rates = <250000000>; + power-domains = <&pd IMX_SC_R_USB_2>; + status = "disabled"; + + usbotg3_cdns3: usb@5b120000 { + compatible = "cdns,usb3"; + reg = <0x5b130000 0x10000>, /* memory area for HOST registers */ + <0x5b140000 0x10000>, /* memory area for DEVICE registers */ + <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */ + reg-names = "xhci", "dev", "otg"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + phys = <&usb3_phy>; + phy-names = "cdns3,usb3-phy"; + status = "disabled"; + }; + }; + + usb3_phy: usb-phy@5b160000 { + compatible = "nxp,salvo-phy"; + reg = <0x5b160000 0x40000>; + clocks = <&usb3_lpcg IMX_LPCG_CLK_6>; + clock-names = "salvo_phy_clk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + /* LPCG clocks */ sdhc0_lpcg: clock-controller@5b200000 { compatible = "fsl,imx8qxp-lpcg"; @@ -234,4 +281,26 @@ conn_subsys: bus@5b000000 { clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk"; power-domains = <&pd IMX_SC_R_USB_0_PHY>; }; + + usb3_lpcg: clock-controller@5b280000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b280000 0x10000>; + #clock-cells = <1>; + clock-indices = , , + , , + , ; + clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&conn_ipg_clk>, + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>; + clock-output-names = "usb3_app_clk", + "usb3_lpm_clk", + "usb3_ipg_clk", + "usb3_core_pclk", + "usb3_phy_clk", + "usb3_aclk"; + power-domains = <&pd IMX_SC_R_USB_2_PHY>; + }; }; From 2faf4ebcee2e587e9a82dd14c9584acab2ce0fce Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 27 Mar 2023 10:55:23 -0400 Subject: [PATCH 0884/1040] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3 Enable USB3 controller, phy and typec related nodes. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index a56c8d0974ec..7924b0969ad8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx8qxp.dtsi" +#include / { model = "Freescale i.MX8QXP MEK"; @@ -28,6 +29,21 @@ gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + gpio-sbu-mux { + compatible = "gpio-sbu-mux"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec_mux>; + select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; }; &dsp { @@ -127,6 +143,42 @@ }; }; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x50>; + interrupt-parent = <&lsio_gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + port { + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + + usb_con1: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "source"; + data-role = "dual"; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + }; &lpuart0 { @@ -204,6 +256,27 @@ status = "okay"; }; +&usb3_phy { + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usbotg3_cdns3 { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb3_drd_sw: endpoint { + remote-endpoint = <&typec_dr_sw>; + }; + }; +}; + + &vpu { compatible = "nxp,imx8qxp-vpu"; status = "okay"; @@ -267,6 +340,18 @@ >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 + >; + }; + + pinctrl_typec_mux: typecmuxgrp { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 From 5e4f393ccbf0af0828ab0914695649a5b90db230 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 4 Apr 2023 10:02:42 +0200 Subject: [PATCH 0885/1040] ARM: dts: imx6ull: Add chargebyte Tarragon support This adds the support for chargebyte Tarragon, which is an Electrical Vehicle Supply Equipment (EVSE) for AC charging stations (according to IEC 61851, ISO 15118). The Tarragon board is based on an i.MX6ULL SoC and is available in 4 variants (Master, Slave, SlaveXT, Micro), which provide more or less peripherals. Supported features: * 512 MB DDR RAM * eMMC * Debug UART * 100 Mbit Ethernet * USB 2.0 Host interface * Powerline communication (QCA700x) * 2x RS485 * Digital in- and outputs (12 V) * One-Wire master for external temp sensors * 2x relay outputs * 2x motor interfaces Link: https://chargebyte.com/products/charging-station-communication/charge-control-c Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 4 + .../arm/boot/dts/imx6ull-tarragon-common.dtsi | 852 ++++++++++++++++++ arch/arm/boot/dts/imx6ull-tarragon-master.dts | 82 ++ arch/arm/boot/dts/imx6ull-tarragon-micro.dts | 10 + arch/arm/boot/dts/imx6ull-tarragon-slave.dts | 32 + .../arm/boot/dts/imx6ull-tarragon-slavext.dts | 64 ++ 6 files changed, 1044 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-common.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-master.dts create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-micro.dts create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-slave.dts create mode 100644 arch/arm/boot/dts/imx6ull-tarragon-slavext.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index fd4f7230cb55..404e6f5a1cc7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -760,6 +760,10 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ imx6ull-phytec-tauri-emmc.dtb \ imx6ull-phytec-tauri-nand.dtb \ + imx6ull-tarragon-master.dtb \ + imx6ull-tarragon-micro.dtb \ + imx6ull-tarragon-slave.dtb \ + imx6ull-tarragon-slavext.dtb \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ulz-14x14-evk.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi b/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi new file mode 100644 index 000000000000..3fdece5bd31f --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-common.dtsi @@ -0,0 +1,852 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +/dts-v1/; + +#include +#include +#include +#include "imx6ull.dtsi" + +/ { + aliases { + mmc0 = &usdhc2; /* eMMC */ + }; + + chosen { + stdout-path = &uart4; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&pinctrl_emmc_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + }; + + reg_dcdc_3v3: regulator-dcdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "dcdc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "ldo-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_status_leds>; + + led-1 { + function = LED_FUNCTION_BOOT; + color = ; + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + + led-2 { + function = LED_FUNCTION_PROGRAMMING; + color = ; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_motor + &pinctrl_adc_cp + &pinctrl_adc_pp>; + vref-supply = <&vgen1_reg>; + status = "okay"; +}; + +&cpu0 { + clock-frequency = <792000000>; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-cs = <3>; + cs-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH + &gpio3 2 GPIO_ACTIVE_HIGH + &gpio3 4 GPIO_ACTIVE_HIGH>; +}; + +&ecspi4 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + num-cs = <1>; + cs-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 + &pinctrl_enet1_phy_rst + &pinctrl_enet_mdio>; + phy-supply = <®_dcdc_3v3>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + phy-reset-duration = <25>; + phy-handle = <ðphy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_phy_int>; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpio2 7 IRQ_TYPE_EDGE_FALLING>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + max-speed = <100>; + smsc,disable-energy-detect; + }; + }; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "CP_INVERT", + "", + "", /* 15 */ + "", + "", + "", + "MOTOR_1_FAULT_N", + "", /* 20 */ + "", + "ROTARY_SWITCH_1_2_N", + "ROTARY_SWITCH_1_4_N", + "ROTARY_SWITCH_1_8_N", + "MOTOR_2_FAULT_N"; /* 25 */ +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "EXT_GPIO", + "MOTOR_1_DRIVER_IN1_N", + "MOTOR_1_DRIVER_IN2", + "MOTOR_2_DRIVER_IN1", + "STM32_BOOT0", /* 10 */ + "STM32_RST_N", + "RELAY_1_ENABLE", + "RELAY_2_ENABLE", + "", + "", /* 15 */ + "QCA700X_MAINS_BOOTLOADER_N", + "QCA700X_CP_RST_N", + "QCA700X_CP_BOOTLOADER_N", + "", + "DIGITAL_OUT_1", /* 20 */ + "DIGITAL_OUT_2", + "DIGITAL_OUT_3", + "DIGITAL_OUT_4", + "DIGITAL_OUT_5", + "DIGITAL_OUT_6", /* 25 */ + "ROTARY_SWITCH_2_8_N", + "ROTARY_SWITCH_2_4_N", + "ROTARY_SWITCH_2_2_N"; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", /* 5 */ + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "BOARD_VARIANT_1", + "BOARD_VARIANT_2", + "BOARD_VARIANT_0", /* 15 */ + "BOARD_VARIANT_3", + "", + "ROTARY_SWITCH_2_1_N", + "", + "DIGITAL_IN_5", /* 20 */ + "", + "", + "DIGITAL_IN_6", + "", + "DIGITAL_IN_1", /* 25 */ + "DIGITAL_IN_2", + "DIGITAL_IN_4", + "DIGITAL_IN_3"; + + pmic-int-hog { + gpio-hog; + gpios = <19 0>; + input; + }; +}; + +&gpio5 { + gpio-line-names = "ROTARY_SWITCH_1_1_N", /* 0 */ + "", + "RELAY_2_SENSE", + "RELAY_1_SENSE", + "", + "", /* 5 */ + "", + "QCA700X_MAINS_RST_N", + "MOTOR_2_DRIVER_IN2", + "", + "CP_POSITIVE_PEAK_RST", /* 10 */ + "CP_NEGATIVE_PEAK_RST"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio1 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pfuze3001: pmic@8 { + compatible = "fsl,pfuze3001"; + reg = <0x08>; + + regulators { + sw1_reg: sw1 { + regulator-name = "SW1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-name = "SW2"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + snvs_reg: vsnvs { + regulator-name = "VSNVS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-name = "VLDO1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-name = "VLDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-name = "VCCSD"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-name = "V33"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-name = "VLDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-name = "VLDO4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + onewire@18 { + compatible = "maxim,ds2484"; + reg = <0x18>; + }; + + accelerometer@19 { + compatible = "st,iis328dq", "st,h3lis331dl-accel"; + reg = <0x19>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accelerometer_int1_snvs>; + vdd-supply = <®_dcdc_3v3>; + vddio-supply = <®_dcdc_3v3>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_board_var + &pinctrl_digital_input + &pinctrl_digital_output + &pinctrl_gpio_motor + &pinctrl_hog_pins + &pinctrl_rotary_switch1 + &pinctrl_rotary_switch2>; + + pinctrl_adc_cp: adc-cpgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + >; + }; + + pinctrl_adc_motor: adc-motorgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_adc_pp: adc-ppgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0xb0 + >; + }; + + pinctrl_board_var: board-vargrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__GPIO4_IO15 0xb0 + MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0xb0 + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0xb0 + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0xb0 + >; + }; + + pinctrl_digital_input: digital-inputgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0xb0 + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0xb0 + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0xb0 + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0xb0 + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0xb0 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0xb0 + >; + }; + + pinctrl_digital_output: digital-outputgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x400000b0 + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x400000b0 + MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x400000b0 + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x400000b0 + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x400000b0 + MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x400000b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x10b0 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0xb0 + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xb0 + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x10b0 + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x10b0 + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x10b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x10b0 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x10b0 + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x10b0 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x10b0 + >; + }; + + pinctrl_emmc_rst: emmc-rstgrp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x400010b0 + >; + }; + + pinctrl_enet_mdio: enet-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x10b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x10b0 + >; + }; + + pinctrl_enet1_phy_int: enet1-phy-intgrp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x100b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x100b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x100b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0xb0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0xb0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0xb0 + >; + }; + + pinctrl_ext_uart: ext-uartgrp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0xb0 + MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0xb0 + >; + }; + + pinctrl_fan_enable: fan-enablegrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x400000b0 + >; + }; + + pinctrl_gpio_motor: gpio-motorgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x400000b0 + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x400000b0 + MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x400000b0 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0xb0 + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0xb0 + >; + }; + + pinctrl_hog_pins: hog-pinsgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x400000b0 + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x400000b0 + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x400070a0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x400000b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x400000b0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x400008b0 + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x400008b0 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x400008b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x400008b0 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x70b1 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0xb0 + >; + }; + + pinctrl_pwm_cp: pinctrl-pwm-cpgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x60a0 + >; + }; + + pinctrl_pwm_digital_input_ref: pwm-digital-input-refgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0xb0 + >; + }; + + pinctrl_pwm_fan: pwm-fangrp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x60a0 + >; + }; + + pinctrl_qca700x_cp_btld: qca700x-cp-btldgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x400000b0 + >; + }; + + pinctrl_qca700x_cp_int: qca700x-cp-intgrp { + fsl,pins = < + MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x10b0 + >; + }; + + pinctrl_qca700x_cp_rst: qca700x-cp-rstgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x400000b0 + >; + }; + + pinctrl_qca700x_mains_btld: qca700x-mains-btldgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x400000b0 + >; + }; + + pinctrl_rotary_switch1: rotary-switch1grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0xb0 + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0xb0 + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0xb0 + >; + }; + + pinctrl_rotary_switch2: rotary-switch2grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0xb0 + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0xb0 + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0xb0 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0xb0 + >; + }; + + pinctrl_rs485_1: rs485-1grp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0xb0 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0xb0 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0xb0 + >; + }; + + pinctrl_rs485_2: rs485-2grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x10b0 + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x10b0 + >; + }; + + pinctrl_status_leds: status-ledsgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0xb0 + MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0xb0 + MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0xb0 + >; + }; + + pinctrl_stm32: stm32grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x10b0 + MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x10b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0xb0 + MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0xb0 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x70b0 + MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x70b0 + >; + }; + + pinctrl_usb_pwr: usb-pwrgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0xb0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x7071 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x7071 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x7071 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x7071 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x7071 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x7071 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x7071 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x7071 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x7071 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x7071 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70b1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70b1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70b1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70b1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70b1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70b1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70b1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70b1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70b1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70b1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x70f1 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x70f1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x70f1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x70f1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x70f1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x70f1 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x70f1 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x70f1 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x70f1 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x70f1 + >; + }; + + pinctrl_wdog2: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x10b0 + >; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_cp_peak_snvs + &pinctrl_gpio_motor_snvs + &pinctrl_relay_sense_snvs + &pinctrl_rotary_switch1_snvs>; + + pinctrl_accelerometer_int1_snvs: accelerometer-int1-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x130a0 + >; + }; + + pinctrl_cp_peak_snvs: cp-peak-snvsgrp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x130a0 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 + >; + }; + + pinctrl_enet1_phy_rst: enet1-phy-rstgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x100a0 + >; + }; + + pinctrl_fan_sense_snvs: fan-sense-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x100a0 + >; + }; + + pinctrl_gpio_motor_snvs: gpio-motor-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 + >; + }; + + pinctrl_qca700x_mains_int: qca700x-mains-intgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x130a0 + >; + }; + + pinctrl_qca700x_mains_rst: qca700x-mains-rstgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x400100a0 + >; + }; + + pinctrl_relay_sense_snvs: relay-sense-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x100a0 + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x100a0 + >; + }; + + pinctrl_rotary_switch1_snvs: rotary-switch1-snvsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x110a0 + >; + }; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_digital_input_ref>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_cp>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rs485_1>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + fsl,dte-mode; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rs485_2>; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stm32>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ext_uart>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb + &pinctrl_usb_pwr>; + dr_mode = "host"; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-cal-45-dn-ohms = <35>; + fsl,tx-cal-45-dp-ohms = <35>; +}; + +&usbphy2 { + fsl,tx-cal-45-dn-ohms = <35>; + fsl,tx-cal-45-dp-ohms = <35>; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <&sw2_reg>; + vqmmc-supply = <®_1v8>; + mmc-pwrseq = <&emmc_pwrseq>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog2>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-master.dts b/arch/arm/boot/dts/imx6ull-tarragon-master.dts new file mode 100644 index 000000000000..67007ce383e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-master.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Master"; + compatible = "chargebyte,imx6ull-tarragon-master", "fsl,imx6ull"; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_sense_snvs>; + fan-supply = <®_fan>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + + reg_fan: regulator { + compatible = "regulator-fixed"; + regulator-name = "fan-supply"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_enable>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&ecspi4 { + status = "okay"; + + qca700x_mains: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_mains_int + &pinctrl_qca700x_mains_rst + &pinctrl_qca700x_mains_btld>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_fan>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-micro.dts b/arch/arm/boot/dts/imx6ull-tarragon-micro.dts new file mode 100644 index 000000000000..e471c2005bee --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-micro.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Micro"; + compatible = "chargebyte,imx6ull-tarragon-micro", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slave.dts b/arch/arm/boot/dts/imx6ull-tarragon-slave.dts new file mode 100644 index 000000000000..cee223b5f8e1 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-slave.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon Slave"; + compatible = "chargebyte,imx6ull-tarragon-slave", "fsl,imx6ull"; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts b/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts new file mode 100644 index 000000000000..7fd53b7a4372 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-tarragon-slavext.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +// +// Copyright (C) 2023 chargebyte GmbH + +#include "imx6ull-tarragon-common.dtsi" + +/ { + model = "chargebyte Tarragon SlaveXT"; + compatible = "chargebyte,imx6ull-tarragon-slavext", "fsl,imx6ull"; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pwms = <&pwm7 0 40000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_sense_snvs>; + fan-supply = <®_fan>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; + + reg_fan: regulator { + compatible = "regulator-fixed"; + regulator-name = "fan-supply"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fan_enable>; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +&ecspi2 { + status = "okay"; + + qca700x_cp: ethernet@0 { + reg = <0x0>; + compatible = "qca,qca7000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qca700x_cp_int + &pinctrl_qca700x_cp_rst + &pinctrl_qca700x_cp_btld>; + interrupt-parent = <&gpio2>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + spi-cpha; + spi-cpol; + spi-max-frequency = <16000000>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_fan>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; From 27cc508d61d8b7a44b7b79450e2df9cf13dbe616 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 4 Apr 2023 10:02:43 +0200 Subject: [PATCH 0886/1040] ARM: imx_v6_v7_defconfig: Enable Tarragon peripheral drivers We need to enable some drivers in order to use the following peripherals of Tarragon: * QCA7000/7005 Powerline chip * One-Wire Master DS2484 with external thermal sensors * external 4 pin PWM fan * ST IIS328DQ I2C accelerometer Signed-off-by: Stefan Wahren Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v6_v7_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 9475839e7fe1..2e2af31eeb4c 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -128,6 +128,7 @@ CONFIG_CS89x0_PLATFORM=y # CONFIG_NET_VENDOR_MICREL is not set # CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_QCA7000_SPI=m # CONFIG_NET_VENDOR_SEEQ is not set CONFIG_SMC91X=y CONFIG_SMC911X=y @@ -216,6 +217,9 @@ CONFIG_GPIO_PCF857X=y CONFIG_GPIO_BD71815=y CONFIG_GPIO_STMPE=y CONFIG_GPIO_74X164=y +CONFIG_W1=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_SLAVE_THERM=m CONFIG_POWER_RESET=y CONFIG_POWER_RESET_SYSCON=y CONFIG_POWER_RESET_SYSCON_POWEROFF=y @@ -224,6 +228,7 @@ CONFIG_RN5T618_POWER=m CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_SY7636A=y CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -409,6 +414,7 @@ CONFIG_CLK_IMX8MQ=y CONFIG_SOC_IMX8M=y CONFIG_EXTCON_USB_GPIO=y CONFIG_IIO=y +CONFIG_IIO_ST_ACCEL_3AXIS=m CONFIG_MMA8452=y CONFIG_IMX7D_ADC=y CONFIG_RN5T618_ADC=y From c8c96afa6e7ab025c345b84be2c9d65eb87d86e0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Apr 2023 18:52:12 +0200 Subject: [PATCH 0887/1040] arm64: dts: imx8mm: Add display pipeline components Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Mini. This makes the DSI display pipeline available on this SoC. Reviewed-by: Alexander Stein Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index a9552867e547..ba06b5273b91 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1119,6 +1119,61 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + csi: csi@32e20000 { compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; reg = <0x32e20000 0x1000>; From d825fb6455d5c5f8689e1b54f5c03a1aac094608 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Apr 2023 18:52:13 +0200 Subject: [PATCH 0888/1040] arm64: dts: imx8mn: Add display pipeline components Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Nano. This makes the DSI display pipeline available on this SoC. Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index ed9ac6c5047c..6f1101b7e2fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1057,6 +1057,61 @@ #size-cells = <1>; ranges; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi@32e10000 { + compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <266000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = ; + power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; From eda09fe149df41a0493137df946834133a87330d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Apr 2023 18:52:14 +0200 Subject: [PATCH 0889/1040] arm64: dts: imx8mp: Add display pipeline components Add LCDIF scanout engine and DSIM bridge nodes for i.MX8M Plus. This makes the DSI display pipeline available on this SoC. Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 55 +++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 8b4a3397b417..7879bbedd01b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1174,6 +1174,61 @@ #size-cells = <1>; ranges; + mipi_dsi: dsi@32e60000 { + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x400>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <200000000>, <24000000>; + samsung,pll-clock-frequency = <24000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsim_from_lcdif1: endpoint { + remote-endpoint = <&lcdif1_to_dsim>; + }; + }; + }; + }; + + lcdif1: display-controller@32e80000 { + compatible = "fsl,imx8mp-lcdif"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; + status = "disabled"; + + port { + lcdif1_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif1>; + }; + }; + }; + lcdif2: display-controller@32e90000 { compatible = "fsl,imx8mp-lcdif"; reg = <0x32e90000 0x238>; From 14079448cccc2fb8e2709d5ea194bd5e6a11ded9 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Mar 2023 14:56:04 -0500 Subject: [PATCH 0890/1040] ARM: dts: qcom: sdx65: add IPA information Add IPA-related nodes and definitions to "sdx65.dtsi". The SMP2P nodes (ipa_smp2p_out and ipa_smp2p_in) are already present. Enable IPA in "sdx65-mtp.dts"; this GSI firmware is loaded by Trust Zone on this platform. Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Tested-by: Rohit Agarwal Signed-off-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327195605.2854123-2-elder@linaro.org --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 ++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 39 ++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index ed98c83c141f..72e25de0db5f 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -245,6 +245,11 @@ status = "okay"; }; +&ipa { + qcom,gsi-loader = "skip"; + status = "okay"; +}; + &qpic_bam { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 192f9f94bc8b..74671cc12c88 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -299,6 +300,44 @@ #hwlock-cells = <1>; }; + ipa: ipa@3f40000 { + compatible = "qcom,sdx65-ipa"; + + reg = <0x03f40000 0x10000>, + <0x03f50000 0x5000>, + <0x03e04000 0xfc000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + iommus = <&apps_smmu 0x5e0 0x0>, + <&apps_smmu 0x5e2 0x0>; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; + interconnect-names = "memory", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From 280ecc191281892bf33ed6bfdea46b4c27ce582c Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Mar 2023 14:56:05 -0500 Subject: [PATCH 0891/1040] ARM: dts: qcom: sdx65: move status properties to end of nodes Move a few device tree "status" properties so that they are the last specified property, in "qcom-sdx65-mtp.dts" and "qcom-sdx65.dtsi". Note that properties must always be specified before sub-nodes. Reviewed-by: Konrad Dybcio Suggested-by: Konrad Dybcio Signed-off-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230327195605.2854123-3-elder@linaro.org --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 6 +++--- arch/arm/boot/dts/qcom-sdx65.dtsi | 8 +++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 72e25de0db5f..57bc3b03d3aa 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -270,8 +270,8 @@ }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + status = "okay"; }; &usb { @@ -283,14 +283,14 @@ }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4b_0p88>; vdda33-supply = <&vreg_l10b_3p08>; vdda18-supply = <&vreg_l5b_1p8>; + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4b_0p88>; vdda-pll-supply = <&vreg_l1b_1p2>; + status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 74671cc12c88..525dd8a1f664 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -224,16 +224,15 @@ "qcom,usb-snps-hs-7nm-phy"; reg = <0xff4000 0x120>; #phy-cells = <0>; - status = "disabled"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "ref"; resets = <&gcc GCC_QUSB2PHY_BCR>; + status = "disabled"; }; usb_qmpphy: phy@ff6000 { compatible = "qcom,sdx65-qmp-usb3-uni-phy"; reg = <0x00ff6000 0x1c8>; - status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -247,6 +246,8 @@ <&gcc GCC_USB3_PHY_BCR>; reset-names = "phy", "common"; + status = "disabled"; + usb_ssphy: phy@ff6200 { reg = <0x00ff6e00 0x160>, <0x00ff7000 0x1ec>, @@ -394,7 +395,6 @@ usb: usb@a6f8800 { compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; reg = <0x0a6f8800 0x400>; - status = "disabled"; #address-cells = <1>; #size-cells = <1>; ranges; @@ -424,6 +424,8 @@ resets = <&gcc GCC_USB30_BCR>; + status = "disabled"; + usb_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; From f77256439ccb794ec02eb07dfc6f1f96972a8cff Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Apr 2023 08:09:02 +0200 Subject: [PATCH 0892/1040] arm64: dts: qcom: sc8280xp: label the Soundwire nodes Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405060906.143058-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 4c75da1bac2d..071b2f226695 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2515,7 +2515,6 @@ status = "disabled"; }; - /* RX */ swr1: soundwire-controller@3210000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03210000 0 0x2000>; @@ -2590,13 +2589,13 @@ status = "disabled"; }; - /* WSA */ swr0: soundwire-controller@3250000 { reg = <0 0x03250000 0 0x2000>; compatible = "qcom,soundwire-v1.6.0"; interrupts = ; clocks = <&wsamacro>; clock-names = "iface"; + label = "WSA"; qcom,din-ports = <2>; qcom,dout-ports = <6>; @@ -2618,7 +2617,6 @@ status = "disabled"; }; - /* TX */ swr2: soundwire-controller@3330000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03330000 0 0x2000>; From add214009d0632bf3f28158f81e4d202d8c9aa0e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Apr 2023 08:09:03 +0200 Subject: [PATCH 0893/1040] arm64: dts: qcom: sm8450: label the Soundwire nodes Use labels, instead of comments, for Soundwire controllers. Naming them is useful, because they are specialized and have also naming in datasheet/programming guide. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405060906.143058-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index c59a922ce9f8..f0589cfe7560 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2135,13 +2135,13 @@ #sound-dai-cells = <1>; }; - /* WSA2 */ swr4: soundwire-controller@31f0000 { compatible = "qcom,soundwire-v1.7.0"; reg = <0 0x031f0000 0 0x2000>; interrupts = ; clocks = <&wsa2macro>; clock-names = "iface"; + label = "WSA2"; qcom,din-ports = <2>; qcom,dout-ports = <6>; @@ -2250,13 +2250,13 @@ #sound-dai-cells = <1>; }; - /* WSA */ swr0: soundwire-controller@3250000 { compatible = "qcom,soundwire-v1.7.0"; reg = <0 0x03250000 0 0x2000>; interrupts = ; clocks = <&wsamacro>; clock-names = "iface"; + label = "WSA"; qcom,din-ports = <2>; qcom,dout-ports = <6>; From 465b99f3b4ca55f25124adff6d6ccac4371f1930 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Apr 2023 08:09:04 +0200 Subject: [PATCH 0894/1040] arm64: dts: qcom: sc8280xp: simplify interrupts-extended The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405060906.143058-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 071b2f226695..9fb0c7bcbfdf 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2620,8 +2620,8 @@ swr2: soundwire-controller@3330000 { compatible = "qcom,soundwire-v1.6.0"; reg = <0 0x03330000 0 0x2000>; - interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "core", "wakeup"; clocks = <&txmacro>; From 563065020d9ae67999f3f3f3a6ec3508e17a4d88 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Apr 2023 08:09:05 +0200 Subject: [PATCH 0895/1040] arm64: dts: qcom: sm8250: simplify interrupts-extended The parent controller for the interrupt is GIC, so no need for interrupts-extended. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405060906.143058-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4e7875f8786f..fe569b07efe3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2367,7 +2367,7 @@ swr2: soundwire-controller@3230000 { reg = <0 0x03230000 0 0x2000>; compatible = "qcom,soundwire-v1.5.1"; - interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; interrupt-names = "core"; status = "disabled"; From d6573b4c202e75edd8b7ffbef6496613a1ef89df Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Apr 2023 08:09:06 +0200 Subject: [PATCH 0896/1040] arm64: dts: qcom: sm8450: simplify interrupts-extended The parent controller for both interrupts is GIC, so no need for interrupts-extended. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405060906.143058-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f0589cfe7560..eebad05cd941 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2280,8 +2280,8 @@ swr2: soundwire-controller@33b0000 { compatible = "qcom,soundwire-v1.7.0"; reg = <0 0x033b0000 0 0x2000>; - interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupts = , + ; interrupt-names = "core", "wakeup"; clocks = <&vamacro>; From 6340b391e15094575911ab0d96bfff09deadafba Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 8 Mar 2023 13:26:48 +0530 Subject: [PATCH 0897/1040] arm64: dts: qcom: Remove "iommus" property from PCIe nodes Currently, most of the Qualcomm SoCs specify both "iommus" and "iommu-map" properties for the PCIe nodes. First one passes the SMR mask to the iommu driver and the latter specifies the SID for each PCIe device. But with "iommus" property, the PCIe controller will be added to the iommu group along with the devices. This makes no sense because the controller will not initiate any DMA transaction on its own. And moreover, it is not strictly required to pass the SMR mask to the iommu driver. If the "iommus" property is not present, then the default mask of "0" would be used which should work for all PCIe devices. On the other side, if the SMR mask specified doesn't match the one expected by the hypervisor, then all the PCIe transactions will end up triggering "Unidentified Stream Fault" by the SMMU. So to get rid of these hassles and also prohibit PCIe controllers from adding to the iommu group, let's remove the "iommus" property from PCIe nodes. Reported-by: Rob Herring Link: https://lore.kernel.org/linux-arm-msm/20230227195535.GA749409-robh@kernel.org Signed-off-by: Manivannan Sadhasivam Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308075648.134119-1-manivannan.sadhasivam@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 -- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 -- 7 files changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0cdb16316021..f4003e0f8fac 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2140,8 +2140,6 @@ dma-coherent; - iommus = <&apps_smmu 0x1c80 0x1>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index da4b200281d8..e35add9f3299 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2329,7 +2329,6 @@ "slave_q2a", "tbu"; - iommus = <&apps_smmu 0x1c10 0xf>; iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, <0x100 &apps_smmu 0x1c11 0x1>, <0x200 &apps_smmu 0x1c12 0x1>, @@ -2440,7 +2439,6 @@ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommus = <&apps_smmu 0x1c00 0xf>; iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, <0x100 &apps_smmu 0x1c01 0x1>, <0x200 &apps_smmu 0x1c02 0x1>, diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c9c04ac9bfcd..72e4ae0b6aa7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1848,7 +1848,6 @@ "slave_q2a", "tbu"; - iommus = <&apps_smmu 0x1d80 0x3f>; iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, <0x100 &apps_smmu 0x1d81 0x1>; @@ -1947,7 +1946,6 @@ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommus = <&apps_smmu 0x1e00 0x3f>; iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, <0x100 &apps_smmu 0x1e01 0x1>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index fe569b07efe3..bde8bdd2e811 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1877,7 +1877,6 @@ "tbu", "ddrss_sf_tbu"; - iommus = <&apps_smmu 0x1c00 0x7f>; iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, <0x100 &apps_smmu 0x1c01 0x1>; @@ -1984,7 +1983,6 @@ assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; assigned-clock-rates = <19200000>; - iommus = <&apps_smmu 0x1c80 0x7f>; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; @@ -2093,7 +2091,6 @@ assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; assigned-clock-rates = <19200000>; - iommus = <&apps_smmu 0x1d00 0x7f>; iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, <0x100 &apps_smmu 0x1d01 0x1>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 8985a59602f9..ebcb481571c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1532,7 +1532,6 @@ "aggre1", "aggre0"; - iommus = <&apps_smmu 0x1c00 0x7f>; iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, <0x100 &apps_smmu 0x1c01 0x1>; @@ -1616,7 +1615,6 @@ "ddrss_sf_tbu", "aggre1"; - iommus = <&apps_smmu 0x1c80 0x7f>; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index eebad05cd941..0bd205a11f2b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1786,7 +1786,6 @@ "aggre0", "aggre1"; - iommus = <&apps_smmu 0x1c00 0x7f>; iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, <0x100 &apps_smmu 0x1c01 0x1>; @@ -1899,7 +1898,6 @@ "ddrss_sf_tbu", "aggre1"; - iommus = <&apps_smmu 0x1c80 0x7f>; iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 7a1994bf4086..68a60eadd03f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1698,7 +1698,6 @@ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommus = <&apps_smmu 0x1400 0x7f>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; @@ -1795,7 +1794,6 @@ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - iommus = <&apps_smmu 0x1480 0x7f>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>; From a10e2244f49a838e2274672dfeb4ab1bc9349230 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Mar 2023 14:49:25 +0100 Subject: [PATCH 0898/1040] arm64: dts: qcom: sm8550: add ADSP audio codec macros Add the Low Power Audio SubSystem (LPASS) / ADSP audio codec macros on Qualcomm SM8550. The nodes are very similar to SM8450, except missing NPL clock which is not exposed on SM8550 and should not be touched. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230310134925.514125-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 195 +++++++++++++++++++++++++++ 1 file changed, 195 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 68a60eadd03f..70ace9f151a8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1984,6 +1984,97 @@ }; }; + lpass_wsa2macro: codec@6aa0000 { + compatible = "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06aa0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&wsa2_swr_active>; + #sound-dai-cells = <1>; + }; + + lpass_rxmacro: codec@6ac0000 { + compatible = "qcom,sm8550-lpass-rx-macro"; + reg = <0 0x06ac0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", "macro", "dcodec", "fsgen"; + + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&rx_swr_active>; + #sound-dai-cells = <1>; + }; + + lpass_txmacro: codec@6ae0000 { + compatible = "qcom,sm8550-lpass-tx-macro"; + reg = <0 0x06ae0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&tx_swr_active>; + #sound-dai-cells = <1>; + }; + + lpass_wsamacro: codec@6b00000 { + compatible = "qcom,sm8550-lpass-wsa-macro"; + reg = <0 0x06b00000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_vamacro>; + clock-names = "mclk", "macro", "dcodec", "fsgen"; + + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&wsa_swr_active>; + #sound-dai-cells = <1>; + }; + + lpass_vamacro: codec@6d44000 { + compatible = "qcom,sm8550-lpass-va-macro"; + reg = <0 0x06d44000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec"; + + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + lpass_tlmm: pinctrl@6e80000 { compatible = "qcom,sm8550-lpass-lpi-pinctrl"; reg = <0 0x06e80000 0 0x20000>, @@ -1995,6 +2086,110 @@ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; clock-names = "core", "audio"; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio7"; + function = "dmic1_data"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic02_default: dmic02-default-state { + clk-pins { + pins = "gpio8"; + function = "dmic2_clk"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio9"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; }; lpass_lpiaon_noc: interconnect@7400000 { From d0367098dc1e925d22a6706e358636d12371116c Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 20 Mar 2023 16:15:30 +0530 Subject: [PATCH 0899/1040] arm64: dts: qcom: ipq5332: add few device nodes Add the nodes for QUP peripheral, PRNG and WDOG. While at it, enable the I2C device for MI01.2 board. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230320104530.30411-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 14 +++++ arch/arm64/boot/dts/qcom/ipq5332.dtsi | 67 +++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts index 702013b867d7..3af1d5556950 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts @@ -28,6 +28,13 @@ status = "okay"; }; +&blsp1_i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c_1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &sdhc { bus-width = <4>; max-frequency = <192000000>; @@ -50,6 +57,13 @@ /* PINCTRL */ &tlmm { + i2c_1_pins: i2c-1-state { + pins = "gpio29", "gpio30"; + function = "blsp1_i2c0"; + drive-strength = <8>; + bias-pull-up; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio13"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 04ef80f267bf..12e0e179e139 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -134,6 +134,13 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; + rng: rng@e3000 { + compatible = "qcom,prng-ee"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; @@ -191,6 +198,16 @@ status = "disabled"; }; + blsp_dma: dma-controller@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x1d000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + blsp1_uart0: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x078af000 0x200>; @@ -201,6 +218,48 @@ status = "disabled"; }; + blsp1_spi0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b5000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_i2c1: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b6000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + blsp1_spi2: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ @@ -233,6 +292,14 @@ }; }; + watchdog: watchdog@b017000 { + compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; + reg = <0x0b017000 0x1000>; + interrupts = ; + clocks = <&sleep_clk>; + timeout-sec = <30>; + }; + apcs_glb: mailbox@b111000 { compatible = "qcom,ipq5332-apcs-apps-global", "qcom,ipq6018-apcs-apps-global"; From 5808c532ca0a983d643319caca44f2bcb148298f Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 20 Mar 2023 07:43:42 -0700 Subject: [PATCH 0900/1040] soc: qcom: smd-rpm: Use GFP_ATOMIC in write path Preparing for better lockdep annotations for things that happen in runpm suspend/resume path vs shrinker/reclaim in the following patches, we need to avoid allocations that can trigger reclaim in the icc_set_bw() path. In the RPMh case, rpmh_write_batch() already uses GFP_ATOMIC, so it should be reasonable to use in the smd-rpm case as well. Alternatively, 256bytes is small enough for a function that isn't called recursively to allocate on-stack. Signed-off-by: Rob Clark Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230320144356.803762-21-robdclark@gmail.com --- drivers/soc/qcom/smd-rpm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 523627d5d398..0c1aa809cc4e 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -113,7 +113,7 @@ int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, if (WARN_ON(size >= 256)) return -EINVAL; - pkt = kmalloc(size, GFP_KERNEL); + pkt = kmalloc(size, GFP_ATOMIC); if (!pkt) return -ENOMEM; From 49f1d0b65f87692a11386a8b8cd3a4aa3a1d0daa Mon Sep 17 00:00:00 2001 From: Roan van Dijk Date: Thu, 30 Mar 2023 11:16:13 +0200 Subject: [PATCH 0901/1040] ARM: stm32: add initial documentation for STM32MP151 This patch adds initial documentation of STM32MP151 microprocessor (MPU) based on Arm Cortex-A7. Signed-off-by: Roan van Dijk Signed-off-by: Alexandre Torgue --- Documentation/arm/index.rst | 1 + .../arm/stm32/stm32mp151-overview.rst | 36 +++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 Documentation/arm/stm32/stm32mp151-overview.rst diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index ae42fe886f0d..056ac11372af 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -58,6 +58,7 @@ SoC-specific documents stm32/stm32f769-overview stm32/stm32f429-overview stm32/stm32mp13-overview + stm32/stm32mp151-overview stm32/stm32mp157-overview stm32/stm32-dma-mdma-chaining diff --git a/Documentation/arm/stm32/stm32mp151-overview.rst b/Documentation/arm/stm32/stm32mp151-overview.rst new file mode 100644 index 000000000000..f42a2ac309c0 --- /dev/null +++ b/Documentation/arm/stm32/stm32mp151-overview.rst @@ -0,0 +1,36 @@ +=================== +STM32MP151 Overview +=================== + +Introduction +------------ + +The STM32MP151 is a Cortex-A MPU aimed at various applications. +It features: + +- Single Cortex-A7 application core +- Standard memories interface support +- Standard connectivity, widely inherited from the STM32 MCU family +- Comprehensive security support + +More details: + +- Cortex-A7 core running up to @800MHz +- FMC controller to connect SDRAM, NOR and NAND memories +- QSPI +- SD/MMC/SDIO support +- Ethernet controller +- ADC/DAC +- USB EHCI/OHCI controllers +- USB OTG +- I2C, SPI busses support +- Several general purpose timers +- Serial Audio interface +- LCD-TFT controller +- DCMIPP +- SPDIFRX +- DFSDM + +:Authors: + +- Roan van Dijk From 22a9554e548424a15b744273d4509c884c9f14b1 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 19 Feb 2023 13:14:18 +0100 Subject: [PATCH 0902/1040] arm64: dts: marvell: mochabin: enlarge PCI memory window Armada 7040 uses a rather small 15MB memory window for every PCI adapter, however this is not sufficient for Qualcomm QCA6390 802.11ax cards that are shipped along with the OpenWrt WLAN model of MOCHAbin as ath11k requires at least 16MB of memory. So, similar to what MACCHIATOBin has been doing for years, lets move to using the second PCIe 2 memory window and expand it to 128MB to make it future proof. Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index 7ca71f2d7afb..39ce6e25a8ef 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -455,4 +455,5 @@ phys = <&cp0_comphy5 2>; phy-names = "cp0-pcie2-x1-phy"; reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>; + ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x8000000>; }; From 4b6a412ee561ce8d530b6a0dfcf05d2ae7691fd9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 21:13:13 +0100 Subject: [PATCH 0903/1040] arm64: dts: marvell: align thermal node names with bindings Bindings expect thermal node names to end with '-thermal': armada-8040-db.dtb: thermal-zones: 'ap-thermal-cpu0', ... do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 10 +++++----- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 4e6d29ad32eb..2c920e22cec2 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -317,7 +317,7 @@ * first one that will have a critical trip point will be chosen. */ thermal-zones { - ap_thermal_ic: ap-thermal-ic { + ap_thermal_ic: ap-ic-thermal { polling-delay-passive = <0>; /* Interrupt driven */ polling-delay = <0>; /* Interrupt driven */ @@ -334,7 +334,7 @@ cooling-maps { }; }; - ap_thermal_cpu0: ap-thermal-cpu0 { + ap_thermal_cpu0: ap-cpu0-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -367,7 +367,7 @@ }; }; - ap_thermal_cpu1: ap-thermal-cpu1 { + ap_thermal_cpu1: ap-cpu1-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -400,7 +400,7 @@ }; }; - ap_thermal_cpu2: ap-thermal-cpu2 { + ap_thermal_cpu2: ap-cpu2-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; @@ -433,7 +433,7 @@ }; }; - ap_thermal_cpu3: ap-thermal-cpu3 { + ap_thermal_cpu3: ap-cpu3-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 7d0043824f2a..0cc9ee9871e7 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -25,7 +25,7 @@ * The cooling maps are empty as there are no cooling devices. */ thermal-zones { - CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) { + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) { polling-delay-passive = <0>; /* Interrupt driven */ polling-delay = <0>; /* Interrupt driven */ From 6d5a6740f6df4c41a96d57d542207a7d5cab0393 Mon Sep 17 00:00:00 2001 From: Enrico Mioso Date: Thu, 2 Feb 2023 10:37:06 +0100 Subject: [PATCH 0904/1040] arm64: dts: marvell: add DTS for GL.iNet GL-MV1000 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The GL-MV1000 (Brume) is a small form-factor gateway router. It is based on the Marvell Armada 88F3720 SOC (1GHz), has 3 gigabit ethernet ports, 1 GB RAM, 16M SPI flash, 8GB eMMC and an uSD slot, as well as an USB 2.0 type A and an USB 3.0 type C port. Signed-off-by: Enrico Mioso CC: Pali Reviewed-by: Pali Rohár Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../dts/marvell/armada-3720-gl-mv1000.dts | 239 ++++++++++++++++++ 2 files changed, 240 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index 058237681fe5..79ac09b58a89 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-emmc.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-ultra.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-gl-mv1000.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts new file mode 100644 index 000000000000..b1b45b4fa9d4 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) + +/dts-v1/; +#include +#include +#include "armada-372x.dtsi" + +/ { + model = "GL.iNet GL-MV1000"; + compatible = "glinet,gl-mv1000", "marvell,armada3720"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + + vcc_sd_reg1: regulator { + compatible = "regulator-gpio"; + regulator-name = "vcc_sd1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + gpios-states = <0>; + states = <1800000 0x1 + 3300000 0x0>; + enable-active-high; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&gpionb 14 GPIO_ACTIVE_LOW>; + }; + + switch { + label = "switch"; + linux,code = ; + gpios = <&gpiosb 22 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + vpn { + label = "green:vpn"; + gpios = <&gpionb 11 GPIO_ACTIVE_LOW>; + }; + + wan { + label = "green:wan"; + gpios = <&gpionb 12 GPIO_ACTIVE_LOW>; + }; + + led_power: power { + label = "green:power"; + gpios = <&gpionb 13 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +&spi0 { + status = "okay"; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <104000000>; + m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "firmware"; + reg = <0 0xf0000>; + }; + + partition@f0000 { + label = "u-boot-env"; + reg = <0xf0000 0x8000>; + }; + + factory: partition@f8000 { + label = "factory"; + reg = <0xf8000 0x8000>; + read-only; + }; + + partition@100000 { + label = "dtb"; + reg = <0x100000 0x10000>; + read-only; + }; + + partition@110000 { + label = "rescue"; + reg = <0x110000 0x1000000>; + }; + }; + }; +}; + +&sdhci1 { + wp-inverted; + bus-width = <4>; + cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>; + marvell,pad-type = "sd"; + no-1-8-v; + vqmmc-supply = <&vcc_sd_reg1>; + status = "okay"; +}; + +&sdhci0 { + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; + non-removable; + no-sd; + no-sdio; + marvell,pad-type = "fixed-1-8v"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&mdio { + switch0: switch0@1 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dsa,member = <0 0>; + + ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <ð0>; + }; + + port@1 { + reg = <1>; + label = "wan"; + phy-handle = <&switch0phy0>; + }; + + port@2 { + reg = <2>; + label = "lan0"; + phy-handle = <&switch0phy1>; + + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + phy-handle = <&switch0phy2>; + + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch0phy0: switch0phy0@11 { + reg = <0x11>; + }; + switch0phy1: switch0phy1@12 { + reg = <0x12>; + }; + switch0phy2: switch0phy2@13 { + reg = <0x13>; + }; + }; + }; +}; + +ð0 { + nvmem-cells = <&macaddr_factory_0>; + nvmem-cell-names = "mac-address"; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_factory_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; From 8aea8659a5f3ae8dc63c9f632ce1f676a1483556 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 7 Apr 2023 17:17:20 +0200 Subject: [PATCH 0905/1040] ARM: dts: kirkwood: Add missing phy-mode and fixed links The DSA framework has got more picky about always having a phy-mode for the CPU port. The Kirkwood Ethernet is an RGMII port. Set the switch to impose the RGMII delays. Additionally, the cpu label has never actually been used in the binding, so remove it. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-dir665.dts | 3 ++- arch/arm/boot/dts/kirkwood-l-50.dts | 2 +- arch/arm/boot/dts/kirkwood-linksys-viper.dts | 3 ++- arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts | 3 ++- arch/arm/boot/dts/kirkwood-rd88f6281.dtsi | 2 +- 5 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts index f9f4b0143ba8..0c0851cd9bec 100644 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -232,7 +232,7 @@ port@6 { reg = <6>; - label = "cpu"; + phy-mode = "rgmii-id"; ethernet = <ð0port>; fixed-link { speed = <1000>; @@ -251,6 +251,7 @@ ethernet0-port@0 { speed = <1000>; duplex = <1>; + phy-mode = "rgmii"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-l-50.dts b/arch/arm/boot/dts/kirkwood-l-50.dts index 60c1e94f5dd3..9fd3581bb24b 100644 --- a/arch/arm/boot/dts/kirkwood-l-50.dts +++ b/arch/arm/boot/dts/kirkwood-l-50.dts @@ -254,7 +254,6 @@ port@6 { reg = <6>; - label = "cpu"; phy-mode = "rgmii-id"; ethernet = <ð1port>; fixed-link { @@ -330,6 +329,7 @@ ethernet1-port@0 { speed = <1000>; duplex = <1>; + phy-mode = "rgmii"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts index 2f9660f3b457..27fd6e2337d5 100644 --- a/arch/arm/boot/dts/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts @@ -198,7 +198,7 @@ port@5 { reg = <5>; - label = "cpu"; + phy-mode = "rgmii-id"; ethernet = <ð0port>; fixed-link { speed = <1000>; @@ -221,6 +221,7 @@ ethernet0-port@0 { speed = <1000>; duplex = <1>; + phy-mode = "rgmii"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index ced576acfb95..5a77286136c7 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -149,7 +149,7 @@ port@5 { reg = <5>; - label = "cpu"; + phy-mode = "rgmii-id"; ethernet = <ð0port>; fixed-link { speed = <1000>; @@ -166,6 +166,7 @@ ethernet0-port@0 { speed = <1000>; duplex = <1>; + phy-mode = "rgmii"; }; }; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index e21aa674945d..9d62f910cddf 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -105,7 +105,7 @@ port@5 { reg = <5>; - label = "cpu"; + phy-mode = "rgmii-id"; ethernet = <ð0port>; fixed-link { speed = <1000>; From e2e1bcb19b7522a582026460bf5d49fd2ac15e62 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 7 Apr 2023 17:17:21 +0200 Subject: [PATCH 0906/1040] ARM: dts: orion5: Add missing phy-mode and fixed links The DSA framework has got more picky about always having a phy-mode for the CPU port. The Orion5x Ethernet is an RGMII port. Set the switch to impose the RGMII delays. Additionally, the cpu label has never actually been used in the binding, so remove it. Lastly, add a fixed-link node indicating the expected speed/duplex of the link to the SoC. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts index 4f4888ec9138..fb203e7d37f5 100644 --- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts @@ -137,8 +137,12 @@ port@3 { reg = <3>; - label = "cpu"; ethernet = <ðport>; + phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; }; port@5 { @@ -208,6 +212,7 @@ /* Hardwired to DSA switch */ speed = <1000>; duplex = <1>; + phy-mode = "rgmii"; }; }; From 0939de7d89d2efc4f565ce1961b4020787e9f297 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 7 Apr 2023 17:17:22 +0200 Subject: [PATCH 0907/1040] ARM: dts: armada: Add missing phy-mode and fixed links The DSA framework has got more picky about always having a phy-mode for the CPU port. The Armada Ethernet supports RGMII, SGMII, 1000base-x and 2500Base-X. Set the switch phy-mode based on how the SoC Ethernet ports is been configured. For RGMII mode, have the switch add the delays. Additionally, the cpu label has never actually been used in the binding, so remove it. Lastly, add a fixed-link node indicating the expected speed/duplex of the link to the SoC. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-rd.dts | 2 +- arch/arm/boot/dts/armada-381-netgear-gs110emx.dts | 2 +- arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts | 7 ++++++- arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts | 7 ++++++- arch/arm/boot/dts/armada-385-linksys.dtsi | 2 +- arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 -- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 2 +- 7 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index be005c9f42ef..2fce8e794265 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -171,8 +171,8 @@ port@5 { reg = <5>; - label = "cpu"; ethernet = <ð1>; + phy-mode = "rgmii-id"; fixed-link { speed = <1000>; full-duplex; diff --git a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts index 095df5567c93..f4c4b213ef4e 100644 --- a/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts +++ b/arch/arm/boot/dts/armada-381-netgear-gs110emx.dts @@ -148,7 +148,7 @@ port@0 { ethernet = <ð0>; - label = "cpu"; + phy-mode = "rgmii"; reg = <0>; fixed-link { diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts index c9ac630e5874..1990f7d0cc79 100644 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts +++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-l8.dts @@ -68,8 +68,13 @@ port@10 { reg = <10>; - label = "cpu"; + phy-mode = "2500base-x"; + ethernet = <ð1>; + fixed-link { + speed = <2500>; + full-duplex; + }; }; }; diff --git a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts index fa653b379490..b795ad573891 100644 --- a/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts +++ b/arch/arm/boot/dts/armada-385-clearfog-gtr-s4.dts @@ -48,8 +48,13 @@ port@5 { reg = <5>; - label = "cpu"; + phy-mode = "2500base-x"; ethernet = <ð1>; + + fixed-link { + speed = <2500>; + full-duplex; + }; }; }; diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 85e8d966f6c1..fc8216fd9f60 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -195,7 +195,7 @@ port@5 { reg = <5>; - label = "cpu"; + phy-mode = "sgmii"; ethernet = <ð2>; fixed-link { diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 0c1f238e4c30..2d8d319bec83 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -479,7 +479,6 @@ ports@5 { reg = <5>; - label = "cpu"; ethernet = <ð1>; phy-mode = "rgmii-id"; @@ -491,7 +490,6 @@ ports@6 { reg = <6>; - label = "cpu"; ethernet = <ð0>; phy-mode = "rgmii-id"; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index dbe8dfe236fb..7a0614fd0c93 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -302,7 +302,7 @@ port@5 { reg = <5>; - label = "cpu"; + phy-mode = "rgmii-id"; ethernet = <ð0>; fixed-link { speed = <1000>; From 218669c662e3a38fdbd7e0ce56a20784da29546e Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Fri, 7 Apr 2023 17:18:39 +0200 Subject: [PATCH 0908/1040] ARM64: dts: marvell: cn9310: Add missing phy-mode The DSA framework has got more picky about always having a phy-mode for the CPU port. The SoC Ethernet is being configured to 10gbase-r. Set the switch phy-mode based on this. Additionally, the SoC Ethernet is using in-band signalling to determine the link speed, so add same parameter to the switch. Additionally, the cpu label has never actually been used in the binding, so remove it. Signed-off-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 8e4ec243fb8f..32cfb3e2efc3 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -282,8 +282,9 @@ port@a { reg = <10>; - label = "cpu"; ethernet = <&cp0_eth0>; + phy-mode = "10gbase-r"; + managed = "in-band-status"; }; }; From 88704a0cd71909c3107561261412a5d5beb23358 Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Thu, 6 Apr 2023 17:27:32 +0530 Subject: [PATCH 0909/1040] soc: qcom: rpmh-rsc: Support RSC v3 minor versions RSC v3 register offsets are same for all minor versions of v3. Fix a minor version check to pick correct offsets for all v3 minor versions. Fixes: 40482e4f7364 ("soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets") Signed-off-by: Tushar Nimkar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406115732.9293-1-quic_tnimkar@quicinc.com --- drivers/soc/qcom/rpmh-rsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 0f8b2249f889..f93544f6d796 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -1073,7 +1073,7 @@ static int rpmh_rsc_probe(struct platform_device *pdev) drv->ver.minor = rsc_id & (MINOR_VER_MASK << MINOR_VER_SHIFT); drv->ver.minor >>= MINOR_VER_SHIFT; - if (drv->ver.major == 3 && drv->ver.minor == 0) + if (drv->ver.major == 3 && drv->ver.minor >= 0) drv->regs = rpmh_rsc_reg_offset_ver_3_0; else drv->regs = rpmh_rsc_reg_offset_ver_2_7; From cb5d1dd3a74a7c7c3ad31d5fa2cc00e86c209dcc Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 30 Mar 2023 14:11:00 -0700 Subject: [PATCH 0910/1040] MAINTAINERS: qcom: Add reviewer for Qualcomm Chromebooks Developers on the ChromeOS team generally want to be notified to review changes that affect Chromebook device tree files. While we could individually add developers, the set of developers and the time each one has available to review patches will change over time. Let's try adding a group list as a reviewer and see if that's an effective way to manage things. A few notes: * Though this email address is actually backed by a mailing list, I'm adding it as "R"eviewer and not "L"ist since it's not a publicly readable mailing list and it's intended just to have a few people on it. This also hopefully conveys a little more responisbility for the people that are part of this group. * I've added all sc7180 and sc7280 files here. At the moment I'm not aware of any non-Chromebooks being supported that use these chips. If later something shows up then we can try to narrow down. * I've added "sdm845-cheza" to this list but not the rest of "sdm845". Cheza never shipped but some developers still find the old developer boards useful and thus it continues to get minimal maintenance. Most sdm845 device tree work, however, seems to be for non-Chromebooks. Cc: Stephen Boyd Cc: Matthias Kaehlcke Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230330141051.1.If8eb4f30cb53a00a5bef1b7d3cc645c3536615ec@changeid --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..b4e9c5bda234 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2604,6 +2604,12 @@ F: include/dt-bindings/*/qcom* F: include/linux/*/qcom* F: include/linux/soc/qcom/ +ARM/QUALCOMM CHROMEBOOK SUPPORT +R: cros-qcom-dts-watchers@chromium.org +F: arch/arm64/boot/dts/qcom/sc7180* +F: arch/arm64/boot/dts/qcom/sc7280* +F: arch/arm64/boot/dts/qcom/sdm845-cheza* + ARM/RDA MICRO ARCHITECTURE M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) From fe88480a6be92ecbf6f205ff3a7d7e5ded0562dd Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Tue, 31 Jan 2023 21:04:13 +0100 Subject: [PATCH 0911/1040] arm64: dts: qcom: msm8994-angler: Fix cont_splash_mem mapping Angler's cont_splash_mem mapping is shorter in downstream [1], therefore 380cd3a34b7f was wrong. Obviously also 0e5ded926f2a was wrong (workaround which fixed booting at the time). This fixes error: [ 0.000000] memory@3401000 (0x0000000003401000--0x0000000005601000) overlaps with tzapp@4800000 (0x0000000004800000--0x0000000006100000) [1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm64/boot/dts/huawei/huawei_msm8994_angler_row_vn1/huawei-fingerprint.dtsi#16 Fixes: 380cd3a34b7f ("arm64: dts: msm8994-angler: fix the memory map") Fixes: 0e5ded926f2a ("arm64: dts: qcom: msm8994-angler: Disable cont_splash_mem") Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230131200414.24373-2-pvorel@suse.cz --- arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 7b0f62144c3e..59b9ed78cf0c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -2,7 +2,7 @@ /* * Copyright (c) 2015, Huawei Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022, Petr Vorel + * Copyright (c) 2021-2023, Petr Vorel */ /dts-v1/; @@ -31,6 +31,11 @@ #size-cells = <2>; ranges; + cont_splash_mem: memory@3401000 { + reg = <0 0x03401000 0 0x1000000>; + no-map; + }; + tzapp_mem: tzapp@4800000 { reg = <0 0x04800000 0 0x1900000>; no-map; From c85c8a992794dfcd7cea7a41871710c27c5592a6 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Tue, 31 Jan 2023 21:04:14 +0100 Subject: [PATCH 0912/1040] arm64: dts: qcom: msm8994-angler: removed clash with smem_region This fixes memory overlap error: [ 0.000000] reserved@6300000 (0x0000000006300000--0x0000000007000000) overlaps with smem_region@6a00000 (0x0000000006a00000--0x0000000006c00000) smem_region is the same as in downstream (qcom,smem) [1], therefore split reserved memory into two sections on either side of smem_region. Not adding labels as it's not expected to be used. [1] https://android.googlesource.com/kernel/msm/+/refs/heads/android-msm-angler-3.10-marshmallow-mr1/arch/arm/boot/dts/qcom/msm8994.dtsi#948 Fixes: 380cd3a34b7f ("arm64: dts: msm8994-angler: fix the memory map") Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230131200414.24373-3-pvorel@suse.cz --- arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi | 5 ----- arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8994.dtsi | 5 +++++ 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index cd77dcb55872..b8f2a01bcb96 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -60,11 +60,6 @@ reg = <0x0 0x05000000 0x0 0x1a00000>; no-map; }; - - reserved@6c00000 { - reg = <0x0 0x06c00000 0x0 0x400000>; - no-map; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 59b9ed78cf0c..29e79ae0849d 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -41,8 +41,8 @@ no-map; }; - removed_region: reserved@6300000 { - reg = <0 0x06300000 0 0xD00000>; + reserved@6300000 { + reg = <0 0x06300000 0 0x700000>; no-map; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 768fe2326933..6d436d20350a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -228,6 +228,11 @@ reg = <0 0xc9400000 0 0x3f00000>; no-map; }; + + reserved@6c00000 { + reg = <0 0x06c00000 0 0x400000>; + no-map; + }; }; smd { From b065b23d3c3bc91f7e54f9bff4294a7bfbd2afb6 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 16 Mar 2023 12:59:35 +0530 Subject: [PATCH 0913/1040] dt-bindings: clock: Add ipq9574 clock and reset definitions Add clock and reset ID definitions for ipq9574 Reviewed-by: Krzysztof Kozlowski Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316072940.29137-2-quic_devipriy@quicinc.com --- .../bindings/clock/qcom,ipq9574-gcc.yaml | 61 +++++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 213 ++++++++++++++++++ include/dt-bindings/reset/qcom,ipq9574-gcc.h | 164 ++++++++++++++ 3 files changed, 438 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,ipq9574-gcc.h create mode 100644 include/dt-bindings/reset/qcom,ipq9574-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml new file mode 100644 index 000000000000..afc68eb9d7cc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9574 + +maintainers: + - Anusha Rao + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ9574 + + See also:: + include/dt-bindings/clock/qcom,ipq9574-gcc.h + include/dt-bindings/reset/qcom,ipq9574-gcc.h + +properties: + compatible: + const: qcom,ipq9574-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: Bias PLL ubi clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: USB3 PHY pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq9574-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&bias_pll_ubi_nc_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h new file mode 100644 index 000000000000..5a2961bfe893 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2023 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define GCC_SLEEP_CLK_SRC 6 +#define APSS_AHB_CLK_SRC 7 +#define APSS_AXI_CLK_SRC 8 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 15 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 16 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC 17 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC 18 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC 19 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC 20 +#define BLSP1_UART1_APPS_CLK_SRC 21 +#define BLSP1_UART2_APPS_CLK_SRC 22 +#define BLSP1_UART3_APPS_CLK_SRC 23 +#define BLSP1_UART4_APPS_CLK_SRC 24 +#define BLSP1_UART5_APPS_CLK_SRC 25 +#define BLSP1_UART6_APPS_CLK_SRC 26 +#define GCC_APSS_AHB_CLK 27 +#define GCC_APSS_AXI_CLK 28 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36 +#define GCC_BLSP1_QUP5_I2C_APPS_CLK 37 +#define GCC_BLSP1_QUP5_SPI_APPS_CLK 38 +#define GCC_BLSP1_QUP6_I2C_APPS_CLK 39 +#define GCC_BLSP1_QUP6_SPI_APPS_CLK 40 +#define GCC_BLSP1_UART1_APPS_CLK 41 +#define GCC_BLSP1_UART2_APPS_CLK 42 +#define GCC_BLSP1_UART3_APPS_CLK 43 +#define GCC_BLSP1_UART4_APPS_CLK 44 +#define GCC_BLSP1_UART5_APPS_CLK 45 +#define GCC_BLSP1_UART6_APPS_CLK 46 +#define PCIE0_AXI_M_CLK_SRC 47 +#define GCC_PCIE0_AXI_M_CLK 48 +#define PCIE1_AXI_M_CLK_SRC 49 +#define GCC_PCIE1_AXI_M_CLK 50 +#define PCIE2_AXI_M_CLK_SRC 51 +#define GCC_PCIE2_AXI_M_CLK 52 +#define PCIE3_AXI_M_CLK_SRC 53 +#define GCC_PCIE3_AXI_M_CLK 54 +#define PCIE0_AXI_S_CLK_SRC 55 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 56 +#define GCC_PCIE0_AXI_S_CLK 57 +#define PCIE1_AXI_S_CLK_SRC 58 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 59 +#define GCC_PCIE1_AXI_S_CLK 60 +#define PCIE2_AXI_S_CLK_SRC 61 +#define GCC_PCIE2_AXI_S_BRIDGE_CLK 62 +#define GCC_PCIE2_AXI_S_CLK 63 +#define PCIE3_AXI_S_CLK_SRC 64 +#define GCC_PCIE3_AXI_S_BRIDGE_CLK 65 +#define GCC_PCIE3_AXI_S_CLK 66 +#define PCIE0_PIPE_CLK_SRC 67 +#define PCIE1_PIPE_CLK_SRC 68 +#define PCIE2_PIPE_CLK_SRC 69 +#define PCIE3_PIPE_CLK_SRC 70 +#define PCIE_AUX_CLK_SRC 71 +#define GCC_PCIE0_AUX_CLK 72 +#define GCC_PCIE1_AUX_CLK 73 +#define GCC_PCIE2_AUX_CLK 74 +#define GCC_PCIE3_AUX_CLK 75 +#define PCIE0_RCHNG_CLK_SRC 76 +#define GCC_PCIE0_RCHNG_CLK 77 +#define PCIE1_RCHNG_CLK_SRC 78 +#define GCC_PCIE1_RCHNG_CLK 79 +#define PCIE2_RCHNG_CLK_SRC 80 +#define GCC_PCIE2_RCHNG_CLK 81 +#define PCIE3_RCHNG_CLK_SRC 82 +#define GCC_PCIE3_RCHNG_CLK 83 +#define GCC_PCIE0_AHB_CLK 84 +#define GCC_PCIE1_AHB_CLK 85 +#define GCC_PCIE2_AHB_CLK 86 +#define GCC_PCIE3_AHB_CLK 87 +#define USB0_AUX_CLK_SRC 88 +#define GCC_USB0_AUX_CLK 89 +#define USB0_MASTER_CLK_SRC 90 +#define GCC_USB0_MASTER_CLK 91 +#define GCC_SNOC_USB_CLK 92 +#define GCC_ANOC_USB_AXI_CLK 93 +#define USB0_MOCK_UTMI_CLK_SRC 94 +#define USB0_MOCK_UTMI_DIV_CLK_SRC 95 +#define GCC_USB0_MOCK_UTMI_CLK 96 +#define USB0_PIPE_CLK_SRC 97 +#define GCC_USB0_PHY_CFG_AHB_CLK 98 +#define SDCC1_APPS_CLK_SRC 99 +#define GCC_SDCC1_APPS_CLK 100 +#define SDCC1_ICE_CORE_CLK_SRC 101 +#define GCC_SDCC1_ICE_CORE_CLK 102 +#define GCC_SDCC1_AHB_CLK 103 +#define PCNOC_BFDCD_CLK_SRC 104 +#define GCC_NSSCFG_CLK 105 +#define GCC_NSSNOC_NSSCC_CLK 106 +#define GCC_NSSCC_CLK 107 +#define GCC_NSSNOC_PCNOC_1_CLK 108 +#define GCC_QDSS_DAP_AHB_CLK 109 +#define GCC_QDSS_CFG_AHB_CLK 110 +#define GCC_QPIC_AHB_CLK 111 +#define GCC_QPIC_CLK 112 +#define GCC_BLSP1_AHB_CLK 113 +#define GCC_MDIO_AHB_CLK 114 +#define GCC_PRNG_AHB_CLK 115 +#define GCC_UNIPHY0_AHB_CLK 116 +#define GCC_UNIPHY1_AHB_CLK 117 +#define GCC_UNIPHY2_AHB_CLK 118 +#define GCC_CMN_12GPLL_AHB_CLK 119 +#define GCC_CMN_12GPLL_APU_CLK 120 +#define SYSTEM_NOC_BFDCD_CLK_SRC 121 +#define GCC_NSSNOC_SNOC_CLK 122 +#define GCC_NSSNOC_SNOC_1_CLK 123 +#define GCC_QDSS_ETR_USB_CLK 124 +#define WCSS_AHB_CLK_SRC 125 +#define GCC_Q6_AHB_CLK 126 +#define GCC_Q6_AHB_S_CLK 127 +#define GCC_WCSS_ECAHB_CLK 128 +#define GCC_WCSS_ACMT_CLK 129 +#define GCC_SYS_NOC_WCSS_AHB_CLK 130 +#define WCSS_AXI_M_CLK_SRC 131 +#define GCC_ANOC_WCSS_AXI_M_CLK 132 +#define QDSS_AT_CLK_SRC 133 +#define GCC_Q6SS_ATBM_CLK 134 +#define GCC_WCSS_DBG_IFC_ATB_CLK 135 +#define GCC_NSSNOC_ATB_CLK 136 +#define GCC_QDSS_AT_CLK 137 +#define GCC_SYS_NOC_AT_CLK 138 +#define GCC_PCNOC_AT_CLK 139 +#define GCC_USB0_EUD_AT_CLK 140 +#define GCC_QDSS_EUD_AT_CLK 141 +#define QDSS_STM_CLK_SRC 142 +#define GCC_QDSS_STM_CLK 143 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 144 +#define QDSS_TRACECLKIN_CLK_SRC 145 +#define GCC_QDSS_TRACECLKIN_CLK 146 +#define QDSS_TSCTR_CLK_SRC 147 +#define GCC_Q6_TSCTR_1TO2_CLK 148 +#define GCC_WCSS_DBG_IFC_NTS_CLK 149 +#define GCC_QDSS_TSCTR_DIV2_CLK 150 +#define GCC_QDSS_TS_CLK 151 +#define GCC_QDSS_TSCTR_DIV4_CLK 152 +#define GCC_NSS_TS_CLK 153 +#define GCC_QDSS_TSCTR_DIV8_CLK 154 +#define GCC_QDSS_TSCTR_DIV16_CLK 155 +#define GCC_Q6SS_PCLKDBG_CLK 156 +#define GCC_Q6SS_TRIG_CLK 157 +#define GCC_WCSS_DBG_IFC_APB_CLK 158 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 159 +#define GCC_QDSS_DAP_CLK 160 +#define GCC_QDSS_APB2JTAG_CLK 161 +#define GCC_QDSS_TSCTR_DIV3_CLK 162 +#define QPIC_IO_MACRO_CLK_SRC 163 +#define GCC_QPIC_IO_MACRO_CLK 164 +#define Q6_AXI_CLK_SRC 165 +#define GCC_Q6_AXIM_CLK 166 +#define GCC_WCSS_Q6_TBU_CLK 167 +#define GCC_MEM_NOC_Q6_AXI_CLK 168 +#define Q6_AXIM2_CLK_SRC 169 +#define NSSNOC_MEMNOC_BFDCD_CLK_SRC 170 +#define GCC_NSSNOC_MEMNOC_CLK 171 +#define GCC_NSSNOC_MEM_NOC_1_CLK 172 +#define GCC_NSS_TBU_CLK 173 +#define GCC_MEM_NOC_NSSNOC_CLK 174 +#define LPASS_AXIM_CLK_SRC 175 +#define LPASS_SWAY_CLK_SRC 176 +#define ADSS_PWM_CLK_SRC 177 +#define GCC_ADSS_PWM_CLK 178 +#define GP1_CLK_SRC 179 +#define GP2_CLK_SRC 180 +#define GP3_CLK_SRC 181 +#define DDRSS_SMS_SLOW_CLK_SRC 182 +#define GCC_XO_CLK_SRC 183 +#define GCC_XO_CLK 184 +#define GCC_NSSNOC_QOSGEN_REF_CLK 185 +#define GCC_NSSNOC_TIMEOUT_REF_CLK 186 +#define GCC_XO_DIV4_CLK 187 +#define GCC_UNIPHY0_SYS_CLK 188 +#define GCC_UNIPHY1_SYS_CLK 189 +#define GCC_UNIPHY2_SYS_CLK 190 +#define GCC_CMN_12GPLL_SYS_CLK 191 +#define GCC_NSSNOC_XO_DCD_CLK 192 +#define GCC_Q6SS_BOOT_CLK 193 +#define UNIPHY_SYS_CLK_SRC 194 +#define NSS_TS_CLK_SRC 195 +#define GCC_ANOC_PCIE0_1LANE_M_CLK 196 +#define GCC_ANOC_PCIE1_1LANE_M_CLK 197 +#define GCC_ANOC_PCIE2_2LANE_M_CLK 198 +#define GCC_ANOC_PCIE3_2LANE_M_CLK 199 +#define GCC_SNOC_PCIE0_1LANE_S_CLK 200 +#define GCC_SNOC_PCIE1_1LANE_S_CLK 201 +#define GCC_SNOC_PCIE2_2LANE_S_CLK 202 +#define GCC_SNOC_PCIE3_2LANE_S_CLK 203 +#endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h new file mode 100644 index 000000000000..d01dc6a24cf1 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H +#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H + +#define GCC_ADSS_BCR 0 +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1 +#define GCC_BLSP1_BCR 2 +#define GCC_BLSP1_QUP1_BCR 3 +#define GCC_BLSP1_QUP2_BCR 4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_QUP4_BCR 6 +#define GCC_BLSP1_QUP5_BCR 7 +#define GCC_BLSP1_QUP6_BCR 8 +#define GCC_BLSP1_UART1_BCR 9 +#define GCC_BLSP1_UART2_BCR 10 +#define GCC_BLSP1_UART3_BCR 11 +#define GCC_BLSP1_UART4_BCR 12 +#define GCC_BLSP1_UART5_BCR 13 +#define GCC_BLSP1_UART6_BCR 14 +#define GCC_BOOT_ROM_BCR 15 +#define GCC_MDIO_BCR 16 +#define GCC_NSS_BCR 17 +#define GCC_NSS_TBU_BCR 18 +#define GCC_PCIE0_BCR 19 +#define GCC_PCIE0_LINK_DOWN_BCR 20 +#define GCC_PCIE0_PHY_BCR 21 +#define GCC_PCIE0PHY_PHY_BCR 22 +#define GCC_PCIE1_BCR 23 +#define GCC_PCIE1_LINK_DOWN_BCR 24 +#define GCC_PCIE1_PHY_BCR 25 +#define GCC_PCIE1PHY_PHY_BCR 26 +#define GCC_PCIE2_BCR 27 +#define GCC_PCIE2_LINK_DOWN_BCR 28 +#define GCC_PCIE2_PHY_BCR 29 +#define GCC_PCIE2PHY_PHY_BCR 30 +#define GCC_PCIE3_BCR 31 +#define GCC_PCIE3_LINK_DOWN_BCR 32 +#define GCC_PCIE3_PHY_BCR 33 +#define GCC_PCIE3PHY_PHY_BCR 34 +#define GCC_PRNG_BCR 35 +#define GCC_QUSB2_0_PHY_BCR 36 +#define GCC_SDCC_BCR 37 +#define GCC_TLMM_BCR 38 +#define GCC_UNIPHY0_BCR 39 +#define GCC_UNIPHY1_BCR 40 +#define GCC_UNIPHY2_BCR 41 +#define GCC_USB0_PHY_BCR 42 +#define GCC_USB3PHY_0_PHY_BCR 43 +#define GCC_USB_BCR 44 +#define GCC_ANOC0_TBU_BCR 45 +#define GCC_ANOC1_TBU_BCR 46 +#define GCC_ANOC_BCR 47 +#define GCC_APSS_TCU_BCR 48 +#define GCC_CMN_BLK_BCR 49 +#define GCC_CMN_BLK_AHB_ARES 50 +#define GCC_CMN_BLK_SYS_ARES 51 +#define GCC_CMN_BLK_APU_ARES 52 +#define GCC_DCC_BCR 53 +#define GCC_DDRSS_BCR 54 +#define GCC_IMEM_BCR 55 +#define GCC_LPASS_BCR 56 +#define GCC_MPM_BCR 57 +#define GCC_MSG_RAM_BCR 58 +#define GCC_NSSNOC_MEMNOC_1_ARES 59 +#define GCC_NSSNOC_PCNOC_1_ARES 60 +#define GCC_NSSNOC_SNOC_1_ARES 61 +#define GCC_NSSNOC_XO_DCD_ARES 62 +#define GCC_NSSNOC_TS_ARES 63 +#define GCC_NSSCC_ARES 64 +#define GCC_NSSNOC_NSSCC_ARES 65 +#define GCC_NSSNOC_ATB_ARES 66 +#define GCC_NSSNOC_MEMNOC_ARES 67 +#define GCC_NSSNOC_QOSGEN_REF_ARES 68 +#define GCC_NSSNOC_SNOC_ARES 69 +#define GCC_NSSNOC_TIMEOUT_REF_ARES 70 +#define GCC_NSS_CFG_ARES 71 +#define GCC_UBI0_DBG_ARES 72 +#define GCC_PCIE0_AHB_ARES 73 +#define GCC_PCIE0_AUX_ARES 74 +#define GCC_PCIE0_AXI_M_ARES 75 +#define GCC_PCIE0_AXI_M_STICKY_ARES 76 +#define GCC_PCIE0_AXI_S_ARES 77 +#define GCC_PCIE0_AXI_S_STICKY_ARES 78 +#define GCC_PCIE0_CORE_STICKY_ARES 79 +#define GCC_PCIE0_PIPE_ARES 80 +#define GCC_PCIE1_AHB_ARES 81 +#define GCC_PCIE1_AUX_ARES 82 +#define GCC_PCIE1_AXI_M_ARES 83 +#define GCC_PCIE1_AXI_M_STICKY_ARES 84 +#define GCC_PCIE1_AXI_S_ARES 85 +#define GCC_PCIE1_AXI_S_STICKY_ARES 86 +#define GCC_PCIE1_CORE_STICKY_ARES 87 +#define GCC_PCIE1_PIPE_ARES 88 +#define GCC_PCIE2_AHB_ARES 89 +#define GCC_PCIE2_AUX_ARES 90 +#define GCC_PCIE2_AXI_M_ARES 91 +#define GCC_PCIE2_AXI_M_STICKY_ARES 92 +#define GCC_PCIE2_AXI_S_ARES 93 +#define GCC_PCIE2_AXI_S_STICKY_ARES 94 +#define GCC_PCIE2_CORE_STICKY_ARES 95 +#define GCC_PCIE2_PIPE_ARES 96 +#define GCC_PCIE3_AHB_ARES 97 +#define GCC_PCIE3_AUX_ARES 98 +#define GCC_PCIE3_AXI_M_ARES 99 +#define GCC_PCIE3_AXI_M_STICKY_ARES 100 +#define GCC_PCIE3_AXI_S_ARES 101 +#define GCC_PCIE3_AXI_S_STICKY_ARES 102 +#define GCC_PCIE3_CORE_STICKY_ARES 103 +#define GCC_PCIE3_PIPE_ARES 104 +#define GCC_PCNOC_BCR 105 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 106 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 107 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 108 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 109 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 110 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 111 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 112 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 113 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 114 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 115 +#define GCC_PCNOC_TBU_BCR 116 +#define GCC_Q6SS_DBG_ARES 117 +#define GCC_Q6_AHB_ARES 118 +#define GCC_Q6_AHB_S_ARES 119 +#define GCC_Q6_AXIM2_ARES 120 +#define GCC_Q6_AXIM_ARES 121 +#define GCC_QDSS_BCR 122 +#define GCC_QPIC_BCR 123 +#define GCC_QPIC_AHB_ARES 124 +#define GCC_QPIC_ARES 125 +#define GCC_RBCPR_BCR 126 +#define GCC_RBCPR_MX_BCR 127 +#define GCC_SEC_CTRL_BCR 128 +#define GCC_SMMU_CFG_BCR 129 +#define GCC_SNOC_BCR 130 +#define GCC_SPDM_BCR 131 +#define GCC_TME_BCR 132 +#define GCC_UNIPHY0_SYS_RESET 133 +#define GCC_UNIPHY0_AHB_RESET 134 +#define GCC_UNIPHY0_XPCS_RESET 135 +#define GCC_UNIPHY1_SYS_RESET 136 +#define GCC_UNIPHY1_AHB_RESET 137 +#define GCC_UNIPHY1_XPCS_RESET 138 +#define GCC_UNIPHY2_SYS_RESET 139 +#define GCC_UNIPHY2_AHB_RESET 140 +#define GCC_UNIPHY2_XPCS_RESET 141 +#define GCC_USB_MISC_RESET 142 +#define GCC_WCSSAON_RESET 143 +#define GCC_WCSS_ACMT_ARES 144 +#define GCC_WCSS_AHB_S_ARES 145 +#define GCC_WCSS_AXI_M_ARES 146 +#define GCC_WCSS_BCR 147 +#define GCC_WCSS_DBG_ARES 148 +#define GCC_WCSS_DBG_BDG_ARES 149 +#define GCC_WCSS_ECAHB_ARES 150 +#define GCC_WCSS_Q6_BCR 151 +#define GCC_WCSS_Q6_TBU_BCR 152 +#define GCC_TCSR_BCR 153 + +#endif From 34d1a90bdb8a2759b9646c8596eea495b4cb02ac Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 16 Mar 2023 12:59:40 +0530 Subject: [PATCH 0914/1040] arm64: defconfig: Enable IPQ9574 SoC base configs Enables clk & pinctrl related configs for Qualcomm IPQ9574 SoC Reviewed-by: Krzysztof Kozlowski Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316072940.29137-7-quic_devipriy@quicinc.com --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5c191a3058b5..ac8eb9e7e2c7 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -549,6 +549,7 @@ CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ5332=y CONFIG_PINCTRL_IPQ6018=y +CONFIG_PINCTRL_IPQ9574=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_MSM8953=y CONFIG_PINCTRL_MSM8976=y @@ -1138,6 +1139,7 @@ CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_GCC_5332=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y +CONFIG_IPQ_GCC_9574=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8994=m From 97cb36ff52a1061a0d3ef4bf448813acef207140 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 16 Mar 2023 12:59:39 +0530 Subject: [PATCH 0915/1040] arm64: dts: qcom: Add ipq9574 SoC and AL02 board support Add initial device tree support for Qualcomm IPQ9574 SoC and AL02 board Co-developed-by: Anusha Rao Signed-off-by: Anusha Rao Co-developed-by: Poovendhan Selvaraj Signed-off-by: Poovendhan Selvaraj Signed-off-by: Devi Priya Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230316072940.29137-6-quic_devipriy@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 84 ++++++ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 270 +++++++++++++++++++ 3 files changed, 355 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f6ff4024a60e..915ff1e0d645 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts new file mode 100644 index 000000000000..2c8430197ec0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 AL02-C7 board device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq9574.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7"; + compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <384000000>; + bus-width = <8>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio5"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio4"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio0", "gpio1", "gpio2", + "gpio3", "gpio6", "gpio7", + "gpio8", "gpio9"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + + rclk-pins { + pins = "gpio10"; + function = "sdc_rclk"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi new file mode 100644 index 000000000000..3bb7435f5e7f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -0,0 +1,270 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * IPQ9574 SoC device tree source + * + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + bias_pll_ubi_nc_clk: bias-pll-ubi-nc-clk { + compatible = "fixed-clock"; + clock-frequency = <353000000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a73-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_region: tz@4a600000 { + reg = <0x0 0x4a600000 0x0 0x400000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9574-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 65>; + interrupt-controller; + #interrupt-cells = <2>; + + uart2_pins: uart2-state { + pins = "gpio34", "gpio35"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,ipq9574-gcc"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&bias_pll_ubi_nc_clk>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x07804000 0x1000>, <0x07805000 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board_clk>; + clock-names = "iface", "core", "xo"; + non-removable; + status = "disabled"; + }; + + blsp1_uart2: serial@78b1000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b1000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x1000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x1000>; /* GICV */ + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + ranges = <0 0x0b00c000 0x3000>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xffd>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xffd>; + msi-controller; + }; + + v2m2: v2m@2000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00002000 0xffd>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@b123000 { + reg = <0x0b123000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@b124000 { + reg = <0x0b124000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From d84f8f2687bdc67f20262e822b206419bcfd0038 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:05 -0700 Subject: [PATCH 0916/1040] arm64: dts: sc7180: Rename qspi data12 as data23 There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.1.Ifc1b5be04653f4ab119698a5944bfecded2080d6@changeid --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 3c799b564b64..25eb4e60d0bb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1548,7 +1548,7 @@ function = "qspi_data"; }; - qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio66", "gpio67"; function = "qspi_data"; }; From 14acf21c0d3f7b7298ffcd2e5b5db4a476ec6202 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:06 -0700 Subject: [PATCH 0917/1040] arm64: dts: sc7280: Rename qspi data12 as data23 There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: 7720ea001b52 ("arm64: dts: qcom: sc7280: Add QSPI node") Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.2.I4043491bb24b1e92267c5033d76cdb0fe60934da@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f4003e0f8fac..18a4b097ebbd 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4358,7 +4358,7 @@ function = "qspi_data"; }; - qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio16", "gpio17"; function = "qspi_data"; }; From 37f7349b56decc91c66f8039712e63740b1f25f9 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:07 -0700 Subject: [PATCH 0918/1040] arm64: dts: sdm845: Rename qspi data12 as data23 There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: e1ce853932b7 ("arm64: dts: qcom: sdm845: Add qspi (quad SPI) node") Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.3.I88528d037b7fda4e53a40f661be5ac61628691cd@changeid --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e35add9f3299..e7fabd5d81ae 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2772,7 +2772,7 @@ function = "qspi_data"; }; - qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio93", "gpio94"; function = "qspi_data"; }; From ced32c299e5d6c447ad0b80d7a16b44e0e72e8e0 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:08 -0700 Subject: [PATCH 0919/1040] arm64: dts: qcom: sc7180: Annotate l13a on trogdor to always-on The l13a rail on trogdor devices has always been intended to be always-on on both S0 and S3. Different trogdor variants use l13a in slightly different ways, but the overall theme is that it's a 1.8V rail that the board uses for things that it wants powered in on S0 and S3. On many boards this includes the boot SPI (AKA qspi). For all intents and purposes this patch is actually a no-op since something else in the system seems to already be keeping the rail on all the time (confirmed via multimeter). That "something else" was postulated to be the modem but the rail is on / stays on even without the modem/wifi coming up so it's likely the boot config. In any case, making the fact that this is always-on explicit seems like a good idea. Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.4.I9f47a8a53eacff6229711a827993792ceeb36971@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 423630c4d02c..1f2e1f701761 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -512,6 +512,8 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; }; pp1800_prox: From e8df226339fa032c49f8db4281903930d018a22c Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:13 -0700 Subject: [PATCH 0920/1040] arm64: dts: qcom: sc7180: Remove superfluous "input-enable"s from trogdor As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at trogdor: * ap_ec_int_l, fp_to_ap_irq_l, h1_ap_int_odl, p_sensor_int_l: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). * bios_flash_wp_l: Superfluous. This pin is exposed to userspace through the kernel's GPIO API and will be configured automatically. That means that in none of the cases for trogdor did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.9.I94dbc53176e8adb0d7673b7feb2368e85418f938@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 1f2e1f701761..39100b0c1140 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1206,7 +1206,6 @@ ap_spi_fp: &spi10 { ap_ec_int_l: ap-ec-int-l-state { pins = "gpio94"; function = "gpio"; - input-enable; bias-pull-up; }; @@ -1229,7 +1228,6 @@ ap_spi_fp: &spi10 { bios_flash_wp_l: bios-flash-wp-l-state { pins = "gpio66"; function = "gpio"; - input-enable; bias-disable; }; @@ -1271,7 +1269,6 @@ ap_spi_fp: &spi10 { fp_to_ap_irq_l: fp-to-ap-irq-l-state { pins = "gpio4"; function = "gpio"; - input-enable; /* Has external pullup */ bias-disable; @@ -1286,7 +1283,6 @@ ap_spi_fp: &spi10 { h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio42"; function = "gpio"; - input-enable; bias-pull-up; }; @@ -1335,7 +1331,6 @@ ap_spi_fp: &spi10 { p_sensor_int_l: p-sensor-int-l-state { pins = "gpio24"; function = "gpio"; - input-enable; /* Has external pullup */ bias-disable; From 6d4794d658a0967a7f257f16d6a7a48afb8c8e05 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:14 -0700 Subject: [PATCH 0921/1040] arm64: dts: qcom: sc7280: Remove superfluous "input-enable"s from idp-ec-h1 As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at the sc7280-idp-ec-h1.dtsi file: * ap_ec_int_l, h1_ap_int_odl: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). That means that in none of the cases for sc7280-idp-ec-h1.dtsi did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.10.I1343c20f4aaac8e2c1918b756f7ed66f6ceace9c@changeid --- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index 3cfeb118d379..ebae545c587c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -82,14 +82,12 @@ ap_h1_spi: &spi14 { ap_ec_int_l: ap-ec-int-l-state { pins = "gpio18"; function = "gpio"; - input-enable; bias-pull-up; }; h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio104"; function = "gpio"; - input-enable; bias-pull-up; }; From 406fed87083578d07c7cea9483b85b51469594e0 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:15 -0700 Subject: [PATCH 0922/1040] arm64: dts: qcom: sdm845: Remove superfluous "input-enable"s from cheza As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at cheza * ec_ap_int_l, h1_ap_int_odl: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). * bios_flash_wp_l: Superfluous. This pin is exposed to userspace through the kernel's GPIO API and will be configured automatically. That means that in none of the cases for cheza did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.11.Ia439c29517b1c0625325a54387b047f099d16425@changeid --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 59ad6a8403d2..e1bab53642ab 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -1153,14 +1153,12 @@ ap_ts_i2c: &i2c14 { bios_flash_wp_r_l: bios-flash-wp-r-l-state { pins = "gpio128"; function = "gpio"; - input-enable; bias-disable; }; ec_ap_int_l: ec-ap-int-l-state { pins = "gpio122"; function = "gpio"; - input-enable; bias-pull-up; }; @@ -1188,7 +1186,6 @@ ap_ts_i2c: &i2c14 { h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio129"; function = "gpio"; - input-enable; bias-pull-up; }; From ab752f03e2feb3323dfd9c1ce161ac759ce09634 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:16 -0700 Subject: [PATCH 0923/1040] arm64: dts: qcom: sc7180: Fix trogdor qspi pin config In commit 7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt") we specified the pull settings on the boot SPI (the qspi) data lines as pullups to "park" the lines. This seemed like the right thing to do, but I never really probed the lines to confirm. Since that time, I've done A LOT of research, experiements and poking of the lines with a voltmeter. A first batch of discoveries: - There is an external pullup on CS (clearly shown on schematics) - There are weak external pulldowns on CLK/MOSI (believed to be Cr50's internal pulldowns) - There is no pull on MISO. - When qspi isn't actively transferring it still drives CS, CLK, and MOSI. CS and MOSI are driven high and CLK is driven low. It does not drive MISO and (if no internal pulls are enabled) the line floats. The above means that it's good to have some sort of pull on MISO, at the very least. The pullup that we had before was actually fine (and my voltmeter confirms that it actually affected the state of the pin) but a pulldown would work equally well (and would match MOSI and CLK better). The above also means that we could save a tiny bit of power (not measurable by my setup) by setting up a sleep state for these pins. If nothing else this prevents us from driving high against Cr50's internal pulldown on MOSI. However, Qualcomm has also asserted in the past that it burns a little extra power to drive a pin, especially since these are configured with a slightly higher drive strength Let's fix all this. Since the external pulls are different for the two data lines, we'll split them into separate configs. Then we'll change the MISO pin to a pulldown and add a sleep state. On a slightly tangental (but not totally unrelated note), I also discovered some interesting things with these pins in suspend. First, I found that if we don't switch the pins to GPIO that the qspi peripheral continues to drive them in suspend. That'll be solved by what we're already doing above. Second, I found that something in the system suspend path (after Linux stops running) reconfigures these pins so that they don't have their normal pulls enabled but instead change to "keepers" (bias-bus-hold in DT speak). If a pin was floating before we entered suspend then it would stop floating. I found that I could manually pull a pin to a different level and then probe it and it would stay there. This is exactly keeper behavior. With the solution we have the switch to "keeper" doesn't matter too much but it's good to document. While talking about "keepers", it can also be noted that I found that the "keepers" on these pins were at least enough to win a fight against Cr50's internal pulls. That means it's best to make sure that the state of the pins are already correct before the mysterious transition to a keeper. Otherwise we'll burn (a small amount of) power in S3 via this fight. Luckily with the current solution we don't hit this case. NOTE: I've left "sc7180-idp" behavior totally alone in this patch. I didn't add a sleep state and I didn't change any pulls--I just adapted it to the fact that the data lines have separate configs. Qualcomm doesn't provide me with schematics for IDP and thus I don't actually know how the pulls are configured. Since this is just a development platform and worked well enough, it seems safer to leave it alone. Dependencies: - This patch has a hard dependency on ("pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE"). Something in the boot code seemed to have been confused and thought it needed to set the "OUTPUT ENABLE" bit for these pins even though it was using them as SPI. Thus if we don't honor the "output-disable" property we could end up driving the SPI pins while in sleep mode. - In general, it's probably best not to backport this to a kernel that doesn't have commit d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching lines when we first mux to output"). That landed a while ago, but it's still good to be explicit in case someone was backporting. If we don't have that then there might be a glitch when we first switch over to GPIO before we disable the output. - This patch _doesn't_ really have any dependency on the qspi driver patch that supports setting the pinctrl sleep state--they can go in either order. If we define the sleep state and the driver never selects it that's fine. If the driver tries to select a sleep state that we don't define that's fine. Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.12.I6f03f86546e6ce9abb1d24fd9ece663c3a5b950c@changeid --- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 9 ++++-- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 34 ++++++++++++++++---- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++-- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index fcabbc6a897f..9f052270e090 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -349,7 +349,7 @@ &qspi { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; flash@0 { compatible = "jedec,spi-nor"; @@ -507,8 +507,11 @@ bias-disable; }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ +&qspi_data0 { + bias-pull-up; +}; + +&qspi_data1 { bias-pull-up; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 39100b0c1140..ca6920de7ea8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -424,8 +424,9 @@ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; flash@0 { compatible = "jedec,spi-nor"; @@ -1046,17 +1047,20 @@ ap_spi_fp: &spi10 { }; &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ }; &qspi_clk { drive-strength = <8>; - bias-disable; + bias-disable; /* Rely on Cr50 internal pulldown */ }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-disable; /* Rely on Cr50 internal pulldown */ +}; + +&qspi_data1 { + bias-pull-down; }; &qup_i2c2_default { @@ -1336,6 +1340,22 @@ ap_spi_fp: &spi10 { bias-disable; }; + qspi_sleep: qspi-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio68"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; + qup_uart3_sleep: qup-uart3-sleep-state { cts-pins { /* diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 25eb4e60d0bb..33a4c70b0dad 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1543,8 +1543,13 @@ function = "qspi_cs"; }; - qspi_data01: qspi-data01-state { - pins = "gpio64", "gpio65"; + qspi_data0: qspi-data0-state { + pins = "gpio64"; + function = "qspi_data"; + }; + + qspi_data1: qspi-data1-state { + pins = "gpio65"; function = "qspi_data"; }; From 5f89df31096d67c244d8f36502f651ce701ddcde Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:17 -0700 Subject: [PATCH 0924/1040] arm64: dts: qcom: sc7280: Fix qspi pin config Similar to sc7180 (see the patch ("arm64: dts: qcom: sc7180: Fix trogdor qspi pin config")), we should adjust the qspi pin config for sc7280. I won't re-describe all the research/arguments in the sc7180 patch here, but there are a few differences for sc7280 worth noting: 1. On herobrine the SPI flash (qspi) is wired up differently on the board. Rather than Cr50 and the AP being wired directly together, there's actually a mux that will _either_ connect the AP to the flash or Cr50 to the flash. This means that the internal pulls on Cr50 don't affect us and we should enable our own pulldowns. 2. On herobrine, EEs added an external pulldown on the MISO line. The argument in the schematic said that we added it (but not one on MOSI and CLK) because Cr50 already enabled pulldowns on MOSI and CLK. ...though, as per #1, those Cr50 pulldowns would only affect the line when the mux was swung to Cr50. The ironic result of #1 and #2 is that the external pulldowns on CLK/MISO/MOSI on herobrine are _exactly opposite_ of the ones on trogdor. 3. While I still don't have the actual exact schematics for all variants of IDP/CRD that were produced, I have some reference schematics that give me a belief of how the qspi is hooked up there. From this, I'm fairly certain that all of the older variants of IDP/CRD either have a pulldown on the CLK/MOSI/MISO lines (maybe through a direct connect to Cr50) or have no pull (in other words, they don't have a pullup). I'll go ahead and enable internal pulldowns on all the lines since that won't hurt to double-pull if there's an external pulldown and it's nice to have a pulldown if there's nothing external. Note that this only affects _older_ CRDs. Newer revs are considered "herobrine" (see the hoglin/zoglin device trees). 4. I didn't find the same strange "auto-switch-to-keeper" at suspend when probing on sc7280. Whatever pulls (or lack thereof) I left at suspend time seemed to persist into suspend. Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.13.Ib44c3e417c414a4227db8def75ded37ad368212c@changeid --- .../boot/dts/qcom/sc7280-chrome-common.dtsi | 25 +++++++++++++++++-- .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 14 +++++++---- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 13 ++++++---- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++-- 4 files changed, 47 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 16fb20369c01..f562e4d2b655 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -60,8 +60,9 @@ */ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; spi_flash: flash@0 { compatible = "jedec,spi-nor"; @@ -85,3 +86,23 @@ iommus = <&apps_smmu 0x1c02 0x1>; }; }; + +/* PINCTRL - chrome-common pinctrl */ + +&tlmm { + qspi_sleep: qspi-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index b6137816f2f3..e651f633341f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -692,18 +692,22 @@ ap_ec_spi: &spi10 { }; &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ drive-strength = <8>; }; &qspi_clk { - bias-disable; + bias-pull-down; /* No external pulls */ drive-strength = <8>; }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-pull-down; /* No external pulls */ + drive-strength = <8>; +}; + +&qspi_data1 { + bias-disable; /* External pulldown */ drive-strength = <8>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 5dc9bee28e7f..c6dc200c00ce 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -636,16 +636,19 @@ }; &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ }; &qspi_clk { - bias-disable; + bias-pull-down; /* No external pulls or external pulldown */ }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-pull-down; /* No external pulls or external pulldown */ +}; + +&qspi_data1 { + bias-pull-down; /* No external pulls or external pulldown */ }; &qup_uart5_tx { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 18a4b097ebbd..0d22fe42b133 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4353,8 +4353,13 @@ function = "qspi_cs"; }; - qspi_data01: qspi-data01-state { - pins = "gpio12", "gpio13"; + qspi_data0: qspi-data0-state { + pins = "gpio12"; + function = "qspi_data"; + }; + + qspi_data1: qspi-data1-state { + pins = "gpio13"; function = "qspi_data"; }; From 9f5cdeb7031062a36e135ebb88bd99c03f32e5ee Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Mar 2023 10:30:18 -0700 Subject: [PATCH 0925/1040] arm64: dts: qcom: sdm845: Fix cheza qspi pin config Cheza's SPI flash hookups (qspi) are exactly the same as trogdor's. Apply the same solution that's described in the patch ("arm64: dts: qcom: sc7180: Fix trogdor qspi pin config") Signed-off-by: Douglas Anderson Acked-by: Linus Walleij Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323102605.14.I82951106ab8170f973a4c1c7d9b034655bbe2f60@changeid --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 34 +++++++++++++++++----- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++++-- 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index e1bab53642ab..d05c511718df 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -317,8 +317,9 @@ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; flash@0 { compatible = "jedec,spi-nor"; @@ -993,16 +994,19 @@ ap_ts_i2c: &i2c14 { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ }; &qspi_clk { - bias-disable; + bias-disable; /* Rely on Cr50 internal pulldown */ }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-disable; /* Rely on Cr50 internal pulldown */ +}; + +&qspi_data1 { + bias-pull-down; }; &qup_i2c3_default { @@ -1231,6 +1235,22 @@ ap_ts_i2c: &i2c14 { output-high; }; + qspi_sleep: qspi-sleep-state { + pins = "gpio90", "gpio91", "gpio92", "gpio95"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; + sdc2_clk: sdc2-clk-state { pins = "sdc2_clk"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e7fabd5d81ae..fe1e8b644ac7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2767,8 +2767,13 @@ function = "qspi_cs"; }; - qspi_data01: qspi-data01-state { - pins = "gpio91", "gpio92"; + qspi_data0: qspi-data0-state { + pins = "gpio91"; + function = "qspi_data"; + }; + + qspi_data1: qspi-data1-state { + pins = "gpio92"; function = "qspi_data"; }; From 04b5840664822cefff61deb727f497b59c341e0e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 7 Apr 2023 15:28:34 +0200 Subject: [PATCH 0926/1040] arm64: dts: qcom: sc7280: Fix up the gic node Fix the following schema warning: gic-its@17a40000: False schema does not allow {'compatible': ['arm,gic-v3-its'], 'msi-controller': True, '#msi-cells': [[1]], 'reg': [[0, 396623872, 0, 131072]], 'status': ['disabled']} And reorder the properties to be more in order with all other nodes. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-4-6efb4196f51f@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0d22fe42b133..31728f461422 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5185,20 +5185,20 @@ intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; reg = <0 0x17a00000 0 0x10000>, /* GICD */ <0 0x17a60000 0 0x100000>; /* GICR * 8 */ interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <2>; + #size-cells = <2>; + ranges; - gic-its@17a40000 { + msi-controller@17a40000 { compatible = "arm,gic-v3-its"; + reg = <0 0x17a40000 0 0x20000>; msi-controller; #msi-cells = <1>; - reg = <0 0x17a40000 0 0x20000>; status = "disabled"; }; }; From 7891372d6c5b3d73c304e26fa1e3b17c022281a1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 7 Apr 2023 15:28:35 +0200 Subject: [PATCH 0927/1040] arm64: dts: qcom: pm8916: Fix pm8941-misc node name Fix the node name to make dtbs_check happy: qcom/apq8016-sbc.dtb: pmic@0: 'extcon@1300' does not match any of the regexes: '(.*)?(wled|leds)@[0-9a-f]+$', '^adc-tm@[0-9a-f]+$', '^adc@[0-9a-f]+$', '^audio-codec@[0-9a-f]+$', '^charger@[0-9a-f]+$', '^mpps@[0-9a-f]+$', '^nvram@[0-9a-f]+$', '^rtc@[0-9a-f]+$', '^temp-alarm@[0-9a-f]+$', '^usb-detect@[0-9a-f]+$', '^usb-vbus-regulator@[0-9a-f]+$', '^vibrator@[0-9a-f]+$', 'gpio@[0-9a-f]+$', 'pinctrl-[0-9]+', 'pon@[0-9a-f]+$' Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-5-6efb4196f51f@linaro.org --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index e2a6b66d8847..f4fb1a92ab55 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -41,7 +41,7 @@ }; }; - pm8916_usbin: extcon@1300 { + pm8916_usbin: usb-detect@1300 { compatible = "qcom,pm8941-misc"; reg = <0x1300>; interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>; From 149959d0b18113881cb0a47ad8f8d36b60ff6f9f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 7 Apr 2023 15:28:36 +0200 Subject: [PATCH 0928/1040] arm64: dts: qcom: sdm845-oneplus: Fix speaker GPIO node Drop the unnecessary mux{} level to make dtbs check happy. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407-topic-msm_dtb-v1-6-6efb4196f51f@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 0c268c560d37..8c2b9382337c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -814,13 +814,11 @@ }; speaker_default: speaker-default-state { - mux { - pins = "gpio69"; - function = "gpio"; - drive-strength = <16>; - bias-pull-up; - output-high; - }; + pins = "gpio69"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + output-high; }; }; From 27eba11291b0f9a8e9ca1f50ba0f6fd3fdda486b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 6 Apr 2023 21:28:11 +0200 Subject: [PATCH 0929/1040] arm64: dts: qcom: sa8775p-ride: add PMIC regulators Add PMIC regulators for sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406192811.460888-4-brgl@bgdev.pl --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 233 ++++++++++++++++++++++ 1 file changed, 233 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index a0d2024a69df..f238a02a5448 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "sa8775p.dtsi" #include "sa8775p-pmics.dtsi" @@ -25,6 +27,237 @@ }; }; +&apps_rsc { + regulators-0 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1816000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1996000>; + regulator-initial-mode = ; + }; + + vreg_s9a: smps9 { + regulator-name = "vreg_s9a"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + regulator-initial-mode = ; + }; + + vreg_l4a: ldo4 { + regulator-name = "vreg_l4a"; + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6a: ldo6 { + regulator-name = "vreg_l6a"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9a: ldo9 { + regulator-name = "vreg_l9a"; + regulator-min-microvolt = <2970000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_l1c: ldo1 { + regulator-name = "vreg_l1c"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3c: ldo3 { + regulator-name = "vreg_l3c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4c: ldo4 { + regulator-name = "vreg_l4c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + /* + * FIXME: This should have regulator-allow-set-load but + * we're getting an over-current fault from the PMIC + * when switching to LPM. + */ + }; + + vreg_l5c: ldo5 { + regulator-name = "vreg_l5c"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6c: ldo6 { + regulator-name = "vreg_l6c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7c: ldo7 { + regulator-name = "vreg_l7c"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8c: ldo8 { + regulator-name = "vreg_l8c"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9c: ldo9 { + regulator-name = "vreg_l9c"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2700000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id = "e"; + + vreg_s4e: smps4 { + regulator-name = "vreg_s4e"; + regulator-min-microvolt = <970000>; + regulator-max-microvolt = <1520000>; + regulator-initial-mode = ; + }; + + vreg_s7e: smps7 { + regulator-name = "vreg_s7e"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + regulator-initial-mode = ; + }; + + vreg_s9e: smps9 { + regulator-name = "vreg_s9e"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + }; + + vreg_l6e: ldo6 { + regulator-name = "vreg_l6e"; + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8e: ldo8 { + regulator-name = "vreg_l8e"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; +}; + &i2c18 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c18_default>; From 74588aada59a9870139ef4c39d640939dcc08381 Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Thu, 6 Apr 2023 19:31:44 +0200 Subject: [PATCH 0930/1040] arm64: dts: qcom: sdm845: add SLPI remoteproc Add the SLPI remoteproc to the SDM845 Qualcomm SoC which is responsible for exposing the sensors connected to the SoC. The SLPI communicates over GLink edge 'dsps' and is similar to other DSPs e.g. ADSP or CDSP. This patch allows the SLPI to boot and expose itself over QRTR as service 400. Signed-off-by: Dylan Van Assche Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406173148.28309-2-me@dylanvanassche.be --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 36 ++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index fe1e8b644ac7..760da18fff27 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3328,6 +3328,42 @@ "gcc_gpu_gpll0_div_clk_src"; }; + slpi_pas: remoteproc@5c00000 { + compatible = "qcom,sdm845-slpi-pas"; + reg = <0 0x5c00000 0 0x4000>; + + interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + qcom,qmp = <&aoss_qmp>; + + power-domains = <&rpmhpd SDM845_CX>, + <&rpmhpd SDM845_MX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&slpi_mem>; + + qcom,smem-states = <&slpi_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "dsps"; + qcom,remote-pid = <3>; + mboxes = <&apss_shared 24>; + }; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, From 77c7a41e052502f0d8827c63eddae6dd5d717b20 Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Thu, 6 Apr 2023 19:31:45 +0200 Subject: [PATCH 0931/1040] dt-bindings: firmware: qcom: scm: add SSC_Q6 and ADSP_Q6 VMIDs SSC_Q6 and ADSP_Q6 are used in the FastRPC driver for accessing the secure world. Signed-off-by: Dylan Van Assche Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406173148.28309-3-me@dylanvanassche.be --- include/dt-bindings/firmware/qcom,scm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h index 1a4e68fa0744..d1dc09e72923 100644 --- a/include/dt-bindings/firmware/qcom,scm.h +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -8,6 +8,8 @@ #define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H #define QCOM_SCM_VMID_HLOS 0x3 +#define QCOM_SCM_VMID_SSC_Q6 0x5 +#define QCOM_SCM_VMID_ADSP_Q6 0x6 #define QCOM_SCM_VMID_MSS_MSA 0xF #define QCOM_SCM_VMID_WLAN 0x18 #define QCOM_SCM_VMID_WLAN_CE 0x19 From 755b5e094feb974f65cc51371c3482042d5fbadc Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Thu, 6 Apr 2023 19:31:46 +0200 Subject: [PATCH 0932/1040] arm64: dts: qcom: sdm845: add SLPI FastRPC support Qualcomm SDM845 SoC features a SLPI DSP which uses FastRPC through an allocated memory region to load files from the host filesystem such as sensor configuration files. Add a FastRPC node at /dev/fastrpc-sdsp and a DMA region, similar to downstream, to allow userspace to communicate with the SLPI via the FastRPC interface for initializing the sensors on the SLPI. Signed-off-by: Dylan Van Assche Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406173148.28309-4-me@dylanvanassche.be --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 760da18fff27..21c710547d1b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -876,6 +877,14 @@ size = <0 0x4000>; no-map; }; + + fastrpc_mem: fastrpc { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + reusable; + }; }; adsp_pas: remoteproc-adsp { @@ -3361,6 +3370,23 @@ label = "dsps"; qcom,remote-pid = <3>; mboxes = <&apss_shared 24>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + qcom,non-secure-domain; + qcom,vmids = ; + memory-region = <&fastrpc_mem>; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@0 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <0>; + }; + }; }; }; From c3998dc09f0e70c1e359b819b1b5d0c482f30500 Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Thu, 6 Apr 2023 19:31:47 +0200 Subject: [PATCH 0933/1040] arm64: dts: qcom: sdm845-oneplus: enable SLPI Enable the SLPI DSP on the Oneplus 6 phone with a Qualcomm SDM845 SoC. Signed-off-by: Dylan Van Assche Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406173148.28309-5-me@dylanvanassche.be --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 8c2b9382337c..50a1c23f747d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -550,6 +550,11 @@ bias-disable; }; +&slpi_pas { + firmware-name = "qcom/sdm845/oneplus6/slpi.mbn"; + status = "okay"; +}; + &sound { compatible = "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; From 48bd05786ec72b991430d5493743293df5da56a8 Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Thu, 6 Apr 2023 19:31:48 +0200 Subject: [PATCH 0934/1040] arm64: dts: qcom: sdm845-shift-axolotl: enable SLPI Enable the SLPI DSP on the SHIFTPHONES SHIFT6mq phone with a Qualcomm SDM845 SoC. Signed-off-by: Dylan Van Assche Reviewed-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406173148.28309-6-me@dylanvanassche.be --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index b54e304abf71..bd9571a258cf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -572,6 +572,11 @@ status = "okay"; }; +&slpi_pas { + firmware-name = "qcom/sdm845/axolotl/slpi.mbn"; + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <0 4>, <81 4>; From fbc3a1df2866608ca43e7e6d602f66208a5afd88 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Apr 2023 14:55:45 +0200 Subject: [PATCH 0935/1040] arm64: dts: qcom: sdm845-polaris: Drop inexistent properties Drop the qcom,snoc-host-cap-skip-quirk that was never introduced to solve schema warnings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406-topic-ath10k_bindings-v3-2-00895afc7764@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 1b7fdbae6a2b..56f2d855df78 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -712,7 +712,5 @@ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; - - qcom,snoc-host-cap-skip-quirk; status = "okay"; }; From 1ad3efe52cd10a94bdee63216cc5c09e813594ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Apr 2023 17:50:30 +0200 Subject: [PATCH 0936/1040] dt-bindings: firmware: document Qualcomm QCM2290 SCM Add a compatible for Qualcomm QCM2290 SCM and add it to the core clock users list. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-1-dae06f8830dc@linaro.org --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index c3851b13cd5a..367d04ad1923 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -40,6 +40,7 @@ properties: - qcom,scm-msm8994 - qcom,scm-msm8996 - qcom,scm-msm8998 + - qcom,scm-qcm2290 - qcom,scm-qdu1000 - qcom,scm-sa8775p - qcom,scm-sc7180 @@ -110,6 +111,7 @@ allOf: - qcom,scm-msm8960 - qcom,scm-msm8974 - qcom,scm-msm8976 + - qcom,scm-qcm2290 - qcom,scm-sm6375 then: required: @@ -128,6 +130,7 @@ allOf: - qcom,scm-apq8064 - qcom,scm-msm8660 - qcom,scm-msm8960 + - qcom,scm-qcm2290 - qcom,scm-sm6375 then: properties: From 941a8a4505cd44e826536ce41ffb863196d68769 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Apr 2023 17:50:31 +0200 Subject: [PATCH 0937/1040] dt-bindings: arm: qcom: Add QRB2210/QCM2290 and RB1 board Document QRB210, a QRB version of QCM2290. Document QTI Robotics RB1 as a QRB2210 device. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-2-dae06f8830dc@linaro.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index f8d29b65f28b..fb16cfe36b1e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -47,7 +47,9 @@ description: | msm8996 msm8998 qcs404 + qcm2290 qdu1000 + qrb2210 qru1000 sa8155p sa8540p @@ -354,6 +356,13 @@ properties: - const: swir,wp8548 - const: qcom,mdm9615 + - description: Qualcomm Technologies, Inc. Robotics RB1 + items: + - enum: + - qcom,qrb2210-rb1 + - const: qcom,qrb2210 + - const: qcom,qcm2290 + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform items: - enum: From a64a0192b70cfe7537072ae61a5e0d1d99f976bc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Apr 2023 17:50:32 +0200 Subject: [PATCH 0938/1040] arm64: dts: qcom: Add initial QCM2290 device tree Add an initial device tree for the QCM2290 low-end SoC, featuring 4 "customized" Cortex-A53 cores and up to 4 GiB of LPDDR(3/4X). This revision brings support for: - TSENS & thermal zones - SDHCI1/2 - I2C, SPI, UART - MPSS - ADSP - Wi-Fi Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-3-dae06f8830dc@linaro.org --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 1561 +++++++++++++++++++++++++ 1 file changed, 1561 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcm2290.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi new file mode 100644 index 000000000000..ae5abc76bcc7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -0,0 +1,1561 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + * + * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&cpufreq_hw 0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-qcm2290", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + #reset-cells = <1>; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x40000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@45700000 { + reg = <0x0 0x45700000 0x0 0x600000>; + no-map; + }; + + xbl_aop_mem: xbl-aop@45e00000 { + reg = <0x0 0x45e00000 0x0 0x140000>; + no-map; + }; + + sec_apps_mem: sec-apps@45fff000 { + reg = <0x0 0x45fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@46000000 { + compatible = "qcom,smem"; + reg = <0x0 0x46000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + }; + + pil_modem_mem: modem@4ab00000 { + reg = <0x0 0x4ab00000 0x0 0x6900000>; + no-map; + }; + + pil_video_mem: video@51400000 { + reg = <0x0 0x51400000 0x0 0x500000>; + no-map; + }; + + wlan_msa_mem: wlan-msa@51900000 { + reg = <0x0 0x51900000 0x0 0x100000>; + no-map; + }; + + pil_adsp_mem: adsp@51a00000 { + reg = <0x0 0x51a00000 0x0 0x1c00000>; + no-map; + }; + + pil_ipa_fw_mem: ipa-fw@53600000 { + reg = <0x0 0x53600000 0x0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: ipa-gsi@53610000 { + reg = <0x0 0x53610000 0x0 0x5000>; + no-map; + }; + + pil_gpu_mem: zap@53615000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x53615000 0x0 0x2000>; + no-map; + }; + + cont_splash_memory: framebuffer@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + no-map; + }; + + dfps_data_memory: dpfs-data@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + no-map; + }; + + removed_mem: reserved@60000000 { + reg = <0x0 0x60000000 0x0 0x3900000>; + no-map; + }; + + rmtfs_mem: memory@89b01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x89b01000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + rpm-glink { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcm2290"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,qcm2290-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apcs_glb 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + adsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + adsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + mboxes = <&apcs_glb 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wlan_smp2p_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + + tcsr_mutex: hwlock@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,qcm2290-tlmm"; + reg = <0x0 0x00500000 0x0 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 127>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio6", "gpio7"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default-state { + pins = "gpio8", "gpio9"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default-state { + pins = "gpio14", "gpio15"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1","gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default-state { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default-state { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default-state { + pins = "gpio12", "gpio13", "gpio96", "gpio97"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default-state { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart4_default: qup-uart4-default-state { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_state_on: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_state_off: sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,gcc-qcm2290"; + reg = <0x0 0x01400000 0x0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_hsphy: phy@1613000 { + compatible = "qcom,qcm2290-qusb2-phy"; + reg = <0x0 0x01613000 0x0 0x180>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + #phy-cells = <0>; + + status = "disabled"; + }; + + qfprom@1b44000 { + compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b44000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts = ; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + + tsens0: thermal-sensor@4411000 { + compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; + reg = <0x0 0x04411000 0x0 0x1ff>, + <0x0 0x04410000 0x0 0x8>; + #qcom,sensors = <10>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + rng: rng@4453000 { + compatible = "qcom,prng-ee"; + reg = <0x0 0x04453000 0x0 0x1000>; + clocks = <&rpmcc RPM_SMD_HWKM_CLK>; + clock-names = "core"; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x0 0x045f0000 0x0 0x7000>; + }; + + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x0 0x04690000 0x0 0x10000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>, + <0x0 0x04748000 0x0 0x8000>; + reg-names = "hc", + "cqhci", + "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", + "core", + "xo", + "ice"; + + resets = <&gcc GCC_SDCC1_BCR>; + + power-domains = <&rpmpd QCM2290_VDDCX>; + iommus = <&apps_smmu 0xc0 0x0>; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + bus-width = <8>; + + status = "disabled"; + }; + + sdhc_2: mmc@4784000 { + compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x04784000 0x0 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + + resets = <&gcc GCC_SDCC2_BCR>; + + power-domains = <&rpmpd QCM2290_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + iommus = <&apps_smmu 0xa0 0x0>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + bus-width = <4>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + }; + }; + + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x04a00000 0x0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xf6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + iommus = <&apps_smmu 0xe3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi0_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@4a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a80000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi1_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi2_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@4a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a8c000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi3_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c4_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@4a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@4a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a90000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart4_default>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_i2c5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a94000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_spi5_default>; + pinctrl-names = "default"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + usb: usb@4ef8800 { + compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; + reg = <0x0 0x04ef8800 0x0 0x400>; + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + wakeup-source; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_dwc3: usb@4e00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x04e00000 0x0 0xcd00>; + interrupts = ; + phys = <&usb_hsphy>; + phy-names = "usb2-phy"; + iommus = <&apps_smmu 0x120 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + remoteproc_mpss: remoteproc@6080000 { + compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; + reg = <0x0 0x06080000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd QCM2290_VDDCX>; + + memory-region = <&pil_modem_mem>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 12>; + }; + }; + + remoteproc_adsp: remoteproc@ab00000 { + compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; + reg = <0x0 0x0ab00000 0x0 0x100>; + + interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, + <&rpmpd QCM2290_VDD_LPI_MX>; + + memory-region = <&pil_adsp_mem>; + + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "lpass"; + qcom,remote-pid = <2>; + mboxes = <&apcs_glb 8>; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + wifi: wifi@c800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x0 0x0c800000 0x0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x1a0 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + + watchdog@f017000 { + compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; + reg = <0x0 0x0f017000 0x0 0x1000>; + interrupts = , + ; + clocks = <&sleep_clk>; + }; + + apcs_glb: mailbox@f111000 { + compatible = "qcom,qcm2290-apcs-hmss-global"; + reg = <0x0 0x0f111000 0x0 0x1000>; + #mbox-cells = <1>; + }; + + timer@f120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f120000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0f121000 0x8000>; + + frame@0 { + reg = <0x0 0x1000>, + <0x1000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@2000 { + reg = <0x2000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@3000 { + reg = <0x3000 0x1000>; + interrupts = ; + frame-number = <2>; + status = "disabled"; + }; + + frame@4000 { + reg = <0x4000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@5000 { + reg = <0x5000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@6000 { + reg = <0x6000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@7000 { + reg = <0x7000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x0f200000 0x0 0x10000>, + <0x0 0x0f300000 0x0 0x100000>; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + cpufreq_hw: cpufreq@f521000 { + compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; + reg = <0x0 0x0f521000 0x0 0x1000>; + reg-names = "freq-domain0"; + interrupts = ; + interrupt-names = "dcvsh-irq-0"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; + + thermal-zones { + mapss-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 0>; + + trips { + mapss_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mapss_crit: mapss-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 1>; + + trips { + video_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + video_crit: video-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 2>; + + trips { + wlan_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + wlan_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + wlan_crit: wlan-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 3>; + + trips { + cpuss0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss0_crit: cpuss0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 4>; + + trips { + cpuss1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpuss1_crit: cpuss1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 5>; + + trips { + mdm0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm0_crit: mdm0-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + mdm1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 6>; + + trips { + mdm1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + mdm1_crit: mdm1-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 7>; + + trips { + gpu_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + hm-center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 8>; + + trips { + hm_center_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + hm_center_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + hm_center_crit: hm-center-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camera-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&tsens0 9>; + + trips { + camera_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + camera_crit: camera-crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; From c309b9a54039053892cc5417193e9f0089073ae3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Apr 2023 17:50:33 +0200 Subject: [PATCH 0939/1040] arm64: dts: qcom: Add initial PM2250 device tree Introduce an initial device tree for the PM2250 (sometimes known as PM4125) PMIC. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-4-dae06f8830dc@linaro.org --- arch/arm64/boot/dts/qcom/pm2250.dtsi | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm2250.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm2250.dtsi b/arch/arm64/boot/dts/qcom/pm2250.dtsi new file mode 100644 index 000000000000..5f1d15db5c99 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm2250.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + */ + +#include +#include +#include +#include + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm2250", "qcom,spmi-pmic"; + reg = <0x0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + + pm2250_pwrkey: pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + debounce = <15625>; + bias-pull-up; + }; + + pm2250_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts-extended = <&spmi_bus 0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + + pm2250_gpios: gpio@c000 { + compatible = "qcom,pm2250-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm2250_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + pmic@1 { + compatible = "qcom,pm2250", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; From e18771961336647121c40cad4585caa794980887 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Apr 2023 17:50:34 +0200 Subject: [PATCH 0940/1040] arm64: dts: qcom: Add initial QTI RB1 device tree Add an initial device tree for the QTI RB1 development board, based on the QRB2210 (QCM2290 derivative) SoC. This device tree targets the SoM revision 4, a.k.a. the Mass Production SKU. To get a successful boot, run: cat arch/arm64/boot/Image.gz arch/arm64/boot/dts/qcom/qrb2210-rb1.dtb >\ .Image.gz-dtb mkbootimg \ --kernel .Image.gz-dtb \ --ramdisk some_initrd \ --output rb1-boot.img \ --pagesize 4096 \ --base 0x8000 \ --cmdline 'some cmdline' fastboot boot rb1-boot.img There's no dtbo or other craziness to worry about. For the best dev experience, you can erase boot and use fastboot boot everytime, so that the bootloader doesn't mess with you. If you have a SoM revision 3 or older (there should be a sticker on it with text like -r00, where r is the revision), you will need to apply this additional diff: aliases { - serial0 = &uart0; + serial0 = &uart4; /* UART connected to the Micro-USB port via a FTDI chip */ - &uart0 { + &uart4 { That should however only concern preproduction boards. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230403-topic-rb1_qcm-v2-5-dae06f8830dc@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 112 +++++++++++++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qrb2210-rb1.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 915ff1e0d645..c5f42cb43ee9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts new file mode 100644 index 000000000000..ef3616093289 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2023, Linaro Ltd + */ + +/dts-v1/; + +#include "qcm2290.dtsi" +#include "pm2250.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Robotics RB1"; + compatible = "qcom,qrb2210-rb1", "qcom,qrb2210", "qcom,qcm2290"; + + aliases { + serial0 = &uart0; + sdhc1 = &sdhc_1; + sdhc2 = &sdhc_2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-0 = <&key_volp_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; +}; + +&pm2250_resin { + linux,code = ; + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + non-removable; + supports-cqe; + no-sdio; + no-sd; + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdc2_state_on &sd_det_in_on>; + pinctrl-1 = <&sdc2_state_off &sd_det_in_off>; + pinctrl-names = "default", "sleep"; + no-sdio; + no-mmc; + status = "okay"; +}; + +&tlmm { + sd_det_in_on: sd-det-in-on-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sd_det_in_off: sd-det-in-off-state { + pins = "gpio88"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + key_volp_n: key-volp-n-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + output-disable; + }; +}; + +/* UART connected to the Micro-USB port via a FTDI chip */ +&uart0 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_hsphy { + status = "okay"; +}; + +&xo_board { + clock-frequency = <38400000>; +}; From d93bd4630ce163f3761aedc0b342b072bee6db6b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:40 +0100 Subject: [PATCH 0941/1040] arm64: dts: qcom: ipq8074: add compatible fallback to mailbox IPQ8074 mailbox is compatible with IPQ6018. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index fe37dcdc52c8..84e715aa4310 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -686,7 +686,8 @@ }; apcs_glb: mailbox@b111000 { - compatible = "qcom,ipq8074-apcs-apps-global"; + compatible = "qcom,ipq8074-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; clocks = <&a53pll>, <&xo>; clock-names = "pll", "xo"; From 81cd4883b1a2d7c612df9f526598e6a841ab3881 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:41 +0100 Subject: [PATCH 0942/1040] arm64: dts: qcom: msm8976: add compatible fallback to mailbox MSM8976 mailbox is compatible with MSM8994. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 05929d7a1d23..1f0bd24a074a 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1035,7 +1035,8 @@ }; apcs: mailbox@b011000 { - compatible = "qcom,msm8976-apcs-kpss-global", "syscon"; + compatible = "qcom,msm8976-apcs-kpss-global", + "qcom,msm8994-apcs-kpss-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; }; From 112f33b369e5e38119910a3365537bcc5d3d4135 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:42 +0100 Subject: [PATCH 0943/1040] arm64: dts: qcom: msm8998: add compatible fallback to mailbox MSM8998 mailbox is compatible with MSM8994. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 09b222f363c2..b150437a8355 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2489,7 +2489,8 @@ }; apcs_glb: mailbox@17911000 { - compatible = "qcom,msm8998-apcs-hmss-global"; + compatible = "qcom,msm8998-apcs-hmss-global", + "qcom,msm8994-apcs-kpss-global"; reg = <0x17911000 0x1000>; #mbox-cells = <1>; From 2d034324fdba6555fb642b127167ae5ba0e30158 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:43 +0100 Subject: [PATCH 0944/1040] arm64: dts: qcom: sdm630: add compatible fallback to mailbox SDM630 mailbox is compatible with MSM8994. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8bdb36a63474..ef63aa86ad67 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2267,7 +2267,8 @@ }; apcs_glb: mailbox@17911000 { - compatible = "qcom,sdm660-apcs-hmss-global"; + compatible = "qcom,sdm660-apcs-hmss-global", + "qcom,msm8994-apcs-kpss-global"; reg = <0x17911000 0x1000>; #mbox-cells = <1>; From fb6198bb4980cd4a7a89affe6bef4e6e81e97316 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:44 +0100 Subject: [PATCH 0945/1040] arm64: dts: qcom: sm6115: add compatible fallback to mailbox SM6115 mailbox is compatible with MSM8994. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 3426a36053ea..e90984af0da3 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -2244,7 +2244,8 @@ }; apcs_glb: mailbox@f111000 { - compatible = "qcom,sm6115-apcs-hmss-global"; + compatible = "qcom,sm6115-apcs-hmss-global", + "qcom,msm8994-apcs-kpss-global"; reg = <0x0 0x0f111000 0x0 0x1000>; #mbox-cells = <1>; From 61799f9d573fe31222b0224acbb545fae259366a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:45 +0100 Subject: [PATCH 0946/1040] arm64: dts: qcom: sm6125: add compatible fallback to mailbox SM6125 mailbox is compatible with MSM8994. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index fd577eb705f8..a6b6adee16fb 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1210,7 +1210,8 @@ }; apcs_glb: mailbox@f111000 { - compatible = "qcom,sm6125-apcs-hmss-global"; + compatible = "qcom,sm6125-apcs-hmss-global", + "qcom,msm8994-apcs-kpss-global"; reg = <0x0f111000 0x1000>; #mbox-cells = <1>; From 4c90ceae6ec093ee9a73a48c8dacaa6d1404770b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:46 +0100 Subject: [PATCH 0947/1040] arm64: dts: qcom: qcs404: add compatible fallback to mailbox QCS404 mailbox is compatible with MSM8916. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 42fc33ab8b2e..eefed585738c 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1302,7 +1302,8 @@ }; apcs_glb: mailbox@b011000 { - compatible = "qcom,qcs404-apcs-apps-global", "syscon"; + compatible = "qcom,qcs404-apcs-apps-global", + "qcom,msm8916-apcs-kpss-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; From c1393bdf181143b21cb1ad8dbad6f3840b171855 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:47 +0100 Subject: [PATCH 0948/1040] arm64: dts: qcom: sc7180: add compatible fallback to mailbox SC7180 mailbox is compatible with SDM845. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-11-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 33a4c70b0dad..ea1ffade1aa1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3418,7 +3418,8 @@ }; apss_shared: mailbox@17c00000 { - compatible = "qcom,sc7180-apss-shared"; + compatible = "qcom,sc7180-apss-shared", + "qcom,sdm845-apss-shared"; reg = <0 0x17c00000 0 0x10000>; #mbox-cells = <1>; }; From 9b2e284a5dc2d23a7102ff87fac3aa9d6b88118e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 22 Mar 2023 18:41:48 +0100 Subject: [PATCH 0949/1040] arm64: dts: qcom: sm8150: add compatible fallback to mailbox SC8150 mailbox is compatible with SDM845. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230322174148.810938-12-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 72e4ae0b6aa7..69587aaa0559 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4124,7 +4124,8 @@ }; apss_shared: mailbox@17c00000 { - compatible = "qcom,sm8150-apss-shared"; + compatible = "qcom,sm8150-apss-shared", + "qcom,sdm845-apss-shared"; reg = <0x0 0x17c00000 0x0 0x1000>; #mbox-cells = <1>; }; From 68434024dae509455bdd2a9e321a2cf58a6d0a75 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Thu, 23 Mar 2023 08:59:23 +0800 Subject: [PATCH 0950/1040] arm64: dts: qcom: Split elish dts into common dtsi and elish-boe dts There are two panel variants of xiaomi-elish, BOE and CSOT panels. In order to support both panels, so split elish dts into common dtsi and elish-boe dts. Signed-off-by: Jianhua Lu Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323005925.23179-1-lujianhua000@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 2 +- .../arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts | 13 +++++++++++++ ...mi-elish.dts => sm8250-xiaomi-elish-common.dtsi} | 4 ---- 3 files changed, 14 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts rename arch/arm64/boot/dts/qcom/{sm8250-xiaomi-elish.dts => sm8250-xiaomi-elish-common.dtsi} (99%) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index c5f42cb43ee9..7ac4e4db0b69 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -186,7 +186,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts new file mode 100644 index 000000000000..bd9ad109daf9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Jianhua Lu + */ + +/dts-v1/; + +#include "sm8250-xiaomi-elish-common.dtsi" + +/ { + model = "Xiaomi Mi Pad 5 Pro (BOE)"; + compatible = "xiaomi,elish", "qcom,sm8250"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi similarity index 99% rename from arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts rename to arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index fe7972347609..43436270edd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -3,8 +3,6 @@ * Copyright (c) 2022, 2023 Jianhua Lu */ -/dts-v1/; - #include #include #include "sm8250.dtsi" @@ -24,8 +22,6 @@ /delete-node/ &xbl_aop_mem; / { - model = "Xiaomi Mi Pad 5 Pro"; - compatible = "xiaomi,elish", "qcom,sm8250"; classis-type = "tablet"; /* required for bootloader to select correct board */ From 51c4c2bd6f314de8b1bb7b5c949d2432be19d419 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Thu, 23 Mar 2023 08:59:24 +0800 Subject: [PATCH 0951/1040] arm64: dts: qcom: sm8250-xiaomi-elish-boe: Add mdss and dsi panel Add nodes for BOE NT36523 panel found in xiaomi-elish. This panel is a dual dsi mode panel and the dsi phy type is cphy. Signed-off-by: Jianhua Lu Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323005925.23179-2-lujianhua000@gmail.com --- .../boot/dts/qcom/sm8250-xiaomi-elish-boe.dts | 5 ++ .../dts/qcom/sm8250-xiaomi-elish-common.dtsi | 75 +++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts index bd9ad109daf9..8b2ae39950ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts @@ -11,3 +11,8 @@ model = "Xiaomi Mi Pad 5 Pro (BOE)"; compatible = "xiaomi,elish", "qcom,sm8250"; }; + +&display_panel { + compatible = "xiaomi,elish-boe-nt36523"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 43436270edd9..8af6a0120a50 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include "sm8250.dtsi" #include "pm8150.dtsi" @@ -469,6 +470,76 @@ status = "okay"; }; +&dsi0 { + vdda-supply = <&vreg_l9a_1p2>; + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + qcom,master-dsi; + status = "okay"; + + display_panel: panel@0 { + reg = <0>; + vddio-supply = <&vreg_l14a_1p88>; + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1{ + reg = <1>; + + panel_in_1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + + }; + }; +}; + +&dsi0_out { + data-lanes = <0 1 2>; + remote-endpoint = <&panel_in_0>; +}; + +&dsi0_phy { + vdds-supply = <&vreg_l5a_0p88>; + phy-type = ; + status = "okay"; +}; + +&dsi1 { + vdda-supply = <&vreg_l9a_1p2>; + qcom,dual-dsi-mode; + qcom,sync-dual-dsi; + /* DSI1 is slave, so use DSI0 clocks */ + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + status = "okay"; +}; + +&dsi1_out { + data-lanes = <0 1 2>; + remote-endpoint = <&panel_in_1>; +}; + +&dsi1_phy { + vdds-supply = <&vreg_l5a_0p88>; + phy-type = ; + status = "okay"; +}; + &gmu { status = "okay"; }; @@ -533,6 +604,10 @@ }; }; +&mdss { + status = "okay"; +}; + &pcie0 { status = "okay"; }; From 8a786036c7b682c4d77abf7f396b87bc7eec98f9 Mon Sep 17 00:00:00 2001 From: Jianhua Lu Date: Thu, 23 Mar 2023 08:59:25 +0800 Subject: [PATCH 0952/1040] arm64: dts: qcom: sm8250-xiaomi-elish-csot: Add Xiaomi Mi Pad 5 Pro CSOT variant Add support for the Xiaomi Mi Pad 5 Pro CSOT variant. The CSOT variant uses China Star Optoelectronics Technology (CSOT) panel based on NT36523 display controller. Signed-off-by: Jianhua Lu Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323005925.23179-3-lujianhua000@gmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sm8250-xiaomi-elish-csot.dts | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7ac4e4db0b69..f7f564e5bda0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -187,6 +187,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-csot.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts new file mode 100644 index 000000000000..a4d5341495cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Jianhua Lu + */ + +/dts-v1/; + +#include "sm8250-xiaomi-elish-common.dtsi" + +/ { + model = "Xiaomi Mi Pad 5 Pro (CSOT)"; + compatible = "xiaomi,elish", "qcom,sm8250"; +}; + +&display_panel { + compatible = "xiaomi,elish-csot-nt36523"; + status = "okay"; +}; From 814e1461feb3491807668359bfbda14a324486c1 Mon Sep 17 00:00:00 2001 From: Lux Aliaga Date: Mon, 6 Mar 2023 14:08:15 -0300 Subject: [PATCH 0953/1040] dt-bindings: arm: qcom: Document xiaomi,laurel-sprout board Document the Xiaomi Mi A3 (xiaomi-laurel-sprout) smartphone which is based on the Snapdragon 665 SoC. Signed-off-by: Lux Aliaga Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306170817.3806-6-they@mint.lgbt --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index fb16cfe36b1e..4770d7aadb63 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -881,6 +881,7 @@ properties: - items: - enum: - sony,pdx201 + - xiaomi,laurel-sprout - const: qcom,sm6125 - items: From f8399e8a2f80adfac2e7f5dbe223eb428fdb6fe9 Mon Sep 17 00:00:00 2001 From: Lux Aliaga Date: Mon, 6 Mar 2023 14:08:14 -0300 Subject: [PATCH 0954/1040] arm64: dts: qcom: sm6125: Add UFS nodes Adds a UFS host controller node and its corresponding PHY to the sm6125 platform. Signed-off-by: Lux Aliaga Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306170817.3806-5-they@mint.lgbt --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 64 ++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a6b6adee16fb..9484752fb850 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -737,6 +737,70 @@ status = "disabled"; }; + ufs_mem_hc: ufs@4804000 { + compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x04804000 0x3000>, <0x04810000 0x8000>; + reg-names = "std", "ice"; + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "ice_core_clk"; + freq-table-hz = <50000000 240000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>, + <75000000 300000000>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + #reset-cells = <1>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + lanes-per-direction = <1>; + + iommus = <&apps_smmu 0x200 0x0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@4807000 { + compatible = "qcom,sm6125-qmp-ufs-phy"; + reg = <0x04807000 0xdb8>; + + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + #phy-cells = <0>; + + status = "disabled"; + }; + gpi_dma0: dma-controller@4a00000 { compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0x04a00000 0x60000>; From b76c8ceabe871470cee17990289e8dd39b96054e Mon Sep 17 00:00:00 2001 From: Lux Aliaga Date: Mon, 6 Mar 2023 14:08:16 -0300 Subject: [PATCH 0955/1040] arm64: dts: qcom: sm6125: Initial support for xiaomi-laurel-sprout Add support for the Xiaomi Mi A3 (xiaomi-laurel-sprout). Here's a summary on what's defined. - dmesg output to bootloader preconfigured display - USB - UFS - SD card - SMD RPM regulators - Volume Up, Down and Power buttons - Thermistors Signed-off-by: Lux Aliaga Reviewed-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230306170817.3806-7-they@mint.lgbt --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 421 ++++++++++++++++++ 2 files changed, 422 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f7f564e5bda0..79211b0e72fb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -174,6 +174,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts new file mode 100644 index 000000000000..b1038eb8cebc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -0,0 +1,421 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Lux Aliaga + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "sm6125.dtsi" +#include "pm6125.dtsi" + +/ { + model = "Xiaomi Mi A3"; + compatible = "xiaomi,laurel-sprout", "qcom,sm6125"; + chassis-type = "handset"; + + /* required for bootloader to select correct board */ + qcom,msm-id = <394 0>; /* sm6125 v1 */ + qcom,board-id = <11 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@5c000000 { + compatible = "simple-framebuffer"; + reg = <0 0x5c000000 0 (1560 * 720 * 4)>; + width = <720>; + height = <1560>; + stride = <(720 * 4)>; + format = "a8r8g8b8"; + }; + }; + + reserved-memory { + debug_mem: debug@ffb00000 { + reg = <0x0 0xffb00000 0x0 0xc0000>; + no-map; + }; + + last_log_mem: lastlog@ffbc0000 { + reg = <0x0 0xffbc0000 0x0 0x80000>; + no-map; + }; + + pstore_mem: ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc40000 0x0 0xc0000>; + record-size = <0x1000>; + console-size = <0x40000>; + msg-size = <0x20000 0x20000>; + }; + + cmdline_mem: memory@ffd00000 { + reg = <0x0 0xffd40000 0x0 0x1000>; + no-map; + }; + }; + + extcon_usb: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + thermal-zones { + rf-pa0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + quiet-thermal { + polling-delay-passive = <0>; + polling-delay = <5000>; + thermal-sensors = <&pm6125_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pm6125_adc_tm 2>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; +}; + +&hsusb_phy1 { + vdd-supply = <&vreg_l7a>; + vdda-pll-supply = <&vreg_l10a>; + vdda-phy-dpdm-supply = <&vreg_l15a>; + status = "okay"; +}; + +&pm6125_adc { + pinctrl-names = "default"; + pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm>; + + adc-chan@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "rf_pa0_therm"; + }; + + adc-chan@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "quiet_therm"; + }; + + adc-chan@52 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "camera_flash_therm"; + }; + + adc-chan@54 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "emmc_ufs_therm"; + }; +}; + +&pm6125_adc_tm { + status = "okay"; + + rf-pa0-therm@0 { + reg = <0>; + io-channels = <&pm6125_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pm6125_adc ADC5_AMUX_THM2_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + xo-therm@2 { + reg = <2>; + io-channels = <&pm6125_adc ADC5_XO_THERM_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm6125_gpios { + camera_flash_therm: camera-flash-therm-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + emmc_ufs_therm: emmc-ufs-therm-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; + + vol_up_n: vol-up-n-state { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + vreg_s6a: s6 { + regulator-min-microvolt = <936000>; + regulator-max-microvolt = <1422000>; + }; + + vreg_l1a: l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + }; + + vreg_l2a: l2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1056000>; + }; + + vreg_l3a: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1064000>; + }; + + vreg_l4a: l4 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + regulator-allow-set-load; + }; + + vreg_l5a: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + vreg_l6a: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a: l7 { + regulator-min-microvolt = <872000>; + regulator-max-microvolt = <976000>; + }; + + vreg_l8a: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + }; + + vreg_l10a: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1896000>; + regulator-allow-set-load; + }; + + vreg_l11a: l11 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1952000>; + regulator-allow-set-load; + }; + + vreg_l12a: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1996000>; + }; + + vreg_l13a: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1832000>; + }; + + vreg_l14a: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a: l15 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a: l17 { + regulator-min-microvolt = <1248000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l18a: l18 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1264000>; + regulator-allow-set-load; + }; + + vreg_l19a: l19 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + vreg_l20a: l20 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + }; + + vreg_l21a: l21 { + regulator-min-microvolt = <2600000>; + regulator-max-microvolt = <2856000>; + }; + + vreg_l22a: l22 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + vreg_l23a: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l24a: l24 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + }; +}; + +&sdc2_off_state { + sd-cd-pins { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&sdc2_on_state { + sd-cd-pins { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 98 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&vreg_l22a>; + vqmmc-supply = <&vreg_l5a>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <22 2>, <28 6>; +}; + +&ufs_mem_hc { + vcc-supply = <&vreg_l24a>; + vccq2-supply = <&vreg_l11a>; + vcc-max-microamp = <600000>; + vccq2-max-microamp = <600000>; + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l10a>; + vdda-phy-max-microamp = <51400>; + vdda-pll-max-microamp = <14200>; + vddp-ref-clk-supply = <&vreg_l18a>; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + extcon = <&extcon_usb>; +}; From e10121114e8fe10067c4c4dd1eb1241bd30c2bb3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:57:58 +0200 Subject: [PATCH 0956/1040] arm64: dts: qcom: msm8994: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 26059f861250..9dbde79f26a2 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -481,7 +481,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; ts_reset_active: ts-reset-active-state { diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 6d436d20350a..2831966be960 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -845,7 +845,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; i2c5_default: i2c5-default-state { From 8db80be2af20ccdfca2c8d3a2adaf60621c2f34e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:57:59 +0200 Subject: [PATCH 0957/1040] arm64: dts: qcom: msm8996: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4661a556772e..2b35cb3f5292 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1552,7 +1552,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; blsp2_i2c1_default: blsp2-i2c1-state { From ecdc2fe1204ff515f59385a87994ea17a8d0d6c4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:00 +0200 Subject: [PATCH 0958/1040] arm64: dts: qcom: msm8998: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 1 - arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi | 1 - arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 2 -- arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts | 3 --- 4 files changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index 8b71b1f8f300..b35e2d9f428c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -640,7 +640,6 @@ function = "gpio"; bias-disable; drive-strength = <2>; - input-enable; }; ts_int_n: ts-int-n-state { diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index ce03c7c239e5..062d56c42385 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -501,7 +501,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; ts_int_active: ts-int-active-state { diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 8e1c25b15f57..687e96068cb2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -844,7 +844,6 @@ function = "gpio"; bias-pull-up; drive-strength = <2>; - input-enable; }; chat_cam_pwr_en: chat-cam-pwr-en-default-state { @@ -873,7 +872,6 @@ function = "gpio"; bias-disable; drive-strength = <2>; - input-enable; }; ts_int_n: ts-int-n-state { diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index 7956b151c7a4..2444b87fddf7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -528,7 +528,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; mdss_dsi_active_state: mdss-dsi-active-state { @@ -620,7 +619,6 @@ function = "gpio"; drive-strength = <16>; bias-pull-up; - input-enable; }; ts_int_suspend_state: ts-int-suspend-state { @@ -642,7 +640,6 @@ function = "gpio"; bias-pull-down; drive-strength = <2>; - input-enable; }; wsa_leftspk_pwr_n_state: wsa-leftspk-pwr-n-state { From 8b58f799056b561e349bb56014f87a71ae517d10 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:01 +0200 Subject: [PATCH 0959/1040] arm64: dts: qcom: qcs404: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 04c82d1624eb..10655401528e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -296,7 +296,6 @@ drive-strength = <2>; bias-pull-up; - input-enable; }; }; From 87e1f7b1a041a37390bf4fa7913683fb4f8d00d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:02 +0200 Subject: [PATCH 0960/1040] arm64: dts: qcom: sc8280xp: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-5-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 9fb0c7bcbfdf..8fa9fbfe5d00 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2726,7 +2726,6 @@ pins = "gpio7"; function = "dmic1_data"; drive-strength = <8>; - input-enable; }; }; @@ -2744,7 +2743,6 @@ function = "dmic1_data"; drive-strength = <2>; bias-pull-down; - input-enable; }; }; @@ -2760,7 +2758,6 @@ pins = "gpio9"; function = "dmic2_data"; drive-strength = <8>; - input-enable; }; }; @@ -2778,7 +2775,6 @@ function = "dmic2_data"; drive-strength = <2>; bias-pull-down; - input-enable; }; }; From 2ee8a1525223af4d691aaa620e2d88d4ee2266c7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:03 +0200 Subject: [PATCH 0961/1040] arm64: dts: qcom: sdm845: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 3 --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 -- arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi | 1 - arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts | 2 -- arch/arm64/boot/dts/qcom/sdm845.dtsi | 5 ----- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 5 ----- 6 files changed, 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 50a1c23f747d..5c384345c05d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -778,7 +778,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; tri_state_key_default: tri-state-key-default-state { @@ -807,7 +806,6 @@ function = "mdp_vsync"; drive-strength = <2>; bias-disable; - input-enable; }; panel_esd_pin: panel-esd-state { @@ -815,7 +813,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; speaker_default: speaker-default-state { diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index bd9571a258cf..0ad891348e0c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -613,7 +613,6 @@ function = "gpio"; drive-strength = <8>; bias-pull-up; - input-enable; }; ts_int_suspend: ts-int-suspend-state { @@ -621,7 +620,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; ts_reset_active: ts-reset-active-state { diff --git a/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi index 0d7c37f39176..c15d48860646 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-wcd9340.dtsi @@ -80,7 +80,6 @@ pins = "gpio54"; function = "gpio"; - input-enable; bias-pull-down; drive-strength = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 56f2d855df78..8ae0ffccaab2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -586,7 +586,6 @@ function = "gpio"; bias-pull-down; drive-strength = <16>; - input-enable; }; ts_reset_sleep: ts-reset-sleep-state { @@ -601,7 +600,6 @@ function = "gpio"; bias-pull-down; drive-strength = <2>; - input-enable; }; sde_dsi_active: sde-dsi-active-state { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 21c710547d1b..90424442bb4a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3186,7 +3186,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; quat_mi2s_active: quat-mi2s-active-state { @@ -3202,7 +3201,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; quat_mi2s_sd0_active: quat-mi2s-sd0-active-state { @@ -3217,7 +3215,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; quat_mi2s_sd1_active: quat-mi2s-sd1-active-state { @@ -3232,7 +3229,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; quat_mi2s_sd2_active: quat-mi2s-sd2-active-state { @@ -3247,7 +3243,6 @@ function = "gpio"; drive-strength = <2>; bias-pull-down; - input-enable; }; quat_mi2s_sd3_active: quat-mi2s-sd3-active-state { diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 5c688cb6a7ce..1326c171fe72 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -606,7 +606,6 @@ pins = "gpio37"; function = "gpio"; - input-enable; bias-pull-up; drive-strength = <2>; }; @@ -615,7 +614,6 @@ pins = "gpio125"; function = "gpio"; - input-enable; bias-pull-up; drive-strength = <2>; }; @@ -624,7 +622,6 @@ pins = "gpio92"; function = "gpio"; - input-enable; bias-pull-up; drive-strength = <2>; }; @@ -633,7 +630,6 @@ pins = "gpio124"; function = "gpio"; - input-enable; bias-disable; }; @@ -641,7 +637,6 @@ pins = "gpio95"; function = "gpio"; - input-enable; bias-disable; }; }; From 36f038ad3a0779b58c2fea6b1b1df18d12d6c06d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:04 +0200 Subject: [PATCH 0962/1040] arm64: dts: qcom: sm6125: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-7-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index b22b3f9a910d..9f8a9ef398a2 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -468,7 +468,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; }; From a3752cc30e1557a7c5bbd5bda8ccd91dba0f3a06 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:05 +0200 Subject: [PATCH 0963/1040] arm64: dts: qcom: sm6350: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-8-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 2a3ad478892b..dddd6e44d280 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -367,7 +367,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; }; From 5a5fd14b22881d60911541750a4d6f66e501ea6e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:06 +0200 Subject: [PATCH 0964/1040] arm64: dts: qcom: sm8250: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 ------- 2 files changed, 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index c96cc9c90a5f..2f22d348d45d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -625,7 +625,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; ap2mdm_default: ap2mdm-default-state { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index bde8bdd2e811..c16c4231cbfa 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2433,7 +2433,6 @@ pins = "gpio10"; function = "wsa_swr_clk"; drive-strength = <2>; - input-enable; bias-pull-down; }; @@ -2441,7 +2440,6 @@ pins = "gpio11"; function = "wsa_swr_data"; drive-strength = <2>; - input-enable; bias-pull-down; }; }; @@ -2457,7 +2455,6 @@ pins = "gpio7"; function = "dmic1_data"; drive-strength = <8>; - input-enable; }; }; @@ -2475,7 +2472,6 @@ function = "dmic1_data"; drive-strength = <2>; bias-pull-down; - input-enable; }; }; @@ -2520,7 +2516,6 @@ pins = "gpio0"; function = "swr_tx_clk"; drive-strength = <2>; - input-enable; bias-pull-down; }; @@ -2528,7 +2523,6 @@ pins = "gpio1"; function = "swr_tx_data"; drive-strength = <2>; - input-enable; bias-bus-hold; }; @@ -2536,7 +2530,6 @@ pins = "gpio2"; function = "swr_tx_data"; drive-strength = <2>; - input-enable; bias-pull-down; }; }; From d1333bce9e019f1e529a8f1c83f4e2a1a8612bbf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 19:58:07 +0200 Subject: [PATCH 0965/1040] arm64: dts: qcom: sm8450: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407175807.124394-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 1 - arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi index 67538b5a557e..001fb2723fbb 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi @@ -754,7 +754,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; telec_pwr_en: telec-pwr-en-state { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 0bd205a11f2b..595533aeafc4 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3688,7 +3688,6 @@ pins = "gpio7"; function = "dmic1_data"; drive-strength = <8>; - input-enable; }; }; @@ -3704,7 +3703,6 @@ pins = "gpio9"; function = "dmic2_data"; drive-strength = <8>; - input-enable; }; }; From 536ba6c48d8e1a47d688326dfbd04ab37a6eb8dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 20:15:41 +0200 Subject: [PATCH 0966/1040] arm64: dts: qcom: sc8280xp-crd: correct pin drive-strength Fix typo in drive-strength property name. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407181541.139349-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 6b4e1541ee39..5b25d54b9591 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -870,7 +870,7 @@ pins = "gpio101"; function = "gpio"; bias-disable; - drive-strengh = <16>; + drive-strength = <16>; output-high; }; @@ -895,7 +895,7 @@ pins = "gpio48"; function = "gpio"; bias-disable; - drive-strengh = <16>; + drive-strength = <16>; output-high; }; From 47ce7e168486de0a581f5903e72ba2cbc68123ec Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 20:07:10 +0200 Subject: [PATCH 0967/1040] arm64: dts: qcom: sc8280xp-lenovo-thinkpad: correct pin drive-strength Fix typo in drive-strength property name. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407180710.128815-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index a1db3cf80c47..bdcba719fc38 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1428,7 +1428,7 @@ pins = "gpio101"; function = "gpio"; bias-disable; - drive-strengh = <16>; + drive-strength = <16>; output-high; }; @@ -1445,7 +1445,7 @@ pins = "gpio48"; function = "gpio"; bias-disable; - drive-strengh = <16>; + drive-strength = <16>; output-high; }; From 8624e6063cb15cc7ceeee6d54fc1761ab3d0baf7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 20:00:45 +0200 Subject: [PATCH 0968/1040] arm64: dts: qcom: apq8016: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Cc: Douglas Anderson Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407180045.126952-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 27ceaa94c8bd..59860a2223b8 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -729,7 +729,6 @@ function = "gpio"; drive-strength = <8>; - input-enable; bias-pull-up; }; @@ -770,7 +769,6 @@ function = "gpio"; drive-strength = <8>; - input-enable; bias-pull-up; }; }; From 087fc87e1882a44637a48cc537b49df9bec91780 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 20:06:54 +0200 Subject: [PATCH 0969/1040] arm64: dts: qcom: sm8150: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407180655.128771-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 69024f7c7f10..b039773c4465 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -479,7 +479,6 @@ pins = "gpio42"; function = "gpio"; bias-pull-up; - input-enable; }; }; From a72768eecb9d98ed5b5f75f5be02a365b5541456 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 20:06:55 +0200 Subject: [PATCH 0970/1040] arm64: dts: qcom: sm8350: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407180655.128771-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index 89382ad73133..7ae1eb0a7cce 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -877,7 +877,6 @@ function = "gpio"; drive-strength = <2>; bias-disable; - input-enable; }; sdc2_card_det_active: sd-card-det-active-state { From b12428640ebeea3ee7e7ae817e1bd345612537df Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Fri, 7 Apr 2023 18:53:42 +0200 Subject: [PATCH 0971/1040] arm64: dts: MSM8953: Add wcnss nodes Add nodes for remoteproc, smp2p and smsm to make it possible to use wifi/bt functionality on this platform. Signed-off-by: Adam Skladowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407165345.42800-2-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 130 ++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 684668170353..b351336c201c 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -326,6 +326,31 @@ }; }; + smp2p-wcnss { + compatible = "qcom,smp2p"; + qcom,smem = <451>, <431>; + + interrupts = ; + + qcom,ipc = <&apcs 8 18>; + + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + smp2p_wcnss_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + smp2p_wcnss_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smsm { compatible = "qcom,smsm"; @@ -340,6 +365,14 @@ #qcom,smem-state-cells = <1>; }; + + wcnss_smsm: wcnss@6 { + reg = <6>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; }; soc: soc@0 { @@ -630,6 +663,37 @@ drive-strength = <2>; bias-disable; }; + + wcnss_pin_a: wcnss-active-state { + + wcss-wlan2-pins { + pins = "gpio76"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan1-pins { + pins = "gpio77"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan0-pins { + pins = "gpio78"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan-pins { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1245,6 +1309,72 @@ status = "disabled"; }; + wcnss: remoteproc@a21b000 { + compatible = "qcom,pronto-v3-pil", "qcom,pronto"; + reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; + reg-names = "ccu", "dxe", "pmu"; + + memory-region = <&wcnss_fw_mem>; + + interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8953_VDDCX>, + <&rpmpd MSM8953_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&smp2p_wcnss_out 0>; + qcom,smem-state-names = "stop"; + + pinctrl-names = "default"; + pinctrl-0 = <&wcnss_pin_a>; + + status = "disabled"; + + wcnss_iris: iris { + /* Separate chip, compatible is board-specific */ + clocks = <&rpmcc RPM_SMD_RF_CLK2>; + clock-names = "xo"; + }; + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss_ctrl: wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&wcnss>; + + wcnss_bt: bluetooth { + compatible = "qcom,wcnss-bt"; + }; + + wcnss_wifi: wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", + "tx-rings-empty"; + }; + }; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; From 2bbada24e8a6c9eaf5caf015688dba0dcc3925d7 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Fri, 7 Apr 2023 18:53:43 +0200 Subject: [PATCH 0972/1040] arm64: dts: MSM8953: Add mpss nodes Add nodes for remoteproc, smp2p and smsm to make it possible to use modem functionality on this platform. Signed-off-by: Adam Skladowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407165345.42800-3-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 87 +++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index b351336c201c..615996b36c74 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -326,6 +326,31 @@ }; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupts = ; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-wcnss { compatible = "qcom,smp2p"; qcom,smem = <451>, <431>; @@ -366,6 +391,14 @@ #qcom,smem-state-cells = <1>; }; + modem_smsm: modem@1 { + reg = <1>; + interrupts = ; + + interrupt-controller; + #interrupt-cells = <2>; + }; + wcnss_smsm: wcnss@6 { reg = <6>; interrupts = ; @@ -995,6 +1028,60 @@ #size-cells = <0>; }; + mpss: remoteproc@4080000 { + compatible = "qcom,msm8953-mss-pil"; + reg = <0x04080000 0x100>, + <0x04020000 0x040>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + power-domains = <&rpmpd MSM8953_VDDCX>, + <&rpmpd MSM8953_VDDMX>, + <&rpmpd MSM8953_VDDMD>; + power-domain-names = "cx", "mx","mss"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "bus", "mem", "xo"; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&gcc GCC_MSS_BCR>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + smd-edge { + interrupts = ; + + qcom,smd-edge = <0>; + qcom,ipc = <&apcs 8 12>; + qcom,remote-pid = <1>; + + label = "modem"; + }; + }; + usb3: usb@70f8800 { compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; reg = <0x070f8800 0x400>; From e58d100fa24309291ec500f9d161ff1ade20cabd Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Fri, 7 Apr 2023 18:53:44 +0200 Subject: [PATCH 0973/1040] arm64: dts: MSM8953: Add lpass nodes Add nodes for remoteproc, smp2p and smsm in preparation for audio support on this platform. Signed-off-by: Adam Skladowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407165345.42800-4-a39.skl@gmail.com --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 141 ++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 615996b36c74..602cb188a635 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -6,6 +6,9 @@ #include #include #include +#include +#include +#include #include / { @@ -326,6 +329,30 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + + interrupts = ; + + mboxes = <&apcs 10>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-modem { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -1532,6 +1559,120 @@ status = "disabled"; }; }; + + lpass: remoteproc@c200000 { + compatible = "qcom,msm8953-adsp-pil"; + reg = <0x0c200000 0x100>; + + interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + power-domains = <&rpmpd MSM8953_VDDCX>; + power-domain-names = "cx"; + + memory-region = <&adsp_fw_mem>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + smd-edge { + interrupts = ; + + label = "lpass"; + mboxes = <&apcs 8>; + qcom,smd-edge = <1>; + qcom,remote-pid = <2>; + + apr { + compatible = "qcom,apr-v2"; + qcom,smd-channels = "apr_audio_svc"; + qcom,apr-domain = ; + #address-cells = <1>; + #size-cells = <0>; + + q6core: service@3 { + reg = ; + compatible = "qcom,q6core"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@16 { + reg = ; + qcom,sd-lines = <0 1>; + }; + dai@20 { + reg = ; + qcom,sd-lines = <0 1>; + }; + dai@127 { + reg = ; + qcom,sd-lines = <0>; + }; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@0 { + reg = <0>; + direction = ; + }; + dai@1 { + reg = <1>; + direction = ; + }; + dai@2 { + reg = <2>; + direction = ; + }; + dai@3 { + reg = <3>; + direction = ; + is-compress-dai; + }; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + }; + }; }; thermal-zones { From 2afbf43a4aec6e31dac7835e65d52c867f2be400 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 7 Apr 2023 13:50:26 +0300 Subject: [PATCH 0974/1040] soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver This takes the already existing duplicated support in both ufs-qcom and sdhci-msm drivers and makes it a dedicated driver that can be used by both mentioned drivers. The reason for this is because, staring with SM8550, the ICE IP block is shared between UFS and SDCC, which means we need to probe a dedicated device and share it between those two consumers. So let's add the ICE dedicated driver as a soc driver. Platforms that already have ICE supported, will use it as a library as the of_qcom_ice_get will return an ICE instance created for the consumer device. This allows the backwards compatibility with old-style devicetree approach. Also, add support to HW version 4.x since it works out-of-the-box with the current driver. The 4.x HW version is found on SM8550 platform. Signed-off-by: Abel Vesa Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407105029.2274111-4-abel.vesa@linaro.org --- drivers/soc/qcom/Kconfig | 4 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ice.c | 366 ++++++++++++++++++++++++++++++++++++++ include/soc/qcom/ice.h | 37 ++++ 4 files changed, 408 insertions(+) create mode 100644 drivers/soc/qcom/ice.c create mode 100644 include/soc/qcom/ice.h diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a8f283086a21..64a977e75ec4 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -275,4 +275,8 @@ config QCOM_ICC_BWMON the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high memory throughput even with lower CPU frequencies. +config QCOM_INLINE_CRYPTO_ENGINE + tristate + select QCOM_SCM + endmenu diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 6e88da899f60..0f43a88b4894 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o +obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += ice.o diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c new file mode 100644 index 000000000000..a6123ea96272 --- /dev/null +++ b/drivers/soc/qcom/ice.c @@ -0,0 +1,366 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm ICE (Inline Crypto Engine) support. + * + * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019, Google LLC + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include + +#include + +#include + +#define AES_256_XTS_KEY_SIZE 64 + +/* QCOM ICE registers */ +#define QCOM_ICE_REG_VERSION 0x0008 +#define QCOM_ICE_REG_FUSE_SETTING 0x0010 +#define QCOM_ICE_REG_BIST_STATUS 0x0070 +#define QCOM_ICE_REG_ADVANCED_CONTROL 0x1000 + +/* BIST ("built-in self-test") status flags */ +#define QCOM_ICE_BIST_STATUS_MASK GENMASK(31, 28) + +#define QCOM_ICE_FUSE_SETTING_MASK 0x1 +#define QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK 0x2 +#define QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK 0x4 + +#define qcom_ice_writel(engine, val, reg) \ + writel((val), (engine)->base + (reg)) + +#define qcom_ice_readl(engine, reg) \ + readl((engine)->base + (reg)) + +struct qcom_ice { + struct device *dev; + void __iomem *base; + struct device_link *link; + + struct clk *core_clk; +}; + +static bool qcom_ice_check_supported(struct qcom_ice *ice) +{ + u32 regval = qcom_ice_readl(ice, QCOM_ICE_REG_VERSION); + struct device *dev = ice->dev; + int major = FIELD_GET(GENMASK(31, 24), regval); + int minor = FIELD_GET(GENMASK(23, 16), regval); + int step = FIELD_GET(GENMASK(15, 0), regval); + + /* For now this driver only supports ICE version 3 and 4. */ + if (major != 3 && major != 4) { + dev_warn(dev, "Unsupported ICE version: v%d.%d.%d\n", + major, minor, step); + return false; + } + + dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", + major, minor, step); + + /* If fuses are blown, ICE might not work in the standard way. */ + regval = qcom_ice_readl(ice, QCOM_ICE_REG_FUSE_SETTING); + if (regval & (QCOM_ICE_FUSE_SETTING_MASK | + QCOM_ICE_FORCE_HW_KEY0_SETTING_MASK | + QCOM_ICE_FORCE_HW_KEY1_SETTING_MASK)) { + dev_warn(dev, "Fuses are blown; ICE is unusable!\n"); + return false; + } + + return true; +} + +static void qcom_ice_low_power_mode_enable(struct qcom_ice *ice) +{ + u32 regval; + + regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL); + + /* Enable low power mode sequence */ + regval |= 0x7000; + qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL); +} + +static void qcom_ice_optimization_enable(struct qcom_ice *ice) +{ + u32 regval; + + /* ICE Optimizations Enable Sequence */ + regval = qcom_ice_readl(ice, QCOM_ICE_REG_ADVANCED_CONTROL); + regval |= 0xd807100; + /* ICE HPG requires delay before writing */ + udelay(5); + qcom_ice_writel(ice, regval, QCOM_ICE_REG_ADVANCED_CONTROL); + udelay(5); +} + +/* + * Wait until the ICE BIST (built-in self-test) has completed. + * + * This may be necessary before ICE can be used. + * Note that we don't really care whether the BIST passed or failed; + * we really just want to make sure that it isn't still running. This is + * because (a) the BIST is a FIPS compliance thing that never fails in + * practice, (b) ICE is documented to reject crypto requests if the BIST + * fails, so we needn't do it in software too, and (c) properly testing + * storage encryption requires testing the full storage stack anyway, + * and not relying on hardware-level self-tests. + */ +static int qcom_ice_wait_bist_status(struct qcom_ice *ice) +{ + u32 regval; + int err; + + err = readl_poll_timeout(ice->base + QCOM_ICE_REG_BIST_STATUS, + regval, !(regval & QCOM_ICE_BIST_STATUS_MASK), + 50, 5000); + if (err) + dev_err(ice->dev, "Timed out waiting for ICE self-test to complete\n"); + + return err; +} + +int qcom_ice_enable(struct qcom_ice *ice) +{ + qcom_ice_low_power_mode_enable(ice); + qcom_ice_optimization_enable(ice); + + return qcom_ice_wait_bist_status(ice); +} +EXPORT_SYMBOL_GPL(qcom_ice_enable); + +int qcom_ice_resume(struct qcom_ice *ice) +{ + struct device *dev = ice->dev; + int err; + + err = clk_prepare_enable(ice->core_clk); + if (err) { + dev_err(dev, "failed to enable core clock (%d)\n", + err); + return err; + } + + return qcom_ice_wait_bist_status(ice); +} +EXPORT_SYMBOL_GPL(qcom_ice_resume); + +int qcom_ice_suspend(struct qcom_ice *ice) +{ + clk_disable_unprepare(ice->core_clk); + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_ice_suspend); + +int qcom_ice_program_key(struct qcom_ice *ice, + u8 algorithm_id, u8 key_size, + const u8 crypto_key[], u8 data_unit_size, + int slot) +{ + struct device *dev = ice->dev; + union { + u8 bytes[AES_256_XTS_KEY_SIZE]; + u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)]; + } key; + int i; + int err; + + /* Only AES-256-XTS has been tested so far. */ + if (algorithm_id != QCOM_ICE_CRYPTO_ALG_AES_XTS || + key_size != QCOM_ICE_CRYPTO_KEY_SIZE_256) { + dev_err_ratelimited(dev, + "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n", + algorithm_id, key_size); + return -EINVAL; + } + + memcpy(key.bytes, crypto_key, AES_256_XTS_KEY_SIZE); + + /* The SCM call requires that the key words are encoded in big endian */ + for (i = 0; i < ARRAY_SIZE(key.words); i++) + __cpu_to_be32s(&key.words[i]); + + err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE, + QCOM_SCM_ICE_CIPHER_AES_256_XTS, + data_unit_size); + + memzero_explicit(&key, sizeof(key)); + + return err; +} +EXPORT_SYMBOL_GPL(qcom_ice_program_key); + +int qcom_ice_evict_key(struct qcom_ice *ice, int slot) +{ + return qcom_scm_ice_invalidate_key(slot); +} +EXPORT_SYMBOL_GPL(qcom_ice_evict_key); + +static struct qcom_ice *qcom_ice_create(struct device *dev, + void __iomem *base) +{ + struct qcom_ice *engine; + + if (!qcom_scm_is_available()) + return ERR_PTR(-EPROBE_DEFER); + + if (!qcom_scm_ice_available()) { + dev_warn(dev, "ICE SCM interface not found\n"); + return NULL; + } + + engine = devm_kzalloc(dev, sizeof(*engine), GFP_KERNEL); + if (!engine) + return ERR_PTR(-ENOMEM); + + engine->dev = dev; + engine->base = base; + + /* + * Legacy DT binding uses different clk names for each consumer, + * so lets try those first. If none of those are a match, it means + * the we only have one clock and it is part of the dedicated DT node. + * Also, enable the clock before we check what HW version the driver + * supports. + */ + engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + + if (!qcom_ice_check_supported(engine)) + return ERR_PTR(-EOPNOTSUPP); + + dev_dbg(dev, "Registered Qualcomm Inline Crypto Engine\n"); + + return engine; +} + +/** + * of_qcom_ice_get() - get an ICE instance from a DT node + * @dev: device pointer for the consumer device + * + * This function will provide an ICE instance either by creating one for the + * consumer device if its DT node provides the 'ice' reg range and the 'ice' + * clock (for legacy DT style). On the other hand, if consumer provides a + * phandle via 'qcom,ice' property to an ICE DT, the ICE instance will already + * be created and so this function will return that instead. + * + * Return: ICE pointer on success, NULL if there is no ICE data provided by the + * consumer or ERR_PTR() on error. + */ +struct qcom_ice *of_qcom_ice_get(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct qcom_ice *ice; + struct device_node *node; + struct resource *res; + void __iomem *base; + + if (!dev || !dev->of_node) + return ERR_PTR(-ENODEV); + + /* + * In order to support legacy style devicetree bindings, we need + * to create the ICE instance using the consumer device and the reg + * range called 'ice' it provides. + */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ice"); + if (res) { + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return ERR_CAST(base); + + /* create ICE instance using consumer dev */ + return qcom_ice_create(&pdev->dev, base); + } + + /* + * If the consumer node does not provider an 'ice' reg range + * (legacy DT binding), then it must at least provide a phandle + * to the ICE devicetree node, otherwise ICE is not supported. + */ + node = of_parse_phandle(dev->of_node, "qcom,ice", 0); + if (!node) + return NULL; + + pdev = of_find_device_by_node(node); + if (!pdev) { + dev_err(dev, "Cannot find device node %s\n", node->name); + ice = ERR_PTR(-EPROBE_DEFER); + goto out; + } + + ice = platform_get_drvdata(pdev); + if (!ice) { + dev_err(dev, "Cannot get ice instance from %s\n", + dev_name(&pdev->dev)); + platform_device_put(pdev); + ice = ERR_PTR(-EPROBE_DEFER); + goto out; + } + + ice->link = device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER); + if (!ice->link) { + dev_err(&pdev->dev, + "Failed to create device link to consumer %s\n", + dev_name(dev)); + platform_device_put(pdev); + ice = ERR_PTR(-EINVAL); + } + +out: + of_node_put(node); + + return ice; +} +EXPORT_SYMBOL_GPL(of_qcom_ice_get); + +static int qcom_ice_probe(struct platform_device *pdev) +{ + struct qcom_ice *engine; + void __iomem *base; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_warn(&pdev->dev, "ICE registers not found\n"); + return PTR_ERR(base); + } + + engine = qcom_ice_create(&pdev->dev, base); + if (IS_ERR(engine)) + return PTR_ERR(engine); + + platform_set_drvdata(pdev, engine); + + return 0; +} + +static const struct of_device_id qcom_ice_of_match_table[] = { + { .compatible = "qcom,inline-crypto-engine" }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table); + +static struct platform_driver qcom_ice_driver = { + .probe = qcom_ice_probe, + .driver = { + .name = "qcom-ice", + .of_match_table = qcom_ice_of_match_table, + }, +}; + +module_platform_driver(qcom_ice_driver); + +MODULE_DESCRIPTION("Qualcomm Inline Crypto Engine driver"); +MODULE_LICENSE("GPL"); diff --git a/include/soc/qcom/ice.h b/include/soc/qcom/ice.h new file mode 100644 index 000000000000..5870a94599a2 --- /dev/null +++ b/include/soc/qcom/ice.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef __QCOM_ICE_H__ +#define __QCOM_ICE_H__ + +#include + +struct qcom_ice; + +enum qcom_ice_crypto_key_size { + QCOM_ICE_CRYPTO_KEY_SIZE_INVALID = 0x0, + QCOM_ICE_CRYPTO_KEY_SIZE_128 = 0x1, + QCOM_ICE_CRYPTO_KEY_SIZE_192 = 0x2, + QCOM_ICE_CRYPTO_KEY_SIZE_256 = 0x3, + QCOM_ICE_CRYPTO_KEY_SIZE_512 = 0x4, +}; + +enum qcom_ice_crypto_alg { + QCOM_ICE_CRYPTO_ALG_AES_XTS = 0x0, + QCOM_ICE_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1, + QCOM_ICE_CRYPTO_ALG_AES_ECB = 0x2, + QCOM_ICE_CRYPTO_ALG_ESSIV_AES_CBC = 0x3, +}; + +int qcom_ice_enable(struct qcom_ice *ice); +int qcom_ice_resume(struct qcom_ice *ice); +int qcom_ice_suspend(struct qcom_ice *ice); +int qcom_ice_program_key(struct qcom_ice *ice, + u8 algorithm_id, u8 key_size, + const u8 crypto_key[], u8 data_unit_size, + int slot); +int qcom_ice_evict_key(struct qcom_ice *ice, int slot); +struct qcom_ice *of_qcom_ice_get(struct device *dev); +#endif /* __QCOM_ICE_H__ */ From b8630c48b43fcf77039c04a1d30153e283cf41b4 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 7 Apr 2023 13:50:29 +0300 Subject: [PATCH 0975/1040] arm64: dts: qcom: sm8550: Add the Inline Crypto Engine node Add support for UFS ICE by adding the qcom,ice property and the ICE dedicated devicetree node. Signed-off-by: Abel Vesa Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407105029.2274111-7-abel.vesa@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 70ace9f151a8..49de420bc1af 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1925,9 +1925,18 @@ <0 0>, <0 0>, <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; + ice: crypto@1d88000 { + compatible = "qcom,sm8550-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; From f6ff91a47ac57cb1118d94020302617b6b22c0d1 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 7 Apr 2023 13:50:24 +0300 Subject: [PATCH 0976/1040] dt-bindings: crypto: Add Qualcomm Inline Crypto Engine Add schema file for new Qualcomm Inline Crypto Engine driver. Signed-off-by: Abel Vesa Reviewed-by: Krzysztof Kozlowski Reviewed-by: Eric Biggers Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407105029.2274111-2-abel.vesa@linaro.org --- .../crypto/qcom,inline-crypto-engine.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml new file mode 100644 index 000000000000..92e1d76e29ee --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine + +maintainers: + - Bjorn Andersson + +properties: + compatible: + items: + - enum: + - qcom,sm8550-inline-crypto-engine + - const: qcom,inline-crypto-engine + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include + + crypto@1d88000 { + compatible = "qcom,sm8550-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x01d88000 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; +... From d4a7e17f402de8ebdbae4844b011a5b18f93e341 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 24 Mar 2023 21:22:40 +0100 Subject: [PATCH 0977/1040] arm64: dts: qcom: msm8916-thwc-ufi001c: add function to pin config Bindings require pin configuration nodes to have the function, even if it is GPIO: msm8916-thwc-ufi001c.dtb: pinctrl@1000000: sim-ctrl-default-state: 'oneOf' conditional failed, one must be fixed: 'esim-sel-pins', 'sim-en-pins', 'sim-sel-pins' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230324202244.744271-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts index 8433c9710b1c..978f0abcdf8f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts @@ -44,18 +44,21 @@ sim_ctrl_default: sim-ctrl-default-state { esim-sel-pins { pins = "gpio0", "gpio3"; + function = "gpio"; bias-disable; output-low; }; sim-en-pins { pins = "gpio1"; + function = "gpio"; bias-disable; output-low; }; sim-sel-pins { pins = "gpio2"; + function = "gpio"; bias-disable; output-high; }; From 8b0ac59c2da69aaf8e65c6bd648a06b755975302 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 7 Apr 2023 21:54:41 +0200 Subject: [PATCH 0978/1040] arm64: dts: qcom: sm6115-j606f: Add ramoops node Add a ramoops node to enable retrieving crash logs. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406-topic-lenovo_features-v2-1-625d7cb4a944@linaro.org --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 10c9d338446c..cd47fbc993ba 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -52,6 +52,17 @@ wakeup-source; }; }; + + reserved-memory { + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x1000>; + console-size = <0x40000>; + ftrace-size = <0x20000>; + ecc-size = <16>; + }; + }; }; &dispcc { From ecc61a207d0fad45ba991e0ce0273382b20bb226 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 7 Apr 2023 21:54:42 +0200 Subject: [PATCH 0979/1040] arm64: dts: qcom: sm6115: Add RMTFS Add a node for RMTFS and associate it with MSA and NAV IDs to enable modem functionality on SM6115. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406-topic-lenovo_features-v2-2-625d7cb4a944@linaro.org --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index e90984af0da3..631ca327e064 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -290,6 +291,15 @@ reg = <0x0 0x60000000 0x0 0x3900000>; no-map; }; + + rmtfs_mem: memory@89b01000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x89b01000 0x0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; }; rpm-glink { From 7584284537c2a82227ed2ea359b2c53f28e6abbf Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 7 Apr 2023 21:54:43 +0200 Subject: [PATCH 0980/1040] arm64: dts: qcom: sm6115p-j606f: Enable remoteprocs Enable the [AC]DSP and MPSS and specify the firmware paths. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406-topic-lenovo_features-v2-3-625d7cb4a944@linaro.org --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index cd47fbc993ba..bc232deb802b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -89,6 +89,21 @@ status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/sm6115/LENOVO/J606F/adsp.mbn"; + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm6115/LENOVO/J606F/cdsp.mbn"; + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm6115/LENOVO/J606F/modem.mbn"; + status = "okay"; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm6125-regulators"; From 137e5c267232c89b2284ea44229545d4820bcb26 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 7 Apr 2023 21:54:44 +0200 Subject: [PATCH 0981/1040] arm64: dts: qcom: sm6115p-j606f: Enable ATH10K WiFi Enable the onboard QCA Wi-Fi. HW identifiers for reference: qmi chip_id 0x320 chip_family 0x4001 board_id 0xff soc_id 0x400e0000 Firmware sources: /vendor/firmware_mnt/image/wlanmdsp.bin -> qcom/.../wlanmdsp.mbn /vendor/firmware_mnt/image/bdwlan.bXX [1] -> [2] -> ath10k/.../board-2.bin [3] -> ath10k/.../firmware-5.bin Not sure where 3 comes from on the device itself, gotta investigate that.. According to [4], it's called WCN3990_STRAIT. [1] XX = board_id printed when the file is missing or by your downstream kernel firmware loader in the dmesg; if XX=ff, use bdwlan.bin [2] https://github.com/jhugo/linux/blob/5.5rc2_wifi/README [3] https://github.com/kvalo/ath10k-firmware/blob/master/WCN3990/hw1.0/HL3.1/WLAN.HL.3.1-01040-QCAHLSWMTPLZ-1/firmware-5.bin [4] https://git.codelinaro.org/clo/la/platform/vendor/qcom-opensource/wlan/qca-wifi-host-cmn/-/blob/LA.VENDOR.1.0.r1-20700-WAIPIO.QSSI13.0/hif/src/hif_hw_version.h#L55 Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230406-topic-lenovo_features-v2-4-625d7cb4a944@linaro.org --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index bc232deb802b..ea3340d31110 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -315,6 +315,15 @@ status = "okay"; }; +&wifi { + vdd-0.8-cx-mx-supply = <&pm6125_l8>; + vdd-1.8-xo-supply = <&pm6125_l16>; + vdd-1.3-rfa-supply = <&pm6125_l17>; + vdd-3.3-ch0-supply = <&pm6125_l23>; + qcom,ath10k-calibration-variant = "Lenovo_P11"; + status = "okay"; +}; + &xo_board { clock-frequency = <19200000>; }; From a9e76cf1146b4911b14c102f5237e28abbbccfef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 7 Apr 2023 21:26:05 +0200 Subject: [PATCH 0982/1040] arm64: dts: qcom: sdm630: move DSI opp-table out of DSI node The DSI OPP table on SDM630 is used by one DSI0, but on SDM660 is shared by two nodes (DSI0 and DSI1), thus it should be rather in top-level, not in DSI0. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230407192605.168666-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 38 ++++++++++++++-------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index ef63aa86ad67..37e72b1c56dc 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -328,6 +328,25 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-262500000 { + opp-hz = /bits/ 64 <262500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -1591,25 +1610,6 @@ status = "disabled"; - dsi_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-131250000 { - opp-hz = /bits/ 64 <131250000>; - required-opps = <&rpmpd_opp_svs>; - }; - - opp-210000000 { - opp-hz = /bits/ 64 <210000000>; - required-opps = <&rpmpd_opp_svs_plus>; - }; - - opp-262500000 { - opp-hz = /bits/ 64 <262500000>; - required-opps = <&rpmpd_opp_nom>; - }; - }; - ports { #address-cells = <1>; #size-cells = <0>; From f6b161efbb456b11731a4afa330c82223e883832 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Thu, 23 Mar 2023 15:01:19 +0530 Subject: [PATCH 0983/1040] dt-bindings: arm: qcom: document MI01.6 board based on IPQ5332 family Document the MI01.6 (Reference Design Platform 468) board based on IPQ5332 family of SoCs. Signed-off-by: Kathiravan T Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323093120.20558-2-quic_kathirav@quicinc.com --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 4770d7aadb63..785b969294a8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -86,6 +86,7 @@ description: | adp ap-al02-c7 ap-mi01.2 + ap-mi01.6 cdp cp01-c1 dragonboard @@ -330,6 +331,7 @@ properties: - items: - enum: - qcom,ipq5332-ap-mi01.2 + - qcom,ipq5332-ap-mi01.6 - const: qcom,ipq5332 - items: From f1d33c902a1be727416fce3161db37a84d3f38d1 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Thu, 23 Mar 2023 15:01:20 +0530 Subject: [PATCH 0984/1040] arm64: dts: qcom: ipq5332: add support for the RDP468 variant Add the initial device tree support for the Reference Design Platform(RDP) 468 based on IPQ5332 family of SoCs. This patch carries the support for Console UART, SPI NOR, eMMC. Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230323093120.20558-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 103 ++++++++++++++++++++ 2 files changed, 104 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 79211b0e72fb..e0e2def48470 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts new file mode 100644 index 000000000000..3b6a5cb8bf07 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP468 board device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5332.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6"; + compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332"; + + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&blsp1_spi0 { + pinctrl-0 = <&spi_0_data_clk_pins &spi_0_cs_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + }; +}; + +&sdhc { + bus-width = <4>; + max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio13"; + function = "sdc_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio12"; + function = "sdc_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "sdc_data"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + spi_0_data_clk_pins: spi-0-data-clk-state { + pins = "gpio14", "gpio15", "gpio16"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-down; + }; + + spi_0_cs_pins: spi-0-cs-state { + pins = "gpio17"; + function = "blsp0_spi"; + drive-strength = <2>; + bias-pull-up; + }; +}; From a6d1d862638b51f2a874948f75fd7284d066f900 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 31 Mar 2023 20:29:14 +0530 Subject: [PATCH 0985/1040] ARM: dts: qcom: sdx55: Move reset and wake gpios to board dts The reset and wake properties in the PCIe EP node belong to the board dts as they can be customized per board design. So let's move them from SoC dtsi. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230331145915.11653-1-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 3 +++ arch/arm/boot/dts/qcom-sdx55.dtsi | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index 81f33eba39e5..b73b707342af 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -255,6 +255,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default &pcie_ep_wake_default>; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; }; &qpic_bam { diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 9148a840b8a0..342c3d14001e 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -421,8 +421,6 @@ ; interrupt-names = "global", "doorbell"; - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; From 23fbf5339d4b18858bcd38811c0eb96df00e8289 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Fri, 31 Mar 2023 20:29:15 +0530 Subject: [PATCH 0986/1040] ARM: dts: qcom: sdx55-fn980: Move "status" property to the end of node To align with rest of the devicetree files, let's move the "status" property to the end of the nodes. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230331145915.11653-2-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index b73b707342af..8fadc6e70692 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -243,21 +243,21 @@ }; &pcie_phy { - status = "okay"; - vdda-phy-supply = <&vreg_l1e_bb_1p2>; vdda-pll-supply = <&vreg_l4e_bb_0p875>; + + status = "okay"; }; &pcie_ep { - status = "okay"; - pinctrl-names = "default"; pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default &pcie_ep_wake_default>; reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; }; &qpic_bam { @@ -280,8 +280,8 @@ }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + status = "okay"; }; &tlmm { @@ -308,16 +308,18 @@ }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4e_bb_0p875>; vdda33-supply = <&vreg_l10e_3p1>; vdda18-supply = <&vreg_l5e_bb_1p7>; + + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4e_bb_0p875>; vdda-pll-supply = <&vreg_l1e_bb_1p2>; + + status = "okay"; }; &usb { From 1642ab96efa427f88e8a54c11b01b1b333ce58bd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:51 +0200 Subject: [PATCH 0987/1040] arm64: dts: qcom: sm8150: Don't start Adreno in headless mode Now that there's display support, there is no reason to assume the default mode for Adreno should be headless. Keep it like that for boards that previously enabled it, so as not to create regressions though. Tested-by: Marijn Suijten # On Sony Xperia 5 Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-3-2dede22dd7f7@linaro.org --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 5 +++++ arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 5 +++++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +--------- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 8f014a232526..c0200e7f3f74 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -359,6 +359,11 @@ }; &gpu { + /* + * NOTE: "amd,imageon" makes Adreno start in headless mode, remove it + * after display support is added on this board. + */ + compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index eff995a07ab7..34ec84916bdd 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -354,6 +354,11 @@ }; &gpu { + /* + * NOTE: "amd,imageon" makes Adreno start in headless mode, remove it + * after display support is added on this board. + */ + compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 69587aaa0559..39e43a46bb30 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2153,15 +2153,7 @@ }; gpu: gpu@2c00000 { - /* - * note: the amd,imageon compatible makes it possible - * to use the drm/msm driver without the display node, - * make sure to remove it when display node is added - */ - compatible = "qcom,adreno-640.1", - "qcom,adreno", - "amd,imageon"; - + compatible = "qcom,adreno-640.1", "qcom,adreno"; reg = <0 0x02c00000 0 0x40000>; reg-names = "kgsl_3d0_reg_memory"; From b53ae6b63181f4575fc62cd0efb341c8151b0a74 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:52 +0200 Subject: [PATCH 0988/1040] arm64: dts: qcom: sm8150: Add GPU speedbin support SM8150 has (at least) two GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Tested-by: Marijn Suijten # On Sony Xperia 5 (speed bin 0x3) Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-4-2dede22dd7f7@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 39e43a46bb30..2273fa571988 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -950,6 +950,17 @@ status = "disabled"; }; + qfprom: efuse@784000 { + compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@133 { + reg = <0x133 0x1>; + bits = <5 3>; + }; + }; qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; @@ -2165,44 +2176,52 @@ qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + status = "disabled"; zap-shader { memory-region = <&gpu_mem>; }; - /* note: downstream checks gpu binning for 675 Mhz */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-675000000 { opp-hz = /bits/ 64 <675000000>; opp-level = ; + opp-supported-hw = <0x2>; }; opp-585000000 { opp-hz = /bits/ 64 <585000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-499200000 { opp-hz = /bits/ 64 <499200000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-427000000 { opp-hz = /bits/ 64 <427000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-345000000 { opp-hz = /bits/ 64 <345000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; opp-level = ; + opp-supported-hw = <0x3>; }; }; }; From 2a50d1a038be17972220a810c28e9b777cdfcb22 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 31 Mar 2023 03:14:53 +0200 Subject: [PATCH 0989/1040] arm64: dts: qcom: sm8250: Add GPU speedbin support SM8250 has (at least) four GPU speed bins. With the support added on the driver side, wire up bin detection in the DTS to restrict lower-quality SKUs from running at frequencies they were not validated at. Tested-by: Marijn Suijten # On Sony Xperia 5 II (speed bin 0x7) Reviewed-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-5-2dede22dd7f7@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c16c4231cbfa..7bea916900e2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -960,6 +960,18 @@ #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x8ff>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@19b { + reg = <0x19b 0x1>; + bits = <5 3>; + }; + }; + rng: rng@793000 { compatible = "qcom,prng-ee"; reg = <0 0x00793000 0 0x1000>; @@ -2550,49 +2562,58 @@ qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + status = "disabled"; zap-shader { memory-region = <&gpu_mem>; }; - /* note: downstream checks gpu binning for 670 Mhz */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-670000000 { opp-hz = /bits/ 64 <670000000>; opp-level = ; + opp-supported-hw = <0xa>; }; opp-587000000 { opp-hz = /bits/ 64 <587000000>; opp-level = ; + opp-supported-hw = <0xb>; }; opp-525000000 { opp-hz = /bits/ 64 <525000000>; opp-level = ; + opp-supported-hw = <0xf>; }; opp-490000000 { opp-hz = /bits/ 64 <490000000>; opp-level = ; + opp-supported-hw = <0xf>; }; opp-441600000 { opp-hz = /bits/ 64 <441600000>; opp-level = ; + opp-supported-hw = <0xf>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; opp-level = ; + opp-supported-hw = <0xf>; }; opp-305000000 { opp-hz = /bits/ 64 <305000000>; opp-level = ; + opp-supported-hw = <0xf>; }; }; }; From 61b006389bb7af6da29be4b1c2b93708ffe383a4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Apr 2023 08:11:29 +0200 Subject: [PATCH 0990/1040] arm64: dts: qcom: sm8550: add Soundwire controllers Add nodes for LPASS Soundwire v2.0.0 controllers. Use labels with indices matching downstream DTS, to make any comparisons easier. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230405061129.143553-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 109 +++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 49de420bc1af..f110d6cc195d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2011,6 +2011,33 @@ #sound-dai-cells = <1>; }; + swr3: soundwire-controller@6ab0000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06ab0000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsa2macro>; + clock-names = "iface"; + label = "WSA2"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + lpass_rxmacro: codec@6ac0000 { compatible = "qcom,sm8550-lpass-rx-macro"; reg = <0 0x06ac0000 0 0x1000>; @@ -2030,6 +2057,33 @@ #sound-dai-cells = <1>; }; + swr1: soundwire-controller@6ad0000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06ad0000 0 0x10000>; + interrupts = ; + clocks = <&lpass_rxmacro>; + clock-names = "iface"; + label = "RX"; + + qcom,din-ports = <0>; + qcom,dout-ports = <10>; + + qcom,ports-sinterval = <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + lpass_txmacro: codec@6ae0000 { compatible = "qcom,sm8550-lpass-tx-macro"; reg = <0 0x06ae0000 0 0x1000>; @@ -2068,6 +2122,61 @@ #sound-dai-cells = <1>; }; + swr0: soundwire-controller@6b10000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06b10000 0 0x10000>; + interrupts = ; + clocks = <&lpass_wsamacro>; + clock-names = "iface"; + label = "WSA"; + + qcom,din-ports = <4>; + qcom,dout-ports = <9>; + + qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; + qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + + swr2: soundwire-controller@6d30000 { + compatible = "qcom,soundwire-v2.0.0"; + reg = <0 0x06d30000 0 0x10000>; + interrupts = , + ; + interrupt-names = "core", "wakeup"; + clocks = <&lpass_vamacro>; + clock-names = "iface"; + label = "TX"; + + qcom,din-ports = <4>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; + + #address-cells = <2>; + #size-cells = <0>; + #sound-dai-cells = <1>; + status = "disabled"; + }; + lpass_vamacro: codec@6d44000 { compatible = "qcom,sm8550-lpass-va-macro"; reg = <0 0x06d44000 0 0x1000>; From 562d222f23f0fbdf76a8ba87ce0c9cdcd39e30f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Apr 2023 18:01:16 +0200 Subject: [PATCH 0991/1040] arm64: dts: imx8mp: Add support for Data Modul i.MX8M Plus eDM SBC Add support for Data Modul i.MX8M Plus eDM SBC board. This is an evaluation board for various custom display units. Currently supported are serial console, ethernet, eMMC, SD, SPI NOR, USB host and USB OTG. Reviewed-by: Fabio Estevam Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx8mp-data-modul-edm-sbc.dts | 977 ++++++++++++++++++ 2 files changed, 978 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e2f86df16ab0..ef7d17aef58f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -89,6 +89,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts new file mode 100644 index 000000000000..13674dc64be9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts @@ -0,0 +1,977 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "Data Modul i.MX8M Plus eDM SBC"; + compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp"; + + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + /* There are 1/2/4 GiB options, adjusted by bootloader. */ + reg = <0x0 0x40000000 0 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_backlight>; + brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 5000000 0>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + clk_xtal25: clock-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + panel: panel { + /* Compatible string is filled in by panel board DT Overlay. */ + backlight = <&backlight>; + power-supply = <®_panel_vcc>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_panel_vcc: regulator-panel-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_vcc_reg>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "PANEL_VCC"; + /* GPIO flags are ignored, enable-active-high applies. */ + gpio = <&gpio3 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3_SD"; + /* GPIO flags are ignored, enable-active-high applies. */ + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; /* SD2_RESET */ + enable-active-high; + off-on-delay-us = <12000>; + startup-delay-us = <100>; + vin-supply = <&buck4>; + }; + + watchdog { /* TPS3813 */ + compatible = "linux,wdt-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_watchdog_gpio>; + always-running; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + hw_algo = "level"; + /* Reset triggers in 2..3 seconds */ + hw_margin_ms = <1500>; + /* Disabled by default */ + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { /* W25Q128JVEI */ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; /* Up to 133 MHz */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; + +&ecspi2 { /* Feature connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless feature board plugged in. */ + status = "disabled"; +}; + +&ecspi3 { /* Display connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&eqos { /* First ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <&phy_eqos>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8031 PHY */ + phy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + /* + * Dedicated ENET_WOL# signal is unused, the PHY + * can wake the SoC up via INT signal as well. + */ + interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + qca,keep-pll-enabled; + vddio-supply = <&vddio_eqos>; + + vddio_eqos: vddio-regulator { + regulator-name = "VDDIO_EQOS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh_eqos: vddh-regulator { + regulator-name = "VDDH_EQOS"; + }; + }; + }; +}; + +&fec { /* Second ethernet */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-handle = <&phy_fec>; + phy-mode = "rgmii-id"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8031 PHY */ + phy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + /* + * Dedicated ENET_WOL# signal is unused, the PHY + * can wake the SoC up via INT signal as well. + */ + interrupts-extended = <&gpio2 2 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + qca,keep-pll-enabled; + vddio-supply = <&vddio_fec>; + + vddio_fec: vddio-regulator { + regulator-name = "VDDIO_FEC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh_fec: vddh-regulator { + regulator-name = "VDDH_FEC"; + }; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "USBHUB_RESET#", "WDOG_B#", "PMIC_INT#", + "", "M2_PCIE_RST#", "M2_PCIE_WAKE#", "GPIO5_IO03", + "GPIO5_IO04", "PDM_SEL", "ENET_WOL#", "ENET_INT#", + "", "", "", "ENET_RST#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "ENET2_INT#", "", "", "", "", "", + "WDOG_KICK#", "ENET2_RST#", "CAN_INT#", "RTC_IRQ#", + "", "", "", "", + "", "", "", "SD2_RESET#", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", + "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", + "CSI2_PD_1V8", "CSI2_RESET_1V8#", "", "", + "", "", "EEPROM_WP_1V8#", "", "", "", "", "", + "MEMCFG0", "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", + "", "M2_W_DISABLE1_1V8#", + "M2_W_DISABLE2_1V8#", "", "I2C5_SCL_3V3", "I2C5_SDA_3V3", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "DSI_RESET_1V8#", "MEMCFG2", "", "MEMCFG1", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "GRAPHICS_PRSNT_1V8#", "DSI_IRQ_1V8#", + "", "DIS_USB_DN1", "DIS_USB_DN2", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", "", "WDOG_EN", "", "", + "", "SPI1_CS#", "", "", + "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", + "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", + "", "", "", "", + "", "SPI3_CS#", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + usb-hub@2c { + compatible = "microchip,usb2514bi"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + individual-port-switching; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + self-powered; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + compatible = "st,m41t62"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio2 11 IRQ_TYPE_LEVEL_LOW>; + }; + + pcieclk: clk@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + /* + * i.MX 8M Plus Data Sheet for Consumer Products + * 3.1.4 Operating ranges + * MIMX8ML8CVNKZAB + */ + regulators { + buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck2: BUCK2 { /* VDD_ARM */ + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-ramp-delay = <3125>; + regulator-always-on; + regulator-boot-on; + }; + + buck4: BUCK4 { /* VDD_3V3 */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { /* VDD_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { /* NVCC_DRAM_1V1 */ + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { /* NVCC_SNVS_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3: LDO3 { /* VDDA_1V8 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { /* PMIC_LDO4 */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5: LDO5 { /* NVCC_SD2 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c5 { /* HDMI EDID bus */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_pwm>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +/* SD slot */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <&buck4>; + vqmmc-supply = <&buck5>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&uart1 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; /* Optional */ +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { /* A53 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { /* Lower plug direct */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { /* Upper plug via HUB */ + dr_mode = "host"; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; + +/* IOMUXC node should be at the end of DT to improve readability. */ +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, + <&pinctrl_panel_expansion>; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x44 + MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x44 + MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x44 + MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x40 + >; + }; + + pinctrl_eqos: eqos-grp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + /* ENET_RST# */ + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6 + /* ENET_INT# */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090 + >; + }; + + pinctrl_fec: fec-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + /* ENET2_RST# */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6 + /* ENET2_INT# */ + MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_hog_feature: hog-feature-grp { + fsl,pins = < + /* GPIO5_IO03 */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40000006 + /* GPIO5_IO04 */ + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40000006 + + /* CAN_INT# */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x40000090 + >; + }; + + pinctrl_hog_panel: hog-panel-grp { + fsl,pins = < + /* GRAPHICS_GPIO0_1V8 */ + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x26 + >; + }; + + pinctrl_hog_misc: hog-misc-grp { + fsl,pins = < + /* ENET_WOL# -- shared by both PHYs */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000090 + + /* PG_V_IN_VAR# */ + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000 + /* CSI2_PD_1V8 */ + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0 + /* CSI2_RESET_1V8# */ + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0 + + /* DIS_USB_DN1 */ + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 + /* DIS_USB_DN2 */ + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0 + + /* EEPROM_WP_1V8# */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x100 + /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x0 + /* GRAPHICS_PRSNT_1V8# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000 + + /* CLK_CCM_CLKO1_3V3 */ + MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10 + >; + }; + + pinctrl_hog_sbc: hog-sbc-grp { + fsl,pins = < + /* MEMCFG[0..2] straps */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x40000140 + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40000140 + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x40000140 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c5: i2c5-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x40000084 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x40000084 + >; + }; + + pinctrl_i2c5_gpio: i2c5-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x84 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x84 + >; + }; + + pinctrl_panel_backlight: panel-backlight-grp { + fsl,pins = < + /* BL_ENABLE_1V8 */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x104 + >; + }; + + pinctrl_panel_expansion: panel-expansion-grp { + fsl,pins = < + /* DSI_RESET_1V8# */ + MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x2 + /* DSI_IRQ_1V8# */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x40000090 + >; + }; + + pinctrl_panel_pwm: panel-pwm-grp { + fsl,pins = < + /* BL_PWM_3V3 */ + MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x12 + >; + }; + + pinctrl_panel_vcc_reg: panel-vcc-grp { + fsl,pins = < + /* TFT_ENABLE_1V8 */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x104 + >; + }; + + pinctrl_pcie0: pcie-grp { + fsl,pins = < + /* M2_PCIE_RST# */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 + /* M2_W_DISABLE1_1V8# */ + MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2 + /* M2_W_DISABLE2_1V8# */ + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2 + /* CLK_M2_32K768 */ + MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14 + /* M2_PCIE_WAKE# */ + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140 + /* M2_PCIE_CLKREQ# */ + MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 + >; + }; + + pinctrl_pdm: pdm-grp { + fsl,pins = < + /* PDM_SEL */ + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x0 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x0 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0 + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + /* PMIC_nINT */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + /* RTC_IRQ# */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000090 + >; + }; + + pinctrl_sai1: sai1-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0xd6 + MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0xd6 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 + >; + }; + + pinctrl_sai3: sai3-grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x49 + MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x49 + MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x49 + MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x49 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x49 + MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x49 + MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x20 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40000080 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x141 + >; + }; + + pinctrl_usb_hub: usb-hub-grp { + fsl,pins = < + /* USBHUB_RESET# */ + MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x4 + >; + }; + + pinctrl_usb1: usb1-grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x6 + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x80 + >; + }; + + pinctrl_watchdog_gpio: watchdog-gpio-grp { + fsl,pins = < + /* WDOG_B# */ + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x26 + /* WDOG_EN -- ungate WDT RESET# signal propagation */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x6 + /* WDOG_KICK# / WDI */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26 + >; + }; +}; From b4b992e2332fe566481939573f56675d451aae63 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 7 Apr 2023 18:14:46 -0300 Subject: [PATCH 0992/1040] ARM: imx_v4_v5_defconfig: Build CONFIG_IMX_SDMA as module Build CONFIG_IMX_SDMA as a module to allow the SDMA firmware be retrieved after the rootfs is mounted. This change aligns with the one already done for imx_v6_v7_defconfig in commit 5a7374ec715d ("ARM: imx_v6_v7_defconfig: build imx sdma driver as module"). Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/configs/imx_v4_v5_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig index 711a79e9be00..c9a602aee715 100644 --- a/arch/arm/configs/imx_v4_v5_defconfig +++ b/arch/arm/configs/imx_v4_v5_defconfig @@ -160,7 +160,7 @@ CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y CONFIG_DMADEVICES=y CONFIG_IMX_DMA=y -CONFIG_IMX_SDMA=y +CONFIG_IMX_SDMA=m # CONFIG_IOMMU_SUPPORT is not set CONFIG_IIO=y CONFIG_FSL_MX25_ADC=y From a9efe94fbd0bb1c9c32393b1dd7cddd75c07db42 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:16 +0200 Subject: [PATCH 0993/1040] ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-3-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 6cdadba6a3ac..5cce4918f84c 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -822,7 +822,7 @@ clocks = <&ccu CLK_APB2_UART0>; resets = <&ccu RST_APB2_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -835,7 +835,7 @@ clocks = <&ccu CLK_APB2_UART1>; resets = <&ccu RST_APB2_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -848,7 +848,7 @@ clocks = <&ccu CLK_APB2_UART2>; resets = <&ccu RST_APB2_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -861,7 +861,7 @@ clocks = <&ccu CLK_APB2_UART3>; resets = <&ccu RST_APB2_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -874,7 +874,7 @@ clocks = <&ccu CLK_APB2_UART4>; resets = <&ccu RST_APB2_UART4>; dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -887,7 +887,7 @@ clocks = <&ccu CLK_APB2_UART5>; resets = <&ccu RST_APB2_UART5>; dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; From d4880d2b81d8167b2cb7e27026c42dd1df9dbf8d Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:17 +0200 Subject: [PATCH 0994/1040] ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-4-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index f630ab55bb6a..4aa9d88c9ea3 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -490,7 +490,7 @@ clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -503,7 +503,7 @@ clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -516,7 +516,7 @@ clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -529,7 +529,7 @@ clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -542,7 +542,7 @@ clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; From 1532d4f4d7803e8a5c4c70c280427b2d25b7abc2 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:18 +0200 Subject: [PATCH 0995/1040] ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-5-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-v3s.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index db194c606fdc..b001251644f7 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -479,7 +479,7 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -492,7 +492,7 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -505,7 +505,7 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART2>; pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; From bb9ecbee05f5fd0042caf264835fad55a132d8c7 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:19 +0200 Subject: [PATCH 0996/1040] ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-6-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 686193bd6bd9..ade1cd50e445 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -710,7 +710,7 @@ clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -723,7 +723,7 @@ clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -736,7 +736,7 @@ clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -749,7 +749,7 @@ clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; From a140b18f0cc79f5c302ecedbde8364d49effa67f Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:20 +0200 Subject: [PATCH 0997/1040] riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230321215624.78383-7-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 951810d46307..922e8e0e2c09 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -211,7 +211,7 @@ clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 14>, <&dma 14>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -224,7 +224,7 @@ clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -237,7 +237,7 @@ clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 16>, <&dma 16>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -250,7 +250,7 @@ clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 17>, <&dma 17>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -263,7 +263,7 @@ clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; dmas = <&dma 18>, <&dma 18>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -276,7 +276,7 @@ clocks = <&ccu CLK_BUS_UART5>; resets = <&ccu RST_BUS_UART5>; dmas = <&dma 19>, <&dma 19>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; From be4c5c6e84429e87cfdf1c8be350a49a714a93e2 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Wed, 22 Mar 2023 23:40:50 +0000 Subject: [PATCH 0998/1040] memory: tegra: read values from correct device When reading MR18 for Dev1 the code was incorrectly reading the value corresponding to Dev0, so fix this by adjusting the index according to the Tegra X1 TRM. Signed-off-by: Diogo Ivo Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230322234050.47332-1-diogo.ivo@tecnico.ulisboa.pt Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210-emc-cc-r21021.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra210-emc-cc-r21021.c b/drivers/memory/tegra/tegra210-emc-cc-r21021.c index cc76adb8d7e8..4cb608c71ead 100644 --- a/drivers/memory/tegra/tegra210-emc-cc-r21021.c +++ b/drivers/memory/tegra/tegra210-emc-cc-r21021.c @@ -277,7 +277,7 @@ static u32 update_clock_tree_delay(struct tegra210_emc *emc, int type) /* * Dev1 LSB. */ - value = tegra210_emc_mrr_read(emc, 2, 18); + value = tegra210_emc_mrr_read(emc, 1, 18); for (i = 0; i < emc->num_channels; i++) { temp[i][0] |= (value & 0x00ff) >> 0; From 67025255ee8b1ec496b01f74e8c298d211bc7a82 Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Fri, 7 Apr 2023 11:13:52 +0200 Subject: [PATCH 0999/1040] dt-bindings: memory-controllers: mediatek,smi-common: add mt8365 Add binding description for mediatek,mt8365-smi-common Reviewed-by: Matthias Brugger Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230407-smi-driver-v2-2-8da6683cdb5c@baylibre.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/mediatek,smi-common.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index a8fda30cccbb..2f36ac23604c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -43,6 +43,7 @@ properties: - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp - mediatek,mt8195-smi-sub-common + - mediatek,mt8365-smi-common - description: for mt7623 items: @@ -133,6 +134,7 @@ allOf: - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp + - mediatek,mt8365-smi-common then: properties: From 4ad9a801a3597ccfd406c911638aca2c61e57bdf Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Fri, 7 Apr 2023 11:13:53 +0200 Subject: [PATCH 1000/1040] dt-bindings: memory-controllers: mediatek,smi-larb: add mt8365 Add binding description for mediatek,mt8365-smi-larb Reviewed-by: Matthias Brugger Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230407-smi-driver-v2-3-8da6683cdb5c@baylibre.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/mediatek,smi-larb.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 5f4ac3609887..aee7f6cf1300 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -34,6 +34,10 @@ properties: - const: mediatek,mt7623-smi-larb - const: mediatek,mt2701-smi-larb + - items: + - const: mediatek,mt8365-smi-larb + - const: mediatek,mt8186-smi-larb + reg: maxItems: 1 From 3ec0e1ea4770e40575bfb2bb4e9ebbbaa3c80d3f Mon Sep 17 00:00:00 2001 From: Alexandre Mergnat Date: Fri, 7 Apr 2023 11:13:51 +0200 Subject: [PATCH 1001/1040] memory: mtk-smi: mt8365: Add SMI Support Add MT8365 SMI common support. Reviewed-by: Yong Wu Signed-off-by: Alexandre Mergnat Link: https://lore.kernel.org/r/20230407-smi-driver-v2-1-8da6683cdb5c@baylibre.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/mtk-smi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 5a9754442bc7..6523cb510518 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -713,6 +713,11 @@ static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { .has_gals = true, }; +static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = { + .type = MTK_SMI_GEN2, + .bus_sel = F_MMU1_LARB(2) | F_MMU1_LARB(4), +}; + static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, @@ -728,6 +733,7 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, + {.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365}, {} }; From 4e859ef0bae3c0839ad362408d2f7321332e4850 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 11 Apr 2023 12:58:38 +0530 Subject: [PATCH 1002/1040] dt-bindings: arm: qcom: Document the Qualcomm qrb4210-rb2 board Document the Qualcomm qrb4210-rb2 board based on Robotics version of the Snapdragon SM4250 Soc, i.e. QRB4210. Acked-by: Krzysztof Kozlowski Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230411072840.2751813-2-bhupesh.sharma@linaro.org --- Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 785b969294a8..d9dd25695c3d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -50,6 +50,7 @@ description: | qcm2290 qdu1000 qrb2210 + qrb4210 qru1000 sa8155p sa8540p @@ -97,6 +98,7 @@ description: | liquid mtp qrd + rb2 ride sbc x100 @@ -874,6 +876,12 @@ properties: - oneplus,billie2 - const: qcom,sm4250 + - items: + - enum: + - qcom,qrb4210-rb2 + - const: qcom,qrb4210 + - const: qcom,sm4250 + - items: - enum: - lenovo,j606f From 8d58a8c0d930c52dd30bd50af24b786d55509cbf Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 11 Apr 2023 12:58:39 +0530 Subject: [PATCH 1003/1040] arm64: dts: qcom: Add base qrb4210-rb2 board dts Add DTS for Qualcomm qrb4210-rb2 board which uses SM4250 SoC. This adds debug uart, emmc, uSD and tlmm support along with regulators found on this board. Also defines the 'xo_board' and 'sleep_clk' frequencies for this board. Signed-off-by: Bhupesh Sharma [bjorn: Squashed separate patch specifying regulator-system-load] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230411072840.2751813-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 227 +++++++++++++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qrb4210-rb2.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index e0e2def48470..d42c59572ace 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts new file mode 100644 index 000000000000..dc80f0bca767 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sm4250.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QRB4210 RB2"; + compatible = "qcom,qrb4210-rb2", "qcom,qrb4210", "qcom,sm4250"; + + aliases { + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm6125-regulators"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l7-l17-l18-supply = <&vreg_s6a_1p352>; + vdd-l2-l3-l4-supply = <&vreg_s6a_1p352>; + vdd-l5-l15-l19-l20-l21-l22-supply = <&vph_pwr>; + vdd-l6-l8-supply = <&vreg_s5a_0p848>; + vdd-l9-l11-supply = <&vreg_s7a_2p04>; + vdd-l10-l13-l14-supply = <&vreg_s7a_2p04>; + vdd-l12-l16-supply = <&vreg_s7a_2p04>; + vdd-l23-l24-supply = <&vph_pwr>; + + vreg_s5a_0p848: s5 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <1128000>; + }; + + vreg_s6a_1p352: s6 { + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1456000>; + }; + + vreg_s7a_2p04: s7 { + regulator-min-microvolt = <1280000>; + regulator-max-microvolt = <2080000>; + }; + + vreg_l1a_1p0: l1 { + regulator-min-microvolt = <952000>; + regulator-max-microvolt = <1152000>; + }; + + vreg_l4a_0p9: l4 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + }; + + vreg_l5a_2p96: l5 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3056000>; + }; + + vreg_l6a_0p6: l6 { + regulator-min-microvolt = <576000>; + regulator-max-microvolt = <656000>; + }; + + vreg_l7a_1p256: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1304000>; + }; + + vreg_l8a_0p664: l8 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <1984000>; + }; + + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <1952000>; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l15a_3p128: l15 { + regulator-min-microvolt = <2920000>; + regulator-max-microvolt = <3232000>; + }; + + vreg_l16a_1p3: l16 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1152000>; + regulator-max-microvolt = <1384000>; + }; + + vreg_l18a_1p232: l18 { + regulator-min-microvolt = <1104000>; + regulator-max-microvolt = <1312000>; + }; + + vreg_l19a_1p8: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l20a_1p8: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + vreg_l21a_2p704: l21 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + }; + + vreg_l22a_2p96: l22 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <3304000>; + regulator-system-load = <100000>; + regulator-allow-set-load; + }; + + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l24a_2p96: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3600000>; + regulator-system-load = <100000>; + regulator-allow-set-load; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&vreg_l24a_2p96>; + vqmmc-supply = <&vreg_l11a_1p8>; + no-sdio; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>; /* card detect gpio */ + vmmc-supply = <&vreg_l22a_2p96>; + vqmmc-supply = <&vreg_l5a_2p96>; + no-sdio; + + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <37 5>, <43 2>, <47 1>, + <49 1>, <52 1>, <54 1>, + <56 3>, <61 2>, <64 1>, + <68 1>, <72 8>, <96 1>; +}; + +&uart4 { + status = "okay"; +}; + +&xo_board { + clock-frequency = <19200000>; +}; From 5ce5e0d08e340ab13169a5f33ed5f98000891a61 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 3 Apr 2023 11:33:04 +0200 Subject: [PATCH 1004/1040] soc: mediatek: Kconfig: Add MTK_CMDQ dependency to MTK_MMSYS The mtk-mmsys and mutex drivers do have a dependency on MTK_CMDQ, even though both can work with *or* without it: since CMDQ support can be enabled either as module or as built-in, it is necessary to add a depends rule in Kconfig, so that we disallow building both mtk-mmsys and mtk-mutex as built-in if mtk-cmdq-helper is built as a module, otherwise obvious linker issues appear. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230403093304.276418-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index d6b83a5508ca..a88cf04fc803 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -76,6 +76,7 @@ config MTK_MMSYS tristate "MediaTek MMSYS Support" default ARCH_MEDIATEK depends on HAS_IOMEM + depends on MTK_CMDQ || MTK_CMDQ=n help Say yes here to add support for the MediaTek Multimedia Subsystem (MMSYS). From 7eb1f2c61fb0edf4211ac379a6f2c1c250460f9e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:40 +0200 Subject: [PATCH 1005/1040] arm64: dts: mediatek: mt6795: Add VDECSYS and VENCSYS clocks In prepration for adding the IOMMUs and LARBs of this SoC, add the VDECSYS and VENCSYS clock controller nodes, providing clocks for the vcodec stateful decoder and stateful decoder hardware. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-11-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index d63efb32e6bb..090400d7fd61 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -624,5 +624,17 @@ clock-names = "source", "hclk"; status = "disabled"; }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@18000000 { + compatible = "mediatek,mt6795-vencsys"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; }; }; From 9415e246ac7376b098eda6aba761b25808434e3c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:42 +0200 Subject: [PATCH 1006/1040] arm64: dts: mediatek: mt6795-xperia-m5: Enable I2C 0-3 busses Properly configure and enable the three i2c controllers that have devices attached on the Sony Xperia M5 smartphone. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-13-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt6795-sony-xperia-m5.dts | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 52ce3284a46f..6df1c848e2d5 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -55,7 +55,71 @@ status = "okay"; }; +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + status = "okay"; +}; + &pio { + i2c0_pins: i2c0-pins { + pins-bus { + pinmux = , + ; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux = , + ; + bias-disable; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = , + ; + bias-disable; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux = , + ; + bias-disable; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = , + ; + bias-disable; + }; + }; + uart0_pins: uart0-pins { pins-rx { pinmux = ; From 9e49cbef6c723ec6336d06450d2c07c87d6e86d3 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:43 +0200 Subject: [PATCH 1007/1040] arm64: dts: mediatek: mt6795-xperia-m5: Add Synaptics RMI4 Touchscreen Add the RMI4 Touchscreen on I2C2 and its pin definitions. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-14-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt6795-sony-xperia-m5.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 6df1c848e2d5..edab90f06a24 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -71,6 +71,28 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_pins>; + syna,startup-delay-ms = <160>; + syna,reset-delay-ms = <90>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; }; &i2c3 { @@ -80,6 +102,19 @@ }; &pio { + ts_pins: touchscreen-pins { + pins-irq { + pinmux = ; + bias-pull-up; + input-enable; + }; + + pins-rst { + pinmux = ; + output-high; + }; + }; + i2c0_pins: i2c0-pins { pins-bus { pinmux = , From d5ed9a0445fa6c29a17948245ac611159d63daa4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:46 +0200 Subject: [PATCH 1008/1040] arm64: dts: mediatek: mt6795-xperia-m5: Add Sensortek STK3310 Proximity Add the STK3310 Proximity sensor and its pins. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-17-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index edab90f06a24..a40b9f526a02 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -99,6 +99,14 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; status = "okay"; + + proximity@48 { + compatible = "sensortek,stk3310"; + reg = <0x48>; + interrupts-extended = <&pio 8 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&proximity_pins>; + }; }; &pio { @@ -115,6 +123,14 @@ }; }; + proximity_pins: proximity-pins { + pins-irq { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + i2c0_pins: i2c0-pins { pins-bus { pinmux = , From f010d1b6867c618ee687b101622e827d90b284b9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 Mar 2023 10:36:47 +0200 Subject: [PATCH 1009/1040] arm64: dts: mediatek: mt6795-xperia-m5: Add NXP PN547 NFC on I2C3 Add support for the NXP PN547 NFC chip found on this smartphone and configure its pins. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230327083647.22017-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../dts/mediatek/mt6795-sony-xperia-m5.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index a40b9f526a02..a0e01a756f03 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -5,6 +5,7 @@ */ /dts-v1/; +#include #include "mt6795.dtsi" / { @@ -100,6 +101,16 @@ pinctrl-0 = <&i2c3_pins>; status = "okay"; + pn547: nfc@28 { + compatible = "nxp,pn544-i2c"; + reg = <0x28>; + interrupts-extended = <&pio 3 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&nfc_pins>; + enable-gpios = <&pio 149 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&pio 94 GPIO_ACTIVE_HIGH>; + }; + proximity@48 { compatible = "sensortek,stk3310"; reg = <0x48>; @@ -110,6 +121,19 @@ }; &pio { + nfc_pins: nfc-pins { + pins-irq { + pinmux = ; + bias-pull-down; + input-enable; + }; + + pins-fw-ven { + pinmux = , + ; + }; + }; + ts_pins: touchscreen-pins { pins-irq { pinmux = ; From 3a07e82edca0e3fc95970e8e5a6b7838f27cbbe0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:01 +0100 Subject: [PATCH 1010/1040] arm64: dts: mediatek: mt8173: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230304123301.33952-1-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index d452cab28c67..d77f6af19065 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -58,7 +58,7 @@ gpios = <&pio 69 GPIO_ACTIVE_LOW>; linux,code = ; linux,input-type = ; - gpio-key,wakeup; + wakeup-source; }; switch-power { @@ -66,7 +66,7 @@ gpios = <&pio 14 GPIO_ACTIVE_HIGH>; linux,code = ; debounce-interval = <30>; - gpio-key,wakeup; + wakeup-source; }; switch-tablet-mode { @@ -74,7 +74,7 @@ gpios = <&pio 121 GPIO_ACTIVE_HIGH>; linux,code = ; linux,input-type = ; - gpio-key,wakeup; + wakeup-source; }; switch-volume-down { From fcb8b72db5800be7ca97ba7fa419d8aff2ffcaf1 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 4 Apr 2023 10:02:38 +0200 Subject: [PATCH 1011/1040] dt-bindings: vendor-prefixes: add chargebyte chargebyte supplies hardware and software products for all aspects of charging communication. https://chargebyte.com/ Signed-off-by: Stefan Wahren Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..b8d8fa1d1fd6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -240,6 +240,8 @@ patternProperties: description: CellWise Microelectronics Co., Ltd "^ceva,.*": description: Ceva, Inc. + "^chargebyte,.*": + description: chargebyte GmbH "^checkpoint,.*": description: Check Point Software Technologies Ltd. "^chefree,.*": From 98896cf432398c8e2c59347190f3efda53bc3670 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 4 Apr 2023 10:02:41 +0200 Subject: [PATCH 1012/1040] dt-bindings: arm: fsl: Add chargebyte Tarragon This adds the compatibles for the chargebyte Tarragon boards. Signed-off-by: Stefan Wahren Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b175f2b1bd30..7fac7f834814 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -707,6 +707,15 @@ properties: - const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM - const: fsl,imx6ull + - description: i.MX6ULL chargebyte Tarragon Boards + items: + - enum: + - chargebyte,imx6ull-tarragon-master + - chargebyte,imx6ull-tarragon-micro + - chargebyte,imx6ull-tarragon-slave + - chargebyte,imx6ull-tarragon-slavext + - const: fsl,imx6ull + - description: i.MX6ULL DHCOM SoM based Boards items: - enum: From e7a985d50841e43ea1794b3597fd7f646ed95a32 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Apr 2023 18:01:15 +0200 Subject: [PATCH 1013/1040] dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC Add DT compatible for Data Modul i.MX8M Plus eDM SBC board. This is an evaluation board for various custom display units. Acked-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 7fac7f834814..15d411084065 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1016,6 +1016,7 @@ properties: items: - enum: - beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit + - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - polyhex,imx8mp-debix # Polyhex Debix boards From 5e60ec02ec30e2db3088196a10fd20be5432bb6d Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 25 Nov 2022 19:14:32 -0600 Subject: [PATCH 1014/1040] arm64: dts: rockchip: add panel to Anbernic RG353 series Add support for the newly mainlined panel to the RG353 series of devices. Signed-off-by: Chris Morgan Link: https://lore.kernel.org/r/20221126011432.22891-2-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3566-anbernic-rg353x.dtsi | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi index 65a80d1f6d91..17450aa283b9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi @@ -20,6 +20,48 @@ assigned-clock-rates = <1200000000>, <200000000>, <241500000>; }; +&dsi_dphy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + dsi0_in: port@0 { + reg = <0>; + dsi0_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi0>; + }; + }; + + dsi0_out: port@1 { + reg = <1>; + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel: panel@0 { + compatible = "anbernic,rg353p-panel", "newvision,nv3051d"; + reg = <0>; + backlight = <&backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst>; + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc3v3_lcd0_n>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + &gpio_keys_control { button-a { gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; @@ -55,6 +97,22 @@ }; }; +&pinctrl { + gpio-lcd { + lcd_rst: lcd-rst { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + &pwm4 { status = "okay"; }; + +&vp1 { + vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi0_in_vp1>; + }; +}; From 0dd58c077325b4260aa87e9db256d41806c2c9c5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:32 +0200 Subject: [PATCH 1015/1040] arm64: dts: mediatek: mt6795: Add tertiary PWM node The PWM at 0x11006000 is the tertiary PWM; unlike PWM0, PWM1, this is not display specific and can be used as a generic PWM controller. This node is left disabled as usage is board-specific. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-21-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 090400d7fd61..17019fbea0af 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -524,6 +524,25 @@ status = "disabled"; }; + pwm2: pwm@11006000 { + compatible = "mediatek,mt6795-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM>, + <&pericfg CLK_PERI_PWM1>, + <&pericfg CLK_PERI_PWM2>, + <&pericfg CLK_PERI_PWM3>, + <&pericfg CLK_PERI_PWM4>, + <&pericfg CLK_PERI_PWM5>, + <&pericfg CLK_PERI_PWM6>, + <&pericfg CLK_PERI_PWM7>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5", "pwm6", "pwm7"; + status = "disabled"; + }; + i2c0: i2c@11007000 { compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; From 9b42966d4c7db49140c6a66e81905edd5a1846f0 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:38 +0200 Subject: [PATCH 1016/1040] arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer Add the BMA255 Accelerometer on I2C3 and its pin definitions. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-27-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- .../boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index a0e01a756f03..9593b3fc403a 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -66,6 +66,13 @@ pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; status = "okay"; + + accelerometer@10 { + compatible = "bosch,bma255"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&accel_pins>; + }; }; &i2c2 { @@ -155,6 +162,14 @@ }; }; + accel_pins: accelerometer-pins { + pins-irq { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + i2c0_pins: i2c0-pins { pins-bus { pinmux = , From 13961ef828cbc254cc272221b7fc54851caa39a7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 12 Apr 2023 13:27:39 +0200 Subject: [PATCH 1017/1040] arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer This smartphone features a Bosch BMM050 Magnetometer on I2C3: enable it with the BMM150 binding, as that driver supports BMM050 as well. For this sensor, there is no interrupt pin; readings were validated in sysfs. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230412112739.160376-28-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 9593b3fc403a..507b5b567a36 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -73,6 +73,11 @@ pinctrl-names = "default"; pinctrl-0 = <&accel_pins>; }; + + magnetometer@12 { + compatible = "bosch,bmm150"; + reg = <0x12>; + }; }; &i2c2 { From 9bdc19fb94581fb805f5033825f41c363f5c3e85 Mon Sep 17 00:00:00 2001 From: Lakshmi Yadlapati Date: Wed, 12 Apr 2023 00:23:05 -0500 Subject: [PATCH 1018/1040] ARM: dts: aspeed: p10bmc: Change power supply info Bonnell system supports new ACBEL FSG032 power supply on I2C addresses 5A and 5B. Update the device tree with new power supply information and device addresses. Signed-off-by: Lakshmi Yadlapati Reviewed-by: Eddie James Link: https://lore.kernel.org/r/20230412052305.1369521-6-lakshmiy@us.ibm.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index 79516dc21c01..81902cbe662c 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -552,14 +552,14 @@ &i2c3 { status = "okay"; - power-supply@58 { - compatible = "ibm,cffps"; - reg = <0x58>; + power-supply@5a { + compatible = "acbel,fsg032"; + reg = <0x5a>; }; - power-supply@59 { - compatible = "ibm,cffps"; - reg = <0x59>; + power-supply@5b { + compatible = "acbel,fsg032"; + reg = <0x5b>; }; }; From 2ecdcd68e3871af219793e4ae35f9e96f3feb9a6 Mon Sep 17 00:00:00 2001 From: Delphine CC Chiu Date: Wed, 29 Mar 2023 16:32:34 +0800 Subject: [PATCH 1019/1040] ARM: dts: aspeed: greatlakes: Add gpio names Add GPIO names for SOC lines. Signed-off-by: Delphine CC Chiu Link: https://lore.kernel.org/r/20230329083235.24123-2-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley --- .../dts/aspeed-bmc-facebook-greatlakes.dts | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts index 8c05bd56ce1e..59819115c39d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts @@ -238,4 +238,53 @@ &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "power-bmc-nic","presence-ocp-debug", + "power-bmc-slot1","power-bmc-slot2", + "power-bmc-slot3","power-bmc-slot4","","", + /*C0-C7*/ "presence-ocp-nic","","","reset-cause-nic-primary", + "reset-cause-nic-secondary","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "slot1-bmc-reset-button","slot2-bmc-reset-button", + "slot3-bmc-reset-button","slot4-bmc-reset-button", + "","","","presence-emmc", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","", + "presence-mb-slot1","presence-mb-slot2", + "presence-mb-slot3","presence-mb-slot4", + /*I0-I7*/ "","","","","","","bb-bmc-button","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","power-nic-bmc-enable","","usb-bmc-enable","","reset-cause-usb-hub","","", + /*N0-N7*/ "","","","","bmc-ready","","","", + /*O0-O7*/ "","","","","","","fan0-bmc-cpld-enable","fan1-bmc-cpld-enable", + /*P0-P7*/ "fan2-bmc-cpld-enable","fan3-bmc-cpld-enable", + "reset-cause-pcie-slot1","reset-cause-pcie-slot2", + "reset-cause-pcie-slot3","reset-cause-pcie-slot4","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","power-p5v-usb","presence-bmc-tpm","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","GND", + /*V0-V7*/ "bmc-slot1-ac-button","bmc-slot2-ac-button", + "bmc-slot3-ac-button","bmc-slot4-ac-button", + "","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","reset-cause-emmc","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&gpio1 { + status = "okay"; + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","","", + /*18C0-18C7*/ "","","","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","","","","","",""; }; From 8d250f34cd2678acfa249a10b92fa5976b61336f Mon Sep 17 00:00:00 2001 From: Delphine CC Chiu Date: Wed, 29 Mar 2023 16:32:35 +0800 Subject: [PATCH 1020/1040] ARM: dts: aspeed: greatlakes: add mctp device Add mctp node on I2C bus Signed-off-by: Delphine CC Chiu Link: https://lore.kernel.org/r/20230329083235.24123-3-Delphine_CC_Chiu@Wiwynn.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts index 59819115c39d..7a53f54833a0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts @@ -156,6 +156,7 @@ &i2c8 { status = "okay"; + mctp-controller; temperature-sensor@1f { compatible = "ti,tmp421"; reg = <0x1f>; @@ -165,6 +166,10 @@ compatible = "st,24c32"; reg = <0x50>; }; + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; }; &i2c9 { @@ -238,7 +243,7 @@ &gpio0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; - status = "okay"; + gpio-line-names = /*A0-A7*/ "","","","","","","","", /*B0-B7*/ "power-bmc-nic","presence-ocp-debug", @@ -280,7 +285,6 @@ }; &gpio1 { - status = "okay"; gpio-line-names = /*18A0-18A7*/ "","","","","","","","", /*18B0-18B7*/ "","","","","","","","", From 7d4f0b0df7c5ec0cec834f87591423a7bbd1bab2 Mon Sep 17 00:00:00 2001 From: Chia-Wei Wang Date: Mon, 20 Mar 2023 16:11:33 +0800 Subject: [PATCH 1021/1040] ARM: dts: aspeed-g6: Add UDMA node Add the device tree node for the UART DMA (UDMA) controller. Signed-off-by: Chia-Wei Wang Link: https://lore.kernel.org/r/20230320081133.23655-6-chiawei_wang@aspeedtech.com Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g6.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 8246a60de0d0..172dd748d807 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -863,6 +863,15 @@ clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; status = "disabled"; }; + + udma: dma-controller@1e79e000 { + compatible = "aspeed,ast2600-udma"; + reg = <0x1e79e000 0x1000>; + interrupts = ; + dma-channels = <28>; + #dma-cells = <1>; + status = "disabled"; + }; }; }; }; From 04ebdc354895e1609ac133b40f8e8d2e0f16e450 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 10 Apr 2023 18:27:26 -0500 Subject: [PATCH 1022/1040] bus: vexpress-config: Add explicit of_platform.h include vexpress-config uses of_platform_* functions which are declared in of_platform.h. of_platform.h gets implicitly included by of_device.h, but that is going to be removed soon. Nothing else depends on of_device.h so it can be dropped. Signed-off-by: Rob Herring Acked-by: Liviu Dudau Link: https://lore.kernel.org/r/20230410232727.1562115-1-robh@kernel.org Signed-off-by: Sudeep Holla --- drivers/bus/vexpress-config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/vexpress-config.c b/drivers/bus/vexpress-config.c index a58ac0c8e282..472a570bd53a 100644 --- a/drivers/bus/vexpress-config.c +++ b/drivers/bus/vexpress-config.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include From 344cad0660ea08c95bd3752d0cbbf3f51944d9af Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 5 Apr 2023 12:54:39 +0200 Subject: [PATCH 1023/1040] ARM: configs: Update U8500 defconfig Update the U8500 defconfig accordingly: - Add the NFC modules used by some U8500-based systems. - Switch out the now deleted UX500 crypto drivers to the STM32 drivers that we have augmented to work with UX500. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230405105439.1739575-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/configs/u8500_defconfig | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig index 3bdc217667a6..0f55815eecb3 100644 --- a/arch/arm/configs/u8500_defconfig +++ b/arch/arm/configs/u8500_defconfig @@ -38,6 +38,10 @@ CONFIG_CFG80211_DEBUGFS=y CONFIG_MAC80211=y CONFIG_MAC80211_LEDS=y CONFIG_CAIF=y +CONFIG_NFC=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=m +CONFIG_NFC_PN544_I2C=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_GNSS=y @@ -180,10 +184,8 @@ CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y -CONFIG_CRYPTO_DEV_UX500=y -CONFIG_CRYPTO_DEV_UX500_CRYP=y -CONFIG_CRYPTO_DEV_UX500_HASH=y -CONFIG_CRYPTO_DEV_UX500_DEBUG=y +CONFIG_CRYPTO_DEV_STM32_HASH=y +CONFIG_CRYPTO_DEV_STM32_CRYP=y CONFIG_PRINTK_TIME=y CONFIG_DEBUG_KERNEL=y CONFIG_MAGIC_SYSRQ=y From 24c15979323885d2c1f17b052d86d63aa052fd8c Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 13 Apr 2023 09:20:42 +0200 Subject: [PATCH 1024/1040] ARM: multi_v7_defconfig: Add OPTEE support STM32MP13 platform relies on OPTEE to boot: Clocks and regulators are handled in the secure world by OPTEE and exported to the non secure world (LINUX) thanks to ARM SCMI protocol. Signed-off-by: Alexandre Torgue Link: https://lore.kernel.org/r/20230413072042.30657-1-alexandre.torgue@foss.st.com Signed-off-by: Arnd Bergmann --- arch/arm/configs/multi_v7_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 42ff3d5a5198..871fffe92187 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -1218,6 +1218,8 @@ CONFIG_FSI_MASTER_ASPEED=m CONFIG_FSI_SCOM=m CONFIG_FSI_SBEFIFO=m CONFIG_FSI_OCC=m +CONFIG_TEE=y +CONFIG_OPTEE=y CONFIG_INTERCONNECT_QCOM=y CONFIG_INTERCONNECT_QCOM_MSM8916=y CONFIG_COUNTER=m From 325ae154b42b32c8ee114f4286364d153117fe59 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 11 Apr 2023 00:03:00 +0200 Subject: [PATCH 1025/1040] ARM: dts: nomadik: Replace deprecated spi-gpio properties As stated in Documentation/devicetree/bindings/spi/spi-gpio.yaml, 'gpio-mosi' and 'gpio-sck' are deprecated properties. Use the recommeded 'mosi-gpios' and 'sck-gpios' instead. Signed-off-by: Fabio Estevam Link: https://lore.kernel.org/r/20230407162504.1683422-1-festevam@gmail.com Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230410220300.2431524-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 8142c017882c..4d741adc16cd 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -210,8 +210,8 @@ * As we're dealing with 3wire SPI, we only define SCK * and MOSI (in the spec MOSI is called "SDA"). */ - gpio-sck = <&gpio0 5 GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 4 GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; cs-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; num-chipselects = <1>; From 04523aceae8c89d3c91ff33bdde6892f63a60f35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 12 Oct 2022 16:00:32 +0200 Subject: [PATCH 1026/1040] soc: ti: smartreflex: Simplify getting the opam_sr pointer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The probe function stores the sr_info pointer using platform_set_drvdata(). Use the corresponding platform_get_drvdata() to retrieve that pointer in the remove and shutdown functions. This simplifies these functions and makes error handling unnecessary. This is a good thing as at least for .remove() returning an error code doesn't have the desired effect. This is a preparation for making platform remove callbacks return void. Signed-off-by: Uwe Kleine-König Reviewed-by: Tony Lindgren Signed-off-by: Arnd Bergmann --- drivers/soc/ti/smartreflex.c | 30 ++---------------------------- 1 file changed, 2 insertions(+), 28 deletions(-) diff --git a/drivers/soc/ti/smartreflex.c b/drivers/soc/ti/smartreflex.c index 9d9496e0a94c..da7898239a46 100644 --- a/drivers/soc/ti/smartreflex.c +++ b/drivers/soc/ti/smartreflex.c @@ -937,21 +937,8 @@ err_list_del: static int omap_sr_remove(struct platform_device *pdev) { - struct omap_sr_data *pdata = pdev->dev.platform_data; struct device *dev = &pdev->dev; - struct omap_sr *sr_info; - - if (!pdata) { - dev_err(&pdev->dev, "%s: platform data missing\n", __func__); - return -EINVAL; - } - - sr_info = _sr_lookup(pdata->voltdm); - if (IS_ERR(sr_info)) { - dev_warn(&pdev->dev, "%s: omap_sr struct not found\n", - __func__); - return PTR_ERR(sr_info); - } + struct omap_sr *sr_info = platform_get_drvdata(pdev); if (sr_info->autocomp_active) sr_stop_vddautocomp(sr_info); @@ -965,20 +952,7 @@ static int omap_sr_remove(struct platform_device *pdev) static void omap_sr_shutdown(struct platform_device *pdev) { - struct omap_sr_data *pdata = pdev->dev.platform_data; - struct omap_sr *sr_info; - - if (!pdata) { - dev_err(&pdev->dev, "%s: platform data missing\n", __func__); - return; - } - - sr_info = _sr_lookup(pdata->voltdm); - if (IS_ERR(sr_info)) { - dev_warn(&pdev->dev, "%s: omap_sr struct not found\n", - __func__); - return; - } + struct omap_sr *sr_info = platform_get_drvdata(pdev); if (sr_info->autocomp_active) sr_stop_vddautocomp(sr_info); From 6f5ab8fa33238fdf6cb28dac7bc2f650db2caf08 Mon Sep 17 00:00:00 2001 From: John Clark Date: Thu, 13 Apr 2023 13:03:37 -0400 Subject: [PATCH 1027/1040] arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x Add gpio-range properties to the pinctrl gpio nodes in rk356x.dtsi Signed-off-by: John Clark Link: https://lore.kernel.org/r/20230413170337.6815-1-inindev@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 802fcc96384e..f62e0fd881a9 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -1808,6 +1808,7 @@ interrupts = ; clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -1819,6 +1820,7 @@ interrupts = ; clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -1830,6 +1832,7 @@ interrupts = ; clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -1841,6 +1844,7 @@ interrupts = ; clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -1852,6 +1856,7 @@ interrupts = ; clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From 348981c783b9852b54ed78c2d9081135eaebfc70 Mon Sep 17 00:00:00 2001 From: Sasha Finkelstein Date: Mon, 3 Apr 2023 16:19:21 +0200 Subject: [PATCH 1028/1040] arm64: dts: apple: t8103: Add PWM controller Adds PWM controller and keyboard backlight bindings for M1 MacBooks Signed-off-by: Sasha Finkelstein Acked-by: Sven Peter Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8103-j293.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/apple/t8103-j313.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/apple/t8103.dtsi | 9 +++++++++ 3 files changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index c363dfef8070..56b0c67bfcda 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -11,10 +11,23 @@ #include "t8103.dtsi" #include "t8103-jxxx.dtsi" +#include / { compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M1, 2020)"; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; }; &bluetooth0 { @@ -32,3 +45,7 @@ &i2c4 { status = "okay"; }; + +&fpwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts index 08409be1cf35..97a4344d8dca 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -11,10 +11,23 @@ #include "t8103.dtsi" #include "t8103-jxxx.dtsi" +#include / { compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Air (M1, 2020)"; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; }; &bluetooth0 { @@ -24,3 +37,7 @@ &wifi0 { brcm,board-type = "apple,shikoku"; }; + +&fpwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 87a9c1ba6d0f..9b0dad6b6184 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -432,6 +432,15 @@ status = "disabled"; /* only used in J293 */ }; + fpwm1: pwm@235044000 { + compatible = "apple,t8103-fpwm", "apple,s5l-fpwm"; + reg = <0x2 0x35044000 0x0 0x4000>; + power-domains = <&ps_fpwm1>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; From b15999c27f9601c63a1add58cea698ea0c27184b Mon Sep 17 00:00:00 2001 From: Sasha Finkelstein <7d578vix8hzw@opayq.net> Date: Mon, 3 Apr 2023 16:19:22 +0200 Subject: [PATCH 1029/1040] arm64: dts: apple: t600x: Add PWM controller Adds PWM controller and keyboard backlight bindings for M1 Pro/Max MacBook Pros Signed-off-by: Sasha Finkelstein Acked-by: Hector Martin Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 9 +++++++++ arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 273d7060d031..b1c875e692c8 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -71,6 +71,15 @@ power-domains = <&ps_sio_cpu>; }; + fpwm0: pwm@39b030000 { + compatible = "apple,t6000-fpwm", "apple,s5l-fpwm"; + reg = <0x3 0x9b030000 0x0 0x4000>; + power-domains = <&ps_fpwm0>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + i2c0: i2c@39b040000 { compatible = "apple,t6000-i2c", "apple,i2c"; reg = <0x3 0x9b040000 0x0 0x4000>; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index 356a73d1ce4c..2e471dfe43cf 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -9,6 +9,8 @@ * Copyright The Asahi Linux Contributors */ +#include + / { aliases { serial0 = &serial0; @@ -34,6 +36,18 @@ device_type = "memory"; reg = <0x100 0 0x2 0>; /* To be filled by loader */ }; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm0 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; }; &serial0 { @@ -101,3 +115,7 @@ wp-inverted; }; }; + +&fpwm0 { + status = "okay"; +}; From 50aa09ac18fac94a907d26dca21aff5507373fb1 Mon Sep 17 00:00:00 2001 From: Sasha Finkelstein Date: Sun, 9 Apr 2023 11:18:46 +0200 Subject: [PATCH 1030/1040] arm64: dts: apple: t8112: Add PWM controller This patch adds the device tree entries for the PWM controller present on M2 macbooks that is connected to the keyboard backlight. Signed-off-by: Sasha Finkelstein Signed-off-by: Hector Martin --- arch/arm64/boot/dts/apple/t8112-j413.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/apple/t8112-j493.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 9 +++++++++ 3 files changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts index 9e758edeaa82..6f69658623bf 100644 --- a/arch/arm64/boot/dts/apple/t8112-j413.dts +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -11,6 +11,7 @@ #include "t8112.dtsi" #include "t8112-jxxx.dtsi" +#include / { compatible = "apple,j413", "apple,t8112", "apple,arm-platform"; @@ -20,6 +21,18 @@ bluetooth0 = &bluetooth0; wifi0 = &wifi0; }; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; }; /* @@ -61,3 +74,7 @@ &i2c4 { status = "okay"; }; + +&fpwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts index 8552c15be265..0ad908349f55 100644 --- a/arch/arm64/boot/dts/apple/t8112-j493.dts +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -11,6 +11,7 @@ #include "t8112.dtsi" #include "t8112-jxxx.dtsi" +#include / { compatible = "apple,j493", "apple,t8112", "apple,arm-platform"; @@ -20,6 +21,18 @@ bluetooth0 = &bluetooth0; wifi0 = &wifi0; }; + + led-controller { + compatible = "pwm-leds"; + led-0 { + pwms = <&fpwm1 0 40000>; + label = "kbd_backlight"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + max-brightness = <255>; + default-state = "keep"; + }; + }; }; /* @@ -50,3 +63,7 @@ &i2c4 { status = "okay"; }; + +&fpwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index 698a436e7dac..1666e6ab250b 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -458,6 +458,15 @@ status = "disabled"; }; + fpwm1: pwm@235044000 { + compatible = "apple,t8112-fpwm", "apple,s5l-fpwm"; + reg = <0x2 0x35044000 0x0 0x4000>; + power-domains = <&ps_fpwm1>; + clocks = <&clkref>; + #pwm-cells = <2>; + status = "disabled"; + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; From d7f5e83913d1bcd50968972a7b50e49c9a14b2af Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 14 Apr 2023 15:54:23 +0300 Subject: [PATCH 1031/1040] arm64: dts: rockchip: Drop RTC clock-frequency on rk3588-rock-5b The hym8563 RTC driver doesn't handle the 'clock-frequency' property, which is also indicated by the following dtbs_check warning: rk3588-rock-5b.dtb: rtc@51: Unevaluated properties are not allowed ('clock-frequency' was unexpected) From schema: Documentation/devicetree/bindings/rtc/haoyu,hym8563.yaml Drop the unsupported property. Fixes: 1e9c2404d887 ("arm64: dts: rockchip: Enable RTC support for Rock 5B") Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230414125425.124994-2-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 88b9f7ddf291..62750beb12aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -60,7 +60,6 @@ compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "hym8563"; pinctrl-names = "default"; pinctrl-0 = <&hym8563_int>; From 0af7164cb0e076dbfeed28956658a1ad94bd5927 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 14 Apr 2023 15:54:24 +0300 Subject: [PATCH 1032/1040] arm64: dts: rockchip: Use generic name for es8316 on Pinebook Pro and Rock 5B Use generic 'audio-codec' name for es8316 node on Pinebook Pro and Rock 5B boards. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230414125425.124994-3-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index 194e48c755f6..3e32159527e5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -675,7 +675,7 @@ i2c-scl-rising-time-ns = <168>; status = "okay"; - es8316: es8316@11 { + es8316: audio-codec@11 { compatible = "everest,es8316"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 62750beb12aa..8cc97d146a73 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -72,7 +72,7 @@ &i2c7 { status = "okay"; - es8316: es8316@11 { + es8316: audio-codec@11 { compatible = "everest,es8316"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; From 1bb69cd4a344299a382695a2de1a84c0b23fe6da Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 14 Apr 2023 15:54:25 +0300 Subject: [PATCH 1033/1040] arm64: dts: rockchip: Add vdd_cpu_big regulators to rk3588-rock-5b The RK8602 and RK8603 voltage regulators on the Rock 5B board provide the power lines vdd_cpu_big0 and vdd_cpu_big1, respectively. Add the necessary device tree nodes and bind them to the corresponding CPU big core nodes. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230414125425.124994-4-cristian.ciocaltea@collabora.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5b.dts | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 8cc97d146a73..3e4aee8f70c1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -53,6 +53,62 @@ }; }; +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + &i2c6 { status = "okay"; From a2116e7b921e74e2da8b76fc4c5dfcb9e2b8b206 Mon Sep 17 00:00:00 2001 From: Kamlesh Gurudasani Date: Mon, 17 Apr 2023 18:57:16 +0530 Subject: [PATCH 1034/1040] arm64: defconfig: Enable crypto test module Enable crypto test module, used for testing crypto engine performance. Signed-off-by: Kamlesh Gurudasani Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b6342b40c600..e4ef0cc35235 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1452,6 +1452,7 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ECHAINIV=y CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_ANSI_CPRNG=y From caa633855af148310fb68fb3996ef25ae6117848 Mon Sep 17 00:00:00 2001 From: Kamlesh Gurudasani Date: Mon, 17 Apr 2023 18:57:17 +0530 Subject: [PATCH 1035/1040] arm64: defconfig: Enable security accelerator driver for TI K3 SoCs Enable TI's SA2UL driver to support security acceleration on TI K3 SoCs. Signed-off-by: Kamlesh Gurudasani Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index e4ef0cc35235..64ce445b3ec0 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1478,6 +1478,7 @@ CONFIG_CRYPTO_DEV_HISI_SEC2=m CONFIG_CRYPTO_DEV_HISI_ZIP=m CONFIG_CRYPTO_DEV_HISI_HPRE=m CONFIG_CRYPTO_DEV_HISI_TRNG=m +CONFIG_CRYPTO_DEV_SA2UL=m CONFIG_DMA_RESTRICTED_POOL=y CONFIG_CMA_SIZE_MBYTES=32 CONFIG_PRINTK_TIME=y From e56ec0cad23eb32d9bbbef88802726873a8ffb60 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 11 Apr 2023 16:30:33 +0530 Subject: [PATCH 1036/1040] arm64: defconfig: Enable TI TSCADC driver Enable TSCADC driver to be built as a module which will add support for TI's TSC/ADC MFDevice. Signed-off-by: Bhavya Kapoor Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 64ce445b3ec0..29a501f9e354 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -691,6 +691,7 @@ CONFIG_MFD_RK808=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_SL28CPLD=y CONFIG_MFD_TPS65219=y +CONFIG_MFD_TI_AM335X_TSCADC=m CONFIG_MFD_ROHM_BD718XX=y CONFIG_MFD_WCD934X=m CONFIG_REGULATOR_FIXED_VOLTAGE=y From 8c0232d68d88b05f21b64fda1691fd1f3f81c7ca Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 11 Apr 2023 16:30:34 +0530 Subject: [PATCH 1037/1040] arm64: defconfig: Enable TI ADC driver Enable ADC driver to be built as a module which will add support for ADC in TI K3 specific SoCs. Signed-off-by: Bhavya Kapoor Reviewed-by: Manorit Chawdhry Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 29a501f9e354..bd80c95d9cb8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1293,6 +1293,7 @@ CONFIG_QCOM_SPMI_ADC5=m CONFIG_ROCKCHIP_SARADC=m CONFIG_RZG2L_ADC=m CONFIG_TI_ADS1015=m +CONFIG_TI_AM335X_ADC=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m CONFIG_IIO_ST_LSM6DSX=m From d4a53049faeaff611f1aff8fcae13c37101e048a Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 13 Apr 2023 15:17:03 +0200 Subject: [PATCH 1038/1040] arm64: defconfig: enable building the nvmem-reboot-mode module This module is used by the Qualcomm sa8775p platform for passing the reboot reason to the bootloader. Enable building it in the arm64 defconfig as a module. Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index bd80c95d9cb8..a24609e14d50 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -614,6 +614,7 @@ CONFIG_POWER_RESET_QCOM_PON=m CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_NVMEM_REBOOT_MODE=m CONFIG_BATTERY_SBS=m CONFIG_BATTERY_BQ27XXX=y CONFIG_BATTERY_MAX17042=m From d3150ed535805403291b95fd84b00b0b5ef41096 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Wed, 5 Apr 2023 13:38:13 +0100 Subject: [PATCH 1039/1040] arm64: dts: rockchip: Add support for volume keys to rk3399-pinephone-pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are implemented via regular ADC, so regular polling is needed, for these keys to work. Co-developed-by: Martijn Braam Signed-off-by: Martijn Braam Co-developed-by: Kamil Trzciński Signed-off-by: Kamil Trzciński Signed-off-by: Ondrej Jirman Signed-off-by: Peter Robinson Tested-by: Ondrej Jirman Link: https://lore.kernel.org/r/20230405123813.2272919-1-pbrobinson@gmail.com [increased Volume-Down voltage to 600mV as suggested by Ondrej] Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-pinephone-pro.dts | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 475ba78acc09..61f3fec5a8b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -10,6 +10,7 @@ */ /dts-v1/; +#include #include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -29,6 +30,26 @@ stdout-path = "serial2:115200n8"; }; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1600000>; + poll-interval = <100>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <600000>; + }; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm0 0 50000 0>; @@ -519,6 +540,11 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-sd-highspeed; From 2c25b94f881cf9389001cc08b1232a8099b3f8bf Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 18 Apr 2023 10:24:27 +0200 Subject: [PATCH 1040/1040] ARM: config: Update Vexpress defconfig The Versatile Express should conform to standard contemporary kernel features: add NO_HZ_FULL and HIGH_RES_TIMERS. Also add the AFS flash partitions as these are used on the platform. The removed SCHED_DEBUG is due to Kconfig changes. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20230418082427.186677-1-linus.walleij@linaro.org Signed-off-by: Arnd Bergmann --- arch/arm/configs/vexpress_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index ac3fd7523698..96ad442089bd 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig @@ -1,5 +1,7 @@ # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y +CONFIG_NO_HZ_FULL=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -42,6 +44,7 @@ CONFIG_NET_9P_VIRTIO=y CONFIG_DEVTMPFS=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_AFS_PARTS=y CONFIG_MTD_BLOCK=y CONFIG_MTD_CFI=y CONFIG_MTD_CFI_INTELEXT=y @@ -137,5 +140,4 @@ CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y CONFIG_MAGIC_SYSRQ=y CONFIG_DETECT_HUNG_TASK=y -# CONFIG_SCHED_DEBUG is not set CONFIG_DEBUG_USER=y