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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

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* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (51 commits)
  [MIPS] Make timer interrupt frequency configurable from kconfig.
  [MIPS] Correct HAL2 Kconfig description
  [MIPS] Fix R4K cache macro names
  [MIPS] Add Missing R4K Cache Macros to IP27 & IP32
  [MIPS] Support for the RM9000-based Basler eXcite smart camera platform.
  [MIPS] Support for the R5500-based NEC EMMA2RH Mark-eins board
  [MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors.
  [MIPS] SN: include asm/sn/types.h for nasid_t.
  [MIPS] Random fixes for sb1250
  [MIPS] Fix bcm1480 compile
  [MIPS] Remove support for NEC DDB5476.
  [MIPS] Remove support for NEC DDB5074.
  [MIPS] Cleanup memory managment initialization.
  [MIPS] SN: Declare bridge_pci_ops.
  [MIPS] Remove unused function alloc_pci_controller.
  [MIPS] IP27: Extract pci_ops into separate file.
  [MIPS] IP27: Use symbolic constants instead of magic numbers.
  [MIPS] vr41xx: remove unnecessay items from vr41xx/Kconfig.
  [MIPS] IP27: Cleanup N/M mode configuration.
  [MIPS] IP27: Throw away old unused hacks.
  ...
This commit is contained in:
Linus Torvalds
2006-06-19 19:07:12 -07:00
parent 4c84a39c8a 1723b4a34a
commit 25f42b6af0
249 changed files with 9995 additions and 4174 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-mips/addrspace.h
-35
View File
@@ -133,57 +133,22 @@
|| defined (CONFIG_CPU_NEVADA) \
|| defined (CONFIG_CPU_TX49XX) \
|| defined (CONFIG_CPU_MIPS64)
#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
#define K1SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
#define K2SIZE _LLCONST_(0x000000ff80000000)
#define KSEGSIZE _LLCONST_(0x000000ff80000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */
#endif
#if defined (CONFIG_CPU_R8000)
/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K2SIZE _LLCONST_(0x0001000000000000)
#define KSEGSIZE _LLCONST_(0x0000010000000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
#endif
#if defined (CONFIG_CPU_R10000)
#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K2SIZE _LLCONST_(0x00000fff80000000)
#define KSEGSIZE _LLCONST_(0x00000fff80000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
#endif
#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */
#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
#define K1SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
#define K2SIZE _LLCONST_(0x0000ffff80000000)
#define KSEGSIZE _LLCONST_(0x0000ffff80000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */
#endif
/*
* Further names for SGI source compatibility. These are stolen from
* IRIX's <sys/mips_addrspace.h>.
*/
#define KUBASE _LLCONST_(0)
#define KUSIZE_32 _LLCONST_(0x0000000080000000) /* KUSIZE
for a 32 bit proc */
#define K0BASE_EXL_WR _LLCONST_(0xa800000000000000) /* exclusive on write */
#define K0BASE_NONCOH _LLCONST_(0x9800000000000000) /* noncoherent */
#define K0BASE_EXL _LLCONST_(0xa000000000000000) /* exclusive */
#ifndef CONFIG_CPU_R8000
/*
include/asm-mips/apm.h
+65
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@@ -0,0 +1,65 @@
/* -*- linux-c -*-
*
* (C) 2003 zecke@handhelds.org
*
* GPL version 2
*
* based on arch/arm/kernel/apm.c
* factor out the information needed by architectures to provide
* apm status
*
*
*/
#ifndef MIPS_ASM_SA1100_APM_H
#define MIPS_ASM_SA1100_APM_H
#include <linux/config.h>
#include <linux/apm_bios.h>
/*
* This structure gets filled in by the machine specific 'get_power_status'
* implementation. Any fields which are not set default to a safe value.
*/
struct apm_power_info {
unsigned char ac_line_status;
#define APM_AC_OFFLINE 0
#define APM_AC_ONLINE 1
#define APM_AC_BACKUP 2
#define APM_AC_UNKNOWN 0xff
unsigned char battery_status;
#define APM_BATTERY_STATUS_HIGH 0
#define APM_BATTERY_STATUS_LOW 1
#define APM_BATTERY_STATUS_CRITICAL 2
#define APM_BATTERY_STATUS_CHARGING 3
#define APM_BATTERY_STATUS_NOT_PRESENT 4
#define APM_BATTERY_STATUS_UNKNOWN 0xff
unsigned char battery_flag;
#define APM_BATTERY_FLAG_HIGH (1 << 0)
#define APM_BATTERY_FLAG_LOW (1 << 1)
#define APM_BATTERY_FLAG_CRITICAL (1 << 2)
#define APM_BATTERY_FLAG_CHARGING (1 << 3)
#define APM_BATTERY_FLAG_NOT_PRESENT (1 << 7)
#define APM_BATTERY_FLAG_UNKNOWN 0xff
int battery_life;
int time;
int units;
#define APM_UNITS_MINS 0
#define APM_UNITS_SECS 1
#define APM_UNITS_UNKNOWN -1
};
/*
* This allows machines to provide their own "apm get power status" function.
*/
extern void (*apm_get_power_status)(struct apm_power_info *);
/*
* Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND)
*/
void apm_queue_event(apm_event_t event);
#endif
include/asm-mips/asmmacro-32.h
+2 -2
View File
@@ -12,7 +12,7 @@
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro fpu_save_double thread status tmp1=t0 tmp2
.macro fpu_save_double thread status tmp1=t0
cfc1 \tmp1, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
@@ -70,7 +70,7 @@
sw \tmp, THREAD_FCR31(\thread)
.endm
.macro fpu_restore_double thread tmp=t0
.macro fpu_restore_double thread status tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
include/asm-mips/asmmacro-64.h
+9 -10
View File
@@ -53,12 +53,12 @@
sdc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_save_double thread status tmp1 tmp2
sll \tmp2, \tmp1, 5
bgez \tmp2, 2f
.macro fpu_save_double thread status tmp
sll \tmp, \status, 5
bgez \tmp, 2f
fpu_save_16odd \thread
2:
fpu_save_16even \thread \tmp1 # clobbers t1
fpu_save_16even \thread \tmp
.endm
.macro fpu_restore_16even thread tmp=t0
@@ -101,13 +101,12 @@
ldc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_restore_double thread tmp
mfc0 t0, CP0_STATUS
sll t1, t0, 5
bgez t1, 1f # 16 register mode?
.macro fpu_restore_double thread status tmp
sll \tmp, \status, 5
bgez \tmp, 1f # 16 register mode?
fpu_restore_16odd a0
1: fpu_restore_16even a0, t0 # clobbers t0
fpu_restore_16odd \thread
1: fpu_restore_16even \thread \tmp
.endm
.macro cpu_save_nonscratch thread
include/asm-mips/bootinfo.h
+13
View File
@@ -217,6 +217,13 @@
*/
#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
/*
* Valid machtype for group NEC EMMA2RH
*/
#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
#define CL_SIZE COMMAND_LINE_SIZE
@@ -258,4 +265,10 @@ extern char arcs_cmdline[CL_SIZE];
* Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
*/
extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
/*
* Platform memory detection hook called by setup_arch
*/
extern void plat_mem_setup(void);
#endif /* _ASM_BOOTINFO_H */
include/asm-mips/ddb5074.h
-11
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@@ -1,11 +0,0 @@
/*
* include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
extern void ddb5074_led_hex(int hex);
extern void ddb5074_led_d2(int on);
extern void ddb5074_led_d3(int on);
include/asm-mips/ddb5xxx/ddb5074.h
-38
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@@ -1,38 +0,0 @@
/*
* include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#ifndef _ASM_DDB5XXX_DDB5074_H
#define _ASM_DDB5XXX_DDB5074_H
#include <asm/nile4.h>
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
#define NILE4_PCI_IO_BASE 0xa6000000
#define NILE4_PCI_MEM_BASE 0xa8000000
#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
#define CPU_NILE4_CASCADE 2
extern void ddb5074_led_hex(int hex);
extern void ddb5074_led_d2(int on);
extern void ddb5074_led_d3(int on);
extern void nile4_irq_setup(u32 base);
#endif
include/asm-mips/ddb5xxx/ddb5476.h
-157
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@@ -1,157 +0,0 @@
/*
* header file specific for ddb5476
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
/* aliases */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
/* PCI intr ack share PCIW0 with PCI IO */
#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
/*
* Interrupt mapping
*
* We have three interrupt controllers:
*
* . CPU itself - 8 sources
* . i8259 - 16 sources
* . vrc5476 - 16 sources
*
* They connected as follows:
* all vrc5476 interrupts are routed to cpu IP2 (by software setting)
* all i2869 are routed to INTC in vrc5476 (by hardware connection)
*
* All VRC5476 PCI interrupts are level-triggered (no ack needed).
* All PCI irq but INTC are active low.
*/
/*
* irq number block assignment
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5476_IRQ 16
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
/*
* vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
*/
#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
#define VRC5476_IRQ_CNTD 1 /* cpu no target */
#define VRC5476_IRQ_MCE 2 /* memory check error */
#define VRC5476_IRQ_DMA 3 /* DMA */
#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
#define VRC5476_IRQ_GPT 6 /* general purpose timer */
#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
#define VRC5476_IRQ_PCI 15 /* PCI internal error */
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 0
#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
#define I8259_IRQ_CASCADE 2
#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A 4 /* M1543 default */
#define I8259_IRQ_PARALLEL 5 /* M1543 default */
#define I8259_IRQ_RESERVED_6 6
#define I8259_IRQ_RESERVED_7 7
#define I8259_IRQ_RTC 8 /* who set this? */
#define I8259_IRQ_USB 9 /* ddb_setup */
#define I8259_IRQ_PMU 10 /* ddb_setup */
#define I8259_IRQ_RESERVED_11 11
#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 13
#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
#define I8259_IRQ_HDC2 15 /* default */
/*
* misc
*/
#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
#define CPU_VRC5476_CASCADE 2
#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
/*
* low-level irq functions
*/
#ifndef __ASSEMBLY__
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(int nile4_irq);
extern void nile4_disable_irq(int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void); /* Debug */
#endif /* !__ASSEMBLY__ */
include/asm-mips/ddb5xxx/ddb5xxx.h
+1 -10
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@@ -174,13 +174,8 @@
static inline void ddb_sync(void)
{
/* The DDB5074 doesn't seem to like these accesses. They kill the board on
* interrupt load
*/
#ifndef CONFIG_DDB5074
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
#endif
}
static inline void ddb_out32(u32 offset, u32 val)
@@ -260,11 +255,7 @@ extern void ddb_pci_reset_bus(void);
/*
* include the board dependent part
*/
#if defined(CONFIG_DDB5074)
#include <asm/ddb5xxx/ddb5074.h>
#elif defined(CONFIG_DDB5476)
#include <asm/ddb5xxx/ddb5476.h>
#elif defined(CONFIG_DDB5477)
#if defined(CONFIG_DDB5477)
#include <asm/ddb5xxx/ddb5477.h>
#else
#error "Unknown DDB board!"
include/asm-mips/emma2rh/emma2rh.h
+330
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@@ -0,0 +1,330 @@
/*
* include/asm-mips/emma2rh/emma2rh.h
* This file is EMMA2RH common header.
*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_EMMA2RH_EMMA2RH_H
#define __ASM_EMMA2RH_EMMA2RH_H
/*
* EMMA2RH registers
*/
#define REGBASE 0x10000000
#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
#define EMMA2RH_PCI_INT (0x200020+REGBASE)
#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
/* the actual ram size is detected at run-time */
#define EMMA2RH_RAM_BASE 0x00000000
#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */
#define EMMA2RH_IO_BASE 0x10000000
#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_GENERALIO_BASE 0x11000000
#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_PCI_IO_BASE 0x12000000
#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define EMMA2RH_PCI_MEM_BASE 0x14000000
#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define EMMA2RH_ROM_BASE 0x1c000000
#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */
#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
#define NUM_CPU_IRQ 8
#define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2
#define EMMA2RH_IRQ_BASE 0
/*
* emma2rh irq defs
*/
#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49
#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50
#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51
#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56
#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57
#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58
/*
* EMMA2RH Register Access
*/
#define EMMA2RH_BASE (0xa0000000)
static inline void emma2rh_sync(void)
{
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
}
static inline void emma2rh_out32(u32 offset, u32 val)
{
*(volatile u32 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u32 emma2rh_in32(u32 offset)
{
u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
static inline void emma2rh_out16(u32 offset, u16 val)
{
*(volatile u16 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u16 emma2rh_in16(u32 offset)
{
u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
static inline void emma2rh_out8(u32 offset, u8 val)
{
*(volatile u8 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u8 emma2rh_in8(u32 offset)
{
u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
/**
* IIC registers map
**/
/*---------------------------------------------------------------------------*/
/* CNT - Control register (00H R/W) */
/*---------------------------------------------------------------------------*/
#define SPT 0x00000001
#define STT 0x00000002
#define ACKE 0x00000004
#define WTIM 0x00000008
#define SPIE 0x00000010
#define WREL 0x00000020
#define LREL 0x00000040
#define IICE 0x00000080
#define CNT_RESERVED 0x000000ff /* reserved bit 0 */
#define I2C_EMMA_START (IICE | STT)
#define I2C_EMMA_STOP (IICE | SPT)
#define I2C_EMMA_REPSTART I2C_EMMA_START
/*---------------------------------------------------------------------------*/
/* STA - Status register (10H Read) */
/*---------------------------------------------------------------------------*/
#define MSTS 0x00000080
#define ALD 0x00000040
#define EXC 0x00000020
#define COI 0x00000010
#define TRC 0x00000008
#define ACKD 0x00000004
#define STD 0x00000002
#define SPD 0x00000001
/*---------------------------------------------------------------------------*/
/* CSEL - Clock select register (20H R/W) */
/*---------------------------------------------------------------------------*/
#define FCL 0x00000080
#define ND50 0x00000040
#define CLD 0x00000020
#define DAD 0x00000010
#define SMC 0x00000008
#define DFC 0x00000004
#define CL 0x00000003
#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */
#define FAST397 0x0000008b
#define FAST297 0x0000008a
#define FAST347 0x0000000b
#define FAST260 0x0000000a
#define FAST130 0x00000008
#define STANDARD108 0x00000083
#define STANDARD83 0x00000082
#define STANDARD95 0x00000003
#define STANDARD73 0x00000002
#define STANDARD36 0x00000001
#define STANDARD71 0x00000000
/*---------------------------------------------------------------------------*/
/* SVA - Slave address register (30H R/W) */
/*---------------------------------------------------------------------------*/
#define SVA 0x000000fe
/*---------------------------------------------------------------------------*/
/* SHR - Shift register (40H R/W) */
/*---------------------------------------------------------------------------*/
#define SR 0x000000ff
/*---------------------------------------------------------------------------*/
/* INT - Interrupt register (50H R/W) */
/* INTM - Interrupt mask register (60H R/W) */
/*---------------------------------------------------------------------------*/
#define INTE0 0x00000001
/***********************************************************************
* I2C registers
***********************************************************************
*/
#define I2C_EMMA_CNT 0x00
#define I2C_EMMA_STA 0x10
#define I2C_EMMA_CSEL 0x20
#define I2C_EMMA_SVA 0x30
#define I2C_EMMA_SHR 0x40
#define I2C_EMMA_INT 0x50
#define I2C_EMMA_INTM 0x60
/*
* include the board dependent part
*/
#if defined(CONFIG_MARKEINS)
#include <asm/emma2rh/markeins.h>
#else
#error "Unknown EMMA2RH board!"
#endif
#endif /* __ASM_EMMA2RH_EMMA2RH_H */
include/asm-mips/emma2rh/markeins.h
+76
View File
@@ -0,0 +1,76 @@
/*
* include/asm-mips/emma2rh/markeins.h
* This file is EMMA2RH board depended header.
*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef MARKEINS_H
#define MARKEINS_H
#define NUM_EMMA2RH_IRQ_SW 32
#define NUM_EMMA2RH_IRQ_GPIO 32
#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
#define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE)
#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17
#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18
#endif /* CONFIG_MARKEINS */
include/asm-mips/fpu.h
+1 -2
View File
@@ -138,10 +138,9 @@ static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
if (cpu_has_fpu) {
if ((tsk == current) && __is_fpu_owner())
_save_fp(current);
return tsk->thread.fpu.hard.fpr;
}
return tsk->thread.fpu.soft.fpr;
return tsk->thread.fpu.fpr;
}
#endif /* _ASM_FPU_H */
include/asm-mips/fpu_emulator.h
+2 -2
View File
@@ -12,8 +12,8 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Further private data for which no space exists in mips_fpu_soft_struct.
* This should be subsumed into the mips_fpu_soft_struct structure as
* Further private data for which no space exists in mips_fpu_struct.
* This should be subsumed into the mips_fpu_struct structure as
* defined in processor.h as soon as the absurd wired absolute assembler
* offsets become dynamic at compile time.
*
include/asm-mips/futex.h
+17 -15
View File
@@ -22,51 +22,53 @@
" .set push \n" \
" .set noat \n" \
" .set mips3 \n" \
"1: ll %1, (%3) # __futex_atomic_op \n" \
"1: ll %1, %4 # __futex_atomic_op \n" \
" .set mips0 \n" \
" " insn " \n" \
" .set mips3 \n" \
"2: sc $1, (%3) \n" \
"2: sc $1, %2 \n" \
" beqzl $1, 1b \n" \
__FUTEX_SMP_SYNC \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %5 \n" \
"4: li %0, %6 \n" \
" j 2b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=r" (oldval) \
: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
: "memory"); \
} else if (cpu_has_llsc) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set mips3 \n" \
"1: ll %1, (%3) # __futex_atomic_op \n" \
"1: ll %1, %4 # __futex_atomic_op \n" \
" .set mips0 \n" \
" " insn " \n" \
" .set mips3 \n" \
"2: sc $1, (%3) \n" \
"2: sc $1, %2 \n" \
" beqz $1, 1b \n" \
__FUTEX_SMP_SYNC \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %5 \n" \
"4: li %0, %6 \n" \
" j 2b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=r" (oldval) \
: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
: "memory"); \
} else \
ret = -ENOSYS; \
}
@@ -89,23 +91,23 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
switch (op) {
case FUTEX_OP_SET:
__futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg);
__futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ADD:
__futex_atomic_op("addu $1, %1, %z4",
__futex_atomic_op("addu $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_OR:
__futex_atomic_op("or $1, %1, %z4",
__futex_atomic_op("or $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ANDN:
__futex_atomic_op("and $1, %1, %z4",
__futex_atomic_op("and $1, %1, %z5",
ret, oldval, uaddr, ~oparg);
break;
case FUTEX_OP_XOR:
__futex_atomic_op("xor $1, %1, %z4",
__futex_atomic_op("xor $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
default:
include/asm-mips/mach-ddb5074/mc146818rtc.h
-31
View File
@@ -1,31 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 2001, 03 by Ralf Baechle
*
* RTC routines for PC style attached Dallas chip.
*/
#ifndef __ASM_MACH_DDB5074_MC146818RTC_H
#define __ASM_MACH_DDB5074_MC146818RTC_H
#include <asm/ddb5xxx/ddb5074.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#define RTC_PORT(x) (0x70 + (x))
#define RTC_IRQ 8
static inline unsigned char CMOS_READ(unsigned long addr)
{
return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
}
static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
{
*(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data;
}
#define RTC_ALWAYS_BCD 1
#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */
include/asm-mips/mach-dec/param.h
-18
View File
@@ -1,18 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_DEC_PARAM_H
#define __ASM_MACH_DEC_PARAM_H
/*
* log2(HZ), change this here if you want another HZ value. This is also
* used in dec_time_init. Minimum is 1, Maximum is 15.
*/
#define LOG_2_HZ 7
#define HZ (1 << LOG_2_HZ)
#endif /* __ASM_MACH_DEC_PARAM_H */
include/asm-mips/mach-mips/param.h → include/asm-mips/mach-emma2rh/irq.h
+4 -4
View File
@@ -5,9 +5,9 @@
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_MIPS_PARAM_H
#define __ASM_MACH_MIPS_PARAM_H
#ifndef __ASM_MACH_EMMA2RH_IRQ_H
#define __ASM_MACH_EMMA2RH_IRQ_H
#define HZ 100 /* Internal kernel timer frequency */
#define NR_IRQS 256
#endif /* __ASM_MACH_MIPS_PARAM_H */
#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
include/asm-mips/mach-excite/cpu-feature-overrides.h
+40
View File
@@ -0,0 +1,40 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
*/
#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
/*
* Basler eXcite has an RM9122 processor.
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-excite/excite.h
+155
View File
@@ -0,0 +1,155 @@
#ifndef __EXCITE_H__
#define __EXCITE_H__
#include <linux/config.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#define EXCITE_CPU_EXT_CLOCK 100000000
#if !defined(__ASSEMBLER__)
void __init excite_kgdb_init(void);
void excite_procfs_init(void);
extern unsigned long memsize;
extern char modetty[];
extern u32 unit_id;
#endif
/* Base name for XICAP devices */
#define XICAP_NAME "xicap_gpi"
/* OCD register offsets */
#define LKB0 0x0038
#define LKB5 0x0128
#define LKM5 0x012C
#define LKB7 0x0138
#define LKM7 0x013c
#define LKB8 0x0140
#define LKM8 0x0144
#define LKB9 0x0148
#define LKM9 0x014c
#define LKB10 0x0150
#define LKM10 0x0154
#define LKB11 0x0158
#define LKM11 0x015c
#define LKB12 0x0160
#define LKM12 0x0164
#define LKB13 0x0168
#define LKM13 0x016c
#define LDP0 0x0200
#define LDP1 0x0210
#define LDP2 0x0220
#define LDP3 0x0230
#define INTPIN0 0x0A40
#define INTPIN1 0x0A44
#define INTPIN2 0x0A48
#define INTPIN3 0x0A4C
#define INTPIN4 0x0A50
#define INTPIN5 0x0A54
#define INTPIN6 0x0A58
#define INTPIN7 0x0A5C
/* TITAN register offsets */
#define CPRR 0x0004
#define CPDSR 0x0008
#define CPTC0R 0x000c
#define CPTC1R 0x0010
#define CPCFG0 0x0020
#define CPCFG1 0x0024
#define CPDST0A 0x0028
#define CPDST0B 0x002c
#define CPDST1A 0x0030
#define CPDST1B 0x0034
#define CPXDSTA 0x0038
#define CPXDSTB 0x003c
#define CPXCISRA 0x0048
#define CPXCISRB 0x004c
#define CPGIG0ER 0x0050
#define CPGIG1ER 0x0054
#define CPGRWL 0x0068
#define CPURSLMT 0x00f8
#define UACFG 0x0200
#define UAINTS 0x0204
#define SDRXFCIE 0x4828
#define SDTXFCIE 0x4928
#define INTP0Status0 0x1B00
#define INTP0Mask0 0x1B04
#define INTP0Set0 0x1B08
#define INTP0Clear0 0x1B0C
#define GXCFG 0x5000
#define GXDMADRPFX 0x5018
#define GXDMA_DESCADR 0x501c
#define GXCH0TDESSTRT 0x5054
/* IRQ definitions */
#define NMICONFIG 0xac0
#define TITAN_MSGINT 0xc4
#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
#define FPGA0_MSGINT 0x5a
#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
#define FPGA1_MSGINT 0x7b
#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
#define PHY_MSGINT 0x9c
#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
/* Pre-release units used interrupt pin #9 */
#define USB_IRQ 11
#else
/* Re-designed units use interrupt pin #1 */
#define USB_MSGINT 0x39
#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
#endif
#define TIMER_IRQ 12
/* Device address ranges */
#define EXCITE_OFFS_OCD 0x1fffc000
#define EXCITE_SIZE_OCD (16 * 1024)
#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
#define EXCITE_OFFS_SCRAM 0x1fffa000
#define EXCITE_SIZE_SCRAM (8 << 10)
#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_OFFS_PCI_IO 0x1fff8000
#define EXCITE_SIZE_PCI_IO (8 << 10)
#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_OFFS_TITAN 0x1fff0000
#define EXCITE_SIZE_TITAN (32 << 10)
#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
#define EXCITE_SIZE_PCI_MEM (64 << 10)
#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_OFFS_FPGA 0x1ffdc000
#define EXCITE_SIZE_FPGA (16 << 10)
#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
#define EXCITE_OFFS_NAND 0x1ffd8000
#define EXCITE_SIZE_NAND (16 << 10)
#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
#define EXCITE_OFFS_BOOTROM 0x1f000000
#define EXCITE_SIZE_BOOTROM (8 << 20)
#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
/* FPGA address offsets */
#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
#endif /* __EXCITE_H__ */
include/asm-mips/mach-excite/excite_nandflash.h
+7
View File
@@ -0,0 +1,7 @@
#ifndef __EXCITE_NANDFLASH_H__
#define __EXCITE_NANDFLASH_H__
/* Resource names */
#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
#endif /* __EXCITE_NANDFLASH_H__ */
include/asm-mips/mach-excite/rm9k_eth.h
+23
View File
@@ -0,0 +1,23 @@
#if !defined(__RM9K_ETH_H__)
#define __RM9K_ETH_H__
#define RM9K_GE_NAME "rm9k_ge"
/* Resource names */
#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
#endif /* !defined(__RM9K_ETH_H__) */
include/asm-mips/mach-excite/rm9k_wdt.h
+12
View File
@@ -0,0 +1,12 @@
#ifndef __RM9K_WDT_H__
#define __RM9K_WDT_H__
/* Device name */
#define WDT_NAME "wdt_gpi"
/* Resource names */
#define WDT_RESOURCE_REGS "excite_watchdog_regs"
#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
#endif /* __RM9K_WDT_H__ */
include/asm-mips/mach-excite/rm9k_xicap.h
+16
View File
@@ -0,0 +1,16 @@
#ifndef __EXCITE_XICAP_H__
#define __EXCITE_XICAP_H__
/* Resource names */
#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
#define XICAP_RESOURCE_XDMA "xicap_xdma"
#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
#define XICAP_RESOURCE_IRQ "xicap_irq"
#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
#endif /* __EXCITE_XICAP_H__ */
include/asm-mips/mach-generic/param.h
-13
View File
@@ -1,13 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_GENERIC_PARAM_H
#define __ASM_MACH_GENERIC_PARAM_H
#define HZ 1000 /* Internal kernel timer frequency */
#endif /* __ASM_MACH_GENERIC_PARAM_H */
include/asm-mips/mach-ip22/cpu-feature-overrides.h
+1 -1
View File
@@ -13,7 +13,7 @@
*/
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
include/asm-mips/mach-ip27/cpu-feature-overrides.h
+3
View File
@@ -31,6 +31,9 @@
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_4kex 1
#define cpu_has_4k_cache 1
#define cpu_has_subset_pcaches 1
#define cpu_dcache_line_size() 32
include/asm-mips/mach-ip32/cpu-feature-overrides.h
+2
View File
@@ -38,6 +38,8 @@
#define cpu_has_vtag_icache 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_4k_cache 1
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
include/asm-mips/mach-jazz/param.h
-16
View File
@@ -1,16 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_JAZZ_PARAM_H
#define __ASM_MACH_JAZZ_PARAM_H
/*
* Jazz is currently using the internal 100Hz timer of the R4030
*/
#define HZ 100 /* Internal kernel timer frequency */
#endif /* __ASM_MACH_JAZZ_PARAM_H */
include/asm-mips/mach-mips/cpu-feature-overrides.h
+2 -2
View File
@@ -17,7 +17,7 @@
#ifdef CONFIG_CPU_MIPS32
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
@@ -47,7 +47,7 @@
#ifdef CONFIG_CPU_MIPS64
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
include/asm-mips/mach-qemu/param.h
-13
View File
@@ -1,13 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005 by Ralf Baechle
*/
#ifndef __ASM_MACH_QEMU_PARAM_H
#define __ASM_MACH_QEMU_PARAM_H
#define HZ 100 /* Internal kernel timer frequency */
#endif /* __ASM_MACH_QEMU_PARAM_H */
include/asm-mips/mach-rm200/cpu-feature-overrides.h
+1 -3
View File
@@ -14,7 +14,7 @@
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
@@ -35,10 +35,8 @@
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 /* No S-cache on R5000 I think ... */
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
include/asm-mips/mach-sim/cpu-feature-overrides.h
+2 -2
View File
@@ -16,7 +16,7 @@
#ifdef CONFIG_CPU_MIPS32
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
#define cpu_has_fpu 0
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
@@ -41,7 +41,7 @@
#ifdef CONFIG_CPU_MIPS64
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
include/asm-mips/mach-wrppmc/mach-gt64120.h
+84
View File
@@ -0,0 +1,84 @@
/*
* This is a direct copy of the ev96100.h file, with a global
* search and replace. The numbers are the same.
*
* The reason I'm duplicating this is so that the 64120/96100
* defines won't be confusing in the source code.
*/
#ifndef __ASM_MIPS_GT64120_H
#define __ASM_MIPS_GT64120_H
/*
* This is the CPU physical memory map of PPMC Board:
*
* 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
* 0x1C000000-0x1C000000 - LED (CS0)
* 0x1C800000-0x1C800007 - UART 16550 port (CS1)
* 0x1F000000-0x1F000000 - MailBox (CS3)
* 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
*/
#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
#define WRPPMC_UART16550_BASE 0x1C800000
#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
#define WRPPMC_LED_BASE 0x1C000000
#define WRPPMC_MBOX_BASE 0x1F000000
#define WRPPMC_BOOTROM_BASE 0x1FC00000
#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
#define WRPPMC_UART16550_IRQ 6
#define WRPPMC_PCI_INTA_IRQ 3
/*
* PCI Bus I/O and Memory resources allocation
*
* NOTE: We only have PCI_0 hose interface
*/
#define GT_PCI_MEM_BASE 0x13000000UL
#define GT_PCI_MEM_SIZE 0x02000000UL
#define GT_PCI_IO_BASE 0x11000000UL
#define GT_PCI_IO_SIZE 0x02000000UL
#define GT_ISA_IO_BASE PCI_IO_BASE
/*
* PCI interrupts will come in on either the INTA or INTD interrups lines,
* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
* boards, they all either come in on IntD or they all come in on IntA, they
* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
* "requested" interrupt numbers and go through the list whenever we get an
* IntA/D.
*
* Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
* INTD is 11.
*/
#define GT_TIMER 4
#define GT_INTA 2
#define GT_INTD 5
#ifndef __ASSEMBLY__
/*
* GT64120 internal register space base address
*/
extern unsigned long gt64120_base;
#define GT64120_BASE (gt64120_base)
/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
#undef WRPPMC_EARLY_DEBUG
#ifdef WRPPMC_EARLY_DEBUG
extern void wrppmc_led_on(int mask);
extern void wrppmc_led_off(int mask);
extern void wrppmc_early_printk(const char *fmt, ...);
#else
#define wrppmc_early_printk(fmt, ...) do {} while (0)
#endif /* WRPPMC_EARLY_DEBUG */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_MIPS_GT64120_H */
include/asm-mips/mipsregs.h
+1 -3
View File
@@ -1451,12 +1451,10 @@ static inline void __emt(unsigned int previous)
{
if ((previous & __EMT_ENABLE))
__asm__ __volatile__(
" .set noreorder \n"
" .set mips32r2 \n"
" .word 0x41600be1 # emt \n"
" ehb \n"
" .set mips0 \n"
" .set reorder \n");
" .set mips0 \n");
}
static inline void __ehb(void)
include/asm-mips/mmzone.h
-11
View File
@@ -14,17 +14,6 @@
#define kvaddr_to_nid(kvaddr) pa_to_nid(__pa(kvaddr))
#define pfn_to_nid(pfn) pa_to_nid((pfn) << PAGE_SHIFT)
#define pfn_valid(pfn) \
({ \
unsigned long __pfn = (pfn); \
int __n = pfn_to_nid(__pfn); \
((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
NODE_DATA(__n)->node_spanned_pages) : 0);\
})
/* XXX: FIXME -- wli */
#define kern_addr_valid(addr) (0)
#endif /* CONFIG_DISCONTIGMEM */
#endif /* _ASM_MMZONE_H_ */
include/asm-mips/page.h
+19
View File
@@ -145,6 +145,25 @@ typedef struct { unsigned long pgprot; } pgprot_t;
#endif
#endif
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) ((pfn) < max_mapnr)
#elif defined(CONFIG_NEED_MULTIPLE_NODES)
#define pfn_valid(pfn) \
({ \
unsigned long __pfn = (pfn); \
int __n = pfn_to_nid(__pfn); \
((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
NODE_DATA(__n)->node_spanned_pages) \
: 0); \
})
#else
#error Provide a definition of pfn_valid
#endif
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
include/asm-mips/param.h
+1 -1
View File
@@ -11,7 +11,7 @@
#ifdef __KERNEL__
# include <param.h> /* Internal kernel timer frequency */
# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif
include/asm-mips/pci/bridge.h
+3
View File
@@ -15,6 +15,7 @@
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/xtalk/xwidget.h> /* generic widget header */
#include <asm/sn/types.h>
/* I/O page size */
@@ -848,4 +849,6 @@ struct bridge_controller {
extern void register_bridge_irq(unsigned int irq);
extern int request_bridge_irq(struct bridge_controller *bc);
extern struct pci_ops bridge_pci_ops;
#endif /* _ASM_PCI_BRIDGE_H */
include/asm-mips/pgtable.h
-2
View File
@@ -379,9 +379,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
__update_cache(vma, address, pte);
}
#ifndef CONFIG_NEED_MULTIPLE_NODES
#define kern_addr_valid(addr) (1)
#endif
#ifdef CONFIG_64BIT_PHYS_ADDR
extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
include/asm-mips/processor.h
+3 -13
View File
@@ -71,11 +71,6 @@ extern unsigned int vced_count, vcei_count;
typedef __u64 fpureg_t;
struct mips_fpu_hard_struct {
fpureg_t fpr[NUM_FPU_REGS];
unsigned int fcr31;
};
/*
* It would be nice to add some more fields for emulator statistics, but there
* are a number of fixed offsets in offset.h and elsewhere that would have to
@@ -83,18 +78,13 @@ struct mips_fpu_hard_struct {
* the FPU emulator for now. See asm-mips/fpu_emulator.h.
*/
struct mips_fpu_soft_struct {
struct mips_fpu_struct {
fpureg_t fpr[NUM_FPU_REGS];
unsigned int fcr31;
};
union mips_fpu_union {
struct mips_fpu_hard_struct hard;
struct mips_fpu_soft_struct soft;
};
#define INIT_FPU { \
{{0,},} \
{0,} \
}
#define NUM_DSP_REGS 6
@@ -133,7 +123,7 @@ struct thread_struct {
unsigned long cp0_status;
/* Saved fpu/fpu emulator stuff. */
union mips_fpu_union fpu;
struct mips_fpu_struct fpu;
#ifdef CONFIG_MIPS_MT_FPAFF
/* Emulated instruction count */
unsigned long emulated_fp;
include/asm-mips/qemu.h
+6
View File
@@ -21,4 +21,10 @@
*/
#define QEMU_C0_COUNTER_CLOCK 100000000
/*
* Magic qemu system control location.
*/
#define QEMU_RESTART_REG 0xBFBF0000
#define QEMU_HALT_REG 0xBFBF0004
#endif /* __ASM_QEMU_H */
include/asm-mips/rm9k-ocd.h
+56
View File
@@ -0,0 +1,56 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if !defined(_ASM_RM9K_OCD_H)
#define _ASM_RM9K_OCD_H
#include <linux/types.h>
#include <linux/spinlock.h>
#include <asm/io.h>
extern volatile void __iomem * const ocd_base;
extern volatile void __iomem * const titan_base;
#define ocd_addr(__x__) (ocd_base + (__x__))
#define titan_addr(__x__) (titan_base + (__x__))
#define scram_addr(__x__) (scram_base + (__x__))
/* OCD register access */
#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
#define ocd_writel(__val__, __offs__) \
__raw_writel((__val__), ocd_addr(__offs__))
#define ocd_writew(__val__, __offs__) \
__raw_writew((__val__), ocd_addr(__offs__))
#define ocd_writeb(__val__, __offs__) \
__raw_writeb((__val__), ocd_addr(__offs__))
/* TITAN register access - 32 bit-wide only */
#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
#define titan_writel(__val__, __offs__) \
__raw_writel((__val__), titan_addr(__offs__))
/* Protect access to shared TITAN registers */
extern spinlock_t titan_lock;
extern int titan_irqflags;
#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
#endif /* !defined(_ASM_RM9K_OCD_H) */
include/asm-mips/sn/addrs.h
-27
View File
@@ -27,13 +27,8 @@
#ifndef __ASSEMBLY__
#if defined(CONFIG_SGI_IO) /* FIXME */
#define PS_UINT_CAST (__psunsigned_t)
#define UINT64_CAST (__uint64_t)
#else /* CONFIG_SGI_IO */
#define PS_UINT_CAST (unsigned long)
#define UINT64_CAST (unsigned long)
#endif /* CONFIG_SGI_IO */
#define HUBREG_CAST (volatile hubreg_t *)
@@ -253,14 +248,6 @@
* for _x.
*/
#ifdef _STANDALONE
/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#endif /* _STANDALONE */
/*
* WARNING:
* When certain Hub chip workaround are defined, it's not sufficient
@@ -327,20 +314,6 @@
PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
#define ARCS_SPB_SIZE 0x0400
#ifdef _STANDALONE
#define ARCS_TVECTOR_OFFSET 0x2800
#define ARCS_PVECTOR_OFFSET 0x2c00
/*
* These addresses are used by the master CPU to install the transfer
* and private vectors. All others use the SPB to find them.
*/
#define TVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
#define PVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
#endif /* _STANDALONE */
#define KLDIR_OFFSET 0x2000
#define KLDIR_ADDR(nasid) \
TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
include/asm-mips/sn/sn0/sn0_fru.h → include/asm-mips/sn/fru.h
+4 -4
View File
@@ -6,10 +6,10 @@
* Derived from IRIX <sys/SN/SN0/sn0_fru.h>
*
* Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
*/
#ifndef _ASM_SN_SN0_SN0_FRU_H
#define _ASM_SN_SN0_SN0_FRU_H
#ifndef __ASM_SN_FRU_H
#define __ASM_SN_FRU_H
#define MAX_DIMMS 8 /* max # of dimm banks */
#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
@@ -41,4 +41,4 @@ typedef struct kf_pci_bus_s {
/* confidence level that the pci dev is bad */
} kf_pci_bus_t;
#endif /* _ASM_SN_SN0_SN0_FRU_H */
#endif /* __ASM_SN_FRU_H */
include/asm-mips/sn/klconfig.h
+3 -86
View File
@@ -37,7 +37,7 @@
//#include <sys/SN/router.h>
// XXX Stolen from <sys/SN/router.h>:
#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */
#include <asm/sn/sn0/sn0_fru.h>
#include <asm/sn/fru.h>
//#include <sys/graph.h>
//#include <sys/xtalk/xbow.h>
@@ -54,32 +54,21 @@
#include <asm/sn/agent.h>
#include <asm/arc/types.h>
#include <asm/arc/hinv.h>
#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35)
#if defined(CONFIG_SGI_IP35)
// The hack file has to be before vector and after sn0_fru....
#include <asm/hack.h>
#include <asm/sn/vector.h>
#include <asm/xtalk/xtalk.h>
#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */
#endif /* CONFIG_SGI_IP35 */
#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
#define KLCFGINFO_MAGIC 0xbeedbabe
#ifdef FRUTEST
typedef u64 klconf_off_t;
#else
typedef s32 klconf_off_t;
#endif
/*
* Some IMPORTANT OFFSETS. These are the offsets on all NODES.
*/
#if 0
#define RAMBASE 0
#define ARCSSPB_OFF 0x1000 /* shift it to sys/arcs/spb.h */
#define OFF_HWGRAPH 0
#endif
#define MAX_MODULE_ID 255
#define SIZE_PAD 4096 /* 4k padding for structures */
/*
@@ -134,15 +123,9 @@ typedef s32 klconf_off_t;
typedef struct console_s {
#if defined(CONFIG_SGI_IO) /* FIXME */
__psunsigned_t uart_base;
__psunsigned_t config_base;
__psunsigned_t memory_base;
#else
unsigned long uart_base;
unsigned long config_base;
unsigned long memory_base;
#endif
short baud;
short flag;
int type;
@@ -174,10 +157,6 @@ typedef struct kl_config_hdr {
#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
#if 0
#define KL_CONFIG_MALLOC_HDR(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
#endif
#define KL_CONFIG_INFO_OFFSET(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_board_info)
#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \
@@ -197,23 +176,13 @@ typedef struct kl_config_hdr {
/* --- New Macros for the changed kl_config_hdr_t structure --- */
#if defined(CONFIG_SGI_IO)
#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
#else
#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
(unsigned long)_k + (_k->ch_malloc_hdr_off)))
#endif
#define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
#if defined(CONFIG_SGI_IO)
#define PTR_CH_CONS_INFO(_k) ((console_t *)\
((__psunsigned_t)_k + (_k->ch_cons_off)))
#else
#define PTR_CH_CONS_INFO(_k) ((console_t *)\
((unsigned long)_k + (_k->ch_cons_off)))
#endif
#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
@@ -490,14 +459,6 @@ typedef struct lboard_s {
#define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts)
#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module)
#ifdef FRUTEST
#define KLCF_NEXT(_brd) ((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next): NULL)
#define KLCF_COMP(_brd, _ndx) (klinfo_t *)((_brd)->brd_compts[(_ndx)])
#define KLCF_COMP_ERROR(_brd, _comp) (_brd = _brd , (_comp)->errinfo)
#else
#define KLCF_NEXT(_brd) \
((_brd)->brd_next ? \
(lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
@@ -509,8 +470,6 @@ typedef struct lboard_s {
#define KLCF_COMP_ERROR(_brd, _comp) \
(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
#endif
#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type)
#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */
@@ -631,18 +590,6 @@ typedef struct klport_s {
klconf_off_t port_offset;
} klport_t;
#if 0
/*
* This is very similar to the klport_s but instead of having a componant
* offset it has a board offset.
*/
typedef struct klxbow_port_s {
nasid_t port_nasid;
unsigned char port_flag;
klconf_off_t board_offset;
} klxbow_port_t;
#endif
typedef struct klcpu_s { /* CPU */
klinfo_t cpu_info;
unsigned short cpu_prid; /* Processor PRID value */
@@ -945,36 +892,6 @@ extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
#if defined(CONFIG_SGI_IO)
extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx);
extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx);
extern lboard_t *find_gfxpipe(int pipenum);
extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum);
extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
unsigned char brd_class);
extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
extern klcpu_t *get_cpuinfo(cpuid_t cpu);
extern int update_klcfg_cpuinfo(nasid_t, int);
extern void board_to_path(lboard_t *brd, char *path);
extern moduleid_t get_module_id(nasid_t nasid);
extern void nic_name_convert(char *old_name, char *new_name);
extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n);
extern lboard_t *brd_from_key(ulong_t key);
extern void device_component_canonical_name_get(lboard_t *,klinfo_t *,
char *);
extern int board_serial_number_get(lboard_t *,char *);
extern int is_master_baseio(nasid_t,moduleid_t,slotid_t);
extern nasid_t get_actual_nasid(lboard_t *brd) ;
extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
#else /* CONFIG_SGI_IO */
extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
#endif /* CONFIG_SGI_IO */
#endif /* _ASM_SN_KLCONFIG_H */
include/asm-mips/sn/kldir.h
+2 -32
View File
@@ -13,10 +13,6 @@
#include <linux/config.h>
#if defined(CONFIG_SGI_IO)
#include <asm/hack.h>
#endif
/*
* The kldir memory area resides at a fixed place in each node's memory and
* provides pointers to most other IP27 memory areas. This allows us to
@@ -136,8 +132,6 @@
#define KLDIR_OFF_STRIDE 0x28
#endif /* __ASSEMBLY__ */
#if !defined(CONFIG_SGI_IO)
/*
* This is defined here because IP27_SYMMON_STK_SIZE must be at least what
* we define here. Since it's set up in the prom. We can't redefine it later
@@ -147,7 +141,7 @@
*/
#define SYMMON_STACK_SIZE 0x8000
#if defined (PROM) || defined (SABLE)
#if defined (PROM)
/*
* These defines are prom version dependent. No code other than the IP27
@@ -184,7 +178,7 @@
#define IP27_FREEMEM_COUNT 1
#define IP27_FREEMEM_STRIDE 0
#endif /* PROM || SABLE*/
#endif /* PROM */
/*
* There will be only one of these in a partition so the IO6 must set it up.
*/
@@ -207,17 +201,11 @@
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
#endif /* !CONFIG_SGI_IO */
#ifndef __ASSEMBLY__
typedef struct kldir_ent_s {
u64 magic; /* Indicates validity of entry */
off_t offset; /* Offset from start of node space */
#if defined(CONFIG_SGI_IO) /* FIXME */
__psunsigned_t pointer; /* Pointer to area in some cases */
#else
unsigned long pointer; /* Pointer to area in some cases */
#endif
size_t size; /* Size in bytes */
u64 count; /* Repeat count if array, 1 if not */
size_t stride; /* Stride if array, 0 if not */
@@ -227,22 +215,4 @@ typedef struct kldir_ent_s {
} kldir_ent_t;
#endif /* !__ASSEMBLY__ */
#if defined(CONFIG_SGI_IO)
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
/*
* The actual offsets of each memory area are machine-dependent
*/
#ifdef CONFIG_SGI_IP27
// Not yet #include <asm/sn/sn0/kldir.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/kldir.h>
#else
#error "kldir.h is currently defined for IP27 and IP35 platforms only"
#endif
#endif /* CONFIG_SGI_IO */
#endif /* _ASM_SN_KLDIR_H */
include/asm-mips/sn/sn0/addrs.h
+6 -81
View File
@@ -49,7 +49,7 @@
* so for now we just use defines bracketed by an ifdef.
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#ifdef CONFIG_SGI_SN_N_MODE
#define NODE_SIZE_BITS 31
#define BWIN_SIZE_BITS 28
@@ -63,7 +63,7 @@
#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
#define NODE_SIZE_BITS 32
#define BWIN_SIZE_BITS 29
@@ -77,7 +77,7 @@
#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
@@ -85,15 +85,15 @@
#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
NASID_SHFT) & NASID_BITMASK)
#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
#if !defined(__ASSEMBLY__)
#define NODE_SWIN_BASE(nasid, widget) \
((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
: RAW_NODE_SWIN_BASE(nasid, widget))
#else /* __ASSEMBLY__ || _STANDALONE */
#else /* __ASSEMBLY__ */
#define NODE_SWIN_BASE(nasid, widget) \
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
#endif /* __ASSEMBLY__ || _STANDALONE */
#endif /* __ASSEMBLY__ */
/*
* The following definitions pertain to the IO special address
@@ -143,12 +143,7 @@
#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
/* Turn on sable logging for the processors whose bits are set. */
#ifdef SABLE
#define SABLE_LOG_TRIGGER(_map) \
*((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
#else
#define SABLE_LOG_TRIGGER(_map)
#endif /* SABLE */
#ifndef __ASSEMBLY__
#define KERN_NMI_ADDR(nasid, slice) \
@@ -281,76 +276,6 @@
#define _ARCSPROM
#ifdef _STANDALONE
/*
* The PROM needs to pass the device base address and the
* device pci cfg space address to the device drivers during
* install. The COMPONENT->Key field is used for this purpose.
* Macros needed by SN0 device drivers to convert the
* COMPONENT->Key field to the respective base address.
* Key field looks as follows:
*
* +----------------------------------------------------+
* |devnasid | widget |pciid |hubwidid|hstnasid | adap |
* | 2 | 1 | 1 | 1 | 2 | 1 |
* +----------------------------------------------------+
* | | | | | | |
* 64 48 40 32 24 8 0
*
* These are used by standalone drivers till the io infrastructure
* is in place.
*/
#ifndef __ASSEMBLY__
#define uchar unsigned char
#define KEY_DEVNASID_SHFT 48
#define KEY_WIDID_SHFT 40
#define KEY_PCIID_SHFT 32
#define KEY_HUBWID_SHFT 24
#define KEY_HSTNASID_SHFT 8
#define MK_SN0_KEY(nasid, widid, pciid) \
((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
#define ADD_HUBWID_KEY(key,hubwid)\
(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
#define ADD_HSTNASID_KEY(key,hstnasid)\
(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT))
#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT))
#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT))
#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT))
#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT))
#define PCI_64_TARGID_SHFT 60
#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
#define GET_PCICFGBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
#define GET_WIDBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key)))
#define PUT_INSTALL_STATUS(c,s) c->Revision = s
#define GET_INSTALL_STATUS(c) c->Revision
#endif /* !__ASSEMBLY__ */
#endif /* _STANDALONE */
#if defined (HUB_ERR_STS_WAR)
#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
include/asm-mips/sn/sn0/arch.h
+3 -14
View File
@@ -13,8 +13,6 @@
#include <linux/config.h>
#ifndef SABLE
#ifndef SN0XXL /* 128 cpu SMP max */
/*
* This is the maximum number of nodes that can be part of a kernel.
@@ -54,25 +52,16 @@
*/
#define MAX_PARTITIONS MAX_REGIONS
#else
#define MAX_COMPACT_NODES 4
#define MAX_NASIDS 4
#define MAXCPUS 8
#endif
#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8)
/*
* Slot constants for SN0
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#ifdef CONFIG_SGI_SN_N_MODE
#define MAX_MEM_SLOTS 16 /* max slots per node */
#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
#define MAX_MEM_SLOTS 32 /* max slots per node */
#endif /* defined(N_MODE) */
#endif /* CONFIG_SGI_SN_M_MODE */
#define SLOT_SHIFT (27)
#define SLOT_MIN_MEM_SIZE (32*1024*1024)
include/asm-mips/sn/sn0/hub.h
-4
View File
@@ -31,10 +31,6 @@
#include <asm/sn/sn0/hubni.h>
//#include <asm/sn/sn0/hubcore.h>
#ifdef SABLE
#define IP27_NO_HUBUART_INT 1
#endif
/* Translation of uncached attributes */
#define UATTR_HSPEC 0
#define UATTR_IO 1
include/asm-mips/sn/sn0/hubio.h
-16
View File
@@ -486,22 +486,6 @@ typedef union h1_icrba_u {
#define ICRBN_A_CERR_SHFT 54
#define ICRBN_A_ERR_MASK 0x3ff
#if 0 /* Disabled, this causes namespace polution and break allmodconfig */
/*
* Easy access macros.
*/
#define a_error icrba_fields_s.error
#define a_ecode icrba_fields_s.ecode
#define a_lnetuce icrba_fields_s.lnetuce
#define a_mark icrba_fields_s.mark
#define a_xerr icrba_fields_s.xerr
#define a_sidn icrba_fields_s.sidn
#define a_tnum icrba_fields_s.tnum
#define a_addr icrba_fields_s.addr
#define a_valid icrba_fields_s.valid
#define a_iow icrba_fields_s.iow
#endif
#endif /* !__ASSEMBLY__ */
#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
include/asm-mips/sn/sn0/hubmd.h
+1 -1
View File
@@ -92,7 +92,7 @@
#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
#ifdef CONFIG_SGI_SN0_N_MODE
#ifdef CONFIG_SGI_SN_N_MODE
#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
#else
#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
include/asm-mips/sn/sn0/hubpi.h
-18
View File
@@ -398,24 +398,6 @@ typedef u64 rtc_time_t;
/* PI_RT_FILTER_CTRL mask and shift definitions */
#if 0
/*
* XXX - This register's definition has changed, but it's only implemented
* in Hub 2.
*/
#define PRFC_DROP_COUNT_SHFT 27
#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27)
#define PRFC_DROP_CTR_SHFT 18
#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18)
#define PRFC_MASK_ENABLE_SHFT 10
#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10)
#define PRFC_MASK_CTR_SHFT 2
#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2)
#define PRFC_OFFSET_SHFT 0
#define PRFC_OFFSET_MASK (UINT64_CAST 3)
#endif /* 0 */
/*
* Bits for NACK_CNT_A/B and NACK_CMP
*/
include/asm-mips/sn/sn0/ip27.h
+1 -8
View File
@@ -6,7 +6,7 @@
* Derived from IRIX <sys/SN/SN0/IP27.h>.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
* Copyright (C) 1999, 2006 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_IP27_H
#define _ASM_SN_SN0_IP27_H
@@ -82,11 +82,4 @@
#define SEND_NMI(_nasid, _slice) \
REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
/* Sanity hazzard ... Below all the Origin hacks are following. */
#define SN00_BRIDGE 0x9200000008000000
#define SN00I_BRIDGE0 0x920000000b000000
#define SN00I_BRIDGE1 0x920000000e000000
#define SN00I_BRIDGE2 0x920000000f000000
#endif /* _ASM_SN_SN0_IP27_H */
include/asm-mips/sni.h
+2 -5
View File
@@ -15,9 +15,6 @@
/*
* ASIC PCI registers for little endian configuration.
*/
#ifndef __MIPSEL__
#error "Fix me for big endian"
#endif
#define PCIMT_UCONF 0xbfff0000
#define PCIMT_IOADTIMEOUT2 0xbfff0008
#define PCIMT_IOMEMCONF 0xbfff0010
@@ -51,9 +48,9 @@
#define PCIMT_PCI_CONF 0xbfff0100
/*
* Data port for the PCI bus.
* Data port for the PCI bus in IO space
*/
#define PCIMT_CONFIG_DATA 0xb4000cfc
#define PCIMT_CONFIG_DATA 0x0cfc
/*
* Board specific registers
include/asm-mips/war.h
+3 -2
View File
@@ -172,7 +172,8 @@
* On the RM9000 there is a problem which makes the CreateDirtyExclusive
* cache operation unusable on SMP systems.
*/
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
defined(CONFIG_BASLER_EXCITE)
#define RM9000_CDEX_SMP_WAR 1
#endif
@@ -182,7 +183,7 @@
* being fetched may case spurious exceptions.
*/
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
defined(CONFIG_PMC_YOSEMITE)
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif