Merge tag 'x86_misc_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull misc x86 updates from Borislav Petkov: - Make error checking of AMD SMN accesses more robust in the callers as they're the only ones who can interpret the results properly - The usual cleanups and fixes, left and right * tag 'x86_misc_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/kmsan: Fix hook for unaligned accesses x86/platform/iosf_mbi: Convert PCIBIOS_* return codes to errnos x86/pci/xen: Fix PCIBIOS_* return code handling x86/pci/intel_mid_pci: Fix PCIBIOS_* return code handling x86/of: Return consistent error type from x86_of_pci_irq_enable() hwmon: (k10temp) Rename _data variable hwmon: (k10temp) Remove unused HAVE_TDIE() macro hwmon: (k10temp) Reduce k10temp_get_ccd_support() parameters hwmon: (k10temp) Define a helper function to read CCD temperature x86/amd_nb: Enhance SMN access error checking hwmon: (k10temp) Check return value of amd_smn_read() EDAC/amd64: Check return value of amd_smn_read() EDAC/amd64: Remove unused register accesses tools/x86/kcpuid: Add missing dir via Makefile x86, arm: Add missing license tag to syscall tables files
This commit is contained in:
Linus Torvalds
+38
-31
@@ -20,7 +20,6 @@ static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg)
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return reg;
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switch (reg) {
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case UMCCH_ADDR_CFG: return UMCCH_ADDR_CFG_DDR5;
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case UMCCH_ADDR_MASK_SEC: return UMCCH_ADDR_MASK_SEC_DDR5;
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case UMCCH_DIMM_CFG: return UMCCH_DIMM_CFG_DDR5;
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}
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@@ -1341,22 +1340,15 @@ static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
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static void umc_dump_misc_regs(struct amd64_pvt *pvt)
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{
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struct amd64_umc *umc;
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u32 i, tmp, umc_base;
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u32 i;
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for_each_umc(i) {
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umc_base = get_umc_base(i);
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umc = &pvt->umc[i];
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edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
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edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
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edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
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edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
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amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp);
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edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);
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amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp);
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edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);
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edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
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edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
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@@ -1369,14 +1361,6 @@ static void umc_dump_misc_regs(struct amd64_pvt *pvt)
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edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
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i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
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if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) {
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amd_smn_read(pvt->mc_node_id,
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umc_base + get_umc_reg(pvt, UMCCH_ADDR_CFG),
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&tmp);
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edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
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i, 1 << ((tmp >> 4) & 0x3));
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}
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umc_debug_display_dimm_sizes(pvt, i);
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}
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}
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@@ -1454,6 +1438,7 @@ static void umc_read_base_mask(struct amd64_pvt *pvt)
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u32 *base, *base_sec;
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u32 *mask, *mask_sec;
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int cs, umc;
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u32 tmp;
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for_each_umc(umc) {
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umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR;
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@@ -1466,13 +1451,17 @@ static void umc_read_base_mask(struct amd64_pvt *pvt)
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base_reg = umc_base_reg + (cs * 4);
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base_reg_sec = umc_base_reg_sec + (cs * 4);
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if (!amd_smn_read(pvt->mc_node_id, base_reg, base))
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if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) {
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*base = tmp;
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edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n",
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umc, cs, *base, base_reg);
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}
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if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec))
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if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) {
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*base_sec = tmp;
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edac_dbg(0, " DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n",
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umc, cs, *base_sec, base_reg_sec);
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}
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}
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umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;
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@@ -1485,13 +1474,17 @@ static void umc_read_base_mask(struct amd64_pvt *pvt)
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mask_reg = umc_mask_reg + (cs * 4);
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mask_reg_sec = umc_mask_reg_sec + (cs * 4);
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if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask))
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if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) {
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*mask = tmp;
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edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n",
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umc, cs, *mask, mask_reg);
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}
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if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec))
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if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) {
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*mask_sec = tmp;
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edac_dbg(0, " DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n",
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umc, cs, *mask_sec, mask_reg_sec);
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}
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}
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}
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}
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@@ -2910,7 +2903,7 @@ static void umc_read_mc_regs(struct amd64_pvt *pvt)
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{
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u8 nid = pvt->mc_node_id;
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struct amd64_umc *umc;
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u32 i, umc_base;
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u32 i, tmp, umc_base;
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/* Read registers from each UMC */
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for_each_umc(i) {
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@@ -2918,11 +2911,20 @@ static void umc_read_mc_regs(struct amd64_pvt *pvt)
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umc_base = get_umc_base(i);
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umc = &pvt->umc[i];
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amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &umc->dimm_cfg);
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amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
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amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
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amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
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amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi);
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if (!amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &tmp))
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umc->dimm_cfg = tmp;
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if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp))
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umc->umc_cfg = tmp;
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if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp))
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umc->sdp_ctrl = tmp;
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if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp))
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umc->ecc_ctrl = tmp;
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if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &tmp))
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umc->umc_cap_hi = tmp;
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}
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}
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@@ -3651,16 +3653,21 @@ static void gpu_read_mc_regs(struct amd64_pvt *pvt)
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{
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u8 nid = pvt->mc_node_id;
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struct amd64_umc *umc;
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u32 i, umc_base;
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u32 i, tmp, umc_base;
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/* Read registers from each UMC */
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for_each_umc(i) {
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umc_base = gpu_get_umc_base(pvt, i, 0);
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umc = &pvt->umc[i];
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amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
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amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
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amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
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if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp))
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umc->umc_cfg = tmp;
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if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp))
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umc->sdp_ctrl = tmp;
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if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp))
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umc->ecc_ctrl = tmp;
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}
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}
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@@ -256,15 +256,11 @@
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#define UMCCH_ADDR_MASK 0x20
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#define UMCCH_ADDR_MASK_SEC 0x28
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#define UMCCH_ADDR_MASK_SEC_DDR5 0x30
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#define UMCCH_ADDR_CFG 0x30
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#define UMCCH_ADDR_CFG_DDR5 0x40
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#define UMCCH_DIMM_CFG 0x80
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#define UMCCH_DIMM_CFG_DDR5 0x90
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#define UMCCH_UMC_CFG 0x100
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#define UMCCH_SDP_CTRL 0x104
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#define UMCCH_ECC_CTRL 0x14C
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#define UMCCH_ECC_BAD_SYMBOL 0xD90
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#define UMCCH_UMC_CAP 0xDF0
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#define UMCCH_UMC_CAP_HI 0xDF4
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/* UMC CH bitfields */
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