tmakin/ack-tegra
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915: Remove early pre-production RPS workarounds for BXT

Browse Source 
Remove WaGsvDisableTurbo and WaRsUseTimeoutMode as these were only for
pre-production Broxton devices, and this code is now defunct.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
This commit is contained in:
Chris Wilson
2017-01-25 17:26:01 +00:00
parent b976dc53ec
commit 1c044f9bbc
1 changed files with 3 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/i915/intel_pm.c
+3 -32
View File
@@ -4935,10 +4935,6 @@ static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
* update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
{ {
/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
return;
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
WARN_ON(val > dev_priv->rps.max_freq); WARN_ON(val > dev_priv->rps.max_freq);
WARN_ON(val < dev_priv->rps.min_freq); WARN_ON(val < dev_priv->rps.min_freq);
@@ -5335,22 +5331,6 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv)
{ {
intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
/* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
/*
* BIOS could leave the Hw Turbo enabled, so need to explicitly
* clear out the Control register just to avoid inconsitency
* with debugfs interface, which will show Turbo as enabled
* only and that is not expected by the User after adding the
* WaGsvDisableTurbo. Apart from this there is no problem even
* if the Turbo is left enabled in the Control register, as the
* Up/Down interrupts would remain masked.
*/
gen9_disable_rps(dev_priv);
intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
return;
}
/* Program defaults and thresholds for RPS*/ /* Program defaults and thresholds for RPS*/
I915_WRITE(GEN6_RC_VIDEO_FREQ, I915_WRITE(GEN6_RC_VIDEO_FREQ,
GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
@@ -5410,18 +5390,9 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
if (intel_enable_rc6() & INTEL_RC6_ENABLE) if (intel_enable_rc6() & INTEL_RC6_ENABLE)
rc6_mask = GEN6_RC_CTL_RC6_ENABLE; rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
/* WaRsUseTimeoutMode:bxt */ I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { I915_WRITE(GEN6_RC_CONTROL,
I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
GEN7_RC_CTL_TO_MODE |
rc6_mask);
} else {
I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
GEN6_RC_CTL_EI_MODE(1) |
rc6_mask);
}
/* /*
* 3b: Enable Coarse Power Gating only when RC6 is enabled. * 3b: Enable Coarse Power Gating only when RC6 is enabled.