Merge tag 'mfd-next-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Drivers:
- ROHM BD96801 Power Management IC
- Cirrus Logic CS40L50 Haptic Driver with Waveform Memory
- Marvell 88PM886 Power Management IC
New Device Support:
- Keyboard Backlight to ChromeOS Embedded Controller
- LEDs to ChromeOS Embedded Controller
- Charge Control to ChromeOS Embedded Controller
- HW Monitoring Service to ChromeOS Embedded Controller
- AUXADCs to MediaTek MT635{7,8,9} Power Management ICs
New Functionality:
- Allow Syscon consumers to supply their own Regmaps on registration
Fix-ups:
- Constify/staticise applicable data structures
- Remove superfluous/duplicated/unused sections
- Device Tree binding adaptions/conversions/creation
- Trivial; spelling, whitespace, coding-style adaptions
- Utilise centrally provided helpers and macros to aid
simplicity/duplication
- Drop i2c_device_id::driver_data where the value is unused
- Replace ACPI/DT firmware helpers with agnostic variants
- Move over to GPIOD (descriptor-based) APIs
- Annotate a bunch of __counted_by() cases
- Straighten out some includes
Bug Fixes:
- Ensure potentially asserted recent lines are deasserted during
initialisation
- Avoid "<module>.ko is added to multiple modules" warnings
- Supply a bunch of MODULE_DESCRIPTIONs to silence modpost warnings
- Fix Wvoid-pointer-to-enum-cast warnings"
* tag 'mfd-next-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (87 commits)
mfd: timberdale: Attach device properties to TSC2007 board info
mfd: tmio: Move header to platform_data
mfd: tmio: Sanitize comments
mfd: tmio: Update include files
mmc: tmio/sdhi: Fix includes
mfd: tmio: Remove obsolete io accessors
mfd: tmio: Remove obsolete platform_data
watchdog: bd96801_wdt: Add missing include for FIELD_*()
dt-bindings: mfd: syscon: Add APM poweroff mailbox
dt-bindings: mfd: syscon: Split and enforce documenting MFD children
dt-bindings: mfd: rk817: Merge support for RK809
dt-bindings: mfd: rk817: Fixup clocks and reference dai-common
dt-bindings: mfd: syscon: Add TI's opp table compatible
mfd: omap-usb-tll: Use struct_size to allocate tll
dt-bindings: mfd: Explain lack of child dependency in simple-mfd
dt-bindings: mfd: Dual licensing for st,stpmic1 bindings
mfd: omap-usb-tll: Annotate struct usbtll_omap with __counted_by
mfd: tps6594-core: Remove unneeded semicolon in tps6594_check_crc_mode()
mfd: lm3533: Move to new GPIO descriptor-based APIs
mfd: tps65912: Use devm helper functions to simplify probe
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,69 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __MFD_88PM886_H
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#define __MFD_88PM886_H
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#define PM886_A1_CHIP_ID 0xa1
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#define PM886_IRQ_ONKEY 0
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#define PM886_PAGE_OFFSET_REGULATORS 1
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#define PM886_REG_ID 0x00
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#define PM886_REG_STATUS1 0x01
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#define PM886_ONKEY_STS1 BIT(0)
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#define PM886_REG_INT_STATUS1 0x05
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#define PM886_REG_INT_ENA_1 0x0a
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#define PM886_INT_ENA1_ONKEY BIT(0)
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#define PM886_REG_MISC_CONFIG1 0x14
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#define PM886_SW_PDOWN BIT(5)
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#define PM886_REG_MISC_CONFIG2 0x15
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#define PM886_INT_INV BIT(0)
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#define PM886_INT_CLEAR BIT(1)
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#define PM886_INT_RC 0x00
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#define PM886_INT_WC BIT(1)
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#define PM886_INT_MASK_MODE BIT(2)
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#define PM886_REG_RTC_SPARE6 0xef
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#define PM886_REG_BUCK_EN 0x08
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#define PM886_REG_LDO_EN1 0x09
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#define PM886_REG_LDO_EN2 0x0a
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#define PM886_REG_LDO1_VOUT 0x20
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#define PM886_REG_LDO2_VOUT 0x26
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#define PM886_REG_LDO3_VOUT 0x2c
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#define PM886_REG_LDO4_VOUT 0x32
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#define PM886_REG_LDO5_VOUT 0x38
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#define PM886_REG_LDO6_VOUT 0x3e
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#define PM886_REG_LDO7_VOUT 0x44
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#define PM886_REG_LDO8_VOUT 0x4a
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#define PM886_REG_LDO9_VOUT 0x50
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#define PM886_REG_LDO10_VOUT 0x56
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#define PM886_REG_LDO11_VOUT 0x5c
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#define PM886_REG_LDO12_VOUT 0x62
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#define PM886_REG_LDO13_VOUT 0x68
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#define PM886_REG_LDO14_VOUT 0x6e
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#define PM886_REG_LDO15_VOUT 0x74
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#define PM886_REG_LDO16_VOUT 0x7a
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#define PM886_REG_BUCK1_VOUT 0xa5
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#define PM886_REG_BUCK2_VOUT 0xb3
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#define PM886_REG_BUCK3_VOUT 0xc1
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#define PM886_REG_BUCK4_VOUT 0xcf
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#define PM886_REG_BUCK5_VOUT 0xdd
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#define PM886_LDO_VSEL_MASK 0x0f
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#define PM886_BUCK_VSEL_MASK 0x7f
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struct pm886_chip {
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struct i2c_client *client;
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unsigned int chip_id;
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struct regmap *regmap;
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};
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#endif /* __MFD_88PM886_H */
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@@ -0,0 +1,137 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* CS40L50 Advanced Haptic Driver with waveform memory,
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* integrated DSP, and closed-loop algorithms
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*
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* Copyright 2024 Cirrus Logic, Inc.
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*
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* Author: James Ogletree <james.ogletree@cirrus.com>
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*/
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#ifndef __MFD_CS40L50_H__
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#define __MFD_CS40L50_H__
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#include <linux/firmware/cirrus/cs_dsp.h>
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#include <linux/gpio/consumer.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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/* Power Supply Configuration */
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#define CS40L50_BLOCK_ENABLES2 0x201C
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#define CS40L50_ERR_RLS 0x2034
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#define CS40L50_BST_LPMODE_SEL 0x3810
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#define CS40L50_DCM_LOW_POWER 0x1
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#define CS40L50_OVERTEMP_WARN 0x4000010
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/* Interrupts */
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#define CS40L50_IRQ1_INT_1 0xE010
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#define CS40L50_IRQ1_BASE CS40L50_IRQ1_INT_1
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#define CS40L50_IRQ1_INT_2 0xE014
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#define CS40L50_IRQ1_INT_8 0xE02C
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#define CS40L50_IRQ1_INT_9 0xE030
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#define CS40L50_IRQ1_INT_10 0xE034
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#define CS40L50_IRQ1_INT_18 0xE054
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#define CS40L50_IRQ1_MASK_1 0xE090
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#define CS40L50_IRQ1_MASK_2 0xE094
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#define CS40L50_IRQ1_MASK_20 0xE0DC
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#define CS40L50_IRQ1_INT_1_OFFSET (CS40L50_IRQ1_INT_1 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_2_OFFSET (CS40L50_IRQ1_INT_2 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_8_OFFSET (CS40L50_IRQ1_INT_8 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_9_OFFSET (CS40L50_IRQ1_INT_9 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_10_OFFSET (CS40L50_IRQ1_INT_10 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_18_OFFSET (CS40L50_IRQ1_INT_18 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ_MASK_2_OVERRIDE 0xFFDF7FFF
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#define CS40L50_IRQ_MASK_20_OVERRIDE 0x15C01000
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#define CS40L50_AMP_SHORT_MASK BIT(31)
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#define CS40L50_DSP_QUEUE_MASK BIT(21)
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#define CS40L50_TEMP_ERR_MASK BIT(31)
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#define CS40L50_BST_UVP_MASK BIT(6)
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#define CS40L50_BST_SHORT_MASK BIT(7)
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#define CS40L50_BST_ILIMIT_MASK BIT(18)
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#define CS40L50_UVLO_VDDBATT_MASK BIT(16)
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#define CS40L50_GLOBAL_ERROR_MASK BIT(15)
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enum cs40l50_irq_list {
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CS40L50_DSP_QUEUE_IRQ,
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CS40L50_GLOBAL_ERROR_IRQ,
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CS40L50_UVLO_VDDBATT_IRQ,
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CS40L50_BST_ILIMIT_IRQ,
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CS40L50_BST_SHORT_IRQ,
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CS40L50_BST_UVP_IRQ,
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CS40L50_TEMP_ERR_IRQ,
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CS40L50_AMP_SHORT_IRQ,
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};
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/* DSP */
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#define CS40L50_XMEM_PACKED_0 0x2000000
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#define CS40L50_XMEM_UNPACKED24_0 0x2800000
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#define CS40L50_SYS_INFO_ID 0x25E0000
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#define CS40L50_DSP_QUEUE_WT 0x28042C8
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#define CS40L50_DSP_QUEUE_RD 0x28042CC
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#define CS40L50_NUM_WAVES 0x2805C18
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#define CS40L50_CORE_BASE 0x2B80000
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#define CS40L50_YMEM_PACKED_0 0x2C00000
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#define CS40L50_YMEM_UNPACKED24_0 0x3400000
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#define CS40L50_PMEM_0 0x3800000
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#define CS40L50_DSP_POLL_US 1000
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#define CS40L50_DSP_TIMEOUT_COUNT 100
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#define CS40L50_RESET_PULSE_US 2200
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#define CS40L50_CP_READY_US 3100
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#define CS40L50_AUTOSUSPEND_MS 2000
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#define CS40L50_PM_ALGO 0x9F206
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#define CS40L50_GLOBAL_ERR_RLS_SET BIT(11)
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#define CS40L50_GLOBAL_ERR_RLS_CLEAR 0
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enum cs40l50_wseqs {
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CS40L50_PWR_ON,
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CS40L50_STANDBY,
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CS40L50_ACTIVE,
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CS40L50_NUM_WSEQS,
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};
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/* DSP Queue */
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#define CS40L50_DSP_QUEUE_BASE 0x11004
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#define CS40L50_DSP_QUEUE_END 0x1101C
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#define CS40L50_DSP_QUEUE 0x11020
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#define CS40L50_PREVENT_HIBER 0x2000003
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#define CS40L50_ALLOW_HIBER 0x2000004
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#define CS40L50_SHUTDOWN 0x2000005
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#define CS40L50_SYSTEM_RESET 0x2000007
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#define CS40L50_START_I2S 0x3000002
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#define CS40L50_OWT_PUSH 0x3000008
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#define CS40L50_STOP_PLAYBACK 0x5000000
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#define CS40L50_OWT_DELETE 0xD000000
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/* Firmware files */
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#define CS40L50_FW "cs40l50.wmfw"
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#define CS40L50_WT "cs40l50.bin"
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/* Device */
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#define CS40L50_DEVID 0x0
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#define CS40L50_REVID 0x4
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#define CS40L50_DEVID_A 0x40A50
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#define CS40L50_REVID_B0 0xB0
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struct cs40l50 {
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struct device *dev;
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struct regmap *regmap;
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struct mutex lock;
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struct cs_dsp dsp;
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struct gpio_desc *reset_gpio;
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struct regmap_irq_chip_data *irq_data;
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const struct firmware *fw;
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const struct firmware *bin;
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struct cs_dsp_wseq wseqs[CS40L50_NUM_WSEQS];
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int irq;
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u32 devid;
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u32 revid;
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};
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int cs40l50_dsp_write(struct device *dev, struct regmap *regmap, u32 val);
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int cs40l50_probe(struct cs40l50 *cs40l50);
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int cs40l50_remove(struct cs40l50 *cs40l50);
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extern const struct regmap_config cs40l50_regmap;
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extern const struct dev_pm_ops cs40l50_pm_ops;
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#endif /* __MFD_CS40L50_H__ */
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@@ -61,7 +61,7 @@
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#define HW_Q8_CTRL_SPARE (0xa7d4)
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#define HW_Q11_CTRL_SPARE (0xa7ec)
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/**
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/*
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* Select FOD5 as sync_trigger for Q8 divider.
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* Transition from logic zero to one
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* sets trigger to sync Q8 divider.
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@@ -70,7 +70,7 @@
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*/
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#define Q9_TO_Q8_SYNC_TRIG BIT(1)
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/**
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/*
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* Enable FOD5 as driver for clock and sync for Q8 divider.
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* Enable fanout buffer for FOD5.
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*
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@@ -78,7 +78,7 @@
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*/
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#define Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK (BIT(0) | BIT(2))
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/**
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/*
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* Select FOD6 as sync_trigger for Q11 divider.
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* Transition from logic zero to one
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* sets trigger to sync Q11 divider.
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@@ -87,7 +87,7 @@
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*/
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#define Q10_TO_Q11_SYNC_TRIG BIT(1)
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/**
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/*
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* Enable FOD6 as driver for clock and sync for Q11 divider.
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* Enable fanout buffer for FOD6.
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*
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@@ -16,6 +16,7 @@
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DEVICE_ATTR(_name, S_IRUGO | S_IWUSR , show_##_name, store_##_name)
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struct device;
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struct gpio_desc;
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struct regmap;
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struct lm3533 {
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@@ -23,7 +24,7 @@ struct lm3533 {
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struct regmap *regmap;
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int gpio_hwen;
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struct gpio_desc *hwen;
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int irq;
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unsigned have_als:1;
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@@ -69,8 +70,6 @@ enum lm3533_boost_ovp {
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};
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struct lm3533_platform_data {
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int gpio_hwen;
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enum lm3533_boost_ovp boost_ovp;
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enum lm3533_boost_freq boost_freq;
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@@ -0,0 +1,215 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (C) 2024 ROHM Semiconductors */
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#ifndef __MFD_BD96801_H__
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#define __MFD_BD96801_H__
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#define BD96801_REG_SSCG_CTRL 0x09
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#define BD96801_REG_SHD_INTB 0x20
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#define BD96801_LDO5_VOL_LVL_REG 0x2c
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#define BD96801_LDO6_VOL_LVL_REG 0x2d
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#define BD96801_LDO7_VOL_LVL_REG 0x2e
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#define BD96801_REG_BUCK_OVP 0x30
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#define BD96801_REG_BUCK_OVD 0x35
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#define BD96801_REG_LDO_OVP 0x31
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#define BD96801_REG_LDO_OVD 0x36
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#define BD96801_REG_BOOT_OVERTIME 0x3a
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#define BD96801_REG_WD_TMO 0x40
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#define BD96801_REG_WD_CONF 0x41
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#define BD96801_REG_WD_FEED 0x42
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#define BD96801_REG_WD_FAILCOUNT 0x43
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#define BD96801_REG_WD_ASK 0x46
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#define BD96801_REG_WD_STATUS 0x4a
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#define BD96801_REG_PMIC_STATE 0x4f
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#define BD96801_REG_EXT_STATE 0x50
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#define BD96801_STATE_STBY 0x09
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#define BD96801_LOCK_REG 0x04
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#define BD96801_UNLOCK 0x9d
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#define BD96801_LOCK 0x00
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/* IRQ register area */
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#define BD96801_REG_INT_MAIN 0x51
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/*
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* The BD96801 has two physical IRQ lines, INTB and ERRB.
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*
|
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* The 'main status register' is located at 0x51.
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* The ERRB status registers are located at 0x52 ... 0x5B
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* INTB status registers are at range 0x5c ... 0x63
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*/
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#define BD96801_REG_INT_SYS_ERRB1 0x52
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#define BD96801_REG_INT_SYS_INTB 0x5c
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#define BD96801_REG_INT_LDO7_INTB 0x63
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/* MASK registers */
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#define BD96801_REG_MASK_SYS_INTB 0x73
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#define BD96801_REG_MASK_SYS_ERRB 0x69
|
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#define BD96801_MAX_REGISTER 0x7a
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#define BD96801_OTP_ERR_MASK BIT(0)
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#define BD96801_DBIST_ERR_MASK BIT(1)
|
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#define BD96801_EEP_ERR_MASK BIT(2)
|
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#define BD96801_ABIST_ERR_MASK BIT(3)
|
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#define BD96801_PRSTB_ERR_MASK BIT(4)
|
||||
#define BD96801_DRMOS1_ERR_MASK BIT(5)
|
||||
#define BD96801_DRMOS2_ERR_MASK BIT(6)
|
||||
#define BD96801_SLAVE_ERR_MASK BIT(7)
|
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#define BD96801_VREF_ERR_MASK BIT(0)
|
||||
#define BD96801_TSD_ERR_MASK BIT(1)
|
||||
#define BD96801_UVLO_ERR_MASK BIT(2)
|
||||
#define BD96801_OVLO_ERR_MASK BIT(3)
|
||||
#define BD96801_OSC_ERR_MASK BIT(4)
|
||||
#define BD96801_PON_ERR_MASK BIT(5)
|
||||
#define BD96801_POFF_ERR_MASK BIT(6)
|
||||
#define BD96801_CMD_SHDN_ERR_MASK BIT(7)
|
||||
#define BD96801_INT_PRSTB_WDT_ERR_MASK BIT(0)
|
||||
#define BD96801_INT_CHIP_IF_ERR_MASK BIT(3)
|
||||
#define BD96801_INT_SHDN_ERR_MASK BIT(7)
|
||||
#define BD96801_OUT_PVIN_ERR_MASK BIT(0)
|
||||
#define BD96801_OUT_OVP_ERR_MASK BIT(1)
|
||||
#define BD96801_OUT_UVP_ERR_MASK BIT(2)
|
||||
#define BD96801_OUT_SHDN_ERR_MASK BIT(7)
|
||||
|
||||
/* ERRB IRQs */
|
||||
enum {
|
||||
/* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
|
||||
BD96801_OTP_ERR_STAT,
|
||||
BD96801_DBIST_ERR_STAT,
|
||||
BD96801_EEP_ERR_STAT,
|
||||
BD96801_ABIST_ERR_STAT,
|
||||
BD96801_PRSTB_ERR_STAT,
|
||||
BD96801_DRMOS1_ERR_STAT,
|
||||
BD96801_DRMOS2_ERR_STAT,
|
||||
BD96801_SLAVE_ERR_STAT,
|
||||
BD96801_VREF_ERR_STAT,
|
||||
BD96801_TSD_ERR_STAT,
|
||||
BD96801_UVLO_ERR_STAT,
|
||||
BD96801_OVLO_ERR_STAT,
|
||||
BD96801_OSC_ERR_STAT,
|
||||
BD96801_PON_ERR_STAT,
|
||||
BD96801_POFF_ERR_STAT,
|
||||
BD96801_CMD_SHDN_ERR_STAT,
|
||||
BD96801_INT_PRSTB_WDT_ERR,
|
||||
BD96801_INT_CHIP_IF_ERR,
|
||||
BD96801_INT_SHDN_ERR_STAT,
|
||||
|
||||
/* Reg 0x55 BUCK1 ERR IRQs */
|
||||
BD96801_BUCK1_PVIN_ERR_STAT,
|
||||
BD96801_BUCK1_OVP_ERR_STAT,
|
||||
BD96801_BUCK1_UVP_ERR_STAT,
|
||||
BD96801_BUCK1_SHDN_ERR_STAT,
|
||||
|
||||
/* Reg 0x56 BUCK2 ERR IRQs */
|
||||
BD96801_BUCK2_PVIN_ERR_STAT,
|
||||
BD96801_BUCK2_OVP_ERR_STAT,
|
||||
BD96801_BUCK2_UVP_ERR_STAT,
|
||||
BD96801_BUCK2_SHDN_ERR_STAT,
|
||||
|
||||
/* Reg 0x57 BUCK3 ERR IRQs */
|
||||
BD96801_BUCK3_PVIN_ERR_STAT,
|
||||
BD96801_BUCK3_OVP_ERR_STAT,
|
||||
BD96801_BUCK3_UVP_ERR_STAT,
|
||||
BD96801_BUCK3_SHDN_ERR_STAT,
|
||||
|
||||
/* Reg 0x58 BUCK4 ERR IRQs */
|
||||
BD96801_BUCK4_PVIN_ERR_STAT,
|
||||
BD96801_BUCK4_OVP_ERR_STAT,
|
||||
BD96801_BUCK4_UVP_ERR_STAT,
|
||||
BD96801_BUCK4_SHDN_ERR_STAT,
|
||||
|
||||
/* Reg 0x59 LDO5 ERR IRQs */
|
||||
BD96801_LDO5_PVIN_ERR_STAT,
|
||||
BD96801_LDO5_OVP_ERR_STAT,
|
||||
BD96801_LDO5_UVP_ERR_STAT,
|
||||
BD96801_LDO5_SHDN_ERR_STAT,
|
||||
|
||||
/* Reg 0x5a LDO6 ERR IRQs */
|
||||
BD96801_LDO6_PVIN_ERR_STAT,
|
||||
BD96801_LDO6_OVP_ERR_STAT,
|
||||
BD96801_LDO6_UVP_ERR_STAT,
|
||||
BD96801_LDO6_SHDN_ERR_STAT,
|
||||
|
||||
/* Reg 0x5b LDO7 ERR IRQs */
|
||||
BD96801_LDO7_PVIN_ERR_STAT,
|
||||
BD96801_LDO7_OVP_ERR_STAT,
|
||||
BD96801_LDO7_UVP_ERR_STAT,
|
||||
BD96801_LDO7_SHDN_ERR_STAT,
|
||||
};
|
||||
|
||||
/* INTB IRQs */
|
||||
enum {
|
||||
/* Reg 0x5c (System INTB) */
|
||||
BD96801_TW_STAT,
|
||||
BD96801_WDT_ERR_STAT,
|
||||
BD96801_I2C_ERR_STAT,
|
||||
BD96801_CHIP_IF_ERR_STAT,
|
||||
|
||||
/* Reg 0x5d (BUCK1 INTB) */
|
||||
BD96801_BUCK1_OCPH_STAT,
|
||||
BD96801_BUCK1_OCPL_STAT,
|
||||
BD96801_BUCK1_OCPN_STAT,
|
||||
BD96801_BUCK1_OVD_STAT,
|
||||
BD96801_BUCK1_UVD_STAT,
|
||||
BD96801_BUCK1_TW_CH_STAT,
|
||||
|
||||
/* Reg 0x5e (BUCK2 INTB) */
|
||||
BD96801_BUCK2_OCPH_STAT,
|
||||
BD96801_BUCK2_OCPL_STAT,
|
||||
BD96801_BUCK2_OCPN_STAT,
|
||||
BD96801_BUCK2_OVD_STAT,
|
||||
BD96801_BUCK2_UVD_STAT,
|
||||
BD96801_BUCK2_TW_CH_STAT,
|
||||
|
||||
/* Reg 0x5f (BUCK3 INTB)*/
|
||||
BD96801_BUCK3_OCPH_STAT,
|
||||
BD96801_BUCK3_OCPL_STAT,
|
||||
BD96801_BUCK3_OCPN_STAT,
|
||||
BD96801_BUCK3_OVD_STAT,
|
||||
BD96801_BUCK3_UVD_STAT,
|
||||
BD96801_BUCK3_TW_CH_STAT,
|
||||
|
||||
/* Reg 0x60 (BUCK4 INTB)*/
|
||||
BD96801_BUCK4_OCPH_STAT,
|
||||
BD96801_BUCK4_OCPL_STAT,
|
||||
BD96801_BUCK4_OCPN_STAT,
|
||||
BD96801_BUCK4_OVD_STAT,
|
||||
BD96801_BUCK4_UVD_STAT,
|
||||
BD96801_BUCK4_TW_CH_STAT,
|
||||
|
||||
/* Reg 0x61 (LDO5 INTB) */
|
||||
BD96801_LDO5_OCPH_STAT, /* bit [0] */
|
||||
BD96801_LDO5_OVD_STAT, /* bit [3] */
|
||||
BD96801_LDO5_UVD_STAT, /* bit [4] */
|
||||
|
||||
/* Reg 0x62 (LDO6 INTB) */
|
||||
BD96801_LDO6_OCPH_STAT, /* bit [0] */
|
||||
BD96801_LDO6_OVD_STAT, /* bit [3] */
|
||||
BD96801_LDO6_UVD_STAT, /* bit [4] */
|
||||
|
||||
/* Reg 0x63 (LDO7 INTB) */
|
||||
BD96801_LDO7_OCPH_STAT, /* bit [0] */
|
||||
BD96801_LDO7_OVD_STAT, /* bit [3] */
|
||||
BD96801_LDO7_UVD_STAT, /* bit [4] */
|
||||
};
|
||||
|
||||
/* IRQ MASKs */
|
||||
#define BD96801_TW_STAT_MASK BIT(0)
|
||||
#define BD96801_WDT_ERR_STAT_MASK BIT(1)
|
||||
#define BD96801_I2C_ERR_STAT_MASK BIT(2)
|
||||
#define BD96801_CHIP_IF_ERR_STAT_MASK BIT(3)
|
||||
|
||||
#define BD96801_BUCK_OCPH_STAT_MASK BIT(0)
|
||||
#define BD96801_BUCK_OCPL_STAT_MASK BIT(1)
|
||||
#define BD96801_BUCK_OCPN_STAT_MASK BIT(2)
|
||||
#define BD96801_BUCK_OVD_STAT_MASK BIT(3)
|
||||
#define BD96801_BUCK_UVD_STAT_MASK BIT(4)
|
||||
#define BD96801_BUCK_TW_CH_STAT_MASK BIT(5)
|
||||
|
||||
#define BD96801_LDO_OCPH_STAT_MASK BIT(0)
|
||||
#define BD96801_LDO_OVD_STAT_MASK BIT(3)
|
||||
#define BD96801_LDO_UVD_STAT_MASK BIT(4)
|
||||
|
||||
#endif
|
||||
@@ -16,6 +16,7 @@ enum rohm_chip_type {
|
||||
ROHM_CHIP_TYPE_BD71828,
|
||||
ROHM_CHIP_TYPE_BD71837,
|
||||
ROHM_CHIP_TYPE_BD71847,
|
||||
ROHM_CHIP_TYPE_BD96801,
|
||||
ROHM_CHIP_TYPE_AMOUNT
|
||||
};
|
||||
|
||||
|
||||
@@ -28,6 +28,8 @@ struct regmap *syscon_regmap_lookup_by_phandle_args(struct device_node *np,
|
||||
unsigned int *out_args);
|
||||
struct regmap *syscon_regmap_lookup_by_phandle_optional(struct device_node *np,
|
||||
const char *property);
|
||||
int of_syscon_register_regmap(struct device_node *np,
|
||||
struct regmap *regmap);
|
||||
#else
|
||||
static inline struct regmap *device_node_to_regmap(struct device_node *np)
|
||||
{
|
||||
@@ -67,6 +69,12 @@ static inline struct regmap *syscon_regmap_lookup_by_phandle_optional(
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int of_syscon_register_regmap(struct device_node *np,
|
||||
struct regmap *regmap)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_MFD_SYSCON_H__ */
|
||||
|
||||
@@ -1,131 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef MFD_TMIO_H
|
||||
#define MFD_TMIO_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/mmc/card.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#define tmio_ioread8(addr) readb(addr)
|
||||
#define tmio_ioread16(addr) readw(addr)
|
||||
#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
|
||||
#define tmio_ioread32(addr) \
|
||||
(((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
|
||||
|
||||
#define tmio_iowrite8(val, addr) writeb((val), (addr))
|
||||
#define tmio_iowrite16(val, addr) writew((val), (addr))
|
||||
#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
|
||||
#define tmio_iowrite32(val, addr) \
|
||||
do { \
|
||||
writew((val), (addr)); \
|
||||
writew((val) >> 16, (addr) + 2); \
|
||||
} while (0)
|
||||
|
||||
#define sd_config_write8(base, shift, reg, val) \
|
||||
tmio_iowrite8((val), (base) + ((reg) << (shift)))
|
||||
#define sd_config_write16(base, shift, reg, val) \
|
||||
tmio_iowrite16((val), (base) + ((reg) << (shift)))
|
||||
#define sd_config_write32(base, shift, reg, val) \
|
||||
do { \
|
||||
tmio_iowrite16((val), (base) + ((reg) << (shift))); \
|
||||
tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
|
||||
} while (0)
|
||||
|
||||
/* tmio MMC platform flags */
|
||||
/*
|
||||
* Some controllers can support a 2-byte block size when the bus width
|
||||
* is configured in 4-bit mode.
|
||||
*/
|
||||
#define TMIO_MMC_BLKSZ_2BYTES BIT(1)
|
||||
/*
|
||||
* Some controllers can support SDIO IRQ signalling.
|
||||
*/
|
||||
#define TMIO_MMC_SDIO_IRQ BIT(2)
|
||||
|
||||
/* Some features are only available or tested on R-Car Gen2 or later */
|
||||
#define TMIO_MMC_MIN_RCAR2 BIT(3)
|
||||
|
||||
/*
|
||||
* Some controllers require waiting for the SD bus to become
|
||||
* idle before writing to some registers.
|
||||
*/
|
||||
#define TMIO_MMC_HAS_IDLE_WAIT BIT(4)
|
||||
|
||||
/*
|
||||
* Use the busy timeout feature. Probably all TMIO versions support it. Yet,
|
||||
* we don't have documentation for old variants, so we enable only known good
|
||||
* variants with this flag. Can be removed once all variants are known good.
|
||||
*/
|
||||
#define TMIO_MMC_USE_BUSY_TIMEOUT BIT(5)
|
||||
|
||||
/*
|
||||
* Some controllers have CMD12 automatically
|
||||
* issue/non-issue register
|
||||
*/
|
||||
#define TMIO_MMC_HAVE_CMD12_CTRL BIT(7)
|
||||
|
||||
/* Controller has some SDIO status bits which must be 1 */
|
||||
#define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8)
|
||||
|
||||
/*
|
||||
* Some controllers have a 32-bit wide data port register
|
||||
*/
|
||||
#define TMIO_MMC_32BIT_DATA_PORT BIT(9)
|
||||
|
||||
/*
|
||||
* Some controllers allows to set SDx actual clock
|
||||
*/
|
||||
#define TMIO_MMC_CLK_ACTUAL BIT(10)
|
||||
|
||||
/* Some controllers have a CBSY bit */
|
||||
#define TMIO_MMC_HAVE_CBSY BIT(11)
|
||||
|
||||
struct dma_chan;
|
||||
|
||||
/*
|
||||
* data for the MMC controller
|
||||
*/
|
||||
struct tmio_mmc_data {
|
||||
void *chan_priv_tx;
|
||||
void *chan_priv_rx;
|
||||
unsigned int hclk;
|
||||
unsigned long capabilities;
|
||||
unsigned long capabilities2;
|
||||
unsigned long flags;
|
||||
u32 ocr_mask; /* available voltages */
|
||||
dma_addr_t dma_rx_offset;
|
||||
unsigned int max_blk_count;
|
||||
unsigned short max_segs;
|
||||
};
|
||||
|
||||
/*
|
||||
* data for the NAND controller
|
||||
*/
|
||||
struct tmio_nand_data {
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
struct mtd_partition *partition;
|
||||
unsigned int num_partitions;
|
||||
const char *const *part_parsers;
|
||||
};
|
||||
|
||||
#define FBIO_TMIO_ACC_WRITE 0x7C639300
|
||||
#define FBIO_TMIO_ACC_SYNC 0x7C639301
|
||||
|
||||
struct tmio_fb_data {
|
||||
int (*lcd_set_power)(struct platform_device *fb_dev,
|
||||
bool on);
|
||||
int (*lcd_mode)(struct platform_device *fb_dev,
|
||||
const struct fb_videomode *mode);
|
||||
int num_modes;
|
||||
struct fb_videomode *modes;
|
||||
|
||||
/* in mm: size of screen */
|
||||
int height;
|
||||
int width;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -314,6 +314,5 @@ struct tps65912 {
|
||||
extern const struct regmap_config tps65912_regmap_config;
|
||||
|
||||
int tps65912_device_init(struct tps65912 *tps);
|
||||
void tps65912_device_exit(struct tps65912 *tps);
|
||||
|
||||
#endif /* __LINUX_MFD_TPS65912_H */
|
||||
|
||||
Reference in New Issue
Block a user