Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (109 commits) PCI: fix coding style issue in pci_save_state() PCI: add pci_request_acs PCI: fix BUG_ON triggered by logical PCIe root port removal PCI: remove ifdefed pci_cleanup_aer_correct_error_status PCI: unconditionally clear AER uncorr status register during cleanup x86/PCI: claim SR-IOV BARs in pcibios_allocate_resource PCI: portdrv: remove redundant definitions PCI: portdrv: remove unnecessary struct pcie_port_data PCI: portdrv: minor cleanup for pcie_port_device_register PCI: portdrv: add missing irq cleanup PCI: portdrv: enable device before irq initialization PCI: portdrv: cleanup service irqs initialization PCI: portdrv: check capabilities first PCI: portdrv: move PME capability check PCI: portdrv: remove redundant pcie type calculation PCI: portdrv: cleanup pcie_device registration PCI: portdrv: remove redundant pcie_port_device_probe PCI: Always set prefetchable base/limit upper32 registers PCI: read-modify-write the pcie device control register when initiating pcie flr PCI: show dma_mask bits in /sys ... Fixed up conflicts in: arch/x86/kernel/amd_iommu_init.c drivers/pci/dmar.c drivers/pci/hotplug/acpiphp_glue.c
This commit is contained in:
Linus Torvalds
+41
-1
@@ -218,6 +218,7 @@ struct pci_dev {
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unsigned int class; /* 3 bytes: (base,sub,prog-if) */
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u8 revision; /* PCI revision, low byte of class word */
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u8 hdr_type; /* PCI header type (`multi' flag masked out) */
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u8 pcie_cap; /* PCI-E capability offset */
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u8 pcie_type; /* PCI-E device/port type */
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u8 rom_base_reg; /* which config register controls the ROM */
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u8 pin; /* which interrupt pin this device uses */
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@@ -280,6 +281,7 @@ struct pci_dev {
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unsigned int is_virtfn:1;
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unsigned int reset_fn:1;
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unsigned int is_hotplug_bridge:1;
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unsigned int aer_firmware_first:1;
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pci_dev_flags_t dev_flags;
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atomic_t enable_cnt; /* pci_enable_device has been called */
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@@ -635,7 +637,13 @@ struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
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unsigned int ss_vendor, unsigned int ss_device,
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struct pci_dev *from);
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struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
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struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
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struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
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unsigned int devfn);
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static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
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unsigned int devfn)
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{
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return pci_get_domain_bus_and_slot(0, bus, devfn);
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}
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struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
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int pci_dev_present(const struct pci_device_id *ids);
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@@ -701,6 +709,7 @@ void pci_disable_device(struct pci_dev *dev);
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void pci_set_master(struct pci_dev *dev);
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void pci_clear_master(struct pci_dev *dev);
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int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
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int pci_set_cacheline_size(struct pci_dev *dev);
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#define HAVE_PCI_SET_MWI
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int __must_check pci_set_mwi(struct pci_dev *dev);
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int pci_try_set_mwi(struct pci_dev *dev);
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@@ -1246,6 +1255,8 @@ extern int pci_pci_problems;
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extern unsigned long pci_cardbus_io_size;
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extern unsigned long pci_cardbus_mem_size;
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extern u8 pci_dfl_cache_line_size;
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extern u8 pci_cache_line_size;
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extern unsigned long pci_hotplug_io_size;
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extern unsigned long pci_hotplug_mem_size;
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@@ -1290,5 +1301,34 @@ extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
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extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
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#endif
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/**
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* pci_pcie_cap - get the saved PCIe capability offset
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* @dev: PCI device
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*
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* PCIe capability offset is calculated at PCI device initialization
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* time and saved in the data structure. This function returns saved
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* PCIe capability offset. Using this instead of pci_find_capability()
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* reduces unnecessary search in the PCI configuration space. If you
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* need to calculate PCIe capability offset from raw device for some
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* reasons, please use pci_find_capability() instead.
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*/
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static inline int pci_pcie_cap(struct pci_dev *dev)
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{
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return dev->pcie_cap;
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}
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/**
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* pci_is_pcie - check if the PCI device is PCI Express capable
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* @dev: PCI device
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*
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* Retrun true if the PCI device is PCI Express capable, false otherwise.
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*/
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static inline bool pci_is_pcie(struct pci_dev *dev)
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{
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return !!pci_pcie_cap(dev);
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}
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void pci_request_acs(void);
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#endif /* __KERNEL__ */
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#endif /* LINUX_PCI_H */
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@@ -365,6 +365,11 @@
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#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
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#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
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/* PCI Bridge Subsystem ID registers */
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#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */
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#define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */
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/* PCI Express capability registers */
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#define PCI_EXP_FLAGS 2 /* Capabilities register */
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@@ -502,6 +507,7 @@
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#define PCI_EXT_CAP_ID_VC 2
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#define PCI_EXT_CAP_ID_DSN 3
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#define PCI_EXT_CAP_ID_PWR 4
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#define PCI_EXT_CAP_ID_ACS 13
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#define PCI_EXT_CAP_ID_ARI 14
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#define PCI_EXT_CAP_ID_ATS 15
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#define PCI_EXT_CAP_ID_SRIOV 16
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@@ -662,4 +668,16 @@
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#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
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#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
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/* Access Control Service */
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#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
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#define PCI_ACS_SV 0x01 /* Source Validation */
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#define PCI_ACS_TB 0x02 /* Translation Blocking */
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#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
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#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
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#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
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#define PCI_ACS_EC 0x20 /* P2P Egress Control */
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#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
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#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
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#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
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#endif /* LINUX_PCI_REGS_H */
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@@ -10,10 +10,7 @@
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#define _PCIEPORT_IF_H_
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/* Port Type */
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#define PCIE_RC_PORT 4 /* Root port of RC */
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#define PCIE_SW_UPSTREAM_PORT 5 /* Upstream port of Switch */
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#define PCIE_SW_DOWNSTREAM_PORT 6 /* Downstream port of Switch */
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#define PCIE_ANY_PORT 7
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#define PCIE_ANY_PORT (~0)
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/* Service Type */
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#define PCIE_PORT_SERVICE_PME_SHIFT 0 /* Power Management Event */
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@@ -25,17 +22,6 @@
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#define PCIE_PORT_SERVICE_VC_SHIFT 3 /* Virtual Channel */
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#define PCIE_PORT_SERVICE_VC (1 << PCIE_PORT_SERVICE_VC_SHIFT)
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/* Root/Upstream/Downstream Port's Interrupt Mode */
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#define PCIE_PORT_NO_IRQ (-1)
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#define PCIE_PORT_INTx_MODE 0
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#define PCIE_PORT_MSI_MODE 1
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#define PCIE_PORT_MSIX_MODE 2
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struct pcie_port_data {
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int port_type; /* Type of the port */
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int port_irq_mode; /* [0:INTx | 1:MSI | 2:MSI-X] */
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};
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struct pcie_device {
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int irq; /* Service IRQ/MSI/MSI-X Vector */
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struct pci_dev *port; /* Root/Upstream/Downstream Port */
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