From 0807237da1abb6680215a6495b724e924d2317cb Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Tue, 24 Oct 2017 12:23:00 +0300 Subject: [PATCH] clk: tegra: apply regulator align to Vmin Apply regulator alignment when using Vmin to determine the lowest possible rate generated by the DFLL. Change-Id: I169528614871733e4a7568f3ec740079b0e9d097 Signed-off-by: Peter De Schrijver Reviewed-on: https://git-master.nvidia.com/r/1584439 GVS: Gerrit_Virtual_Submit Reviewed-by: Aleksandr Frid Reviewed-by: Sachin Nikam --- drivers/clk/tegra/clk-dfll.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index 4ab614ef1bc0..0d93d2f383e5 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -2000,7 +2000,7 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max) */ static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) { - unsigned long rate, v, v_opp; + unsigned long rate, v, v_opp, v_min_align; int ret = -EINVAL; int j, selector, lut; @@ -2011,6 +2011,9 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) td->lut[0] = lut; td->lut_bottom = 0; + v_min_align = DIV_ROUND_UP(td->soc->min_millivolts * 1000, + td->soc->alignment.step_uv) * td->soc->alignment.step_uv; + for (j = 1, rate = 0; ; rate++) { struct dev_pm_opp *opp; @@ -2019,7 +2022,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max) break; v_opp = dev_pm_opp_get_voltage(opp); - if (v_opp <= td->soc->cvb->min_millivolts * 1000) + if (v_opp <= v_min_align) td->dvco_rate_min = dev_pm_opp_get_freq(opp); dev_pm_opp_put(opp);