Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (42 commits) [ARM] Fix tosa build error [ARM] 3610/1: Make reboot work on Versatile [ARM] 3609/1: S3C24XX: defconfig update for s3c2410_defconfig [ARM] 3591/1: Anubis: IDE device definitions [ARM] Include asm/hardware.h not asm/arch/hardware.h [ARM] 3594/1: Poodle: Add touchscreen support + other updates [ARM] 3564/1: sharpsl_pm: Abstract some machine specific parameters [ARM] 3561/1: Poodle: Correct the MMC/SD power control [ARM] 3593/1: Add reboot and shutdown handlers for Zaurus handhelds [ARM] 3599/1: AT91RM9200 remove global variables [ARM] 3607/1: AT91RM9200 misc fixes [ARM] 3605/1: AT91RM9200 Power Management [ARM] 3604/1: AT91RM9200 New boards [ARM] 3603/1: AT91RM9200 remove old files [ARM] 3592/1: AT91RM9200 Serial driver update [ARM] 3590/1: AT91RM9200 Platform devices support [ARM] 3589/1: AT91RM9200 DK/EK board update [ARM] 3588/1: AT91RM9200 CSB337/637 board update [ARM] 3587/1: AT91RM9200 hardware headers [ARM] 3586/1: AT91RM9200 header update ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,81 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Serial Peripheral Interface (SPI) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_SPI_H
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#define AT91RM9200_SPI_H
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#define AT91_SPI_CR 0x00 /* Control Register */
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#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
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#define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */
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#define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
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#define AT91_SPI_MR 0x04 /* Mode Register */
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#define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */
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#define AT91_SPI_PS (1 << 1) /* Peripheral Select */
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#define AT91_SPI_PS_FIXED (0 << 1)
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#define AT91_SPI_PS_VARIABLE (1 << 1)
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#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
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#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */
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#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
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#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */
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#define AT91_SPI_RDR 0x08 /* Receive Data Register */
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#define AT91_SPI_RD (0xffff << 0) /* Receive Data */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_TDR 0x0c /* Transmit Data Register */
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#define AT91_SPI_TD (0xffff << 0) /* Transmit Data */
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#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
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#define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */
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#define AT91_SPI_SR 0x10 /* Status Register */
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#define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */
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#define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */
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#define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */
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#define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */
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#define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */
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#define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */
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#define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */
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#define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */
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#define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */
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#define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */
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#define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */
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#define AT91_SPI_IER 0x14 /* Interrupt Enable Register */
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#define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */
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#define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */
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#define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */
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#define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */
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#define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */
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#define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */
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#define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */
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#define AT91_SPI_BITS_8 (0 << 4)
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#define AT91_SPI_BITS_9 (1 << 4)
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#define AT91_SPI_BITS_10 (2 << 4)
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#define AT91_SPI_BITS_11 (3 << 4)
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#define AT91_SPI_BITS_12 (4 << 4)
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#define AT91_SPI_BITS_13 (5 << 4)
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#define AT91_SPI_BITS_14 (6 << 4)
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#define AT91_SPI_BITS_15 (7 << 4)
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#define AT91_SPI_BITS_16 (8 << 4)
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#define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */
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#define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */
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#define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */
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#endif
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@@ -0,0 +1,96 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
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*
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* Copyright (C) SAN People
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*
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* Serial Synchronous Controller (SSC) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_SSC_H
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#define AT91RM9200_SSC_H
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#define AT91_SSC_CR 0x00 /* Control Register */
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#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
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#define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */
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#define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */
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#define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */
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#define AT91_SSC_SWRST (1 << 15) /* Software Reset */
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#define AT91_SSC_CMR 0x04 /* Clock Mode Register */
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#define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */
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#define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */
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#define AT91_SSC_CKS (3 << 0) /* Clock Selection */
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#define AT91_SSC_CKS_DIV (0 << 0)
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#define AT91_SSC_CKS_CLOCK (1 << 0)
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#define AT91_SSC_CKS_PIN (2 << 0)
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#define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */
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#define AT91_SSC_CKO_NONE (0 << 2)
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#define AT91_SSC_CKO_CONTINUOUS (1 << 2)
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#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
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#define AT91_SSC_CKI_FALLING (0 << 5)
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#define AT91_SSC_CK_RISING (1 << 5)
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#define AT91_SSC_START (0xf << 8) /* Start Selection */
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#define AT91_SSC_START_CONTINUOUS (0 << 8)
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#define AT91_SSC_START_TX_RX (1 << 8)
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#define AT91_SSC_START_LOW_RF (2 << 8)
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#define AT91_SSC_START_HIGH_RF (3 << 8)
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#define AT91_SSC_START_FALLING_RF (4 << 8)
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#define AT91_SSC_START_RISING_RF (5 << 8)
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#define AT91_SSC_START_LEVEL_RF (6 << 8)
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#define AT91_SSC_START_EDGE_RF (7 << 8)
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#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
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#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
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#define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */
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#define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */
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#define AT91_SSC_LOOP (1 << 5) /* Loop Mode */
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#define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */
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#define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */
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#define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */
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#define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */
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#define AT91_SSC_FSOS_NONE (0 << 20)
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#define AT91_SSC_FSOS_NEGATIVE (1 << 20)
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#define AT91_SSC_FSOS_POSITIVE (2 << 20)
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#define AT91_SSC_FSOS_LOW (3 << 20)
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#define AT91_SSC_FSOS_HIGH (4 << 20)
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#define AT91_SSC_FSOS_TOGGLE (5 << 20)
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#define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */
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#define AT91_SSC_FSEDGE_POSITIVE (0 << 24)
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#define AT91_SSC_FSEDGE_NEGATIVE (1 << 24)
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#define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */
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#define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */
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#define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */
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#define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */
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#define AT91_SSC_RHR 0x20 /* Receive Holding Register */
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#define AT91_SSC_THR 0x24 /* Transmit Holding Register */
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#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
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#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
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#define AT91_SSC_SR 0x40 /* Status Register */
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#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
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#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
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#define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */
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#define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */
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#define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */
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#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
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#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
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#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
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#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
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#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
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#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
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#define AT91_SSC_RXENA (1 << 17) /* Receive Enable */
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#define AT91_SSC_IER 0x44 /* Interrupt Enable Register */
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#define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */
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#define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */
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#endif
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@@ -68,8 +68,17 @@
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#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
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#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
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#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
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#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
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#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
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#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
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#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
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#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
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#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
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#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
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#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
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#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
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/*
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@@ -241,7 +250,7 @@
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#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
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#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
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#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
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#define At91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
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#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
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#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
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#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
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@@ -0,0 +1,146 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
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*
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* Copyright (C) SAN People
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*
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* Timer/Counter Unit (TC) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_TC_H
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#define AT91RM9200_TC_H
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#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
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#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
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#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
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#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
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#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
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#define AT91_TC_TC0XC0S_NONE (1 << 0)
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#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
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#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
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#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
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#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
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#define AT91_TC_TC1XC1S_NONE (1 << 2)
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#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
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#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
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#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
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#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
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#define AT91_TC_TC2XC2S_NONE (1 << 4)
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#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
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#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
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#define AT91_TC_CCR 0x00 /* Channel Control Register */
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#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
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#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
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#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
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#define AT91_TC_CMR 0x04 /* Channel Mode Register */
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#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
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#define AT91_TC_TIMER_CLOCK1 (0 << 0)
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#define AT91_TC_TIMER_CLOCK2 (1 << 0)
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#define AT91_TC_TIMER_CLOCK3 (2 << 0)
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#define AT91_TC_TIMER_CLOCK4 (3 << 0)
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#define AT91_TC_TIMER_CLOCK5 (4 << 0)
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#define AT91_TC_XC0 (5 << 0)
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#define AT91_TC_XC1 (6 << 0)
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#define AT91_TC_XC2 (7 << 0)
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#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
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#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
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#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
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#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
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#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
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#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
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#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
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#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
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#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
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#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
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#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
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#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
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#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
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#define AT91_TC_EEVTEDG_NONE (0 << 8)
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#define AT91_TC_EEVTEDG_RISING (1 << 8)
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#define AT91_TC_EEVTEDG_FALLING (2 << 8)
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#define AT91_TC_EEVTEDG_BOTH (3 << 8)
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#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
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#define AT91_TC_EEVT_TIOB (0 << 10)
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#define AT91_TC_EEVT_XC0 (1 << 10)
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#define AT91_TC_EEVT_XC1 (2 << 10)
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#define AT91_TC_EEVT_XC2 (3 << 10)
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#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
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#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
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#define AT91_TC_WAVESEL_UP (0 << 13)
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#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
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#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
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#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
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#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
|
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#define AT91_TC_ACPA_NONE (0 << 16)
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#define AT91_TC_ACPA_SET (1 << 16)
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#define AT91_TC_ACPA_CLEAR (2 << 16)
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#define AT91_TC_ACPA_TOGGLE (3 << 16)
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#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
|
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#define AT91_TC_ACPC_NONE (0 << 18)
|
||||
#define AT91_TC_ACPC_SET (1 << 18)
|
||||
#define AT91_TC_ACPC_CLEAR (2 << 18)
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#define AT91_TC_ACPC_TOGGLE (3 << 18)
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||||
#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
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#define AT91_TC_AEEVT_NONE (0 << 20)
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#define AT91_TC_AEEVT_SET (1 << 20)
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#define AT91_TC_AEEVT_CLEAR (2 << 20)
|
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#define AT91_TC_AEEVT_TOGGLE (3 << 20)
|
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#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
|
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#define AT91_TC_ASWTRG_NONE (0 << 22)
|
||||
#define AT91_TC_ASWTRG_SET (1 << 22)
|
||||
#define AT91_TC_ASWTRG_CLEAR (2 << 22)
|
||||
#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
|
||||
#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
|
||||
#define AT91_TC_BCPB_NONE (0 << 24)
|
||||
#define AT91_TC_BCPB_SET (1 << 24)
|
||||
#define AT91_TC_BCPB_CLEAR (2 << 24)
|
||||
#define AT91_TC_BCPB_TOGGLE (3 << 24)
|
||||
#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
|
||||
#define AT91_TC_BCPC_NONE (0 << 26)
|
||||
#define AT91_TC_BCPC_SET (1 << 26)
|
||||
#define AT91_TC_BCPC_CLEAR (2 << 26)
|
||||
#define AT91_TC_BCPC_TOGGLE (3 << 26)
|
||||
#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
|
||||
#define AT91_TC_BEEVT_NONE (0 << 28)
|
||||
#define AT91_TC_BEEVT_SET (1 << 28)
|
||||
#define AT91_TC_BEEVT_CLEAR (2 << 28)
|
||||
#define AT91_TC_BEEVT_TOGGLE (3 << 28)
|
||||
#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
|
||||
#define AT91_TC_BSWTRG_NONE (0 << 30)
|
||||
#define AT91_TC_BSWTRG_SET (1 << 30)
|
||||
#define AT91_TC_BSWTRG_CLEAR (2 << 30)
|
||||
#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
|
||||
|
||||
#define AT91_TC_CV 0x10 /* Counter Value */
|
||||
#define AT91_TC_RA 0x14 /* Register A */
|
||||
#define AT91_TC_RB 0x18 /* Register B */
|
||||
#define AT91_TC_RC 0x1c /* Register C */
|
||||
|
||||
#define AT91_TC_SR 0x20 /* Status Register */
|
||||
#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
|
||||
#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
|
||||
#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
|
||||
#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
|
||||
#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
|
||||
#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
|
||||
#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
|
||||
#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
|
||||
#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
|
||||
#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
|
||||
#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
|
||||
|
||||
#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
|
||||
#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
|
||||
#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* USB Device Port (UDP) registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91RM9200_UDP_H
|
||||
#define AT91RM9200_UDP_H
|
||||
|
||||
#define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */
|
||||
#define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */
|
||||
#define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */
|
||||
#define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */
|
||||
|
||||
#define AT91_UDP_GLB_STAT 0x04 /* Global State Register */
|
||||
#define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */
|
||||
#define AT91_UDP_CONFG (1 << 1) /* Configured */
|
||||
#define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */
|
||||
#define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */
|
||||
#define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */
|
||||
|
||||
#define AT91_UDP_FADDR 0x08 /* Function Address Register */
|
||||
#define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */
|
||||
#define AT91_UDP_FEN (1 << 8) /* Function Enable */
|
||||
|
||||
#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */
|
||||
#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */
|
||||
#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
|
||||
#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
|
||||
#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
|
||||
#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
|
||||
#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */
|
||||
#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
|
||||
#define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */
|
||||
#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */
|
||||
|
||||
#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */
|
||||
#define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
|
||||
|
||||
#define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */
|
||||
#define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */
|
||||
#define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */
|
||||
#define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */
|
||||
#define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */
|
||||
#define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */
|
||||
#define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */
|
||||
#define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */
|
||||
#define AT91_UDP_DIR (1 << 7) /* Transfer Direction */
|
||||
#define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */
|
||||
#define AT91_UDP_EPTYPE_CTRL (0 << 8)
|
||||
#define AT91_UDP_EPTYPE_ISO_OUT (1 << 8)
|
||||
#define AT91_UDP_EPTYPE_BULK_OUT (2 << 8)
|
||||
#define AT91_UDP_EPTYPE_INT_OUT (3 << 8)
|
||||
#define AT91_UDP_EPTYPE_ISO_IN (5 << 8)
|
||||
#define AT91_UDP_EPTYPE_BULK_IN (6 << 8)
|
||||
#define AT91_UDP_EPTYPE_INT_IN (7 << 8)
|
||||
#define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */
|
||||
#define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */
|
||||
#define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */
|
||||
|
||||
#define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */
|
||||
|
||||
#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */
|
||||
#define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
|
||||
|
||||
#endif
|
||||
@@ -31,14 +31,9 @@
|
||||
#ifndef __ASM_ARCH_BOARD_H
|
||||
#define __ASM_ARCH_BOARD_H
|
||||
|
||||
/* Clocks */
|
||||
extern unsigned long at91_master_clock;
|
||||
|
||||
/* Serial Port */
|
||||
extern int at91_serial_map[AT91_NR_UART];
|
||||
extern int at91_console_port;
|
||||
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
/* USB Device */
|
||||
struct at91_udc_data {
|
||||
@@ -91,10 +86,25 @@ struct at91_nand_data {
|
||||
extern void __init at91_add_device_nand(struct at91_nand_data *data);
|
||||
|
||||
/* I2C*/
|
||||
void __init at91_add_device_i2c(void);
|
||||
extern void __init at91_add_device_i2c(void);
|
||||
|
||||
/* RTC */
|
||||
void __init at91_add_device_rtc(void);
|
||||
/* SPI */
|
||||
extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
|
||||
|
||||
/* Serial */
|
||||
struct at91_uart_config {
|
||||
unsigned short console_tty; /* tty number of serial console */
|
||||
unsigned short nr_tty; /* number of serial tty's */
|
||||
short tty_map[]; /* map UART to tty number */
|
||||
};
|
||||
extern struct platform_device *at91_default_console_device;
|
||||
extern void __init at91_init_serial(struct at91_uart_config *config);
|
||||
|
||||
struct at91_uart_data {
|
||||
short use_dma_tx; /* use transmit DMA? */
|
||||
short use_dma_rx; /* use receive DMA? */
|
||||
};
|
||||
extern void __init at91_add_device_serial(void);
|
||||
|
||||
/* LEDs */
|
||||
extern u8 at91_leds_cpu;
|
||||
|
||||
@@ -13,6 +13,8 @@
|
||||
#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
|
||||
#define __ASM_ARCH_AT91RM9200_GPIO_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
#define PIN_BASE NR_AIC_IRQS
|
||||
|
||||
#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */
|
||||
@@ -188,6 +190,9 @@ extern int at91_set_multi_drive(unsigned pin, int is_on);
|
||||
/* callable at any time */
|
||||
extern int at91_set_gpio_value(unsigned pin, int value);
|
||||
extern int at91_get_gpio_value(unsigned pin);
|
||||
|
||||
extern void at91_gpio_suspend(void);
|
||||
extern void at91_gpio_resume(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -50,9 +50,12 @@
|
||||
#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0)
|
||||
|
||||
/* Internal SRAM */
|
||||
#define AT91_BASE_SRAM 0x00200000 /* Internal SRAM base address */
|
||||
#define AT91_SRAM_BASE 0x00200000 /* Internal SRAM base address */
|
||||
#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */
|
||||
|
||||
/* Internal SRAM is mapped below the IO devices */
|
||||
#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE)
|
||||
|
||||
/* Serial ports */
|
||||
#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */
|
||||
|
||||
@@ -81,14 +84,14 @@ static inline unsigned int at91_sys_read(unsigned int reg_offset)
|
||||
{
|
||||
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
|
||||
|
||||
return readl(addr + reg_offset);
|
||||
return __raw_readl(addr + reg_offset);
|
||||
}
|
||||
|
||||
static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
|
||||
{
|
||||
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
|
||||
|
||||
writel(value, addr + reg_offset);
|
||||
__raw_writel(value, addr + reg_offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -21,7 +21,6 @@
|
||||
#ifndef __ASM_ARCH_IO_H
|
||||
#define __ASM_ARCH_IO_H
|
||||
|
||||
#include <asm/arch/at91rm9200.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xFFFFFFFF
|
||||
|
||||
@@ -37,8 +37,6 @@
|
||||
* symbols in gpio.h for ones handled indirectly as GPIOs.
|
||||
* We make provision for 4 banks of GPIO.
|
||||
*/
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
#define NR_IRQS (NR_AIC_IRQS + (4 * 32))
|
||||
|
||||
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define PHYS_OFFSET (AT91_SDRAM_BASE)
|
||||
|
||||
|
||||
@@ -1,115 +0,0 @@
|
||||
/*
|
||||
* include/asm-arm/arch-at91rm9200/pio.h
|
||||
*
|
||||
* Copyright (C) 2003 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_PIO_H
|
||||
#define __ASM_ARCH_PIO_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
static inline void AT91_CfgPIO_USART0(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA17_TXD0 | AT91_PA18_RXD0 | AT91_PA20_CTS0);
|
||||
|
||||
/*
|
||||
* Errata #39 - RTS0 is not internally connected to PA21. We need to drive
|
||||
* the pin manually. Default is off (RTS is active low).
|
||||
*/
|
||||
at91_sys_write(AT91_PIOA + PIO_PER, AT91_PA21_RTS0);
|
||||
at91_sys_write(AT91_PIOA + PIO_OER, AT91_PA21_RTS0);
|
||||
at91_sys_write(AT91_PIOA + PIO_SODR, AT91_PA21_RTS0);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_USART1(void) {
|
||||
at91_sys_write(AT91_PIOB + PIO_PDR, AT91_PB18_RI1 | AT91_PB19_DTR1
|
||||
| AT91_PB20_TXD1 | AT91_PB21_RXD1 | AT91_PB23_DCD1
|
||||
| AT91_PB24_CTS1 | AT91_PB25_DSR1 | AT91_PB26_RTS1);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_USART2(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA22_RXD2 | AT91_PA23_TXD2);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_USART3(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
|
||||
at91_sys_write(AT91_PIOA + PIO_BSR, AT91_PA5_TXD3 | AT91_PA6_RXD3);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_DBGU(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA31_DTXD | AT91_PA30_DRXD);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the Two-Wire interface.
|
||||
*/
|
||||
static inline void AT91_CfgPIO_TWI(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA25_TWD | AT91_PA26_TWCK);
|
||||
at91_sys_write(AT91_PIOA + PIO_ASR, AT91_PA25_TWD | AT91_PA26_TWCK);
|
||||
at91_sys_write(AT91_PIOA + PIO_MDER, AT91_PA25_TWD | AT91_PA26_TWCK); /* open drain */
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the Serial Peripheral Interface.
|
||||
*/
|
||||
static inline void AT91_CfgPIO_SPI(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA0_MISO | AT91_PA1_MOSI | AT91_PA2_SPCK);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_SPI_CS0(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA3_NPCS0);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_SPI_CS1(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA4_NPCS1);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_SPI_CS2(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA5_NPCS2);
|
||||
}
|
||||
|
||||
static inline void AT91_CfgPIO_SPI_CS3(void) {
|
||||
at91_sys_write(AT91_PIOA + PIO_PDR, AT91_PA6_NPCS3);
|
||||
}
|
||||
|
||||
/*
|
||||
* Select the DataFlash card.
|
||||
*/
|
||||
static inline void AT91_CfgPIO_DataFlashCard(void) {
|
||||
at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(7));
|
||||
at91_sys_write(AT91_PIOB + PIO_OER, AT91_PIO_P(7));
|
||||
at91_sys_write(AT91_PIOB + PIO_CODR, AT91_PIO_P(7));
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable NAND Flash (SmartMedia) interface.
|
||||
*/
|
||||
static inline void AT91_CfgPIO_SmartMedia(void) {
|
||||
/* enable PC0=SMCE, PC1=SMOE, PC3=SMWE, A21=CLE, A22=ALE */
|
||||
at91_sys_write(AT91_PIOC + PIO_ASR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
|
||||
at91_sys_write(AT91_PIOC + PIO_PDR, AT91_PC0_BFCK | AT91_PC1_BFRDY_SMOE | AT91_PC3_BFBAA_SMWE);
|
||||
|
||||
/* Configure PC2 as input (signal READY of the SmartMedia) */
|
||||
at91_sys_write(AT91_PIOC + PIO_PER, AT91_PC2_BFAVD); /* enable direct output enable */
|
||||
at91_sys_write(AT91_PIOC + PIO_ODR, AT91_PC2_BFAVD); /* disable output */
|
||||
|
||||
/* Configure PB1 as input (signal Card Detect of the SmartMedia) */
|
||||
at91_sys_write(AT91_PIOB + PIO_PER, AT91_PIO_P(1)); /* enable direct output enable */
|
||||
at91_sys_write(AT91_PIOB + PIO_ODR, AT91_PIO_P(1)); /* disable output */
|
||||
}
|
||||
|
||||
static inline int AT91_PIO_SmartMedia_RDY(void) {
|
||||
return (at91_sys_read(AT91_PIOC + PIO_PDSR) & AT91_PIO_P(2)) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int AT91_PIO_SmartMedia_CardDetect(void) {
|
||||
return (at91_sys_read(AT91_PIOB + PIO_PDSR) & AT91_PIO_P(1)) ? 1 : 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -21,7 +21,7 @@
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
@@ -48,4 +48,12 @@ static inline void arch_reset(char mode)
|
||||
at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
|
||||
}
|
||||
|
||||
#define ARCH_ID_AT91RM9200 0x09200080
|
||||
#define ARCH_ID_AT91SAM9261 0x019000a0
|
||||
|
||||
static inline unsigned long arch_identify(void)
|
||||
{
|
||||
return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
#ifndef __ASM_ARCH_TIMEX_H
|
||||
#define __ASM_ARCH_TIMEX_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
|
||||
|
||||
|
||||
@@ -21,7 +21,7 @@
|
||||
#ifndef __ASM_ARCH_UNCOMPRESS_H
|
||||
#define __ASM_ARCH_UNCOMPRESS_H
|
||||
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
/*
|
||||
* The following code assumes the serial port has already been
|
||||
|
||||
@@ -21,6 +21,6 @@
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
||||
#define __ASM_ARCH_VMALLOC_H
|
||||
|
||||
#define VMALLOC_END (AT91_IO_VIRT_BASE & PGDIR_MASK)
|
||||
#define VMALLOC_END (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -8,7 +8,7 @@
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
|
||||
ldr \irqnr, [\irqnr] @ get interrupt number
|
||||
cmp \irqnr, #0x0 @ suprious interrupt ?
|
||||
cmp \irqnr, #0x0 @ spurious interrupt ?
|
||||
movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits
|
||||
subne \irqnr, \irqnr, #1 @ convert to 0 based
|
||||
|
||||
|
||||
@@ -251,7 +251,7 @@
|
||||
* CAP CSRs.
|
||||
****************************************************************************/
|
||||
#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
|
||||
#define IXP23XX_PROD_IDG IXP23XX_GLOBAL_REG(0x00)
|
||||
#define IXP23XX_PRODUCT_ID IXP23XX_GLOBAL_REG(0x00)
|
||||
#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04)
|
||||
#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08)
|
||||
#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c)
|
||||
|
||||
@@ -0,0 +1,38 @@
|
||||
/* linux/include/asm-arm/arch-netx/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hardware.h"
|
||||
|
||||
.macro addruart,rx
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
moveq \rx, #0x00100000 @ physical
|
||||
movne \rx, #io_p2v(0x00100000) @ virtual
|
||||
orr \rx, \rx, #0x00000a00
|
||||
.endm
|
||||
|
||||
.macro senduart,rd,rx
|
||||
str \rd, [\rx, #0]
|
||||
.endm
|
||||
|
||||
.macro busyuart,rd,rx
|
||||
1002: ldr \rd, [\rx, #0x18]
|
||||
tst \rd, #(1 << 3)
|
||||
bne 1002b
|
||||
.endm
|
||||
|
||||
.macro waituart,rd,rx
|
||||
1001: ldr \rd, [\rx, #0x18]
|
||||
tst \rd, #(1 << 3)
|
||||
bne 1001b
|
||||
.endm
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-netx/dma.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define MAX_DMA_CHANNELS 0
|
||||
#define MAX_DMA_ADDRESS ~0
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for Hilscher netX based platforms
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <asm/hardware.h>
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
mov \base, #io_p2v(0x00100000)
|
||||
add \base, \base, #0x000ff000
|
||||
|
||||
ldr \irqstat, [\base, #0]
|
||||
clz \irqnr, \irqstat
|
||||
rsb \irqnr, \irqnr, #31
|
||||
cmp \irqstat, #0
|
||||
.endm
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/hardware.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#define NETX_IO_PHYS 0x00100000
|
||||
#define NETX_IO_VIRT 0xe0000000
|
||||
#define NETX_IO_SIZE 0x00100000
|
||||
|
||||
#define SRAM_INTERNAL_PHYS_0 0x00000
|
||||
#define SRAM_INTERNAL_PHYS_1 0x08000
|
||||
#define SRAM_INTERNAL_PHYS_2 0x10000
|
||||
#define SRAM_INTERNAL_PHYS_3 0x18000
|
||||
#define SRAM_INTERNAL_PHYS(no) ((no) * 0x8000)
|
||||
|
||||
#define XPEC_MEM_SIZE 0x4000
|
||||
#define XMAC_MEM_SIZE 0x1000
|
||||
#define SRAM_MEM_SIZE 0x8000
|
||||
|
||||
#define io_p2v(x) ((x) - NETX_IO_PHYS + NETX_IO_VIRT)
|
||||
#define io_v2p(x) ((x) - NETX_IO_VIRT + NETX_IO_PHYS)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-netx/io.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define __io(a) ((void __iomem *)(a))
|
||||
#define __mem_pci(a) (a)
|
||||
#define __mem_isa(a) (a)
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/irqs.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define NETX_IRQ_VIC_START 0
|
||||
#define NETX_IRQ_SOFTINT 0
|
||||
#define NETX_IRQ_TIMER0 1
|
||||
#define NETX_IRQ_TIMER1 2
|
||||
#define NETX_IRQ_TIMER2 3
|
||||
#define NETX_IRQ_SYSTIME_NS 4
|
||||
#define NETX_IRQ_SYSTIME_S 5
|
||||
#define NETX_IRQ_GPIO_15 6
|
||||
#define NETX_IRQ_WATCHDOG 7
|
||||
#define NETX_IRQ_UART0 8
|
||||
#define NETX_IRQ_UART1 9
|
||||
#define NETX_IRQ_UART2 10
|
||||
#define NETX_IRQ_USB 11
|
||||
#define NETX_IRQ_SPI 12
|
||||
#define NETX_IRQ_I2C 13
|
||||
#define NETX_IRQ_LCD 14
|
||||
#define NETX_IRQ_HIF 15
|
||||
#define NETX_IRQ_GPIO_0_14 16
|
||||
#define NETX_IRQ_XPEC0 17
|
||||
#define NETX_IRQ_XPEC1 18
|
||||
#define NETX_IRQ_XPEC2 19
|
||||
#define NETX_IRQ_XPEC3 20
|
||||
#define NETX_IRQ_XPEC(no) (17 + (no))
|
||||
#define NETX_IRQ_MSYNC0 21
|
||||
#define NETX_IRQ_MSYNC1 22
|
||||
#define NETX_IRQ_MSYNC2 23
|
||||
#define NETX_IRQ_MSYNC3 24
|
||||
#define NETX_IRQ_IRQ_PHY 25
|
||||
#define NETX_IRQ_ISO_AREA 26
|
||||
/* int 27 is reserved */
|
||||
/* int 28 is reserved */
|
||||
#define NETX_IRQ_TIMER3 29
|
||||
#define NETX_IRQ_TIMER4 30
|
||||
/* int 31 is reserved */
|
||||
|
||||
#define NETX_IRQS 32
|
||||
|
||||
/* for multiplexed irqs on gpio 0..14 */
|
||||
#define NETX_IRQ_GPIO(x) (NETX_IRQS + (x))
|
||||
#define NETX_IRQ_GPIO_LAST NETX_IRQ_GPIO(14)
|
||||
|
||||
/* Host interface interrupts */
|
||||
#define NETX_IRQ_HIF_CHAINED(x) (NETX_IRQ_GPIO_LAST + 1 + (x))
|
||||
#define NETX_IRQ_HIF_PIO35 NETX_IRQ_HIF_CHAINED(0)
|
||||
#define NETX_IRQ_HIF_PIO36 NETX_IRQ_HIF_CHAINED(1)
|
||||
#define NETX_IRQ_HIF_PIO40 NETX_IRQ_HIF_CHAINED(2)
|
||||
#define NETX_IRQ_HIF_PIO47 NETX_IRQ_HIF_CHAINED(3)
|
||||
#define NETX_IRQ_HIF_PIO72 NETX_IRQ_HIF_CHAINED(4)
|
||||
#define NETX_IRQ_HIF_LAST NETX_IRQ_HIF_CHAINED(4)
|
||||
|
||||
#define NR_IRQS (NETX_IRQ_HIF_LAST + 1)
|
||||
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-netx/memory.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#define PHYS_OFFSET UL(0x80000000)
|
||||
|
||||
/*
|
||||
* Virtual view <-> DMA view memory address translations
|
||||
* virt_to_bus: Used to translate the virtual address to an
|
||||
* address suitable to be passed to set_dma_addr
|
||||
* bus_to_virt: Used to convert an address for DMA operations
|
||||
* to an address that the kernel can use.
|
||||
*/
|
||||
#define __virt_to_bus(x) __virt_to_phys(x)
|
||||
#define __bus_to_virt(x) __phys_to_virt(x)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,410 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/netx-regs.h
|
||||
*
|
||||
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_NETX_REGS_H
|
||||
#define __ASM_ARCH_NETX_REGS_H
|
||||
|
||||
/* offsets relative to the beginning of the io space */
|
||||
#define NETX_OFS_SYSTEM 0x00000
|
||||
#define NETX_OFS_MEMCR 0x00100
|
||||
#define NETX_OFS_DPMAS 0x03000
|
||||
#define NETX_OFS_GPIO 0x00800
|
||||
#define NETX_OFS_PIO 0x00900
|
||||
#define NETX_OFS_UART0 0x00a00
|
||||
#define NETX_OFS_UART1 0x00a40
|
||||
#define NETX_OFS_UART2 0x00a80
|
||||
#define NETX_OF_MIIMU 0x00b00
|
||||
#define NETX_OFS_SPI 0x00c00
|
||||
#define NETX_OFS_I2C 0x00d00
|
||||
#define NETX_OFS_SYSTIME 0x01100
|
||||
#define NETX_OFS_RTC 0x01200
|
||||
#define NETX_OFS_EXTBUS 0x03600
|
||||
#define NETX_OFS_LCD 0x04000
|
||||
#define NETX_OFS_USB 0x20000
|
||||
#define NETX_OFS_XMAC0 0x60000
|
||||
#define NETX_OFS_XMAC1 0x61000
|
||||
#define NETX_OFS_XMAC2 0x62000
|
||||
#define NETX_OFS_XMAC3 0x63000
|
||||
#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000)
|
||||
#define NETX_OFS_PFIFO 0x64000
|
||||
#define NETX_OFS_XPEC0 0x70000
|
||||
#define NETX_OFS_XPEC1 0x74000
|
||||
#define NETX_OFS_XPEC2 0x78000
|
||||
#define NETX_OFS_XPEC3 0x7c000
|
||||
#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000)
|
||||
#define NETX_OFS_VIC 0xff000
|
||||
|
||||
/* physical addresses */
|
||||
#define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM)
|
||||
#define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR)
|
||||
#define NETX_PA_DPMAS (NETX_IO_PHYS + NETX_OFS_DPMAS)
|
||||
#define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO)
|
||||
#define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO)
|
||||
#define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0)
|
||||
#define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1)
|
||||
#define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2)
|
||||
#define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU)
|
||||
#define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI)
|
||||
#define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C)
|
||||
#define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME)
|
||||
#define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC)
|
||||
#define NETX_PA_EXTBUS (NETX_IO_PHYS + NETX_OFS_EXTBUS)
|
||||
#define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD)
|
||||
#define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB)
|
||||
#define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0)
|
||||
#define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1)
|
||||
#define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2)
|
||||
#define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3)
|
||||
#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no))
|
||||
#define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO)
|
||||
#define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0)
|
||||
#define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1)
|
||||
#define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2)
|
||||
#define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3)
|
||||
#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no))
|
||||
#define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC)
|
||||
|
||||
/* virual addresses */
|
||||
#define NETX_VA_SYSTEM (NETX_IO_VIRT + NETX_OFS_SYSTEM)
|
||||
#define NETX_VA_MEMCR (NETX_IO_VIRT + NETX_OFS_MEMCR)
|
||||
#define NETX_VA_DPMAS (NETX_IO_VIRT + NETX_OFS_DPMAS)
|
||||
#define NETX_VA_GPIO (NETX_IO_VIRT + NETX_OFS_GPIO)
|
||||
#define NETX_VA_PIO (NETX_IO_VIRT + NETX_OFS_PIO)
|
||||
#define NETX_VA_UART0 (NETX_IO_VIRT + NETX_OFS_UART0)
|
||||
#define NETX_VA_UART1 (NETX_IO_VIRT + NETX_OFS_UART1)
|
||||
#define NETX_VA_UART2 (NETX_IO_VIRT + NETX_OFS_UART2)
|
||||
#define NETX_VA_MIIMU (NETX_IO_VIRT + NETX_OF_MIIMU)
|
||||
#define NETX_VA_SPI (NETX_IO_VIRT + NETX_OFS_SPI)
|
||||
#define NETX_VA_I2C (NETX_IO_VIRT + NETX_OFS_I2C)
|
||||
#define NETX_VA_SYSTIME (NETX_IO_VIRT + NETX_OFS_SYSTIME)
|
||||
#define NETX_VA_RTC (NETX_IO_VIRT + NETX_OFS_RTC)
|
||||
#define NETX_VA_EXTBUS (NETX_IO_VIRT + NETX_OFS_EXTBUS)
|
||||
#define NETX_VA_LCD (NETX_IO_VIRT + NETX_OFS_LCD)
|
||||
#define NETX_VA_USB (NETX_IO_VIRT + NETX_OFS_USB)
|
||||
#define NETX_VA_XMAC0 (NETX_IO_VIRT + NETX_OFS_XMAC0)
|
||||
#define NETX_VA_XMAC1 (NETX_IO_VIRT + NETX_OFS_XMAC1)
|
||||
#define NETX_VA_XMAC2 (NETX_IO_VIRT + NETX_OFS_XMAC2)
|
||||
#define NETX_VA_XMAC3 (NETX_IO_VIRT + NETX_OFS_XMAC3)
|
||||
#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no))
|
||||
#define NETX_VA_PFIFO (NETX_IO_VIRT + NETX_OFS_PFIFO)
|
||||
#define NETX_VA_XPEC0 (NETX_IO_VIRT + NETX_OFS_XPEC0)
|
||||
#define NETX_VA_XPEC1 (NETX_IO_VIRT + NETX_OFS_XPEC1)
|
||||
#define NETX_VA_XPEC2 (NETX_IO_VIRT + NETX_OFS_XPEC2)
|
||||
#define NETX_VA_XPEC3 (NETX_IO_VIRT + NETX_OFS_XPEC3)
|
||||
#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no))
|
||||
#define NETX_VA_VIC (NETX_IO_VIRT + NETX_OFS_VIC)
|
||||
|
||||
/*********************************
|
||||
* System functions *
|
||||
*********************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_SYSTEM_REG(ofs) __io(NETX_VA_SYSTEM + (ofs))
|
||||
#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
|
||||
#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
|
||||
#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
|
||||
|
||||
/* FIXME: Docs are not consistent */
|
||||
#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08)
|
||||
/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c) */
|
||||
|
||||
#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10)
|
||||
#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34)
|
||||
#define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70)
|
||||
#define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200)
|
||||
#define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204)
|
||||
#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
|
||||
#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
|
||||
|
||||
/* Bits */
|
||||
#define NETX_SYSTEM_RES_CR_RSTIN (1<<0)
|
||||
#define NETX_SYSTEM_RES_CR_WDG_RES (1<<1)
|
||||
#define NETX_SYSTEM_RES_CR_HOST_RES (1<<2)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_RES (1<<3)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC0_RES (1<<4)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC1_RES (1<<5)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC2_RES (1<<6)
|
||||
#define NETX_SYSTEM_RES_CR_XPEC3_RES (1<<7)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18)
|
||||
#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG0 (1<<20)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG1 (1<<21)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG2 (1<<22)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_FLG3 (1<<23)
|
||||
#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN (1<<24)
|
||||
#define NETX_SYSTEM_RES_CR_RSTOUT (1<<25)
|
||||
#define NETX_SYSTEM_RES_CR_EN_RSTOUT (1<<26)
|
||||
|
||||
#define PHY_CONTROL_RESET (1<<31)
|
||||
#define PHY_CONTROL_SIM_BYP (1<<30)
|
||||
#define PHY_CONTROL_CLK_XLATIN (1<<29)
|
||||
#define PHY_CONTROL_PHY1_EN (1<<21)
|
||||
#define PHY_CONTROL_PHY1_NP_MSG_CODE
|
||||
#define PHY_CONTROL_PHY1_AUTOMDIX (1<<17)
|
||||
#define PHY_CONTROL_PHY1_FIXMODE (1<<16)
|
||||
#define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13)
|
||||
#define PHY_CONTROL_PHY0_EN (1<<12)
|
||||
#define PHY_CONTROL_PHY0_NP_MSG_CODE
|
||||
#define PHY_CONTROL_PHY0_AUTOMDIX (1<<8)
|
||||
#define PHY_CONTROL_PHY0_FIXMODE (1<<7)
|
||||
#define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4)
|
||||
#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
|
||||
|
||||
#define PHY_MODE_10BASE_T_HALF 0
|
||||
#define PHY_MODE_10BASE_T_FULL 1
|
||||
#define PHY_MODE_100BASE_TX_FX_FULL 2
|
||||
#define PHY_MODE_100BASE_TX_FX_HALF 3
|
||||
#define PHY_MODE_100BASE_TX_HALF 4
|
||||
#define PHY_MODE_REPEATER 5
|
||||
#define PHY_MODE_POWER_DOWN 6
|
||||
#define PHY_MODE_ALL 7
|
||||
|
||||
/* Bits */
|
||||
#define VECT_CNTL_ENABLE (1 << 5)
|
||||
|
||||
/*******************************
|
||||
* GPIO and timer module *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_GPIO_REG(ofs) __io(NETX_VA_GPIO + (ofs))
|
||||
#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
|
||||
#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
|
||||
#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
|
||||
#define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2))
|
||||
#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
|
||||
#define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc)
|
||||
#define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0)
|
||||
#define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4)
|
||||
#define NETX_GPIO_LINE NETX_GPIO_REG(0xc8)
|
||||
#define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0)
|
||||
|
||||
/* Bits */
|
||||
#define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0)
|
||||
#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1)
|
||||
#define NETX_GPIO_CFG_IOCFG_GP_UART (0x2)
|
||||
#define NETX_GPIO_CFG_INV (1<<2)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3)
|
||||
#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5)
|
||||
#define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5)
|
||||
|
||||
#define NETX_GPIO_COUNTER_CTRL_RUN (1<<0)
|
||||
#define NETX_GPIO_COUNTER_CTRL_SYM (1<<1)
|
||||
#define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2)
|
||||
#define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3)
|
||||
#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4)
|
||||
#define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5)
|
||||
#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6)
|
||||
#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */
|
||||
|
||||
#define GPIO_BIT(gpio) (1<<(gpio))
|
||||
#define COUNTER_BIT(counter) ((1<<16)<<(counter))
|
||||
|
||||
/*******************************
|
||||
* PIO *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs))
|
||||
#define NETX_PIO_INPIO NETX_PIO_REG(0x0)
|
||||
#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
|
||||
#define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
|
||||
|
||||
/*******************************
|
||||
* MII Unit *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_MIIMU __io(NETX_VA_MIIMU)
|
||||
|
||||
/* Bits */
|
||||
#define MIIMU_SNRDY (1<<0)
|
||||
#define MIIMU_PREAMBLE (1<<1)
|
||||
#define MIIMU_OPMODE_WRITE (1<<2)
|
||||
#define MIIMU_MDC_PERIOD (1<<3)
|
||||
#define MIIMU_PHY_NRES (1<<4)
|
||||
#define MIIMU_RTA (1<<5)
|
||||
#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)
|
||||
#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)
|
||||
#define MIIMU_DATA(data) (((data) & 0xffff) << 16)
|
||||
|
||||
/*******************************
|
||||
* xmac / xpec *
|
||||
*******************************/
|
||||
|
||||
/* XPEC register offsets relative to NETX_VA_XPEC(no) */
|
||||
#define NETX_XPEC_R0_OFS 0x00
|
||||
#define NETX_XPEC_R1_OFS 0x04
|
||||
#define NETX_XPEC_R2_OFS 0x08
|
||||
#define NETX_XPEC_R3_OFS 0x0c
|
||||
#define NETX_XPEC_R4_OFS 0x10
|
||||
#define NETX_XPEC_R5_OFS 0x14
|
||||
#define NETX_XPEC_R6_OFS 0x18
|
||||
#define NETX_XPEC_R7_OFS 0x1c
|
||||
#define NETX_XPEC_RANGE01_OFS 0x20
|
||||
#define NETX_XPEC_RANGE23_OFS 0x24
|
||||
#define NETX_XPEC_RANGE45_OFS 0x28
|
||||
#define NETX_XPEC_RANGE67_OFS 0x2c
|
||||
#define NETX_XPEC_PC_OFS 0x48
|
||||
#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))
|
||||
#define NETX_XPEC_IRQ_OFS 0x8c
|
||||
#define NETX_XPEC_SYSTIME_NS_OFS 0x90
|
||||
#define NETX_XPEC_FIFO_DATA_OFS 0x94
|
||||
#define NETX_XPEC_SYSTIME_S_OFS 0x98
|
||||
#define NETX_XPEC_ADC_OFS 0x9c
|
||||
#define NETX_XPEC_URX_COUNT_OFS 0x40
|
||||
#define NETX_XPEC_UTX_COUNT_OFS 0x44
|
||||
#define NETX_XPEC_PC_OFS 0x48
|
||||
#define NETX_XPEC_ZERO_OFS 0x4c
|
||||
#define NETX_XPEC_STATCFG_OFS 0x50
|
||||
#define NETX_XPEC_EC_MASKA_OFS 0x54
|
||||
#define NETX_XPEC_EC_MASKB_OFS 0x58
|
||||
#define NETX_XPEC_EC_MASK0_OFS 0x5c
|
||||
#define NETX_XPEC_EC_MASK8_OFS 0x7c
|
||||
#define NETX_XPEC_EC_MASK9_OFS 0x80
|
||||
#define NETX_XPEC_XPU_HOLD_PC_OFS 0x100
|
||||
#define NETX_XPEC_RAM_START_OFS 0x2000
|
||||
|
||||
/* Bits */
|
||||
#define XPU_HOLD_PC (1<<0)
|
||||
|
||||
/* XMAC register offsets relative to NETX_VA_XMAC(no) */
|
||||
#define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000
|
||||
#define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff
|
||||
#define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400
|
||||
#define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff
|
||||
#define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00
|
||||
#define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04
|
||||
#define NETX_XMAC_STATUS_SHARED0_OFS 0x840
|
||||
#define NETX_XMAC_CONFIG_SHARED0_OFS 0x844
|
||||
#define NETX_XMAC_STATUS_SHARED1_OFS 0x848
|
||||
#define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c
|
||||
#define NETX_XMAC_STATUS_SHARED2_OFS 0x850
|
||||
#define NETX_XMAC_CONFIG_SHARED2_OFS 0x854
|
||||
#define NETX_XMAC_STATUS_SHARED3_OFS 0x858
|
||||
#define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c
|
||||
|
||||
#define RPU_HOLD_PC (1<<15)
|
||||
#define TPU_HOLD_PC (1<<15)
|
||||
|
||||
/*******************************
|
||||
* Pointer FIFO *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs))
|
||||
#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
|
||||
#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
|
||||
#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
|
||||
#define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104)
|
||||
#define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108)
|
||||
#define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c)
|
||||
#define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110)
|
||||
#define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
|
||||
#define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2))
|
||||
|
||||
/*******************************
|
||||
* Dual Port Memory *
|
||||
*******************************/
|
||||
|
||||
/* Registers */
|
||||
#define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs))
|
||||
#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
|
||||
#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
|
||||
#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
|
||||
#define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608)
|
||||
#define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c)
|
||||
#define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs))
|
||||
#define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */
|
||||
#define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624)
|
||||
#define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628)
|
||||
#define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */
|
||||
#define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634)
|
||||
#define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638)
|
||||
|
||||
/* Bits */
|
||||
#define NETX_DPMAS_INT_EN_GLB_EN (1<<31)
|
||||
#define NETX_DPMAS_INT_EN_MEM_LCK (1<<30)
|
||||
#define NETX_DPMAS_INT_EN_WDG (1<<29)
|
||||
#define NETX_DPMAS_INT_EN_PIO72 (1<<28)
|
||||
#define NETX_DPMAS_INT_EN_PIO47 (1<<27)
|
||||
#define NETX_DPMAS_INT_EN_PIO40 (1<<26)
|
||||
#define NETX_DPMAS_INT_EN_PIO36 (1<<25)
|
||||
#define NETX_DPMAS_INT_EN_PIO35 (1<<24)
|
||||
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS (1<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT (2<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_HIF_IO (4<<28)
|
||||
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP (1<<14)
|
||||
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD (2<<14)
|
||||
#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14)
|
||||
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29)
|
||||
#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30)
|
||||
|
||||
#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)
|
||||
#define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26)
|
||||
#define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23)
|
||||
#define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20)
|
||||
#define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17)
|
||||
#define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12)
|
||||
#define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7)
|
||||
#define NETX_EXT_CONFIG_WAIT_POL (1<<6)
|
||||
#define NETX_EXT_CONFIG_WAIT_EN (1<<5)
|
||||
#define NETX_EXT_CONFIG_NRD_MODE (1<<4)
|
||||
#define NETX_EXT_CONFIG_DS_MODE (1<<3)
|
||||
#define NETX_EXT_CONFIG_NWR_MODE (1<<2)
|
||||
#define NETX_EXT_CONFIG_16BIT (1<<1)
|
||||
#define NETX_EXT_CONFIG_CS_ENABLE (1<<0)
|
||||
|
||||
#define NETX_DPMAS_IO_MODE0_WRL (1<<13)
|
||||
#define NETX_DPMAS_IO_MODE0_WAIT (1<<14)
|
||||
#define NETX_DPMAS_IO_MODE0_READY (1<<15)
|
||||
#define NETX_DPMAS_IO_MODE0_CS0 (1<<19)
|
||||
#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20)
|
||||
|
||||
#define NETX_DPMAS_IO_MODE1_CS2 (1<<15)
|
||||
#define NETX_DPMAS_IO_MODE1_CS1 (1<<16)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30)
|
||||
#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36 (3<<30)
|
||||
|
||||
/*******************************
|
||||
* I2C *
|
||||
*******************************/
|
||||
#define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs))
|
||||
#define NETX_I2C_CTRL NETX_I2C_REG(0x0)
|
||||
#define NETX_I2C_DATA NETX_I2C_REG(0x4)
|
||||
|
||||
#endif /* __ASM_ARCH_NETX_REGS_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-netx/param.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/pfifo.h
|
||||
*
|
||||
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef ASM_ARCH_PFIFO_H
|
||||
#define ASM_ARCH_PFIFO_H
|
||||
|
||||
static inline int pfifo_push(int no, unsigned int pointer)
|
||||
{
|
||||
writel(pointer, NETX_PFIFO_BASE(no));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline unsigned int pfifo_pop(int no)
|
||||
{
|
||||
return readl(NETX_PFIFO_BASE(no));
|
||||
}
|
||||
|
||||
static inline int pfifo_fill_level(int no)
|
||||
{
|
||||
|
||||
return readl(NETX_PFIFO_FILL_LEVEL(no));
|
||||
}
|
||||
|
||||
static inline int pfifo_full(int no)
|
||||
{
|
||||
return readl(NETX_PFIFO_FULL) & (1<<no) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int pfifo_empty(int no)
|
||||
{
|
||||
return readl(NETX_PFIFO_EMPTY) & (1<<no) ? 1 : 0;
|
||||
}
|
||||
|
||||
int pfifo_request(unsigned int pfifo_mask);
|
||||
void pfifo_free(unsigned int pfifo_mask);
|
||||
|
||||
#endif /* ASM_ARCH_PFIFO_H */
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/system.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __ASM_ARCH_SYSTEM_H
|
||||
#define __ASM_ARCH_SYSTEM_H
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/hardware.h>
|
||||
#include "netx-regs.h"
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
|
||||
NETX_SYSTEM_RES_CR);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/timex.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#define CLOCK_TICK_RATE 100000000
|
||||
@@ -0,0 +1,76 @@
|
||||
/*
|
||||
* include/asm-arm/arch-netx/uncompress.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code assumes the serial port has already been
|
||||
* initialized by the bootloader. We search for the first enabled
|
||||
* port in the most probable order. If you didn't setup a port in
|
||||
* your bootloader then nothing will appear (which might be desired).
|
||||
*
|
||||
* This does not append a newline
|
||||
*/
|
||||
|
||||
#define REG(x) (*(volatile unsigned long *)(x))
|
||||
|
||||
#define UART1_BASE 0x100a00
|
||||
#define UART2_BASE 0x100a80
|
||||
|
||||
#define UART_DR 0x0
|
||||
|
||||
#define UART_CR 0x14
|
||||
#define CR_UART_EN (1<<0)
|
||||
|
||||
#define UART_FR 0x18
|
||||
#define FR_BUSY (1<<3)
|
||||
#define FR_TXFF (1<<5)
|
||||
|
||||
static void putc(char c)
|
||||
{
|
||||
unsigned long base;
|
||||
|
||||
if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
|
||||
base = UART1_BASE;
|
||||
else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
|
||||
base = UART2_BASE;
|
||||
else
|
||||
return;
|
||||
|
||||
while (REG(base + UART_FR) & FR_TXFF);
|
||||
REG(base + UART_DR) = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
unsigned long base;
|
||||
|
||||
if (REG(UART1_BASE + UART_CR) & CR_UART_EN)
|
||||
base = UART1_BASE;
|
||||
else if (REG(UART2_BASE + UART_CR) & CR_UART_EN)
|
||||
base = UART2_BASE;
|
||||
else
|
||||
return;
|
||||
|
||||
while (REG(base + UART_FR) & FR_BUSY);
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup()
|
||||
#define arch_decomp_wdog()
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-netx/vmalloc.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
|
||||
@@ -0,0 +1,42 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-netx/xc.h
|
||||
*
|
||||
* Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_XC_H
|
||||
#define __ASM_ARCH_XC_H
|
||||
|
||||
struct xc {
|
||||
int no;
|
||||
unsigned int type;
|
||||
unsigned int version;
|
||||
void __iomem *xpec_base;
|
||||
void __iomem *xmac_base;
|
||||
void __iomem *sram_base;
|
||||
int irq;
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
int xc_reset(struct xc *x);
|
||||
int xc_stop(struct xc* x);
|
||||
int xc_start(struct xc *x);
|
||||
int xc_running(struct xc *x);
|
||||
int xc_request_firmware(struct xc* x);
|
||||
struct xc* request_xc(int xcno, struct device *dev);
|
||||
void free_xc(struct xc *x);
|
||||
|
||||
#endif /* __ASM_ARCH_XC_H */
|
||||
@@ -31,6 +31,7 @@
|
||||
#define POODLE_GPIO_CF_CD (14)
|
||||
#define POODLE_GPIO_CF_STSCHG (14)
|
||||
#define POODLE_GPIO_SD_PWR (33)
|
||||
#define POODLE_GPIO_SD_PWR1 (3)
|
||||
#define POODLE_GPIO_nSD_CLK (6)
|
||||
#define POODLE_GPIO_nSD_WP (7)
|
||||
#define POODLE_GPIO_nSD_INT (8)
|
||||
@@ -42,6 +43,7 @@
|
||||
#define POODLE_GPIO_BYPASS_ON (36)
|
||||
#define POODLE_GPIO_CHRG_ON (38)
|
||||
#define POODLE_GPIO_CHRG_FULL (16)
|
||||
#define POODLE_GPIO_DISCHARGE_ON (42) /* Enable battery discharge */
|
||||
|
||||
/* PXA GPIOs */
|
||||
#define POODLE_IRQ_GPIO_ON_KEY IRQ_GPIO(0)
|
||||
@@ -68,4 +70,6 @@
|
||||
#define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
|
||||
#define POODLE_SCOOP_IO_OUT ( 0 )
|
||||
|
||||
extern struct platform_device poodle_locomo_device;
|
||||
|
||||
#endif /* __ASM_ARCH_POODLE_H */
|
||||
|
||||
@@ -1625,7 +1625,7 @@
|
||||
#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
|
||||
#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
|
||||
#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
|
||||
#define SSCR0_SlotsPerFrm(c) ((x) - 1) /* Time slots per frame [1..8] */
|
||||
#define SSCR0_SlotsPerFrm(x) ((x) - 1) /* Time slots per frame [1..8] */
|
||||
#define SSCR0_ADC (1 << 30) /* Audio clock select */
|
||||
#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
|
||||
#endif
|
||||
@@ -1706,6 +1706,10 @@
|
||||
#if defined (CONFIG_PXA27x)
|
||||
#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
|
||||
#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
|
||||
#define SSTSA_P1 __REG(0x41000030) /* SSP Port 1 Tx Timeslot Active */
|
||||
#define SSRSA_P1 __REG(0x41000034) /* SSP Port 1 Rx Timeslot Active */
|
||||
#define SSTSS_P1 __REG(0x41000038) /* SSP Port 1 Timeslot Status */
|
||||
#define SSACD_P1 __REG(0x4100003C) /* SSP Port 1 Audio Clock Divider */
|
||||
#define SSCR0_P2 __REG(0x41700000) /* SSP Port 2 Control Register 0 */
|
||||
#define SSCR1_P2 __REG(0x41700004) /* SSP Port 2 Control Register 1 */
|
||||
#define SSSR_P2 __REG(0x41700008) /* SSP Port 2 Status Register */
|
||||
@@ -1713,6 +1717,10 @@
|
||||
#define SSDR_P2 __REG(0x41700010) /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
|
||||
#define SSTO_P2 __REG(0x41700028) /* SSP Port 2 Time Out Register */
|
||||
#define SSPSP_P2 __REG(0x4170002C) /* SSP Port 2 Programmable Serial Protocol */
|
||||
#define SSTSA_P2 __REG(0x41700030) /* SSP Port 2 Tx Timeslot Active */
|
||||
#define SSRSA_P2 __REG(0x41700034) /* SSP Port 2 Rx Timeslot Active */
|
||||
#define SSTSS_P2 __REG(0x41700038) /* SSP Port 2 Timeslot Status */
|
||||
#define SSACD_P2 __REG(0x4170003C) /* SSP Port 2 Audio Clock Divider */
|
||||
#define SSCR0_P3 __REG(0x41900000) /* SSP Port 3 Control Register 0 */
|
||||
#define SSCR1_P3 __REG(0x41900004) /* SSP Port 3 Control Register 1 */
|
||||
#define SSSR_P3 __REG(0x41900008) /* SSP Port 3 Status Register */
|
||||
@@ -1720,6 +1728,10 @@
|
||||
#define SSDR_P3 __REG(0x41900010) /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
|
||||
#define SSTO_P3 __REG(0x41900028) /* SSP Port 3 Time Out Register */
|
||||
#define SSPSP_P3 __REG(0x4190002C) /* SSP Port 3 Programmable Serial Protocol */
|
||||
#define SSTSA_P3 __REG(0x41900030) /* SSP Port 3 Tx Timeslot Active */
|
||||
#define SSRSA_P3 __REG(0x41900034) /* SSP Port 3 Rx Timeslot Active */
|
||||
#define SSTSS_P3 __REG(0x41900038) /* SSP Port 3 Timeslot Status */
|
||||
#define SSACD_P3 __REG(0x4190003C) /* SSP Port 3 Audio Clock Divider */
|
||||
#else /* PXA255 (only port 2) and PXA26x ports*/
|
||||
#define SSTO_P1 __REG(0x41000028) /* SSP Port 1 Time Out Register */
|
||||
#define SSPSP_P1 __REG(0x4100002C) /* SSP Port 1 Programmable Serial Protocol */
|
||||
@@ -1746,6 +1758,10 @@
|
||||
#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
|
||||
#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
|
||||
#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
|
||||
#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
|
||||
#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
|
||||
#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
|
||||
#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
|
||||
|
||||
/*
|
||||
* MultiMediaCard (MMC) controller
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <asm/proc-fns.h>
|
||||
#include "hardware.h"
|
||||
#include "pxa-regs.h"
|
||||
|
||||
|
||||
@@ -36,16 +36,14 @@ static inline void arch_idle(void)
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
unsigned int hdr_ctrl = (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_RESETCTL_OFFSET);
|
||||
unsigned int val;
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* To reset, we hit the on-board reset register
|
||||
* in the system FPGA
|
||||
*/
|
||||
val = __raw_readl(hdr_ctrl);
|
||||
val |= VERSATILE_SYS_CTRL_RESET_CONFIGCLR;
|
||||
__raw_writel(val, hdr_ctrl);
|
||||
val = __raw_readl(IO_ADDRESS(VERSATILE_SYS_RESETCTL)) & ~0x7;
|
||||
val |= 0x105;
|
||||
|
||||
__raw_writel(0xa05f, IO_ADDRESS(VERSATILE_SYS_LOCK));
|
||||
__raw_writel(val, IO_ADDRESS(VERSATILE_SYS_RESETCTL));
|
||||
__raw_writel(0, IO_ADDRESS(VERSATILE_SYS_LOCK));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -22,16 +22,18 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
|
||||
{
|
||||
__u32 t;
|
||||
|
||||
if (__builtin_constant_p(x)) {
|
||||
t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
|
||||
} else {
|
||||
#ifndef __thumb__
|
||||
if (!__builtin_constant_p(x)) {
|
||||
/*
|
||||
* The compiler needs a bit of a hint here to always do the
|
||||
* right thing and not screw it up to different degrees
|
||||
* depending on the gcc version.
|
||||
*/
|
||||
asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
|
||||
}
|
||||
} else
|
||||
#endif
|
||||
t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
|
||||
|
||||
x = (x << 24) | (x >> 8); /* mov r0,r0,ror #8 */
|
||||
t &= ~0x00FF0000; /* bic r1,r1,#0x00FF0000 */
|
||||
x ^= (t >> 8); /* eor r0,r0,r1,lsr #8 */
|
||||
|
||||
@@ -16,6 +16,7 @@ struct sharpsl_charger_machinfo {
|
||||
void (*exit)(void);
|
||||
int gpio_acin;
|
||||
int gpio_batfull;
|
||||
int batfull_irq;
|
||||
int gpio_batlock;
|
||||
int gpio_fatal;
|
||||
void (*discharge)(int);
|
||||
@@ -34,9 +35,19 @@ struct sharpsl_charger_machinfo {
|
||||
#define SHARPSL_STATUS_FATAL 7
|
||||
unsigned long (*charger_wakeup)(void);
|
||||
int (*should_wakeup)(unsigned int resume_on_alarm);
|
||||
void (*backlight_limit)(int);
|
||||
int (*backlight_get_status) (void);
|
||||
int charge_on_volt;
|
||||
int charge_on_temp;
|
||||
int charge_acin_high;
|
||||
int charge_acin_low;
|
||||
int fatal_acin_volt;
|
||||
int fatal_noacin_volt;
|
||||
int bat_levels;
|
||||
struct battery_thresh *bat_levels_noac;
|
||||
struct battery_thresh *bat_levels_acin;
|
||||
struct battery_thresh *bat_levels_noac_bl;
|
||||
struct battery_thresh *bat_levels_acin_bl;
|
||||
int status_high_acin;
|
||||
int status_low_acin;
|
||||
int status_high_noac;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* linux/include/asm-arm/mach/serial_at91rm9200.h
|
||||
* linux/include/asm-arm/mach/serial_at91.h
|
||||
*
|
||||
* Based on serial_sa1100.h by Nicolas Pitre
|
||||
*
|
||||
@@ -14,7 +14,7 @@ struct uart_port;
|
||||
* This is a temporary structure for registering these
|
||||
* functions; it is intended to be discarded after boot.
|
||||
*/
|
||||
struct at91rm9200_port_fns {
|
||||
struct at91_port_fns {
|
||||
void (*set_mctrl)(struct uart_port *, u_int);
|
||||
u_int (*get_mctrl)(struct uart_port *);
|
||||
void (*enable_ms)(struct uart_port *);
|
||||
@@ -25,11 +25,9 @@ struct at91rm9200_port_fns {
|
||||
};
|
||||
|
||||
#if defined(CONFIG_SERIAL_AT91)
|
||||
void at91_register_uart_fns(struct at91rm9200_port_fns *fns);
|
||||
void at91_register_uart(int idx, int port);
|
||||
void at91_register_uart_fns(struct at91_port_fns *fns);
|
||||
#else
|
||||
#define at91_register_uart_fns(fns) do { } while (0)
|
||||
#define at91_register_uart(idx,port) do { } while (0)
|
||||
#endif
|
||||
|
||||
|
||||
@@ -107,6 +107,9 @@ extern void __show_regs(struct pt_regs *);
|
||||
extern int cpu_architecture(void);
|
||||
extern void cpu_init(void);
|
||||
|
||||
void arm_machine_restart(char mode);
|
||||
extern void (*arm_pm_restart)(char str);
|
||||
|
||||
/*
|
||||
* Intel's XScale3 core supports some v6 features (supersections, L2)
|
||||
* but advertises itself as v5 as it does not support the v6 ISA. For
|
||||
|
||||
@@ -67,8 +67,8 @@
|
||||
/* Parisc type numbers. */
|
||||
#define PORT_MUX 48
|
||||
|
||||
/* Atmel AT91RM9200 SoC */
|
||||
#define PORT_AT91RM9200 49
|
||||
/* Atmel AT91xxx SoC */
|
||||
#define PORT_AT91 49
|
||||
|
||||
/* Macintosh Zilog type numbers */
|
||||
#define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
|
||||
|
||||
Reference in New Issue
Block a user