From 0394419db583f485a0e6b9ddcfcb296de948b810 Mon Sep 17 00:00:00 2001
From: azkali <a.ffcc7@gmail.com>
Date: Mon, 28 Aug 2023 13:25:09 +0200
Subject: [PATCH] panel: dsi-nx: Add dsi-nx panel driver

dsi-nx is a new blanket driver for panels on the Nintendo Switch.
The Switch boots Linux via the "hekate" custom bootloader, which
performs panel initialization and passes panel info to kernel.

This driver is based on panel-jdi-lpm062m326a by SwitchR.
---
 drivers/gpu/drm/panel/Kconfig        |   9 +
 drivers/gpu/drm/panel/Makefile       |   1 +
 drivers/gpu/drm/panel/panel-nx-dsi.c | 767 +++++++++++++++++++++++++++
 3 files changed, 777 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-nx-dsi.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index fff7535d186a..c95a92f1a1e2 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -282,6 +282,15 @@ config DRM_PANEL_JDI_LPM102A188A
 	  The panel has a 2560×1800 resolution. It provides a MIPI DSI interface
 	  to the host.
 
+config DRM_PANEL_NX_DSI
+	tristate "Nintendo Switch 720x1280 DSI panel"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y here if you want to enable support for the DSI panels
+	  used in the Nintendo Switch.
+
 config DRM_PANEL_JDI_LT070ME05000
 	tristate "JDI LT070ME05000 WUXGA DSI panel"
 	depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 495873236f81..a2446f511910 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o
 obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672A) += panel-novatek-nt36672a.o
 obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672E) += panel-novatek-nt36672e.o
 obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o
+obj-$(CONFIG_DRM_PANEL_NX_DSI) += panel-nx-dsi.o
 obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) += panel-mantix-mlaf057we51.o
 obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o
 obj-$(CONFIG_DRM_PANEL_ORISETECH_OTA5601A) += panel-orisetech-ota5601a.o
diff --git a/drivers/gpu/drm/panel/panel-nx-dsi.c b/drivers/gpu/drm/panel/panel-nx-dsi.c
new file mode 100644
index 000000000000..4d6cdf8d4e0a
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-nx-dsi.c
@@ -0,0 +1,767 @@
+/*
+ * Copyright (C) 2018 SwtcR <swtcr0@gmail.com>
+ * Copyright (C) 2023-2024 Azkali <a.ffcc7@gmail.com>
+ *
+ * Based on Sharp ls043t1le01 panel driver by Werner Johansson <werner.johansson@sonymobile.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_modes.h>
+
+/*! MIPI DCS Panel Private CMDs. */
+#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE 0xA0
+#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET 0xB0
+#define MIPI_DCS_PRIV_SM_SET_ELVSS \
+	0xB1 // OLED backlight tuning. Byte7: PWM transition time in frames.
+#define MIPI_DCS_PRIV_SET_POWER_CONTROL 0xB1
+#define MIPI_DCS_PRIV_SET_EXTC 0xB9 // Enable extended commands.
+#define MIPI_DCS_PRIV_UNK_BD 0xBD
+#define MIPI_DCS_PRIV_UNK_D5 0xD5
+#define MIPI_DCS_PRIV_UNK_D6 0xD6
+#define MIPI_DCS_PRIV_UNK_D8 0xD8
+#define MIPI_DCS_PRIV_UNK_D9 0xD9
+
+#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK 0xE2
+
+// BL Control
+#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT   BIT(2)
+#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL  BIT(2)
+#define DCS_CONTROL_DISPLAY_DIMMING_CTRL    BIT(3)
+#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5)
+
+// OLED Panels color mode
+#define DCS_SM_COLOR_MODE_SATURATED 0x00 // Disabled. Similar to vivid but over-saturated. Wide gamut?
+#define DCS_SM_COLOR_MODE_WASHED    0x45
+#define DCS_SM_COLOR_MODE_BASIC     0x03
+#define DCS_SM_COLOR_MODE_POR_RESET 0x20 // Reset value on power on.
+#define DCS_SM_COLOR_MODE_NATURAL   0x23 // Not actually natural..
+#define DCS_SM_COLOR_MODE_VIVID     0x65
+#define DCS_SM_COLOR_MODE_NIGHT0    0x43 // Based on washed out.
+#define DCS_SM_COLOR_MODE_NIGHT1    0x15 // Based on basic.
+#define DCS_SM_COLOR_MODE_NIGHT2    0x35 // Based on natural.
+#define DCS_SM_COLOR_MODE_NIGHT3    0x75 // Based on vivid.
+
+#define DCS_SM_COLOR_MODE_ENABLE    BIT(0)
+
+enum
+{
+	PANEL_JDI_XXX062M     = 0x10,
+	PANEL_JDI_LAM062M109A = 0x0910,
+	PANEL_JDI_LPM062M326A = 0x2610,
+	PANEL_INL_P062CCA_AZ1 = 0x0F20,
+	PANEL_AUO_A062TAN01   = 0x0F30,
+	PANEL_INL_2J055IA_27A = 0x1020,
+	PANEL_AUO_A055TAN01   = 0x1030,
+	PANEL_SHP_LQ055T1SW10 = 0x1040,
+	PANEL_SAM_AMS699VC01  = 0x2050,
+	PANEL_RR_SUPER5_OLED_V1  = 0x10E0,
+	PANEL_RR_SUPER5_OLED_HD_V1  = 0x10E1,
+	PANEL_RR_SUPER7_IPS_V1  = 0x0FE0,
+	PANEL_RR_SUPER7_IPS_HD_V1  = 0x0FE1,
+	PANEL_RR_SUPER7_OLED_7_V1  = 0x20E0,
+	PANEL_RR_SUPER7_OLED_HD_7_V1  = 0x20E1,
+
+	// Found on 6/2" clones. Unknown markings. Quality seems JDI like. Has bad low backlight scaling. ID: [83] 94 [0F].
+	PANEL_OEM_CLONE_6_2   = 0x0F83,
+	// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
+	PANEL_OEM_CLONE_5_5   = 0x00B3,
+	// Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings.
+	PANEL_OEM_CLONE       = 0x0000
+};
+
+struct init_cmd {
+	u8 cmd;
+	int length;
+	u8 data[64];
+};
+
+struct nx_panel {
+	struct drm_panel base;
+	struct mipi_dsi_device *dsi;
+
+	struct backlight_device *backlight;
+	struct regulator *supply1;
+	struct regulator *supply2;
+	struct gpio_desc *reset_gpio;
+
+	bool prepared;
+	bool enabled;
+
+	const struct drm_display_mode *mode;
+
+	struct init_cmd *init_cmds;
+	struct init_cmd *suspend_cmds;
+
+	u8 display_id[3];
+};
+
+struct init_cmd init_cmds_default[] = {
+	{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		120,
+	},
+};
+
+struct init_cmd init_cmds_PANEL_JDI_XXX062M[] = {
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
+	{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x00, 0x0 } },
+	{ MIPI_DCS_PRIV_UNK_D8, 24, { 0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA,
+				      0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA,
+				      0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA,
+				      0xAA, 0xAA, 0xAA, 0xEB, 0xAA, 0xAA } },
+	{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x01, 0x0 } },
+	{ MIPI_DCS_PRIV_UNK_D8,
+	  38,
+	  { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } },
+	{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x02, 0x0 } },
+	{ MIPI_DCS_PRIV_UNK_D8,
+	  14,
+	  { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	    0xFF, 0xFF, 0xFF } },
+	{ MIPI_DCS_PRIV_UNK_BD, 2, { 0x00, 0x00 } },
+	{ MIPI_DCS_PRIV_UNK_D9, 2, { 0x06, 0x0 } },
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0x00, 0x00, 0x00 } },
+	{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		180,
+	},
+	{ MIPI_DCS_SET_DISPLAY_ON, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		20,
+	},
+	{ MIPI_DCS_NOP, -1, { 0x00 } },
+};
+
+struct init_cmd suspend_cmds_PANEL_JDI_XXX062M[] = {
+	{ MIPI_DCS_SET_DISPLAY_OFF, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		50,
+	},
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
+	{ MIPI_DCS_PRIV_UNK_D5,
+	  32,
+	  { 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
+	    0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
+	    0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19 } },
+	{ MIPI_DCS_PRIV_SET_POWER_CONTROL,
+	  10,
+	  { 0x41, 0x0F, 0x4F, 0x33, 0xA4, 0x79, 0xF1, 0x81, 0x2D, 0x00 } },
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0x00, 0x00, 0x00 } },
+	{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		50,
+	},
+	{ MIPI_DCS_NOP, -1, { 0x00 } },
+};
+
+struct init_cmd init_cmds_PANEL_SAM_AMS699VC01[] = {
+	{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		180,
+	},
+
+	// Set color mode to basic (natural). Stock is Saturated (0x00). (Reset value is 0x20).
+	{ MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_BASIC << 8), 2, { 0x00, 0x0 } },
+
+	// Enable backlight and smooth PWM.
+	{ MIPI_DCS_WRITE_CONTROL_DISPLAY | ((DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL | DCS_CONTROL_DISPLAY_DIMMING_CTRL) << 8), 2, { 0x00, 0x0 } },
+
+	// Unlock Level 2 registers.
+	{ MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0x5A, 0x5A, 0x0 } },
+
+	// Set registers offset and set PWM transition to 6 frames (100ms).
+	{ MIPI_DCS_PRIV_SM_SET_REG_OFFSET | (7 << 8), 2, { 0x00, 0x0 } },
+	{ MIPI_DCS_PRIV_SM_SET_ELVSS      | (6 << 8), 2, { 0x00, 0x0 } },
+
+	// Relock Level 2 registers.
+	{ MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0xA5, 0xA5, 0x0 } },
+
+	// MIPI_DCS_SET_BRIGHTNESS 0000: 0%. FF07: 100%.
+	{ MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 3, { 0x00, 0x00, 0x0 } },
+
+	{
+		0xFF,
+		5,
+	},
+};
+
+struct init_cmd init_cmds_PANEL_AUO_A062TAN01[] = {
+	{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		180,
+	},
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 6, { 0x48, 0x11, 0x71, 0x09, 0x32, 0x14 } },
+};
+
+struct init_cmd suspend_cmds_PANEL_AUO_A062TAN01[] = {
+	{
+		0xFF,
+		100,
+	},
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		50,
+	},
+};
+
+struct init_cmd suspend_cmds_PANEL_AUO_A055TAN01[] = {
+	{
+		0xFF,
+		100,
+	},
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 10, { 0x48, 0x11, 0x71, 0x09, 0x32, 0x14, 0x71, 0x31, 0x4D, 0x11 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		50,
+	},
+};
+
+struct init_cmd init_cmds_PANEL_INL_P062CCA_AZ1[] = {
+	{ MIPI_DCS_EXIT_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		180,
+	},
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 6, { 0x48, 0x15, 0x75, 0x09, 0x32, 0x14 } },
+
+};
+
+struct init_cmd suspend_cmds_PANEL_INL_2J055IA_27A[] = {
+	{
+		0xFF,
+		100,
+	},
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 10, { 0x48, 0x15, 0x75, 0x09, 0x32, 0x14, 0x71, 0x31, 0x4D, 0x11 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		50,
+	},
+};
+
+struct init_cmd suspend_cmds_PANEL_SHP_LQ055T1SW10[] = {
+	{
+		0xFF,
+		100,
+	},
+	{ MIPI_DCS_PRIV_SET_EXTC, 3, { 0xFF, 0x83, 0x94 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_PRIV_SET_POWER_CONTROL, 10, { 0x48, 0x13, 0x73, 0x09, 0x32, 0x24, 0x71, 0x31, 0x4C, 0x00 } },
+	{
+		0xFF,
+		5,
+	},
+	{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		50,
+	},
+};
+
+struct init_cmd suspend_cmds_PANEL_SAM_AMS699VC01[] = {
+	{
+		0xFF,
+		100,
+	},
+	{ MIPI_DCS_ENTER_SLEEP_MODE, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		120,
+	},
+};
+
+static inline struct nx_panel *to_nx_panel(struct drm_panel *panel)
+{
+	return container_of(panel, struct nx_panel, base);
+}
+
+static void nx_panel_detect(struct nx_panel *jdi)
+{
+	int ret;
+	jdi->init_cmds = NULL;
+	jdi->suspend_cmds = NULL;
+
+	memset(jdi->display_id, 0, sizeof(jdi->display_id));
+
+	ret = mipi_dsi_dcs_read(jdi->dsi, MIPI_DCS_GET_DISPLAY_ID,
+				jdi->display_id, sizeof(jdi->display_id));
+	if (ret < 0) {
+		dev_err(&jdi->dsi->dev, "failed to read panel ID: %d\n", ret);
+	} else {
+		dev_info(&jdi->dsi->dev, "display ID[%d]: %02x %02x %02x\n",
+			 ret, jdi->display_id[0], jdi->display_id[1],
+			 jdi->display_id[2]);
+	}
+
+	dev_info(&jdi->dsi->dev,
+		 "setting init sequence for ID %02x\n", jdi->display_id[0]);
+
+	switch (jdi->display_id[0]) {
+	case PANEL_JDI_XXX062M:
+		jdi->init_cmds = init_cmds_PANEL_JDI_XXX062M;
+		break;
+	case PANEL_SAM_AMS699VC01:
+		jdi->init_cmds = init_cmds_PANEL_SAM_AMS699VC01;
+		break;
+	case PANEL_INL_P062CCA_AZ1:
+		jdi->init_cmds = init_cmds_PANEL_INL_P062CCA_AZ1;
+		break;
+	case PANEL_AUO_A062TAN01:
+		jdi->init_cmds = init_cmds_PANEL_AUO_A062TAN01;
+		break;
+	case PANEL_INL_2J055IA_27A:
+	case PANEL_AUO_A055TAN01:
+	case PANEL_SHP_LQ055T1SW10:
+	default:
+		dev_info(&jdi->dsi->dev, "using default init sequence\n");
+		jdi->init_cmds = init_cmds_default;
+		break;
+	}
+
+	dev_info(&jdi->dsi->dev,
+		"setting suspend sequence for ID %02x\n", jdi->display_id[0]);
+
+	switch (jdi->display_id[0]) {
+	case PANEL_JDI_XXX062M:
+		jdi->suspend_cmds = suspend_cmds_PANEL_JDI_XXX062M;
+		break;
+	case PANEL_AUO_A062TAN01:
+		jdi->suspend_cmds = suspend_cmds_PANEL_AUO_A062TAN01;
+		break;
+	case PANEL_INL_2J055IA_27A:
+		jdi->suspend_cmds = suspend_cmds_PANEL_INL_2J055IA_27A;
+		break;
+	case PANEL_AUO_A055TAN01:
+		jdi->suspend_cmds = suspend_cmds_PANEL_AUO_A055TAN01;
+		break;
+	case PANEL_SHP_LQ055T1SW10:
+		jdi->suspend_cmds = suspend_cmds_PANEL_SHP_LQ055T1SW10;
+		break;
+	case PANEL_SAM_AMS699VC01:
+		jdi->suspend_cmds = suspend_cmds_PANEL_SAM_AMS699VC01;
+		break;
+	case PANEL_INL_P062CCA_AZ1:
+	default:
+		dev_info(&jdi->dsi->dev, "using default suspend sequence\n");
+		break;
+	}
+
+	msleep(20);
+}
+
+static int jdi_mipi_dsi_dcs_cmds(struct init_cmd *cmds, struct nx_panel *jdi)
+{
+	int ret = 0;
+
+	while (cmds && cmds->length != -1) {
+		if (cmds->cmd == 0xFF)
+			msleep(cmds->length);
+		else {
+			ret = mipi_dsi_dcs_write(jdi->dsi, cmds->cmd,
+						 cmds->data, cmds->length);
+			if (ret < 0) {
+				dev_err(&jdi->dsi->dev,
+					"failed to write dsi_cmd: %d error: %d\n",
+					cmds->cmd, ret);
+				return ret;
+			}
+		}
+		cmds++;
+	}
+
+	return ret;
+}
+
+static int nx_panel_init(struct nx_panel *jdi)
+{
+	struct mipi_dsi_device *dsi = jdi->dsi;
+	struct device *dev = &jdi->dsi->dev;
+	int ret;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	ret = mipi_dsi_set_maximum_return_packet_size(dsi, 3);
+	if (ret < 0) {
+		dev_err(dev, "failed to set maximum return packet size: %d\n",
+			ret);
+		return ret;
+	}
+
+	nx_panel_detect(jdi);
+
+	ret = jdi_mipi_dsi_dcs_cmds(jdi->init_cmds, jdi);
+	if (ret < 0)
+		return ret;
+
+	ret = mipi_dsi_dcs_set_column_address(dsi, 0, jdi->mode->hdisplay - 1);
+	if (ret < 0) {
+		dev_err(dev, "failed to set page address: %d\n", ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_page_address(dsi, 0, jdi->mode->vdisplay - 1);
+	if (ret < 0) {
+		dev_err(dev, "failed to set column address: %d\n", ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret < 0) {
+		dev_err(dev, "failed to set vblank tear on: %d\n", ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT);
+	if (ret < 0) {
+		dev_err(dev, "failed to set pixel format: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int nx_panel_enable(struct drm_panel *panel)
+{
+	struct nx_panel *jdi = to_nx_panel(panel);
+
+	if (jdi->enabled)
+		return 0;
+
+	backlight_enable(jdi->backlight);
+
+	jdi->enabled = true;
+
+	return 0;
+}
+
+static int nx_panel_disable(struct drm_panel *panel)
+{
+	struct nx_panel *jdi = to_nx_panel(panel);
+
+	if (!jdi->enabled)
+		return 0;
+
+	backlight_disable(jdi->backlight);
+
+	jdi->enabled = false;
+
+	return 0;
+}
+
+static int nx_panel_unprepare(struct drm_panel *panel)
+{
+	struct nx_panel *jdi = to_nx_panel(panel);
+	int ret;
+
+	if (!jdi->prepared)
+		return 0;
+
+	jdi->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+	ret = jdi_mipi_dsi_dcs_cmds(jdi->suspend_cmds, jdi);
+	if (ret < 0)
+		dev_err(&jdi->dsi->dev, "failed to write suspend cmds: %d\n",
+			ret);
+
+	if (jdi->reset_gpio)
+		gpiod_set_value(jdi->reset_gpio, 0);
+
+	msleep(10);
+	regulator_disable(jdi->supply2);
+	msleep(10);
+	regulator_disable(jdi->supply1);
+
+	jdi->prepared = false;
+
+	return 0;
+}
+
+static int nx_panel_prepare(struct drm_panel *panel)
+{
+	struct nx_panel *jdi = to_nx_panel(panel);
+	struct device *dev = &jdi->dsi->dev;
+	int ret;
+
+	if (jdi->prepared)
+		return 0;
+
+	ret = regulator_enable(jdi->supply1);
+	if (ret < 0)
+		return ret;
+	msleep(10);
+
+	ret = regulator_enable(jdi->supply2);
+	if (ret < 0)
+		goto poweroff;
+	msleep(10);
+
+	if (jdi->reset_gpio) {
+		gpiod_set_value(jdi->reset_gpio, 0);
+		msleep(10);
+		gpiod_set_value(jdi->reset_gpio, 1);
+		msleep(60);
+	}
+	jdi->dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	ret = nx_panel_init(jdi);
+	if (ret < 0) {
+		dev_err(dev, "failed to init panel: %d\n", ret);
+		goto reset;
+	}
+
+	jdi->prepared = true;
+
+	return 0;
+
+reset:
+	if (jdi->reset_gpio)
+		gpiod_set_value(jdi->reset_gpio, 0);
+	regulator_disable(jdi->supply2);
+
+poweroff:
+	regulator_disable(jdi->supply1);
+	return ret;
+}
+
+static const struct drm_display_mode default_mode = {
+	.clock = 78000,
+	.hdisplay = 720,
+	.hsync_start = 720 + 136,
+	.hsync_end = 720 + 136 + 72,
+	.htotal = 720 + 136 + 72 + 72,
+	.vdisplay = 1280,
+	.vsync_start = 1280 + 10,
+	.vsync_end = 1280 + 10 + 2,
+	.vtotal = 1280 + 10 + 1 + 9,
+	.width_mm = 77,
+	.height_mm = 137,
+};
+
+static int nx_panel_get_modes(struct drm_panel *panel,
+			       struct drm_connector *connector)
+{
+	struct drm_display_mode *mode;
+	struct nx_panel *jdi = to_nx_panel(panel);
+	struct device *dev = &jdi->dsi->dev;
+
+	mode = drm_mode_duplicate(connector->dev, &default_mode);
+	if (!mode) {
+		dev_err(dev, "failed to add mode %ux%ux@%u\n",
+			default_mode.hdisplay, default_mode.vdisplay,
+			drm_mode_vrefresh(&default_mode));
+		return -ENOMEM;
+	}
+
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(connector, mode);
+
+	connector->display_info.width_mm = default_mode.width_mm;
+	connector->display_info.height_mm = default_mode.height_mm;
+
+	return 1;
+}
+
+static const struct drm_panel_funcs nx_panel_funcs = {
+	.prepare = nx_panel_prepare,
+	.unprepare = nx_panel_unprepare,
+	.enable = nx_panel_enable,
+	.disable = nx_panel_disable,
+	.get_modes = nx_panel_get_modes,
+};
+
+static int nx_panel_add(struct nx_panel *jdi)
+{
+	struct device *dev = &jdi->dsi->dev;
+	struct device_node *np;
+
+	jdi->mode = &default_mode;
+
+	jdi->supply1 = devm_regulator_get(dev, "vdd1");
+	if (IS_ERR(jdi->supply1))
+		return PTR_ERR(jdi->supply1);
+
+	jdi->supply2 = devm_regulator_get(dev, "vdd2");
+	if (IS_ERR(jdi->supply2))
+		return PTR_ERR(jdi->supply2);
+
+	jdi->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+	if (IS_ERR(jdi->reset_gpio)) {
+		dev_err(dev, "cannot get reset-gpios %ld\n",
+			PTR_ERR(jdi->reset_gpio));
+		jdi->reset_gpio = NULL;
+	} else {
+		gpiod_set_value(jdi->reset_gpio, 0);
+	}
+
+	np = of_parse_phandle(dev->of_node, "backlight", 0);
+	if (np) {
+		jdi->backlight = of_find_backlight_by_node(np);
+		of_node_put(np);
+
+		if (!jdi->backlight)
+			return -EPROBE_DEFER;
+	}
+
+	drm_panel_init(&jdi->base, &jdi->dsi->dev, &nx_panel_funcs,
+		       DRM_MODE_CONNECTOR_DSI);
+
+	drm_panel_add(&jdi->base);
+
+	return 0;
+}
+
+static void nx_panel_del(struct nx_panel *jdi)
+{
+	if (jdi->base.dev)
+		drm_panel_remove(&jdi->base);
+
+	if (jdi->backlight)
+		put_device(&jdi->backlight->dev);
+}
+
+static int nx_panel_probe(struct mipi_dsi_device *dsi)
+{
+	struct nx_panel *jdi;
+	int ret;
+
+	dsi->lanes = 4;
+	dsi->format = MIPI_DSI_FMT_RGB888;
+	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
+			  MIPI_DSI_CLOCK_NON_CONTINUOUS |
+			  MIPI_DSI_MODE_NO_EOT_PACKET;
+
+	jdi = devm_kzalloc(&dsi->dev, sizeof(*jdi), GFP_KERNEL);
+	if (!jdi)
+		return -ENOMEM;
+
+	mipi_dsi_set_drvdata(dsi, jdi);
+
+	jdi->dsi = dsi;
+
+	ret = nx_panel_add(jdi);
+	if (ret < 0)
+		return ret;
+
+	ret = mipi_dsi_attach(dsi);
+	if (ret < 0) {
+		nx_panel_del(jdi);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void nx_panel_remove(struct mipi_dsi_device *dsi)
+{
+	struct nx_panel *jdi = mipi_dsi_get_drvdata(dsi);
+	int ret;
+
+	ret = nx_panel_disable(&jdi->base);
+	if (ret < 0)
+		dev_err(&dsi->dev, "failed to disable panel: %d\n", ret);
+
+	ret = mipi_dsi_detach(dsi);
+	if (ret < 0)
+		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
+
+	nx_panel_del(jdi);
+}
+
+static void nx_panel_shutdown(struct mipi_dsi_device *dsi)
+{
+	struct nx_panel *jdi = mipi_dsi_get_drvdata(dsi);
+	nx_panel_disable(&jdi->base);
+}
+
+static const struct of_device_id jdi_of_match[] = {
+	{
+		.compatible = "nintendo,panel-nx-dsi",
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jdi_of_match);
+
+static struct mipi_dsi_driver nx_panel_driver = {
+	.driver = {
+		.name = "panel-nx-dsi",
+		.of_match_table = jdi_of_match,
+	},
+	.probe = nx_panel_probe,
+	.remove = nx_panel_remove,
+	.shutdown = nx_panel_shutdown,
+};
+module_mipi_dsi_driver(nx_panel_driver);
+
+MODULE_AUTHOR("SwtcR <swtcr0@gmail.com>");
+MODULE_DESCRIPTION("Nintendo Switch DSI (720x1280) panel driver");
+MODULE_LICENSE("GPL v2");