drm/i915: Shortcut readiness to reset check
If the engine says it is ready for reset, it is ready so avoid further dancing and proceed. v2: reg (Chris) v3: request, ack, mask from following patch (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190412165335.16347-1-mika.kuoppala@linux.intel.com
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committed by
Chris Wilson
parent
e5604e2fb6
commit
019d26004e
@@ -490,20 +490,26 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
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static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
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static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
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{
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{
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struct intel_uncore *uncore = engine->uncore;
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struct intel_uncore *uncore = engine->uncore;
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const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
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u32 request, mask, ack;
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int ret;
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int ret;
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intel_uncore_write_fw(uncore,
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ack = intel_uncore_read_fw(uncore, reg);
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RING_RESET_CTL(engine->mmio_base),
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if (!(ack & RESET_CTL_READY_TO_RESET)) {
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_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
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request = RESET_CTL_REQUEST_RESET;
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mask = RESET_CTL_READY_TO_RESET;
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ack = RESET_CTL_READY_TO_RESET;
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} else {
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return 0;
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}
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ret = __intel_wait_for_register_fw(uncore,
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intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
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RING_RESET_CTL(engine->mmio_base),
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ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
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RESET_CTL_READY_TO_RESET,
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700, 0, NULL);
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RESET_CTL_READY_TO_RESET,
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700, 0,
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NULL);
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if (ret)
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if (ret)
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DRM_ERROR("%s: reset request timeout\n", engine->name);
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DRM_ERROR("%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
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engine->name, request,
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intel_uncore_read_fw(uncore, reg));
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return ret;
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return ret;
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}
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}
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