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Merge 5901037324 ("Merge tag 'for-linus' of https://github.com/openrisc/linux") into android-mainline

Browse Source 
Steps on the way to 6.10-rc1

Change-Id: Ief35eb5990650571b9392125774142343f7c5500
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Signed-off-by: André Draszik <draszik@google.com>
This commit is contained in:
Greg Kroah-Hartman
2024-07-16 17:14:19 +00:00
committed by André Draszik
parent 13adfbfa04 5901037324
commit 016426d5af
362 changed files with 7621 additions and 2825 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/admin-guide/kernel-parameters.txt
+5
View File
@@ -431,6 +431,9 @@
arcrimi= [HW,NET] ARCnet - "RIM I" (entirely mem-mapped) cards
Format: <io>,<irq>,<nodeID>
arm64.no32bit_el0 [ARM64] Unconditionally disable the execution of
32 bit applications.
arm64.nobti [ARM64] Unconditionally disable Branch Target
Identification support
@@ -2255,6 +2258,8 @@
no_x2apic_optout
BIOS x2APIC opt-out request will be ignored
nopost disable Interrupt Posting
posted_msi
enable MSIs delivered as posted interrupts
iomem= Disable strict checking of access to MMIO memory
strict regions from userspace.
Documentation/admin-guide/perf/hisi-pmu.rst
-1
View File
@@ -20,7 +20,6 @@ interrupt, and the PMU driver shall register perf PMU drivers like L3C,
HHA and DDRC etc. The available events and configuration options shall
be described in the sysfs, see:
/sys/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>/, or
/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>.
The "perf list" command shall list the available events from sysfs.
Documentation/admin-guide/perf/hns3-pmu.rst
+4 -4
View File
@@ -16,7 +16,7 @@ HNS3 PMU driver
The HNS3 PMU driver registers a perf PMU with the name of its sicl id.::
/sys/devices/hns3_pmu_sicl_<sicl_id>
/sys/bus/event_source/devices/hns3_pmu_sicl_<sicl_id>
PMU driver provides description of available events, filter modes, format,
identifier and cpumask in sysfs.
@@ -40,9 +40,9 @@ device.
Example usage of checking event code and subevent code::
$# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_time
$# cat /sys/bus/event_source/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_time
config=0x00204
$# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_packet_num
$# cat /sys/bus/event_source/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_packet_num
config=0x10204
Each performance statistic has a pair of events to get two values to
@@ -60,7 +60,7 @@ computation to calculate real performance data is:::
Example usage of checking supported filter mode::
$# cat /sys/devices/hns3_pmu_sicl_0/filtermode/bw_ssu_rpu_byte_num
$# cat /sys/bus/event_source/devices/hns3_pmu_sicl_0/filtermode/bw_ssu_rpu_byte_num
filter mode supported: global/port/port-tc/func/func-queue/
Example usage of perf::
Documentation/admin-guide/perf/qcom_l2_pmu.rst
+1 -1
View File
@@ -10,7 +10,7 @@ There is one logical L2 PMU exposed, which aggregates the results from
the physical PMUs.
The driver provides a description of its available events and configuration
options in sysfs, see /sys/devices/l2cache_0.
options in sysfs, see /sys/bus/event_source/devices/l2cache_0.
The "format" directory describes the format of the events.
Documentation/admin-guide/perf/qcom_l3_pmu.rst
+1 -1
View File
@@ -9,7 +9,7 @@ PMU with device name l3cache_<socket>_<instance>. User space is responsible
for aggregating across slices.
The driver provides a description of its available events and configuration
options in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs
options in sysfs, see /sys/bus/event_source/devices/l3cache*. Given that these are uncore PMUs
the driver also exposes a "cpumask" sysfs attribute which contains a mask
consisting of one CPU per socket which will be used to handle all the PMU
events on that socket.
Documentation/admin-guide/perf/thunderx2-pmu.rst
+1 -1
View File
@@ -22,7 +22,7 @@ The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
(CCPI2) events simultaneously. The PMUs provide a description of their
available events and configuration options under sysfs, see
/sys/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
/sys/bus/event_source/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
The driver does not support sampling, therefore "perf record" will not
work. Per-task perf sessions are also not supported.
Documentation/admin-guide/perf/xgene-pmu.rst
+1 -1
View File
@@ -13,7 +13,7 @@ PMU (perf) driver
The xgene-pmu driver registers several perf PMU drivers. Each of the perf
driver provides description of its available events and configuration options
in sysfs, see /sys/devices/<l3cX/iobX/mcbX/mcX>/.
in sysfs, see /sys/bus/event_source/devices/<l3cX/iobX/mcbX/mcX>/.
The "format" directory describes format of the config (event ID),
config1 (agent ID) fields of the perf_event_attr structure. The "events"
Documentation/arch/x86/resctrl.rst
+6
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@@ -446,6 +446,12 @@ during mkdir.
max_threshold_occupancy is a user configurable value to determine the
occupancy at which an RMID can be freed.
The mon_llc_occupancy_limbo tracepoint gives the precise occupancy in bytes
for a subset of RMID that are not immediately available for allocation.
This can't be relied on to produce output every second, it may be necessary
to attempt to create an empty monitor group to force an update. Output may
only be produced if creation of a control or monitor group fails.
Schemata files - general concepts
---------------------------------
Each line in the file describes one resource. The line starts with
Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+172
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@@ -0,0 +1,172 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
maintainers:
- Anup Patel <anup@brainfault.org>
description:
The RISC-V advanced interrupt architecture (AIA) defines an advanced
platform level interrupt controller (APLIC) for handling wired interrupts
in a RISC-V platform. The RISC-V AIA specification can be found at
https://github.com/riscv/riscv-aia.
The RISC-V APLIC is implemented as hierarchical APLIC domains where all
interrupt sources connect to the root APLIC domain and a parent APLIC
domain can delegate interrupt sources to it's child APLIC domains. There
is one device tree node for each APLIC domain.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
items:
- enum:
- qemu,aplic
- const: riscv,aplic
reg:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
interrupts-extended:
minItems: 1
maxItems: 16384
description:
Given APLIC domain directly injects external interrupts to a set of
RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
node, which has a CPU node (i.e. RISC-V HART) as parent.
msi-parent:
description:
Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
message signaled interrupt controller (IMSIC). If both "msi-parent" and
"interrupts-extended" properties are present then it means the APLIC
domain supports both MSI mode and Direct mode in HW. In this case, the
APLIC driver has to choose between MSI mode or Direct mode.
riscv,num-sources:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 1023
description:
Specifies the number of wired interrupt sources supported by this
APLIC domain.
riscv,children:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 1024
items:
maxItems: 1
description:
A list of child APLIC domains for the given APLIC domain. Each child
APLIC domain is assigned a child index in increasing order, with the
first child APLIC domain assigned child index 0. The APLIC domain child
index is used by firmware to delegate interrupts from the given APLIC
domain to a particular child APLIC domain.
riscv,delegation:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 1024
items:
items:
- description: child APLIC domain phandle
- description: first interrupt number of the parent APLIC domain (inclusive)
- description: last interrupt number of the parent APLIC domain (inclusive)
description:
A interrupt delegation list where each entry is a triple consisting
of child APLIC domain phandle, first interrupt number of the parent
APLIC domain, and last interrupt number of the parent APLIC domain.
Firmware must configure interrupt delegation registers based on
interrupt delegation list.
dependencies:
riscv,delegation: [ "riscv,children" ]
required:
- compatible
- reg
- interrupt-controller
- "#interrupt-cells"
- riscv,num-sources
anyOf:
- required:
- interrupts-extended
- required:
- msi-parent
unevaluatedProperties: false
examples:
- |
// Example 1 (APLIC domains directly injecting interrupt to HARTs):
interrupt-controller@c000000 {
compatible = "qemu,aplic", "riscv,aplic";
interrupts-extended = <&cpu1_intc 11>,
<&cpu2_intc 11>,
<&cpu3_intc 11>,
<&cpu4_intc 11>;
reg = <0xc000000 0x4080>;
interrupt-controller;
#interrupt-cells = <2>;
riscv,num-sources = <63>;
riscv,children = <&aplic1>, <&aplic2>;
riscv,delegation = <&aplic1 1 63>;
};
aplic1: interrupt-controller@d000000 {
compatible = "qemu,aplic", "riscv,aplic";
interrupts-extended = <&cpu1_intc 9>,
<&cpu2_intc 9>;
reg = <0xd000000 0x4080>;
interrupt-controller;
#interrupt-cells = <2>;
riscv,num-sources = <63>;
};
aplic2: interrupt-controller@e000000 {
compatible = "qemu,aplic", "riscv,aplic";
interrupts-extended = <&cpu3_intc 9>,
<&cpu4_intc 9>;
reg = <0xe000000 0x4080>;
interrupt-controller;
#interrupt-cells = <2>;
riscv,num-sources = <63>;
};
- |
// Example 2 (APLIC domains forwarding interrupts as MSIs):
interrupt-controller@c000000 {
compatible = "qemu,aplic", "riscv,aplic";
msi-parent = <&imsic_mlevel>;
reg = <0xc000000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
riscv,num-sources = <63>;
riscv,children = <&aplic3>;
riscv,delegation = <&aplic3 1 63>;
};
aplic3: interrupt-controller@d000000 {
compatible = "qemu,aplic", "riscv,aplic";
msi-parent = <&imsic_slevel>;
reg = <0xd000000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
riscv,num-sources = <63>;
};
...
Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+172
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@@ -0,0 +1,172 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: RISC-V Incoming MSI Controller (IMSIC)
maintainers:
- Anup Patel <anup@brainfault.org>
description: |
The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming
MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
AIA specification can be found at https://github.com/riscv/riscv-aia.
The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
for each privilege level (machine or supervisor). The configuration of
a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
space to receive MSIs from devices. Each IMSIC interrupt file supports a
fixed number of interrupt identities (to distinguish MSIs from devices)
which is same for given privilege level across CPUs (or HARTs).
The device tree of a RISC-V platform will have one IMSIC device tree node
for each privilege level (machine or supervisor) which collectively describe
IMSIC interrupt files at that privilege level across CPUs (or HARTs).
The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
group is a set of IMSIC interrupt files co-located in MMIO space and we can
have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a
RISC-V platform. The MSI target address of a IMSIC interrupt file at given
privilege level (machine or supervisor) encodes group index, HART index,
and guest index (shown below).
XLEN-1 > (HART Index MSB) 12 0
| | | |
-------------------------------------------------------------
|xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
-------------------------------------------------------------
allOf:
- $ref: /schemas/interrupt-controller.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:
compatible:
items:
- enum:
- qemu,imsics
- const: riscv,imsics
reg:
minItems: 1
maxItems: 16384
description:
Base address of each IMSIC group.
interrupt-controller: true
"#interrupt-cells":
const: 0
msi-controller: true
"#msi-cells":
const: 0
interrupts-extended:
minItems: 1
maxItems: 16384
description:
This property represents the set of CPUs (or HARTs) for which given
device tree node describes the IMSIC interrupt files. Each node pointed
to should be a riscv,cpu-intc node, which has a CPU node (i.e. RISC-V
HART) as parent.
riscv,num-ids:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 63
maximum: 2047
description:
Number of interrupt identities supported by IMSIC interrupt file.
riscv,num-guest-ids:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 63
maximum: 2047
description:
Number of interrupt identities are supported by IMSIC guest interrupt
file. When not specified it is assumed to be same as specified by the
riscv,num-ids property.
riscv,guest-index-bits:
minimum: 0
maximum: 7
default: 0
description:
Number of guest index bits in the MSI target address.
riscv,hart-index-bits:
minimum: 0
maximum: 15
description:
Number of HART index bits in the MSI target address. When not
specified it is calculated based on the interrupts-extended property.
riscv,group-index-bits:
minimum: 0
maximum: 7
default: 0
description:
Number of group index bits in the MSI target address.
riscv,group-index-shift:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 55
default: 24
description:
The least significant bit position of the group index bits in the
MSI target address.
required:
- compatible
- reg
- interrupt-controller
- msi-controller
- "#msi-cells"
- interrupts-extended
- riscv,num-ids
unevaluatedProperties: false
examples:
- |
// Example 1 (Machine-level IMSIC files with just one group):
interrupt-controller@24000000 {
compatible = "qemu,imsics", "riscv,imsics";
interrupts-extended = <&cpu1_intc 11>,
<&cpu2_intc 11>,
<&cpu3_intc 11>,
<&cpu4_intc 11>;
reg = <0x28000000 0x4000>;
interrupt-controller;
#interrupt-cells = <0>;
msi-controller;
#msi-cells = <0>;
riscv,num-ids = <127>;
};
- |
// Example 2 (Supervisor-level IMSIC files with two groups):
interrupt-controller@28000000 {
compatible = "qemu,imsics", "riscv,imsics";
interrupts-extended = <&cpu1_intc 9>,
<&cpu2_intc 9>,
<&cpu3_intc 9>,
<&cpu4_intc 9>;
reg = <0x28000000 0x2000>, /* Group0 IMSICs */
<0x29000000 0x2000>; /* Group1 IMSICs */
interrupt-controller;
#interrupt-cells = <0>;
msi-controller;
#msi-cells = <0>;
riscv,num-ids = <127>;
riscv,group-index-bits = <1>;
riscv,group-index-shift = <24>;
};
...
Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.yaml
+16 -1
View File
@@ -89,8 +89,23 @@ examples:
reg = <0x5000d000 0x400>;
};
- |
//Example 2
exti2: interrupt-controller@40013c00 {
#include <dt-bindings/interrupt-controller/arm-gic.h>
exti2: interrupt-controller@5000d000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
interrupts-extended =
<&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
- |
//Example 3
exti3: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <2>;
Documentation/devicetree/bindings/timer/renesas,ostm.yaml
+2
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@@ -26,6 +26,7 @@ properties:
- renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five
- renesas,r9a07g044-ostm # RZ/G2{L,LC}
- renesas,r9a07g054-ostm # RZ/V2L
- renesas,r9a09g057-ostm # RZ/V2H(P)
- const: renesas,ostm # Generic
reg:
@@ -58,6 +59,7 @@ if:
- renesas,r9a07g043-ostm
- renesas,r9a07g044-ostm
- renesas,r9a07g054-ostm
- renesas,r9a09g057-ostm
then:
required:
- resets
Documentation/process/changes.rst
+9
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@@ -62,6 +62,7 @@ Sphinx\ [#f1]_ 2.4.4 sphinx-build --version
cpio any cpio --version
GNU tar 1.28 tar --version
gtags (optional) 6.6.5 gtags --version
mkimage (optional) 2017.01 mkimage --version
====================== =============== ========================================
.. [#f1] Sphinx is needed only to build the Kernel documentation
@@ -189,6 +190,14 @@ The kernel build requires GNU GLOBAL version 6.6.5 or later to generate
tag files through ``make gtags``. This is due to its use of the gtags
``-C (--directory)`` flag.
mkimage
-------
This tool is used when building a Flat Image Tree (FIT), commonly used on ARM
platforms. The tool is available via the ``u-boot-tools`` package or can be
built from the U-Boot source code. See the instructions at
https://docs.u-boot.org/en/latest/build/tools.html#building-tools-for-linux
System utilities
****************
Documentation/process/maintainer-tip.rst
+9 -9
View File
@@ -409,20 +409,20 @@ See :ref:`resend_reminders`.
Merge window
^^^^^^^^^^^^
Please do not expect large patch series to be handled during the merge
window or even during the week before. Such patches should be submitted in
mergeable state *at* *least* a week before the merge window opens.
Exceptions are made for bug fixes and *sometimes* for small standalone
drivers for new hardware or minimally invasive patches for hardware
enablement.
Please do not expect patches to be reviewed or merged by tip
maintainers around or during the merge window. The trees are closed
to all but urgent fixes during this time. They reopen once the merge
window closes and a new -rc1 kernel has been released.
Large series should be submitted in mergeable state *at* *least* a week
before the merge window opens. Exceptions are made for bug fixes and
*sometimes* for small standalone drivers for new hardware or minimally
invasive patches for hardware enablement.
During the merge window, the maintainers instead focus on following the
upstream changes, fixing merge window fallout, collecting bug fixes, and
allowing themselves a breath. Please respect that.
The release candidate -rc1 is the starting point for new patches to be
applied which are targeted for the next merge window.
So called _urgent_ branches will be merged into mainline during the
stabilization phase of each release.
MAINTAINERS
+27
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@@ -3073,6 +3073,13 @@ F: drivers/mmc/host/sdhci-of-arasan.c
N: zynq
N: xilinx
ARM64 FIT SUPPORT
M: Simon Glass <sjg@chromium.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm64/boot/Makefile
F: scripts/make_fit.py
ARM64 PORT (AARCH64 ARCHITECTURE)
M: Catalin Marinas <catalin.marinas@arm.com>
M: Will Deacon <will@kernel.org>
@@ -11461,6 +11468,7 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: Documentation/core-api/irq/irq-domain.rst
F: include/linux/irqdomain.h
F: include/linux/irqdomain_defs.h
F: kernel/irq/irqdomain.c
F: kernel/irq/msi.c
@@ -11470,6 +11478,10 @@ L: linux-kernel@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: include/linux/group_cpus.h
F: include/linux/irq.h
F: include/linux/irqhandler.h
F: include/linux/irqnr.h
F: include/linux/irqreturn.h
F: kernel/irq/
F: lib/group_cpus.c
@@ -11480,6 +11492,7 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core
F: Documentation/devicetree/bindings/interrupt-controller/
F: drivers/irqchip/
F: include/linux/irqchip.h
ISA
M: William Breathitt Gray <william.gray@linaro.org>
@@ -18981,6 +18994,20 @@ S: Maintained
F: drivers/mtd/nand/raw/r852.c
F: drivers/mtd/nand/raw/r852.h
RISC-V AIA DRIVERS
M: Anup Patel <anup@brainfault.org>
L: linux-riscv@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
F: Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
F: drivers/irqchip/irq-riscv-aplic-*.c
F: drivers/irqchip/irq-riscv-aplic-*.h
F: drivers/irqchip/irq-riscv-imsic-*.c
F: drivers/irqchip/irq-riscv-imsic-*.h
F: drivers/irqchip/irq-riscv-intc.c
F: include/linux/irqchip/riscv-aplic.h
F: include/linux/irqchip/riscv-imsic.h
RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
arch/arm/boot/dts/st/stm32mp131.dtsi
+73 -1
View File
@@ -783,10 +783,82 @@
};
exti: interrupt-controller@5000d000 {
compatible = "st,stm32mp13-exti", "syscon";
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
interrupts-extended =
<&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
<&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
<&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<0>, /* EXTI_20 */
<&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
<&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>, /* EXTI_40 */
<0>,
<0>,
<0>,
<&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
<0>,
<&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>, /* EXTI_60 */
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */
};
syscfg: syscon@50020000 {
arch/arm/boot/dts/st/stm32mp151.dtsi
+75
View File
@@ -176,6 +176,81 @@
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x5000d000 0x400>;
interrupts-extended =
<&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
<&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
<&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<0>, /* EXTI_20 */
<&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
<&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>, /* EXTI_40 */
<0>,
<0>,
<0>,
<0>,
<0>,
<&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
<0>,
<&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>, /* EXTI_60 */
<&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<0>,
<&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */
<0>,
<0>,
<&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
};
syscfg: syscon@50020000 {
arch/arm64/Kconfig
+2
View File
@@ -255,9 +255,11 @@ config ARM64
select SYSCTL_EXCEPTION_TRACE
select THREAD_INFO_IN_TASK
select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD
select TRACE_IRQFLAGS_SUPPORT
select TRACE_IRQFLAGS_NMI_SUPPORT
select HAVE_SOFTIRQ_ON_OWN_STACK
select USER_STACKTRACE_SUPPORT
help
ARM 64-bit (AArch64) Linux support.
arch/arm64/Kconfig.platforms
+1
View File
@@ -309,6 +309,7 @@ config ARCH_STM32
select GPIOLIB
select PINCTRL
select PINCTRL_STM32MP257
select STM32_EXTI
select ARM_SMC_MBOX
select ARM_SCMI_PROTOCOL
select COMMON_CLK_SCMI
arch/arm64/Makefile
+9 -2
View File
@@ -158,6 +158,10 @@ libs-$(CONFIG_EFI_STUB) += $(objtree)/drivers/firmware/efi/libstub/lib.a
# Default target when executing plain make
boot := arch/arm64/boot
BOOT_TARGETS := Image vmlinuz.efi image.fit
PHONY += $(BOOT_TARGETS)
ifeq ($(CONFIG_EFI_ZBOOT),)
KBUILD_IMAGE := $(boot)/Image.gz
else
@@ -169,8 +173,10 @@ ifndef KBUILD_MIXED_TREE
all: $(notdir $(KBUILD_IMAGE))
endif
vmlinuz.efi: Image
Image vmlinuz.efi: vmlinux
image.fit: dtbs
vmlinuz.efi image.fit: Image
$(BOOT_TARGETS): vmlinux
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
Image.%: Image
@@ -222,6 +228,7 @@ virtconfig:
define archhelp
echo '* Image.gz - Compressed kernel image (arch/$(ARCH)/boot/Image.gz)'
echo ' Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
echo ' image.fit - Flat Image Tree (arch/$(ARCH)/boot/image.fit)'
echo ' install - Install uncompressed kernel'
echo ' zinstall - Install compressed kernel'
echo ' Install using (your) ~/bin/installkernel or'
arch/arm64/boot/.gitignore
+1
View File
@@ -2,3 +2,4 @@
Image
Image.gz
vmlinuz*
image.fit
arch/arm64/boot/Makefile
+5 -1
View File
@@ -16,7 +16,8 @@
OBJCOPYFLAGS_Image :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo Image.zst
targets := Image Image.bz2 Image.gz Image.lz4 Image.lzma Image.lzo \
Image.zst image.fit
$(obj)/Image: vmlinux FORCE
$(call if_changed,objcopy)
@@ -39,6 +40,9 @@ $(obj)/Image.lzo: $(obj)/Image FORCE
$(obj)/Image.zst: $(obj)/Image FORCE
$(call if_changed,zstd)
$(obj)/image.fit: $(obj)/Image $(obj)/dts/dtbs-list FORCE
$(call if_changed,fit)
EFI_ZBOOT_PAYLOAD := Image
EFI_ZBOOT_BFD_TARGET := elf64-littleaarch64
EFI_ZBOOT_MACH_TYPE := ARM64
arch/arm64/boot/dts/st/stm32mp251.dtsi
+176
View File
@@ -443,6 +443,99 @@
<&clk_dsi_txbyte>;
};
exti1: interrupt-controller@44220000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x44220000 0x400>;
interrupts-extended =
<&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
<&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
<&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<0>, /* EXTI_20 */
<&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
<&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */
<&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<0>, /* EXTI_60 */
<&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */
<0>,
<&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<0>, /* EXTI_80 */
<0>,
<0>,
<&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
};
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
@@ -453,6 +546,8 @@
#size-cells = <1>;
compatible = "st,stm32mp257-pinctrl";
ranges = <0 0x44240000 0xa0400>;
interrupt-parent = <&exti1>;
st,syscfg = <&exti1 0x60 0xff>;
pins-are-numbered;
gpioa: gpio@44240000 {
@@ -582,6 +677,8 @@
#size-cells = <1>;
compatible = "st,stm32mp257-z-pinctrl";
ranges = <0 0x46200000 0x400>;
interrupt-parent = <&exti1>;
st,syscfg = <&exti1 0x60 0xff>;
pins-are-numbered;
gpioz: gpio@46200000 {
@@ -597,5 +694,84 @@
};
};
exti2: interrupt-controller@46230000 {
compatible = "st,stm32mp1-exti", "syscon";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x46230000 0x400>;
interrupts-extended =
<&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
<&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
<&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<0>, /* EXTI_20 */
<&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
<&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */
<0>,
<0>,
<&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
<&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>, /* EXTI_60 */
<&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<0>,
<0>,
<&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */
};
};
};
arch/arm64/include/asm/assembler.h
+5 -8
View File
@@ -50,16 +50,12 @@
msr daif, \flags
.endm
.macro enable_dbg
msr daifclr, #8
.endm
.macro disable_step_tsk, flgs, tmp
tbz \flgs, #TIF_SINGLESTEP, 9990f
mrs \tmp, mdscr_el1
bic \tmp, \tmp, #DBG_MDSCR_SS
msr mdscr_el1, \tmp
isb // Synchronise with enable_dbg
isb // Take effect before a subsequent clear of DAIF.D
9990:
.endm
@@ -480,9 +476,10 @@ alternative_endif
*/
.macro reset_pmuserenr_el0, tmpreg
mrs \tmpreg, id_aa64dfr0_el1
sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
cmp \tmpreg, #1 // Skip if no PMU present
b.lt 9000f
ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
cmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_NI
ccmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
b.eq 9000f // Skip if no PMU present or IMP_DEF
msr pmuserenr_el0, xzr // Disable PMU access from EL0
9000:
.endm
arch/arm64/include/asm/cputype.h
+2
View File
@@ -86,6 +86,7 @@
#define ARM_CPU_PART_CORTEX_X2 0xD48
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
@@ -159,6 +160,7 @@
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
arch/arm64/include/asm/el2_setup.h
+5 -4
View File
@@ -59,13 +59,14 @@
.macro __init_el2_debug
mrs x1, id_aa64dfr0_el1
sbfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
cmp x0, #1
b.lt .Lskip_pmu_\@ // Skip if no PMU present
ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
cmp x0, #ID_AA64DFR0_EL1_PMUVer_NI
ccmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF
mrs x0, pmcr_el0 // Disable debug access traps
ubfx x0, x0, #11, #5 // to EL2 and allow access to
.Lskip_pmu_\@:
csel x2, xzr, x0, lt // all PMU counters from EL1
csel x2, xzr, x0, eq // all PMU counters from EL1
/* Statistical profiling */
ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
arch/arm64/include/asm/irqflags.h
-1
View File
@@ -5,7 +5,6 @@
#ifndef __ASM_IRQFLAGS_H
#define __ASM_IRQFLAGS_H
#include <asm/alternative.h>
#include <asm/barrier.h>
#include <asm/ptrace.h>
#include <asm/sysreg.h>
arch/arm64/include/asm/jump_label.h
+15 -13
View File
@@ -15,17 +15,23 @@
#define JUMP_LABEL_NOP_SIZE AARCH64_INSN_SIZE
#define JUMP_TABLE_ENTRY(key, label) \
".pushsection __jump_table, \"aw\"\n\t" \
".align 3\n\t" \
".long 1b - ., %l["#label"] - .\n\t" \
".quad %c0 - .\n\t" \
".popsection\n\t" \
: : "i"(key) : : label
static __always_inline bool arch_static_branch(struct static_key * const key,
const bool branch)
{
char *k = &((char *)key)[branch];
asm goto(
"1: nop \n\t"
" .pushsection __jump_table, \"aw\" \n\t"
" .align 3 \n\t"
" .long 1b - ., %l[l_yes] - . \n\t"
" .quad %c0 - . \n\t"
" .popsection \n\t"
: : "i"(&((char *)key)[branch]) : : l_yes);
JUMP_TABLE_ENTRY(k, l_yes)
);
return false;
l_yes:
@@ -35,15 +41,11 @@ l_yes:
static __always_inline bool arch_static_branch_jump(struct static_key * const key,
const bool branch)
{
char *k = &((char *)key)[branch];
asm goto(
"1: b %l[l_yes] \n\t"
" .pushsection __jump_table, \"aw\" \n\t"
" .align 3 \n\t"
" .long 1b - ., %l[l_yes] - . \n\t"
" .quad %c0 - . \n\t"
" .popsection \n\t"
: : "i"(&((char *)key)[branch]) : : l_yes);
JUMP_TABLE_ENTRY(k, l_yes)
);
return false;
l_yes:
return true;
arch/arm64/include/asm/pgtable-prot.h
+13 -6
View File
@@ -18,14 +18,21 @@
#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
#define PTE_DEVMAP (_AT(pteval_t, 1) << 57)
#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
/*
* This bit indicates that the entry is present i.e. pmd_page()
* still points to a valid huge page in memory even if the pmd
* has been invalidated.
* PTE_PRESENT_INVALID=1 & PTE_VALID=0 indicates that the pte's fields should be
* interpreted according to the HW layout by SW but any attempted HW access to
* the address will result in a fault. pte_present() returns true.
*/
#define PMD_PRESENT_INVALID (_AT(pteval_t, 1) << 59) /* only when !PMD_SECT_VALID */
#define PTE_PRESENT_INVALID (PTE_NG) /* only when !PTE_VALID */
#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
#define PTE_UFFD_WP (_AT(pteval_t, 1) << 58) /* uffd-wp tracking */
#define PTE_SWP_UFFD_WP (_AT(pteval_t, 1) << 3) /* only for swp ptes */
#else
#define PTE_UFFD_WP (_AT(pteval_t, 0))
#define PTE_SWP_UFFD_WP (_AT(pteval_t, 0))
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
#define _PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
#define _PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
@@ -103,7 +110,7 @@ static inline bool __pure lpa2_is_enabled(void)
__val; \
})
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PRESENT_INVALID | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
#define PAGE_SHARED __pgprot(_PAGE_SHARED)
#define PAGE_SHARED_EXEC __pgprot(_PAGE_SHARED_EXEC)
arch/arm64/include/asm/pgtable.h
+86 -28
View File
@@ -105,7 +105,7 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
/*
* The following only work if pte_present(). Undefined behaviour otherwise.
*/
#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
#define pte_present(pte) (pte_valid(pte) || pte_present_invalid(pte))
#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
@@ -132,6 +132,8 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
#define pte_present_invalid(pte) \
((pte_val(pte) & (PTE_VALID | PTE_PRESENT_INVALID)) == PTE_PRESENT_INVALID)
/*
* Execute-only user mappings do not have the PTE_USER bit set. All valid
* kernel mappings have the PTE_UXN bit set.
@@ -261,6 +263,13 @@ static inline pte_t pte_mkpresent(pte_t pte)
return set_pte_bit(pte, __pgprot(PTE_VALID));
}
static inline pte_t pte_mkinvalid(pte_t pte)
{
pte = set_pte_bit(pte, __pgprot(PTE_PRESENT_INVALID));
pte = clear_pte_bit(pte, __pgprot(PTE_VALID));
return pte;
}
static inline pmd_t pmd_mkcont(pmd_t pmd)
{
return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
@@ -271,9 +280,31 @@ static inline pte_t pte_mkdevmap(pte_t pte)
return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
}
static inline void __set_pte(pte_t *ptep, pte_t pte)
#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
static inline int pte_uffd_wp(pte_t pte)
{
return !!(pte_val(pte) & PTE_UFFD_WP);
}
static inline pte_t pte_mkuffd_wp(pte_t pte)
{
return pte_wrprotect(set_pte_bit(pte, __pgprot(PTE_UFFD_WP)));
}
static inline pte_t pte_clear_uffd_wp(pte_t pte)
{
return clear_pte_bit(pte, __pgprot(PTE_UFFD_WP));
}
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
static inline void __set_pte_nosync(pte_t *ptep, pte_t pte)
{
WRITE_ONCE(*ptep, pte);
}
static inline void __set_pte(pte_t *ptep, pte_t pte)
{
__set_pte_nosync(ptep, pte);
/*
* Only if the new pte is valid and kernel, otherwise TLB maintenance
@@ -463,13 +494,39 @@ static inline pte_t pte_swp_clear_exclusive(pte_t pte)
return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
}
#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
static inline pte_t pte_swp_mkuffd_wp(pte_t pte)
{
return set_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP));
}
static inline int pte_swp_uffd_wp(pte_t pte)
{
return !!(pte_val(pte) & PTE_SWP_UFFD_WP);
}
static inline pte_t pte_swp_clear_uffd_wp(pte_t pte)
{
return clear_pte_bit(pte, __pgprot(PTE_SWP_UFFD_WP));
}
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
#ifdef CONFIG_NUMA_BALANCING
/*
* See the comment in include/linux/pgtable.h
*/
static inline int pte_protnone(pte_t pte)
{
return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
/*
* pte_present_invalid() tells us that the pte is invalid from HW
* perspective but present from SW perspective, so the fields are to be
* interpretted as per the HW layout. The second 2 checks are the unique
* encoding that we use for PROT_NONE. It is insufficient to only use
* the first check because we share the same encoding scheme with pmds
* which support pmd_mkinvalid(), so can be present-invalid without
* being PROT_NONE.
*/
return pte_present_invalid(pte) && !pte_user(pte) && !pte_user_exec(pte);
}
static inline int pmd_protnone(pmd_t pmd)
@@ -478,12 +535,7 @@ static inline int pmd_protnone(pmd_t pmd)
}
#endif
#define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
static inline int pmd_present(pmd_t pmd)
{
return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
}
#define pmd_present(pmd) pte_present(pmd_pte(pmd))
/*
* THP definitions.
@@ -508,14 +560,16 @@ static inline int pmd_trans_huge(pmd_t pmd)
#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
static inline pmd_t pmd_mkinvalid(pmd_t pmd)
{
pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
return pmd;
}
#define pmd_mkinvalid(pmd) pte_pmd(pte_mkinvalid(pmd_pte(pmd)))
#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP
#define pmd_uffd_wp(pmd) pte_uffd_wp(pmd_pte(pmd))
#define pmd_mkuffd_wp(pmd) pte_pmd(pte_mkuffd_wp(pmd_pte(pmd)))
#define pmd_clear_uffd_wp(pmd) pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd)))
#define pmd_swp_uffd_wp(pmd) pte_swp_uffd_wp(pmd_pte(pmd))
#define pmd_swp_mkuffd_wp(pmd) pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd)))
#define pmd_swp_clear_uffd_wp(pmd) \
pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd)))
#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */
#define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
@@ -760,6 +814,7 @@ static inline pmd_t *pud_pgtable(pud_t pud)
#else
#define pud_valid(pud) false
#define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
#define pud_user_exec(pud) pud_user(pud) /* Always 0 with folding */
@@ -1005,6 +1060,8 @@ static inline p4d_t *p4d_offset_kimg(pgd_t *pgdp, u64 addr)
static inline bool pgtable_l5_enabled(void) { return false; }
#define p4d_index(addr) (((addr) >> P4D_SHIFT) & (PTRS_PER_P4D - 1))
/* Match p4d_offset folding in <asm/generic/pgtable-nop4d.h> */
#define p4d_set_fixmap(addr) NULL
#define p4d_set_fixmap_offset(p4dp, addr) ((p4d_t *)p4dp)
@@ -1027,8 +1084,8 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
* in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
*/
const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
PTE_ATTRINDX_MASK;
PTE_PRESENT_INVALID | PTE_VALID | PTE_WRITE |
PTE_GP | PTE_ATTRINDX_MASK;
/* preserve the hardware dirty information */
if (pte_hw_dirty(pte))
pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
@@ -1076,17 +1133,17 @@ static inline int pgd_devmap(pgd_t pgd)
#ifdef CONFIG_PAGE_TABLE_CHECK
static inline bool pte_user_accessible_page(pte_t pte)
{
return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte));
return pte_valid(pte) && (pte_user(pte) || pte_user_exec(pte));
}
static inline bool pmd_user_accessible_page(pmd_t pmd)
{
return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
return pmd_valid(pmd) && !pmd_table(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
}
static inline bool pud_user_accessible_page(pud_t pud)
{
return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud));
return pud_valid(pud) && !pud_table(pud) && (pud_user(pud) || pud_user_exec(pud));
}
#endif
@@ -1248,15 +1305,16 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
* Encode and decode a swap entry:
* bits 0-1: present (must be zero)
* bits 2: remember PG_anon_exclusive
* bits 3-7: swap type
* bits 8-57: swap offset
* bit 58: PTE_PROT_NONE (must be zero)
* bit 3: remember uffd-wp state
* bits 6-10: swap type
* bit 11: PTE_PRESENT_INVALID (must be zero)
* bits 12-61: swap offset
*/
#define __SWP_TYPE_SHIFT 3
#define __SWP_TYPE_SHIFT 6
#define __SWP_TYPE_BITS 5
#define __SWP_OFFSET_BITS 50
#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
#define __SWP_OFFSET_SHIFT 12
#define __SWP_OFFSET_BITS 50
#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
arch/arm64/include/asm/sysreg.h
+12 -12
View File
@@ -1036,18 +1036,18 @@
* Permission Indirection Extension (PIE) permission encodings.
* Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
*/
#define PIE_NONE_O 0x0
#define PIE_R_O 0x1
#define PIE_X_O 0x2
#define PIE_RX_O 0x3
#define PIE_RW_O 0x5
#define PIE_RWnX_O 0x6
#define PIE_RWX_O 0x7
#define PIE_R 0x8
#define PIE_GCS 0x9
#define PIE_RX 0xa
#define PIE_RW 0xc
#define PIE_RWX 0xe
#define PIE_NONE_O UL(0x0)
#define PIE_R_O UL(0x1)
#define PIE_X_O UL(0x2)
#define PIE_RX_O UL(0x3)
#define PIE_RW_O UL(0x5)
#define PIE_RWnX_O UL(0x6)
#define PIE_RWX_O UL(0x7)
#define PIE_R UL(0x8)
#define PIE_GCS UL(0x9)
#define PIE_RX UL(0xa)
#define PIE_RW UL(0xc)
#define PIE_RWX UL(0xe)
#define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4))
arch/arm64/include/asm/tlbflush.h
+20 -13
View File
@@ -142,17 +142,24 @@ static inline unsigned long get_trans_granule(void)
* EL1, Inner Shareable".
*
*/
#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \
({ \
unsigned long __ta = (baddr); \
unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \
__ta &= GENMASK_ULL(36, 0); \
__ta |= __ttl << 37; \
__ta |= (unsigned long)(num) << 39; \
__ta |= (unsigned long)(scale) << 44; \
__ta |= get_trans_granule() << 46; \
__ta |= (unsigned long)(asid) << 48; \
__ta; \
#define TLBIR_ASID_MASK GENMASK_ULL(63, 48)
#define TLBIR_TG_MASK GENMASK_ULL(47, 46)
#define TLBIR_SCALE_MASK GENMASK_ULL(45, 44)
#define TLBIR_NUM_MASK GENMASK_ULL(43, 39)
#define TLBIR_TTL_MASK GENMASK_ULL(38, 37)
#define TLBIR_BADDR_MASK GENMASK_ULL(36, 0)
#define __TLBI_VADDR_RANGE(baddr, asid, scale, num, ttl) \
({ \
unsigned long __ta = 0; \
unsigned long __ttl = (ttl >= 1 && ttl <= 3) ? ttl : 0; \
__ta |= FIELD_PREP(TLBIR_BADDR_MASK, baddr); \
__ta |= FIELD_PREP(TLBIR_TTL_MASK, __ttl); \
__ta |= FIELD_PREP(TLBIR_NUM_MASK, num); \
__ta |= FIELD_PREP(TLBIR_SCALE_MASK, scale); \
__ta |= FIELD_PREP(TLBIR_TG_MASK, get_trans_granule()); \
__ta |= FIELD_PREP(TLBIR_ASID_MASK, asid); \
__ta; \
})
/* These macros are used by the TLBI RANGE feature. */
@@ -439,11 +446,11 @@ static inline void __flush_tlb_range_nosync(struct vm_area_struct *vma,
* When not uses TLB range ops, we can handle up to
* (MAX_DVM_OPS - 1) pages;
* When uses TLB range ops, we can handle up to
* (MAX_TLBI_RANGE_PAGES - 1) pages.
* MAX_TLBI_RANGE_PAGES pages.
*/
if ((!system_supports_tlb_range() &&
(end - start) >= (MAX_DVM_OPS * stride)) ||
pages >= MAX_TLBI_RANGE_PAGES) {
pages > MAX_TLBI_RANGE_PAGES) {
flush_tlb_mm(vma->vm_mm);
return;
}
arch/arm64/kernel/acpi.c
+10
View File
@@ -26,6 +26,7 @@
#include <linux/libfdt.h>
#include <linux/smp.h>
#include <linux/serial_core.h>
#include <linux/suspend.h>
#include <linux/pgtable.h>
#include <acpi/ghes.h>
@@ -227,6 +228,15 @@ done:
if (earlycon_acpi_spcr_enable)
early_init_dt_scan_chosen_stdout();
} else {
#ifdef CONFIG_HIBERNATION
struct acpi_table_header *facs = NULL;
acpi_get_table(ACPI_SIG_FACS, 1, &facs);
if (facs) {
swsusp_hardware_signature =
((struct acpi_table_facs *)facs)->hardware_signature;
acpi_put_table(facs);
}
#endif
acpi_parse_spcr(earlycon_acpi_spcr_enable, true);
if (IS_ENABLED(CONFIG_ACPI_BGRT))
acpi_table_parse(ACPI_SIG_BGRT, acpi_parse_bgrt);
arch/arm64/kernel/perf_callchain.c
+4 -114
View File
@@ -10,95 +10,13 @@
#include <asm/pointer_auth.h>
struct frame_tail {
struct frame_tail __user *fp;
unsigned long lr;
} __attribute__((packed));
/*
* Get the return address for a single stackframe and return a pointer to the
* next frame tail.
*/
static struct frame_tail __user *
user_backtrace(struct frame_tail __user *tail,
struct perf_callchain_entry_ctx *entry)
static bool callchain_trace(void *data, unsigned long pc)
{
struct frame_tail buftail;
unsigned long err;
unsigned long lr;
struct perf_callchain_entry_ctx *entry = data;
/* Also check accessibility of one struct frame_tail beyond */
if (!access_ok(tail, sizeof(buftail)))
return NULL;
pagefault_disable();
err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
pagefault_enable();
if (err)
return NULL;
lr = ptrauth_strip_user_insn_pac(buftail.lr);
perf_callchain_store(entry, lr);
/*
* Frame pointers should strictly progress back up the stack
* (towards higher addresses).
*/
if (tail >= buftail.fp)
return NULL;
return buftail.fp;
return perf_callchain_store(entry, pc) == 0;
}
#ifdef CONFIG_COMPAT
/*
* The registers we're interested in are at the end of the variable
* length saved register structure. The fp points at the end of this
* structure so the address of this struct is:
* (struct compat_frame_tail *)(xxx->fp)-1
*
* This code has been adapted from the ARM OProfile support.
*/
struct compat_frame_tail {
compat_uptr_t fp; /* a (struct compat_frame_tail *) in compat mode */
u32 sp;
u32 lr;
} __attribute__((packed));
static struct compat_frame_tail __user *
compat_user_backtrace(struct compat_frame_tail __user *tail,
struct perf_callchain_entry_ctx *entry)
{
struct compat_frame_tail buftail;
unsigned long err;
/* Also check accessibility of one struct frame_tail beyond */
if (!access_ok(tail, sizeof(buftail)))
return NULL;
pagefault_disable();
err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
pagefault_enable();
if (err)
return NULL;
perf_callchain_store(entry, buftail.lr);
/*
* Frame pointers should strictly progress back up the stack
* (towards higher addresses).
*/
if (tail + 1 >= (struct compat_frame_tail __user *)
compat_ptr(buftail.fp))
return NULL;
return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
}
#endif /* CONFIG_COMPAT */
void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
struct pt_regs *regs)
{
@@ -107,35 +25,7 @@ void perf_callchain_user(struct perf_callchain_entry_ctx *entry,
return;
}
perf_callchain_store(entry, regs->pc);
if (!compat_user_mode(regs)) {
/* AARCH64 mode */
struct frame_tail __user *tail;
tail = (struct frame_tail __user *)regs->regs[29];
while (entry->nr < entry->max_stack &&
tail && !((unsigned long)tail & 0x7))
tail = user_backtrace(tail, entry);
} else {
#ifdef CONFIG_COMPAT
/* AARCH32 compat mode */
struct compat_frame_tail __user *tail;
tail = (struct compat_frame_tail __user *)regs->compat_fp - 1;
while ((entry->nr < entry->max_stack) &&
tail && !((unsigned long)tail & 0x3))
tail = compat_user_backtrace(tail, entry);
#endif
}
}
static bool callchain_trace(void *data, unsigned long pc)
{
struct perf_callchain_entry_ctx *entry = data;
return perf_callchain_store(entry, pc) == 0;
arch_stack_walk_user(callchain_trace, entry, regs);
}
void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry,
arch/arm64/kernel/pi/idreg-override.c
+2
View File
@@ -108,6 +108,7 @@ static const struct ftr_set_desc pfr0 __prel64_initconst = {
.override = &id_aa64pfr0_override,
.fields = {
FIELD("sve", ID_AA64PFR0_EL1_SVE_SHIFT, pfr0_sve_filter),
FIELD("el0", ID_AA64PFR0_EL1_EL0_SHIFT, NULL),
{}
},
};
@@ -223,6 +224,7 @@ static const struct {
{ "nokaslr", "arm64_sw.nokaslr=1" },
{ "rodata=off", "arm64_sw.rodataoff=1" },
{ "arm64.nolva", "id_aa64mmfr2.varange=0" },
{ "arm64.no32bit_el0", "id_aa64pfr0.el0=1" },
};
static int __init parse_hexdigit(const char *p, u64 *v)
arch/arm64/kernel/setup.c
+9 -2
View File
@@ -298,8 +298,15 @@ void __init __no_sanitize_address setup_arch(char **cmdline_p)
dynamic_scs_init();
/*
* Unmask SError as soon as possible after initializing earlycon so
* that we can report any SErrors immediately.
* The primary CPU enters the kernel with all DAIF exceptions masked.
*
* We must unmask Debug and SError before preemption or scheduling is
* possible to ensure that these are consistently unmasked across
* threads, and we want to unmask SError as soon as possible after
* initializing earlycon so that we can report any SErrors immediately.
*
* IRQ and FIQ will be unmasked after the root irqchip has been
* detected and initialized.
*/
local_daif_restore(DAIF_PROCCTX_NOIRQ);
arch/arm64/kernel/smp.c
+7
View File
@@ -269,6 +269,13 @@ asmlinkage notrace void secondary_start_kernel(void)
set_cpu_online(cpu, true);
complete(&cpu_running);
/*
* Secondary CPUs enter the kernel with all DAIF exceptions masked.
*
* As with setup_arch() we must unmask Debug and SError exceptions, and
* as the root irqchip has already been detected and initialized we can
* unmask IRQ and FIQ at the same time.
*/
local_daif_restore(DAIF_PROCCTX);
/*
arch/arm64/kernel/stacktrace.c
+120
View File
@@ -325,3 +325,123 @@ void show_stack(struct task_struct *tsk, unsigned long *sp, const char *loglvl)
dump_backtrace(NULL, tsk, loglvl);
barrier();
}
/*
* The struct defined for userspace stack frame in AARCH64 mode.
*/
struct frame_tail {
struct frame_tail __user *fp;
unsigned long lr;
} __attribute__((packed));
/*
* Get the return address for a single stackframe and return a pointer to the
* next frame tail.
*/
static struct frame_tail __user *
unwind_user_frame(struct frame_tail __user *tail, void *cookie,
stack_trace_consume_fn consume_entry)
{
struct frame_tail buftail;
unsigned long err;
unsigned long lr;
/* Also check accessibility of one struct frame_tail beyond */
if (!access_ok(tail, sizeof(buftail)))
return NULL;
pagefault_disable();
err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
pagefault_enable();
if (err)
return NULL;
lr = ptrauth_strip_user_insn_pac(buftail.lr);
if (!consume_entry(cookie, lr))
return NULL;
/*
* Frame pointers should strictly progress back up the stack
* (towards higher addresses).
*/
if (tail >= buftail.fp)
return NULL;
return buftail.fp;
}
#ifdef CONFIG_COMPAT
/*
* The registers we're interested in are at the end of the variable
* length saved register structure. The fp points at the end of this
* structure so the address of this struct is:
* (struct compat_frame_tail *)(xxx->fp)-1
*
* This code has been adapted from the ARM OProfile support.
*/
struct compat_frame_tail {
compat_uptr_t fp; /* a (struct compat_frame_tail *) in compat mode */
u32 sp;
u32 lr;
} __attribute__((packed));
static struct compat_frame_tail __user *
unwind_compat_user_frame(struct compat_frame_tail __user *tail, void *cookie,
stack_trace_consume_fn consume_entry)
{
struct compat_frame_tail buftail;
unsigned long err;
/* Also check accessibility of one struct frame_tail beyond */
if (!access_ok(tail, sizeof(buftail)))
return NULL;
pagefault_disable();
err = __copy_from_user_inatomic(&buftail, tail, sizeof(buftail));
pagefault_enable();
if (err)
return NULL;
if (!consume_entry(cookie, buftail.lr))
return NULL;
/*
* Frame pointers should strictly progress back up the stack
* (towards higher addresses).
*/
if (tail + 1 >= (struct compat_frame_tail __user *)
compat_ptr(buftail.fp))
return NULL;
return (struct compat_frame_tail __user *)compat_ptr(buftail.fp) - 1;
}
#endif /* CONFIG_COMPAT */
void arch_stack_walk_user(stack_trace_consume_fn consume_entry, void *cookie,
const struct pt_regs *regs)
{
if (!consume_entry(cookie, regs->pc))
return;
if (!compat_user_mode(regs)) {
/* AARCH64 mode */
struct frame_tail __user *tail;
tail = (struct frame_tail __user *)regs->regs[29];
while (tail && !((unsigned long)tail & 0x7))
tail = unwind_user_frame(tail, cookie, consume_entry);
} else {
#ifdef CONFIG_COMPAT
/* AARCH32 compat mode */
struct compat_frame_tail __user *tail;
tail = (struct compat_frame_tail __user *)regs->compat_fp - 1;
while (tail && !((unsigned long)tail & 0x3))
tail = unwind_compat_user_frame(tail, cookie, consume_entry);
#endif
}
}
arch/arm64/mm/mmu.c
+57 -44
View File
@@ -109,28 +109,12 @@ EXPORT_SYMBOL(phys_mem_access_prot);
static phys_addr_t __init early_pgtable_alloc(int shift)
{
phys_addr_t phys;
void *ptr;
phys = memblock_phys_alloc_range(PAGE_SIZE, PAGE_SIZE, 0,
MEMBLOCK_ALLOC_NOLEAKTRACE);
if (!phys)
panic("Failed to allocate page table page\n");
/*
* The FIX_{PGD,PUD,PMD} slots may be in active use, but the FIX_PTE
* slot will be free, so we can (ab)use the FIX_PTE slot to initialise
* any level of table.
*/
ptr = pte_set_fixmap(phys);
memset(ptr, 0, PAGE_SIZE);
/*
* Implicit barriers also ensure the zeroed page is visible to the page
* table walker
*/
pte_clear_fixmap();
return phys;
}
@@ -172,16 +156,25 @@ bool pgattr_change_is_safe(u64 old, u64 new)
return ((old ^ new) & ~mask) == 0;
}
static void init_pte(pmd_t *pmdp, unsigned long addr, unsigned long end,
static void init_clear_pgtable(void *table)
{
clear_page(table);
/* Ensure the zeroing is observed by page table walks. */
dsb(ishst);
}
static void init_pte(pte_t *ptep, unsigned long addr, unsigned long end,
phys_addr_t phys, pgprot_t prot)
{
pte_t *ptep;
ptep = pte_set_fixmap_offset(pmdp, addr);
do {
pte_t old_pte = __ptep_get(ptep);
__set_pte(ptep, pfn_pte(__phys_to_pfn(phys), prot));
/*
* Required barriers to make this visible to the table walker
* are deferred to the end of alloc_init_cont_pte().
*/
__set_pte_nosync(ptep, pfn_pte(__phys_to_pfn(phys), prot));
/*
* After the PTE entry has been populated once, we
@@ -192,8 +185,6 @@ static void init_pte(pmd_t *pmdp, unsigned long addr, unsigned long end,
phys += PAGE_SIZE;
} while (ptep++, addr += PAGE_SIZE, addr != end);
pte_clear_fixmap();
}
static void alloc_init_cont_pte(pmd_t *pmdp, unsigned long addr,
@@ -204,6 +195,7 @@ static void alloc_init_cont_pte(pmd_t *pmdp, unsigned long addr,
{
unsigned long next;
pmd_t pmd = READ_ONCE(*pmdp);
pte_t *ptep;
BUG_ON(pmd_sect(pmd));
if (pmd_none(pmd)) {
@@ -214,10 +206,14 @@ static void alloc_init_cont_pte(pmd_t *pmdp, unsigned long addr,
pmdval |= PMD_TABLE_PXN;
BUG_ON(!pgtable_alloc);
pte_phys = pgtable_alloc(PAGE_SHIFT);
ptep = pte_set_fixmap(pte_phys);
init_clear_pgtable(ptep);
ptep += pte_index(addr);
__pmd_populate(pmdp, pte_phys, pmdval);
pmd = READ_ONCE(*pmdp);
} else {
BUG_ON(pmd_bad(pmd));
ptep = pte_set_fixmap_offset(pmdp, addr);
}
BUG_ON(pmd_bad(pmd));
do {
pgprot_t __prot = prot;
@@ -229,20 +225,26 @@ static void alloc_init_cont_pte(pmd_t *pmdp, unsigned long addr,
(flags & NO_CONT_MAPPINGS) == 0)
__prot = __pgprot(pgprot_val(prot) | PTE_CONT);
init_pte(pmdp, addr, next, phys, __prot);
init_pte(ptep, addr, next, phys, __prot);
ptep += pte_index(next) - pte_index(addr);
phys += next - addr;
} while (addr = next, addr != end);
/*
* Note: barriers and maintenance necessary to clear the fixmap slot
* ensure that all previous pgtable writes are visible to the table
* walker.
*/
pte_clear_fixmap();
}
static void init_pmd(pud_t *pudp, unsigned long addr, unsigned long end,
static void init_pmd(pmd_t *pmdp, unsigned long addr, unsigned long end,
phys_addr_t phys, pgprot_t prot,
phys_addr_t (*pgtable_alloc)(int), int flags)
{
unsigned long next;
pmd_t *pmdp;
pmdp = pmd_set_fixmap_offset(pudp, addr);
do {
pmd_t old_pmd = READ_ONCE(*pmdp);
@@ -268,8 +270,6 @@ static void init_pmd(pud_t *pudp, unsigned long addr, unsigned long end,
}
phys += next - addr;
} while (pmdp++, addr = next, addr != end);
pmd_clear_fixmap();
}
static void alloc_init_cont_pmd(pud_t *pudp, unsigned long addr,
@@ -279,6 +279,7 @@ static void alloc_init_cont_pmd(pud_t *pudp, unsigned long addr,
{
unsigned long next;
pud_t pud = READ_ONCE(*pudp);
pmd_t *pmdp;
/*
* Check for initial section mappings in the pgd/pud.
@@ -292,10 +293,14 @@ static void alloc_init_cont_pmd(pud_t *pudp, unsigned long addr,
pudval |= PUD_TABLE_PXN;
BUG_ON(!pgtable_alloc);
pmd_phys = pgtable_alloc(PMD_SHIFT);
pmdp = pmd_set_fixmap(pmd_phys);
init_clear_pgtable(pmdp);
pmdp += pmd_index(addr);
__pud_populate(pudp, pmd_phys, pudval);
pud = READ_ONCE(*pudp);
} else {
BUG_ON(pud_bad(pud));
pmdp = pmd_set_fixmap_offset(pudp, addr);
}
BUG_ON(pud_bad(pud));
do {
pgprot_t __prot = prot;
@@ -307,10 +312,13 @@ static void alloc_init_cont_pmd(pud_t *pudp, unsigned long addr,
(flags & NO_CONT_MAPPINGS) == 0)
__prot = __pgprot(pgprot_val(prot) | PTE_CONT);
init_pmd(pudp, addr, next, phys, __prot, pgtable_alloc, flags);
init_pmd(pmdp, addr, next, phys, __prot, pgtable_alloc, flags);
pmdp += pmd_index(next) - pmd_index(addr);
phys += next - addr;
} while (addr = next, addr != end);
pmd_clear_fixmap();
}
static void alloc_init_pud(p4d_t *p4dp, unsigned long addr, unsigned long end,
@@ -330,12 +338,15 @@ static void alloc_init_pud(p4d_t *p4dp, unsigned long addr, unsigned long end,
p4dval |= P4D_TABLE_PXN;
BUG_ON(!pgtable_alloc);
pud_phys = pgtable_alloc(PUD_SHIFT);
pudp = pud_set_fixmap(pud_phys);
init_clear_pgtable(pudp);
pudp += pud_index(addr);
__p4d_populate(p4dp, pud_phys, p4dval);
p4d = READ_ONCE(*p4dp);
} else {
BUG_ON(p4d_bad(p4d));
pudp = pud_set_fixmap_offset(p4dp, addr);
}
BUG_ON(p4d_bad(p4d));
pudp = pud_set_fixmap_offset(p4dp, addr);
do {
pud_t old_pud = READ_ONCE(*pudp);
@@ -385,12 +396,15 @@ static void alloc_init_p4d(pgd_t *pgdp, unsigned long addr, unsigned long end,
pgdval |= PGD_TABLE_PXN;
BUG_ON(!pgtable_alloc);
p4d_phys = pgtable_alloc(P4D_SHIFT);
p4dp = p4d_set_fixmap(p4d_phys);
init_clear_pgtable(p4dp);
p4dp += p4d_index(addr);
__pgd_populate(pgdp, p4d_phys, pgdval);
pgd = READ_ONCE(*pgdp);
} else {
BUG_ON(pgd_bad(pgd));
p4dp = p4d_set_fixmap_offset(pgdp, addr);
}
BUG_ON(pgd_bad(pgd));
p4dp = p4d_set_fixmap_offset(pgdp, addr);
do {
p4d_t old_p4d = READ_ONCE(*p4dp);
@@ -457,11 +471,10 @@ void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
static phys_addr_t __pgd_pgtable_alloc(int shift)
{
void *ptr = (void *)__get_free_page(GFP_PGTABLE_KERNEL);
BUG_ON(!ptr);
/* Page is zeroed by init_clear_pgtable() so don't duplicate effort. */
void *ptr = (void *)__get_free_page(GFP_PGTABLE_KERNEL & ~__GFP_ZERO);
/* Ensure the zeroed page is visible to the page table walker */
dsb(ishst);
BUG_ON(!ptr);
return __pa(ptr);
}
arch/arm64/mm/proc.S
-10
View File
@@ -135,14 +135,6 @@ SYM_FUNC_START(cpu_do_resume)
msr tcr_el1, x8
msr vbar_el1, x9
/*
* __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
* debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
* exception. Mask them until local_daif_restore() in cpu_suspend()
* resets them.
*/
disable_daif
msr mdscr_el1, x10
msr sctlr_el1, x12
@@ -466,8 +458,6 @@ SYM_FUNC_START(__cpu_setup)
msr cpacr_el1, xzr // Reset cpacr_el1
mov x1, #1 << 12 // Reset mdscr_el1 and disable
msr mdscr_el1, x1 // access to the DCC from EL0
isb // Unmask debug exceptions now,
enable_dbg // since this is per-cpu
reset_pmuserenr_el0 x1 // Disable PMU access from EL0
reset_amuserenr_el0 x1 // Disable AMU access from EL0
arch/m68k/Kconfig
+2 -2
View File
@@ -3,8 +3,8 @@ config M68K
bool
default y
select ARCH_32BIT_OFF_T
select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_BINFMT_FLAT
select ARCH_HAS_CPU_CACHE_ALIASING
select ARCH_HAS_CPU_FINALIZE_INIT if MMU
select ARCH_HAS_CURRENT_STACK_POINTER
select ARCH_HAS_DMA_PREP_COHERENT if M68K_NONCOHERENT_DMA && !COLDFIRE
@@ -18,7 +18,7 @@ config M68K
select DMA_DIRECT_REMAP if M68K_NONCOHERENT_DMA && !COLDFIRE
select GENERIC_ATOMIC64
select GENERIC_CPU_DEVICES
select GENERIC_IOMAP
select GENERIC_IOMAP if HAS_IOPORT
select GENERIC_IRQ_SHOW
select GENERIC_LIB_ASHLDI3
select GENERIC_LIB_ASHRDI3
arch/m68k/amiga/config.c
+1 -1
View File
@@ -836,7 +836,7 @@ static void amiga_get_hardware_list(struct seq_file *m)
seq_printf(m, "\tZorro II%s AutoConfig: %d Expansion "
"Device%s\n",
AMIGAHW_PRESENT(ZORRO3) ? "I" : "",
zorro_num_autocon, zorro_num_autocon == 1 ? "" : "s");
zorro_num_autocon, str_plural(zorro_num_autocon));
#endif /* CONFIG_ZORRO */
#undef AMIGAHW_ANNOUNCE
arch/m68k/configs/amiga_defconfig
+1 -3
View File
@@ -26,6 +26,7 @@ CONFIG_AMIGA_BUILTIN_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_ATARI_PARTITION=y
CONFIG_MAC_PARTITION=y
@@ -217,7 +218,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -624,8 +624,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/apollo_defconfig
+1 -3
View File
@@ -21,6 +21,7 @@ CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -213,7 +214,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -581,8 +581,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/atari_defconfig
+1 -3
View File
@@ -29,6 +29,7 @@ CONFIG_ATARI_ETHERNEC=y
CONFIG_ATARI_DSP56K=m
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_MAC_PARTITION=y
@@ -220,7 +221,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -601,8 +601,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/bvme6000_defconfig
+1 -3
View File
@@ -19,6 +19,7 @@ CONFIG_BVME6000=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -210,7 +211,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -573,8 +573,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/hp300_defconfig
+1 -3
View File
@@ -20,6 +20,7 @@ CONFIG_HP300=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -212,7 +213,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -583,8 +583,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/mac_defconfig
+1 -3
View File
@@ -20,6 +20,7 @@ CONFIG_MAC=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -211,7 +212,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -600,8 +600,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/multi_defconfig
+1 -3
View File
@@ -44,6 +44,7 @@ CONFIG_AMIGA_BUILTIN_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
@@ -231,7 +232,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -686,8 +686,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/mvme147_defconfig
+1 -3
View File
@@ -18,6 +18,7 @@ CONFIG_MVME147=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -209,7 +210,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -572,8 +572,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/mvme16x_defconfig
+1 -3
View File
@@ -19,6 +19,7 @@ CONFIG_MVME16x=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -210,7 +211,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -573,8 +573,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/q40_defconfig
+1 -3
View File
@@ -19,6 +19,7 @@ CONFIG_HEARTBEAT=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -211,7 +212,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -590,8 +590,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/sun3_defconfig
+1 -3
View File
@@ -16,6 +16,7 @@ CONFIG_SUN3=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -206,7 +207,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -570,8 +570,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/configs/sun3x_defconfig
+1 -3
View File
@@ -16,6 +16,7 @@ CONFIG_SUN3X=y
CONFIG_PROC_HARDWARE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_ATARI_PARTITION=y
@@ -207,7 +208,6 @@ CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
CONFIG_NFT_DUP_IPV6=m
@@ -571,8 +571,6 @@ CONFIG_REED_SOLOMON_TEST=m
CONFIG_ATOMIC64_SELFTEST=m
CONFIG_ASYNC_RAID6_TEST=m
CONFIG_TEST_HEXDUMP=m
CONFIG_STRING_SELFTEST=m
CONFIG_TEST_STRING_HELPERS=m
CONFIG_TEST_KSTRTOX=m
CONFIG_TEST_PRINTF=m
CONFIG_TEST_SCANF=m
arch/m68k/include/asm/thread_info.h
+5 -4
View File
@@ -12,14 +12,15 @@
*/
#if PAGE_SHIFT < 13
#ifdef CONFIG_4KSTACKS
#define THREAD_SIZE 4096
#define THREAD_SIZE_ORDER 0
#else
#define THREAD_SIZE 8192
#define THREAD_SIZE_ORDER 1
#endif
#else
#define THREAD_SIZE PAGE_SIZE
#define THREAD_SIZE_ORDER 0
#endif
#define THREAD_SIZE_ORDER ((THREAD_SIZE / PAGE_SIZE) - 1)
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
#ifndef __ASSEMBLY__
arch/m68k/kernel/entry.S
+3 -1
View File
@@ -430,7 +430,9 @@ resume:
movec %a0,%dfc
/* restore status register */
movew %a1@(TASK_THREAD+THREAD_SR),%sr
movew %a1@(TASK_THREAD+THREAD_SR),%d0
oriw #0x0700,%d0
movew %d0,%sr
rts
arch/m68k/mac/misc.c
+18 -18
View File
@@ -453,30 +453,18 @@ void mac_poweroff(void)
void mac_reset(void)
{
if (macintosh_config->adb_type == MAC_ADB_II &&
macintosh_config->ident != MAC_MODEL_SE30) {
/* need ROMBASE in booter */
/* indeed, plus need to MAP THE ROM !! */
if (mac_bi_data.rombase == 0)
mac_bi_data.rombase = 0x40800000;
/* works on some */
rom_reset = (void *) (mac_bi_data.rombase + 0xa);
local_irq_disable();
rom_reset();
#ifdef CONFIG_ADB_CUDA
} else if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
if (macintosh_config->adb_type == MAC_ADB_EGRET ||
macintosh_config->adb_type == MAC_ADB_CUDA) {
cuda_restart();
} else
#endif
#ifdef CONFIG_ADB_PMU
} else if (macintosh_config->adb_type == MAC_ADB_PB2) {
if (macintosh_config->adb_type == MAC_ADB_PB2) {
pmu_restart();
} else
#endif
} else if (CPU_IS_030) {
if (CPU_IS_030) {
/* 030-specific reset routine. The idea is general, but the
* specific registers to reset are '030-specific. Until I
* have a non-030 machine, I can't test anything else.
@@ -524,6 +512,18 @@ void mac_reset(void)
"jmp %/a0@\n\t" /* jump to the reset vector */
".chip 68k"
: : "r" (offset), "a" (rombase) : "a0");
} else {
/* need ROMBASE in booter */
/* indeed, plus need to MAP THE ROM !! */
if (mac_bi_data.rombase == 0)
mac_bi_data.rombase = 0x40800000;
/* works on some */
rom_reset = (void *)(mac_bi_data.rombase + 0xa);
local_irq_disable();
rom_reset();
}
/* should never get here */
arch/mips/dec/setup.c
+1 -1
View File
@@ -756,7 +756,7 @@ void __init arch_init_irq(void)
NULL))
pr_err("Failed to register fpu interrupt\n");
desc_fpu = irq_to_desc(irq_fpu);
fpu_kstat_irq = this_cpu_ptr(desc_fpu->kstat_irqs);
fpu_kstat_irq = this_cpu_ptr(&desc_fpu->kstat_irqs->cnt);
}
if (dec_interrupt[DEC_IRQ_CASCADE] >= 0) {
if (request_irq(dec_interrupt[DEC_IRQ_CASCADE], no_action,
arch/openrisc/Kconfig
+9
View File
@@ -188,6 +188,15 @@ config SMP
If you don't know what to do here, say N.
config FPU
bool "FPU support"
default y
help
Say N here if you want to disable all floating-point related procedures
in the kernel and reduce binary size.
If you don't know what to do here, say Y.
source "kernel/Kconfig.hz"
config OPENRISC_NO_SPR_SR_DSX
arch/openrisc/include/asm/fpu.h
+22
View File
@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_OPENRISC_FPU_H
#define __ASM_OPENRISC_FPU_H
struct task_struct;
#ifdef CONFIG_FPU
static inline void save_fpu(struct task_struct *task)
{
task->thread.fpcsr = mfspr(SPR_FPCSR);
}
static inline void restore_fpu(struct task_struct *task)
{
mtspr(SPR_FPCSR, task->thread.fpcsr);
}
#else
#define save_fpu(tsk) do { } while (0)
#define restore_fpu(tsk) do { } while (0)
#endif
#endif /* __ASM_OPENRISC_FPU_H */
arch/openrisc/include/asm/processor.h
+1
View File
@@ -44,6 +44,7 @@
struct task_struct;
struct thread_struct {
long fpcsr; /* Floating point control status register. */
};
/*
arch/openrisc/include/asm/ptrace.h
+1 -2
View File
@@ -59,7 +59,7 @@ struct pt_regs {
* -1 for all other exceptions.
*/
long orig_gpr11; /* For restarting system calls */
long fpcsr; /* Floating point control status register. */
long dummy; /* Cheap alignment fix */
long dummy2; /* Cheap alignment fix */
};
@@ -115,6 +115,5 @@ static inline long regs_return_value(struct pt_regs *regs)
#define PT_GPR31 124
#define PT_PC 128
#define PT_ORIG_GPR11 132
#define PT_FPCSR 136
#endif /* __ASM_OPENRISC_PTRACE_H */
arch/openrisc/include/uapi/asm/elf.h
+66 -9
View File
@@ -34,15 +34,72 @@
#include <asm/ptrace.h>
/* The OR1K relocation types... not all relevant for module loader */
#define R_OR32_NONE 0
#define R_OR32_32 1
#define R_OR32_16 2
#define R_OR32_8 3
#define R_OR32_CONST 4
#define R_OR32_CONSTH 5
#define R_OR32_JUMPTARG 6
#define R_OR32_VTINHERIT 7
#define R_OR32_VTENTRY 8
#define R_OR1K_NONE 0
#define R_OR1K_32 1
#define R_OR1K_16 2
#define R_OR1K_8 3
#define R_OR1K_LO_16_IN_INSN 4
#define R_OR1K_HI_16_IN_INSN 5
#define R_OR1K_INSN_REL_26 6
#define R_OR1K_GNU_VTENTRY 7
#define R_OR1K_GNU_VTINHERIT 8
#define R_OR1K_32_PCREL 9
#define R_OR1K_16_PCREL 10
#define R_OR1K_8_PCREL 11
#define R_OR1K_GOTPC_HI16 12
#define R_OR1K_GOTPC_LO16 13
#define R_OR1K_GOT16 14
#define R_OR1K_PLT26 15
#define R_OR1K_GOTOFF_HI16 16
#define R_OR1K_GOTOFF_LO16 17
#define R_OR1K_COPY 18
#define R_OR1K_GLOB_DAT 19
#define R_OR1K_JMP_SLOT 20
#define R_OR1K_RELATIVE 21
#define R_OR1K_TLS_GD_HI16 22
#define R_OR1K_TLS_GD_LO16 23
#define R_OR1K_TLS_LDM_HI16 24
#define R_OR1K_TLS_LDM_LO16 25
#define R_OR1K_TLS_LDO_HI16 26
#define R_OR1K_TLS_LDO_LO16 27
#define R_OR1K_TLS_IE_HI16 28
#define R_OR1K_TLS_IE_LO16 29
#define R_OR1K_TLS_LE_HI16 30
#define R_OR1K_TLS_LE_LO16 31
#define R_OR1K_TLS_TPOFF 32
#define R_OR1K_TLS_DTPOFF 33
#define R_OR1K_TLS_DTPMOD 34
#define R_OR1K_AHI16 35
#define R_OR1K_GOTOFF_AHI16 36
#define R_OR1K_TLS_IE_AHI16 37
#define R_OR1K_TLS_LE_AHI16 38
#define R_OR1K_SLO16 39
#define R_OR1K_GOTOFF_SLO16 40
#define R_OR1K_TLS_LE_SLO16 41
#define R_OR1K_PCREL_PG21 42
#define R_OR1K_GOT_PG21 43
#define R_OR1K_TLS_GD_PG21 44
#define R_OR1K_TLS_LDM_PG21 45
#define R_OR1K_TLS_IE_PG21 46
#define R_OR1K_LO13 47
#define R_OR1K_GOT_LO13 48
#define R_OR1K_TLS_GD_LO13 49
#define R_OR1K_TLS_LDM_LO13 50
#define R_OR1K_TLS_IE_LO13 51
#define R_OR1K_SLO13 52
#define R_OR1K_PLTA26 53
#define R_OR1K_GOT_AHI16 54
/* Old relocation names */
#define R_OR32_NONE R_OR1K_NONE
#define R_OR32_32 R_OR1K_32
#define R_OR32_16 R_OR1K_16
#define R_OR32_8 R_OR1K_8
#define R_OR32_CONST R_OR1K_LO_16_IN_INSN
#define R_OR32_CONSTH R_OR1K_HI_16_IN_INSN
#define R_OR32_JUMPTARG R_OR1K_INSN_REL_26
#define R_OR32_VTENTRY R_OR1K_GNU_VTENTRY
#define R_OR32_VTINHERIT R_OR1K_GNU_VTINHERIT
typedef unsigned long elf_greg_t;
arch/openrisc/kernel/entry.S
+1 -14
View File
@@ -106,8 +106,6 @@
l.mtspr r0,r3,SPR_EPCR_BASE ;\
l.lwz r3,PT_SR(r1) ;\
l.mtspr r0,r3,SPR_ESR_BASE ;\
l.lwz r3,PT_FPCSR(r1) ;\
l.mtspr r0,r3,SPR_FPCSR ;\
l.lwz r2,PT_GPR2(r1) ;\
l.lwz r3,PT_GPR3(r1) ;\
l.lwz r4,PT_GPR4(r1) ;\
@@ -177,8 +175,6 @@ handler: ;\
/* r30 already save */ ;\
l.sw PT_GPR31(r1),r31 ;\
TRACE_IRQS_OFF_ENTRY ;\
l.mfspr r30,r0,SPR_FPCSR ;\
l.sw PT_FPCSR(r1),r30 ;\
/* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
l.addi r30,r0,-1 ;\
l.sw PT_ORIG_GPR11(r1),r30
@@ -219,8 +215,6 @@ handler: ;\
/* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
l.addi r30,r0,-1 ;\
l.sw PT_ORIG_GPR11(r1),r30 ;\
l.mfspr r30,r0,SPR_FPCSR ;\
l.sw PT_FPCSR(r1),r30 ;\
l.addi r3,r1,0 ;\
/* r4 is exception EA */ ;\
l.addi r5,r0,vector ;\
@@ -852,6 +846,7 @@ _syscall_badsys:
EXCEPTION_ENTRY(_fpe_trap_handler)
CLEAR_LWA_FLAG(r3)
/* r4: EA of fault (set by EXCEPTION_HANDLE) */
l.jal do_fpe_trap
l.addi r3,r1,0 /* pt_regs */
@@ -1100,10 +1095,6 @@ ENTRY(_switch)
l.sw PT_GPR28(r1),r28
l.sw PT_GPR30(r1),r30
/* Store the old FPU state to new pt_regs */
l.mfspr r29,r0,SPR_FPCSR
l.sw PT_FPCSR(r1),r29
l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
/* We use thread_info->ksp for storing the address of the above
@@ -1126,10 +1117,6 @@ ENTRY(_switch)
l.lwz r29,PT_SP(r1)
l.sw TI_KSP(r10),r29
/* Restore the old value of FPCSR */
l.lwz r29,PT_FPCSR(r1)
l.mtspr r0,r29,SPR_FPCSR
/* ...and restore the registers, except r11 because the return value
* has already been set above.
*/
arch/openrisc/kernel/module.c
+14 -4
View File
@@ -39,22 +39,32 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
value = sym->st_value + rel[i].r_addend;
switch (ELF32_R_TYPE(rel[i].r_info)) {
case R_OR32_32:
case R_OR1K_32:
*location = value;
break;
case R_OR32_CONST:
case R_OR1K_LO_16_IN_INSN:
*((uint16_t *)location + 1) = value;
break;
case R_OR32_CONSTH:
case R_OR1K_HI_16_IN_INSN:
*((uint16_t *)location + 1) = value >> 16;
break;
case R_OR32_JUMPTARG:
case R_OR1K_INSN_REL_26:
value -= (uint32_t)location;
value >>= 2;
value &= 0x03ffffff;
value |= *location & 0xfc000000;
*location = value;
break;
case R_OR1K_AHI16:
/* Adjust the operand to match with a signed LO16. */
value += 0x8000;
*((uint16_t *)location + 1) = value >> 16;
break;
case R_OR1K_SLO16:
/* Split value lower 16-bits. */
value = ((value & 0xf800) << 10) | (value & 0x7ff);
*location = (*location & ~0x3e007ff) | value;
break;
default:
pr_err("module %s: Unknown relocation: %u\n",
me->name, ELF32_R_TYPE(rel[i].r_info));
arch/openrisc/kernel/process.c
+8 -5
View File
@@ -36,6 +36,7 @@
#include <linux/reboot.h>
#include <linux/uaccess.h>
#include <asm/fpu.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/spr_defs.h>
@@ -65,7 +66,7 @@ void machine_restart(char *cmd)
}
/*
* This is used if pm_power_off has not been set by a power management
* This is used if a sys-off handler was not set by a power management
* driver, in this case we can assume we are on a simulator. On
* OpenRISC simulators l.nop 1 will trigger the simulator exit.
*/
@@ -89,10 +90,8 @@ void machine_halt(void)
void machine_power_off(void)
{
printk(KERN_INFO "*** MACHINE POWER OFF ***\n");
if (pm_power_off != NULL)
pm_power_off();
else
default_power_off();
do_kernel_power_off();
default_power_off();
}
/*
@@ -246,6 +245,8 @@ struct task_struct *__switch_to(struct task_struct *old,
local_irq_save(flags);
save_fpu(current);
/* current_set is an array of saved current pointers
* (one for each cpu). we need them at user->kernel transition,
* while we save them at kernel->user transition
@@ -258,6 +259,8 @@ struct task_struct *__switch_to(struct task_struct *old,
current_thread_info_set[smp_processor_id()] = new_ti;
last = (_switch(old_ti, new_ti))->task;
restore_fpu(current);
local_irq_restore(flags);
return last;
arch/openrisc/kernel/ptrace.c
+9 -9
View File
@@ -88,6 +88,7 @@ static int genregs_set(struct task_struct *target,
return ret;
}
#ifdef CONFIG_FPU
/*
* As OpenRISC shares GPRs and floating point registers we don't need to export
* the floating point registers again. So here we only export the fpcsr special
@@ -97,9 +98,7 @@ static int fpregs_get(struct task_struct *target,
const struct user_regset *regset,
struct membuf to)
{
const struct pt_regs *regs = task_pt_regs(target);
return membuf_store(&to, regs->fpcsr);
return membuf_store(&to, target->thread.fpcsr);
}
static int fpregs_set(struct task_struct *target,
@@ -107,21 +106,20 @@ static int fpregs_set(struct task_struct *target,
unsigned int pos, unsigned int count,
const void *kbuf, const void __user *ubuf)
{
struct pt_regs *regs = task_pt_regs(target);
int ret;
/* FPCSR */
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
&regs->fpcsr, 0, 4);
return ret;
return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
&target->thread.fpcsr, 0, 4);
}
#endif
/*
* Define the register sets available on OpenRISC under Linux
*/
enum or1k_regset {
REGSET_GENERAL,
#ifdef CONFIG_FPU
REGSET_FPU,
#endif
};
static const struct user_regset or1k_regsets[] = {
@@ -133,6 +131,7 @@ static const struct user_regset or1k_regsets[] = {
.regset_get = genregs_get,
.set = genregs_set,
},
#ifdef CONFIG_FPU
[REGSET_FPU] = {
.core_note_type = NT_PRFPREG,
.n = sizeof(struct __or1k_fpu_state) / sizeof(long),
@@ -141,6 +140,7 @@ static const struct user_regset or1k_regsets[] = {
.regset_get = fpregs_get,
.set = fpregs_set,
},
#endif
};
static const struct user_regset_view user_or1k_native_view = {
arch/openrisc/kernel/signal.c
+34 -2
View File
@@ -23,6 +23,7 @@
#include <linux/stddef.h>
#include <linux/resume_user_mode.h>
#include <asm/fpu.h>
#include <asm/processor.h>
#include <asm/syscall.h>
#include <asm/ucontext.h>
@@ -39,6 +40,37 @@ asmlinkage long _sys_rt_sigreturn(struct pt_regs *regs);
asmlinkage int do_work_pending(struct pt_regs *regs, unsigned int thread_flags,
int syscall);
#ifdef CONFIG_FPU
static long restore_fp_state(struct sigcontext __user *sc)
{
long err;
err = __copy_from_user(&current->thread.fpcsr, &sc->fpcsr, sizeof(unsigned long));
if (unlikely(err))
return err;
/* Restore the FPU state */
restore_fpu(current);
return 0;
}
static long save_fp_state(struct sigcontext __user *sc)
{
long err;
/* Sync the user FPU state so we can copy to sigcontext */
save_fpu(current);
err = __copy_to_user(&sc->fpcsr, &current->thread.fpcsr, sizeof(unsigned long));
return err;
}
#else
#define save_fp_state(sc) (0)
#define restore_fp_state(sc) (0)
#endif
static int restore_sigcontext(struct pt_regs *regs,
struct sigcontext __user *sc)
{
@@ -55,7 +87,7 @@ static int restore_sigcontext(struct pt_regs *regs,
err |= __copy_from_user(regs, sc->regs.gpr, 32 * sizeof(unsigned long));
err |= __copy_from_user(&regs->pc, &sc->regs.pc, sizeof(unsigned long));
err |= __copy_from_user(&regs->sr, &sc->regs.sr, sizeof(unsigned long));
err |= __copy_from_user(&regs->fpcsr, &sc->fpcsr, sizeof(unsigned long));
err |= restore_fp_state(sc);
/* make sure the SM-bit is cleared so user-mode cannot fool us */
regs->sr &= ~SPR_SR_SM;
@@ -118,7 +150,7 @@ static int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
err |= __copy_to_user(sc->regs.gpr, regs, 32 * sizeof(unsigned long));
err |= __copy_to_user(&sc->regs.pc, &regs->pc, sizeof(unsigned long));
err |= __copy_to_user(&sc->regs.sr, &regs->sr, sizeof(unsigned long));
err |= __copy_to_user(&sc->fpcsr, &regs->fpcsr, sizeof(unsigned long));
err |= save_fp_state(sc);
return err;
}
arch/openrisc/kernel/traps.c
+74 -62
View File
@@ -31,6 +31,7 @@
#include <linux/uaccess.h>
#include <asm/bug.h>
#include <asm/fpu.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/unwinder.h>
@@ -51,16 +52,16 @@ static void print_trace(void *data, unsigned long addr, int reliable)
{
const char *loglvl = data;
printk("%s[<%p>] %s%pS\n", loglvl, (void *) addr, reliable ? "" : "? ",
(void *) addr);
pr_info("%s[<%p>] %s%pS\n", loglvl, (void *) addr, reliable ? "" : "? ",
(void *) addr);
}
static void print_data(unsigned long base_addr, unsigned long word, int i)
{
if (i == 0)
printk("(%08lx:)\t%08lx", base_addr + (i * 4), word);
pr_info("(%08lx:)\t%08lx", base_addr + (i * 4), word);
else
printk(" %08lx:\t%08lx", base_addr + (i * 4), word);
pr_info(" %08lx:\t%08lx", base_addr + (i * 4), word);
}
/* displays a short stack trace */
@@ -69,7 +70,7 @@ void show_stack(struct task_struct *task, unsigned long *esp, const char *loglvl
if (esp == NULL)
esp = (unsigned long *)&esp;
printk("%sCall trace:\n", loglvl);
pr_info("%sCall trace:\n", loglvl);
unwind_stack((void *)loglvl, esp, print_trace);
}
@@ -83,57 +84,56 @@ void show_registers(struct pt_regs *regs)
if (user_mode(regs))
in_kernel = 0;
printk("CPU #: %d\n"
" PC: %08lx SR: %08lx SP: %08lx FPCSR: %08lx\n",
smp_processor_id(), regs->pc, regs->sr, regs->sp,
regs->fpcsr);
printk("GPR00: %08lx GPR01: %08lx GPR02: %08lx GPR03: %08lx\n",
0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]);
printk("GPR04: %08lx GPR05: %08lx GPR06: %08lx GPR07: %08lx\n",
regs->gpr[4], regs->gpr[5], regs->gpr[6], regs->gpr[7]);
printk("GPR08: %08lx GPR09: %08lx GPR10: %08lx GPR11: %08lx\n",
regs->gpr[8], regs->gpr[9], regs->gpr[10], regs->gpr[11]);
printk("GPR12: %08lx GPR13: %08lx GPR14: %08lx GPR15: %08lx\n",
regs->gpr[12], regs->gpr[13], regs->gpr[14], regs->gpr[15]);
printk("GPR16: %08lx GPR17: %08lx GPR18: %08lx GPR19: %08lx\n",
regs->gpr[16], regs->gpr[17], regs->gpr[18], regs->gpr[19]);
printk("GPR20: %08lx GPR21: %08lx GPR22: %08lx GPR23: %08lx\n",
regs->gpr[20], regs->gpr[21], regs->gpr[22], regs->gpr[23]);
printk("GPR24: %08lx GPR25: %08lx GPR26: %08lx GPR27: %08lx\n",
regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]);
printk("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n",
regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]);
printk(" RES: %08lx oGPR11: %08lx\n",
regs->gpr[11], regs->orig_gpr11);
pr_info("CPU #: %d\n"
" PC: %08lx SR: %08lx SP: %08lx\n",
smp_processor_id(), regs->pc, regs->sr, regs->sp);
pr_info("GPR00: %08lx GPR01: %08lx GPR02: %08lx GPR03: %08lx\n",
0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]);
pr_info("GPR04: %08lx GPR05: %08lx GPR06: %08lx GPR07: %08lx\n",
regs->gpr[4], regs->gpr[5], regs->gpr[6], regs->gpr[7]);
pr_info("GPR08: %08lx GPR09: %08lx GPR10: %08lx GPR11: %08lx\n",
regs->gpr[8], regs->gpr[9], regs->gpr[10], regs->gpr[11]);
pr_info("GPR12: %08lx GPR13: %08lx GPR14: %08lx GPR15: %08lx\n",
regs->gpr[12], regs->gpr[13], regs->gpr[14], regs->gpr[15]);
pr_info("GPR16: %08lx GPR17: %08lx GPR18: %08lx GPR19: %08lx\n",
regs->gpr[16], regs->gpr[17], regs->gpr[18], regs->gpr[19]);
pr_info("GPR20: %08lx GPR21: %08lx GPR22: %08lx GPR23: %08lx\n",
regs->gpr[20], regs->gpr[21], regs->gpr[22], regs->gpr[23]);
pr_info("GPR24: %08lx GPR25: %08lx GPR26: %08lx GPR27: %08lx\n",
regs->gpr[24], regs->gpr[25], regs->gpr[26], regs->gpr[27]);
pr_info("GPR28: %08lx GPR29: %08lx GPR30: %08lx GPR31: %08lx\n",
regs->gpr[28], regs->gpr[29], regs->gpr[30], regs->gpr[31]);
pr_info(" RES: %08lx oGPR11: %08lx\n",
regs->gpr[11], regs->orig_gpr11);
printk("Process %s (pid: %d, stackpage=%08lx)\n",
current->comm, current->pid, (unsigned long)current);
pr_info("Process %s (pid: %d, stackpage=%08lx)\n",
current->comm, current->pid, (unsigned long)current);
/*
* When in-kernel, we also print out the stack and code at the
* time of the fault..
*/
if (in_kernel) {
printk("\nStack: ");
pr_info("\nStack: ");
show_stack(NULL, (unsigned long *)esp, KERN_EMERG);
if (esp < PAGE_OFFSET)
goto bad_stack;
printk("\n");
pr_info("\n");
for (i = -8; i < 24; i += 1) {
unsigned long word;
if (__get_user(word, &((unsigned long *)esp)[i])) {
bad_stack:
printk(" Bad Stack value.");
pr_info(" Bad Stack value.");
break;
}
print_data(esp, word, i);
}
printk("\nCode: ");
pr_info("\nCode: ");
if (regs->pc < PAGE_OFFSET)
goto bad;
@@ -142,14 +142,14 @@ bad_stack:
if (__get_user(word, &((unsigned long *)regs->pc)[i])) {
bad:
printk(" Bad PC value.");
pr_info(" Bad PC value.");
break;
}
print_data(regs->pc, word, i);
}
}
printk("\n");
pr_info("\n");
}
/* This is normally the 'Oops' routine */
@@ -157,10 +157,10 @@ void __noreturn die(const char *str, struct pt_regs *regs, long err)
{
console_verbose();
printk("\n%s#: %04lx\n", str, err & 0xffff);
pr_emerg("\n%s#: %04lx\n", str, err & 0xffff);
show_registers(regs);
#ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
printk("\n\nUNHANDLED_EXCEPTION: entering infinite loop\n");
pr_emerg("\n\nUNHANDLED_EXCEPTION: entering infinite loop\n");
/* shut down interrupts */
local_irq_disable();
@@ -173,36 +173,51 @@ void __noreturn die(const char *str, struct pt_regs *regs, long err)
asmlinkage void unhandled_exception(struct pt_regs *regs, int ea, int vector)
{
printk("Unable to handle exception at EA =0x%x, vector 0x%x",
ea, vector);
pr_emerg("Unable to handle exception at EA =0x%x, vector 0x%x",
ea, vector);
die("Oops", regs, 9);
}
asmlinkage void do_fpe_trap(struct pt_regs *regs, unsigned long address)
{
int code = FPE_FLTUNK;
unsigned long fpcsr = regs->fpcsr;
if (user_mode(regs)) {
int code = FPE_FLTUNK;
#ifdef CONFIG_FPU
unsigned long fpcsr;
if (fpcsr & SPR_FPCSR_IVF)
code = FPE_FLTINV;
else if (fpcsr & SPR_FPCSR_OVF)
code = FPE_FLTOVF;
else if (fpcsr & SPR_FPCSR_UNF)
code = FPE_FLTUND;
else if (fpcsr & SPR_FPCSR_DZF)
code = FPE_FLTDIV;
else if (fpcsr & SPR_FPCSR_IXF)
code = FPE_FLTRES;
save_fpu(current);
fpcsr = current->thread.fpcsr;
/* Clear all flags */
regs->fpcsr &= ~SPR_FPCSR_ALLF;
if (fpcsr & SPR_FPCSR_IVF)
code = FPE_FLTINV;
else if (fpcsr & SPR_FPCSR_OVF)
code = FPE_FLTOVF;
else if (fpcsr & SPR_FPCSR_UNF)
code = FPE_FLTUND;
else if (fpcsr & SPR_FPCSR_DZF)
code = FPE_FLTDIV;
else if (fpcsr & SPR_FPCSR_IXF)
code = FPE_FLTRES;
force_sig_fault(SIGFPE, code, (void __user *)regs->pc);
/* Clear all flags */
current->thread.fpcsr &= ~SPR_FPCSR_ALLF;
restore_fpu(current);
#endif
force_sig_fault(SIGFPE, code, (void __user *)regs->pc);
} else {
pr_emerg("KERNEL: Illegal fpe exception 0x%.8lx\n", regs->pc);
die("Die:", regs, SIGFPE);
}
}
asmlinkage void do_trap(struct pt_regs *regs, unsigned long address)
{
force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->pc);
if (user_mode(regs)) {
force_sig_fault(SIGTRAP, TRAP_BRKPT, (void __user *)regs->pc);
} else {
pr_emerg("KERNEL: Illegal trap exception 0x%.8lx\n", regs->pc);
die("Die:", regs, SIGILL);
}
}
asmlinkage void do_unaligned_access(struct pt_regs *regs, unsigned long address)
@@ -211,8 +226,7 @@ asmlinkage void do_unaligned_access(struct pt_regs *regs, unsigned long address)
/* Send a SIGBUS */
force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)address);
} else {
printk("KERNEL: Unaligned Access 0x%.8lx\n", address);
show_registers(regs);
pr_emerg("KERNEL: Unaligned Access 0x%.8lx\n", address);
die("Die:", regs, address);
}
@@ -224,8 +238,7 @@ asmlinkage void do_bus_fault(struct pt_regs *regs, unsigned long address)
/* Send a SIGBUS */
force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)address);
} else { /* Kernel mode */
printk("KERNEL: Bus error (SIGBUS) 0x%.8lx\n", address);
show_registers(regs);
pr_emerg("KERNEL: Bus error (SIGBUS) 0x%.8lx\n", address);
die("Die:", regs, address);
}
}
@@ -419,9 +432,8 @@ asmlinkage void do_illegal_instruction(struct pt_regs *regs,
/* Send a SIGILL */
force_sig_fault(SIGILL, ILL_ILLOPC, (void __user *)address);
} else { /* Kernel mode */
printk("KERNEL: Illegal instruction (SIGILL) 0x%.8lx\n",
address);
show_registers(regs);
pr_emerg("KERNEL: Illegal instruction (SIGILL) 0x%.8lx\n",
address);
die("Die:", regs, address);
}
}
arch/parisc/kernel/smp.c
+1 -1
View File
@@ -344,7 +344,7 @@ static int smp_boot_one_cpu(int cpuid, struct task_struct *idle)
struct irq_desc *desc = irq_to_desc(i);
if (desc && desc->kstat_irqs)
*per_cpu_ptr(desc->kstat_irqs, cpuid) = 0;
*per_cpu_ptr(desc->kstat_irqs, cpuid) = (struct irqstat) { };
}
#endif
arch/powerpc/include/asm/vdso/gettimeofday.h
+11 -15
View File
@@ -13,6 +13,17 @@
#define VDSO_HAS_TIME 1
/*
* powerpc specific delta calculation.
*
* This variant removes the masking of the subtraction because the
* clocksource mask of all VDSO capable clocksources on powerpc is U64_MAX
* which would result in a pointless operation. The compiler cannot
* optimize it away as the mask comes from the vdso data and is not compile
* time constant.
*/
#define VDSO_DELTA_NOMASK 1
static __always_inline int do_syscall_2(const unsigned long _r0, const unsigned long _r3,
const unsigned long _r4)
{
@@ -104,21 +115,6 @@ static inline bool vdso_clocksource_ok(const struct vdso_data *vd)
}
#define vdso_clocksource_ok vdso_clocksource_ok
/*
* powerpc specific delta calculation.
*
* This variant removes the masking of the subtraction because the
* clocksource mask of all VDSO capable clocksources on powerpc is U64_MAX
* which would result in a pointless operation. The compiler cannot
* optimize it away as the mask comes from the vdso data and is not compile
* time constant.
*/
static __always_inline u64 vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult)
{
return (cycles - last) * mult;
}
#define vdso_calc_delta vdso_calc_delta
#ifndef __powerpc64__
static __always_inline u64 vdso_shift_ns(u64 ns, unsigned long shift)
{
arch/powerpc/kvm/book3s_hv_rm_xics.c
+1 -1
View File
@@ -837,7 +837,7 @@ static inline void this_cpu_inc_rm(unsigned int __percpu *addr)
*/
static void kvmppc_rm_handle_irq_desc(struct irq_desc *desc)
{
this_cpu_inc_rm(desc->kstat_irqs);
this_cpu_inc_rm(&desc->kstat_irqs->cnt);
__this_cpu_inc(kstat.irqs_sum);
}
arch/riscv/Kconfig
+2
View File
@@ -173,6 +173,8 @@ config RISCV
select PCI_DOMAINS_GENERIC if PCI
select PCI_MSI if PCI
select RISCV_ALTERNATIVE if !XIP_KERNEL
select RISCV_APLIC
select RISCV_IMSIC
select RISCV_INTC
select RISCV_TIMER if RISCV_SBI
select SIFIVE_PLIC
arch/s390/include/asm/vdso/gettimeofday.h
+2 -5
View File
@@ -6,16 +6,13 @@
#define VDSO_HAS_CLOCK_GETRES 1
#define VDSO_DELTA_NOMASK 1
#include <asm/syscall.h>
#include <asm/timex.h>
#include <asm/unistd.h>
#include <linux/compiler.h>
#define vdso_calc_delta __arch_vdso_calc_delta
static __always_inline u64 __arch_vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult)
{
return (cycles - last) * mult;
}
static __always_inline const struct vdso_data *__arch_get_vdso_data(void)
{
arch/sh/Kconfig
+2 -1
View File
@@ -125,7 +125,8 @@ config ARCH_HAS_ILOG2_U64
config NO_IOPORT_MAP
def_bool !PCI
depends on !SH_SHMIN && !SH_HP6XX && !SH_SOLUTION_ENGINE
depends on !SH_SHMIN && !SH_HP6XX && !SH_SOLUTION_ENGINE && \
!SH_DREAMCAST
config IO_TRAPPED
bool
arch/sh/boards/board-sh7757lcr.c
+1 -1
View File
@@ -569,7 +569,7 @@ static int __init sh7757lcr_devices_setup(void)
arch_initcall(sh7757lcr_devices_setup);
/* Initialize IRQ setting */
void __init init_sh7757lcr_IRQ(void)
static void __init init_sh7757lcr_IRQ(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ7654);
plat_irq_setup_pins(IRQ_MODE_IRQ3210);
arch/sh/boards/board-sh7785lcr.c
+1 -1
View File
@@ -295,7 +295,7 @@ static int __init sh7785lcr_devices_setup(void)
device_initcall(sh7785lcr_devices_setup);
/* Initialize IRQ setting */
void __init init_sh7785lcr_IRQ(void)
static void __init init_sh7785lcr_IRQ(void)
{
plat_irq_setup_pins(IRQ_MODE_IRQ7654);
plat_irq_setup_pins(IRQ_MODE_IRQ3210);
arch/sh/boards/mach-dreamcast/setup.c
+3
View File
@@ -25,10 +25,13 @@
#include <asm/irq.h>
#include <asm/rtc.h>
#include <asm/machvec.h>
#include <cpu/addrspace.h>
#include <mach/sysasic.h>
static void __init dreamcast_setup(char **cmdline_p)
{
/* GAPS PCI bridge assumes P2 area relative addresses. */
__set_io_port_base(P2SEG);
}
static struct sh_machine_vector mv_dreamcast __initmv = {
arch/sh/boards/mach-highlander/pinmux-r7785rp.c
+1
View File
@@ -5,6 +5,7 @@
#include <linux/init.h>
#include <linux/gpio.h>
#include <cpu/sh7785.h>
#include <mach/highlander.h>
void __init highlander_plat_pinmux_setup(void)
{
arch/sh/boards/mach-sh03/rtc.c
+1 -1
View File
@@ -120,7 +120,7 @@ static int set_rtc_mmss(struct rtc_time *tm)
return retval;
}
int sh03_rtc_settimeofday(struct device *dev, struct rtc_time *tm)
static int sh03_rtc_settimeofday(struct device *dev, struct rtc_time *tm)
{
return set_rtc_mmss(tm);
}
arch/sh/boards/of-generic.c
+2
View File
@@ -10,6 +10,8 @@
#include <linux/of_fdt.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <asm/clock.h>
#include <asm/machvec.h>
#include <asm/rtc.h>
arch/sh/boot/compressed/Makefile
+1 -1
View File
@@ -5,7 +5,7 @@
# create a compressed vmlinux image from the original vmlinux
#
OBJECTS := head_32.o misc.o cache.o piggy.o \
OBJECTS := head_32.o misc.o piggy.o \
ashiftrt.o ashldi3.o ashrsi3.o ashlsi3.o lshrsi3.o
targets := vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 \
arch/sh/boot/compressed/cache.c
-13
View File
@@ -1,13 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
int cache_control(unsigned int command)
{
volatile unsigned int *p = (volatile unsigned int *) 0x80000000;
int i;
for (i = 0; i < (32 * 1024); i += 32) {
(void)*p;
p += (32 / sizeof(int));
}
return 0;
}
arch/sh/boot/compressed/misc.c
+2 -7
View File
@@ -16,6 +16,8 @@
#include <asm/addrspace.h>
#include <asm/page.h>
#include "misc.h"
/*
* gzip declarations
*/
@@ -26,11 +28,6 @@
#undef memcpy
#define memzero(s, n) memset ((s), 0, (n))
/* cache.c */
#define CACHE_ENABLE 0
#define CACHE_DISABLE 1
int cache_control(unsigned int command);
extern char input_data[];
extern int input_len;
static unsigned char *output;
@@ -139,8 +136,6 @@ void decompress_kernel(void)
free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
puts("Uncompressing Linux... ");
cache_control(CACHE_ENABLE);
__decompress(input_data, input_len, NULL, NULL, output, 0, NULL, error);
cache_control(CACHE_DISABLE);
puts("Ok, booting the kernel.\n");
}
arch/sh/boot/compressed/misc.h
+9
View File
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef MISC_H
#define MISC_H
void arch_ftrace_ops_list_func(void);
void decompress_kernel(void);
void ftrace_stub(void);
#endif /* MISC_H */
arch/sh/boot/dts/j2_mimas_v2.dts
-2
View File
@@ -71,8 +71,6 @@
#address-cells = <1>;
#size-cells = <0>;
spi-max-frequency = <25000000>;
reg = <0x40 0x8>;
sdcard@0 {
arch/sh/drivers/dma/dma-api.c
-143
View File
@@ -41,21 +41,6 @@ struct dma_info *get_dma_info(unsigned int chan)
}
EXPORT_SYMBOL(get_dma_info);
struct dma_info *get_dma_info_by_name(const char *dmac_name)
{
struct dma_info *info;
list_for_each_entry(info, &registered_dmac_list, list) {
if (dmac_name && (strcmp(dmac_name, info->name) != 0))
continue;
else
return info;
}
return NULL;
}
EXPORT_SYMBOL(get_dma_info_by_name);
static unsigned int get_nr_channels(void)
{
struct dma_info *info;
@@ -101,93 +86,6 @@ int get_dma_residue(unsigned int chan)
}
EXPORT_SYMBOL(get_dma_residue);
static int search_cap(const char **haystack, const char *needle)
{
const char **p;
for (p = haystack; *p; p++)
if (strcmp(*p, needle) == 0)
return 1;
return 0;
}
/**
* request_dma_bycap - Allocate a DMA channel based on its capabilities
* @dmac: List of DMA controllers to search
* @caps: List of capabilities
*
* Search all channels of all DMA controllers to find a channel which
* matches the requested capabilities. The result is the channel
* number if a match is found, or %-ENODEV if no match is found.
*
* Note that not all DMA controllers export capabilities, in which
* case they can never be allocated using this API, and so
* request_dma() must be used specifying the channel number.
*/
int request_dma_bycap(const char **dmac, const char **caps, const char *dev_id)
{
unsigned int found = 0;
struct dma_info *info;
const char **p;
int i;
BUG_ON(!dmac || !caps);
list_for_each_entry(info, &registered_dmac_list, list)
if (strcmp(*dmac, info->name) == 0) {
found = 1;
break;
}
if (!found)
return -ENODEV;
for (i = 0; i < info->nr_channels; i++) {
struct dma_channel *channel = &info->channels[i];
if (unlikely(!channel->caps))
continue;
for (p = caps; *p; p++) {
if (!search_cap(channel->caps, *p))
break;
if (request_dma(channel->chan, dev_id) == 0)
return channel->chan;
}
}
return -EINVAL;
}
EXPORT_SYMBOL(request_dma_bycap);
int dmac_search_free_channel(const char *dev_id)
{
struct dma_channel *channel = { 0 };
struct dma_info *info = get_dma_info(0);
int i;
for (i = 0; i < info->nr_channels; i++) {
channel = &info->channels[i];
if (unlikely(!channel))
return -ENODEV;
if (atomic_read(&channel->busy) == 0)
break;
}
if (info->ops->request) {
int result = info->ops->request(channel);
if (result)
return result;
atomic_set(&channel->busy, 1);
return channel->chan;
}
return -ENOSYS;
}
int request_dma(unsigned int chan, const char *dev_id)
{
struct dma_channel *channel = { 0 };
@@ -240,35 +138,6 @@ void dma_wait_for_completion(unsigned int chan)
}
EXPORT_SYMBOL(dma_wait_for_completion);
int register_chan_caps(const char *dmac, struct dma_chan_caps *caps)
{
struct dma_info *info;
unsigned int found = 0;
int i;
list_for_each_entry(info, &registered_dmac_list, list)
if (strcmp(dmac, info->name) == 0) {
found = 1;
break;
}
if (unlikely(!found))
return -ENODEV;
for (i = 0; i < info->nr_channels; i++, caps++) {
struct dma_channel *channel;
if ((info->first_channel_nr + i) != caps->ch_num)
return -EINVAL;
channel = &info->channels[i];
channel->caps = caps->caplist;
}
return 0;
}
EXPORT_SYMBOL(register_chan_caps);
void dma_configure_channel(unsigned int chan, unsigned long flags)
{
struct dma_info *info = get_dma_info(chan);
@@ -294,18 +163,6 @@ int dma_xfer(unsigned int chan, unsigned long from,
}
EXPORT_SYMBOL(dma_xfer);
int dma_extend(unsigned int chan, unsigned long op, void *param)
{
struct dma_info *info = get_dma_info(chan);
struct dma_channel *channel = get_dma_channel(chan);
if (info->ops->extend)
return info->ops->extend(channel, op, param);
return -ENOSYS;
}
EXPORT_SYMBOL(dma_extend);
static int dma_proc_show(struct seq_file *m, void *v)
{
struct dma_info *info = v;
arch/sh/drivers/push-switch.c
+2 -4
View File
@@ -91,7 +91,7 @@ err:
return ret;
}
static int switch_drv_remove(struct platform_device *pdev)
static void switch_drv_remove(struct platform_device *pdev)
{
struct push_switch *psw = platform_get_drvdata(pdev);
struct push_switch_platform_info *psw_info = pdev->dev.platform_data;
@@ -106,13 +106,11 @@ static int switch_drv_remove(struct platform_device *pdev)
free_irq(irq, pdev);
kfree(psw);
return 0;
}
static struct platform_driver switch_driver = {
.probe = switch_drv_probe,
.remove = switch_drv_remove,
.remove_new = switch_drv_remove,
.driver = {
.name = DRV_NAME,
},
arch/sh/include/asm/cacheflush.h
+12
View File
@@ -104,6 +104,18 @@ void kunmap_coherent(void *kvaddr);
void cpu_cache_init(void);
void __weak l2_cache_init(void);
void __weak j2_cache_init(void);
void __weak sh2_cache_init(void);
void __weak sh2a_cache_init(void);
void __weak sh3_cache_init(void);
void __weak shx3_cache_init(void);
void __weak sh4_cache_init(void);
void __weak sh7705_cache_init(void);
void __weak sh4__flush_region_init(void);
static inline void *sh_cacheop_vaddr(void *vaddr)
{
if (__in_29bit_mode())
arch/sh/include/asm/dma.h
-7
View File
@@ -56,7 +56,6 @@ struct dma_ops {
int (*get_residue)(struct dma_channel *chan);
int (*xfer)(struct dma_channel *chan);
int (*configure)(struct dma_channel *chan, unsigned long flags);
int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
};
struct dma_channel {
@@ -118,8 +117,6 @@ extern int dma_xfer(unsigned int chan, unsigned long from,
#define dma_read_page(chan, from, to) \
dma_read(chan, from, to, PAGE_SIZE)
extern int request_dma_bycap(const char **dmac, const char **caps,
const char *dev_id);
extern int get_dma_residue(unsigned int chan);
extern struct dma_info *get_dma_info(unsigned int chan);
extern struct dma_channel *get_dma_channel(unsigned int chan);
@@ -128,10 +125,6 @@ extern void dma_configure_channel(unsigned int chan, unsigned long flags);
extern int register_dmac(struct dma_info *info);
extern void unregister_dmac(struct dma_info *info);
extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
extern int dma_extend(unsigned int chan, unsigned long op, void *param);
extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
/* arch/sh/drivers/dma/dma-sysfs.c */
extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
arch/sh/include/asm/fpu.h
+3
View File
@@ -64,6 +64,9 @@ static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs)
preempt_enable();
}
void float_raise(unsigned int flags);
int float_rounding_mode(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_FPU_H */
arch/sh/include/asm/ftrace.h
+10
View File
@@ -33,6 +33,8 @@ static inline unsigned long ftrace_call_adjust(unsigned long addr)
return addr;
}
void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_FUNCTION_TRACER */
@@ -43,6 +45,14 @@ extern void *return_address(unsigned int);
#define ftrace_return_address(n) return_address(n)
#ifdef CONFIG_DYNAMIC_FTRACE
extern void arch_ftrace_nmi_enter(void);
extern void arch_ftrace_nmi_exit(void);
#else
static inline void arch_ftrace_nmi_enter(void) { }
static inline void arch_ftrace_nmi_exit(void) { }
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_FTRACE_H */
arch/sh/include/asm/hw_breakpoint.h
+2
View File
@@ -52,6 +52,8 @@ struct pmu;
/* arch/sh/kernel/hw_breakpoint.c */
extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
extern int arch_bp_generic_fields(int sh_len, int sh_type, int *gen_len,
int *gen_type);
extern int hw_breakpoint_arch_parse(struct perf_event *bp,
const struct perf_event_attr *attr,
struct arch_hw_breakpoint *hw);
arch/sh/include/asm/setup.h
+1
View File
@@ -21,5 +21,6 @@
void sh_mv_setup(void);
void check_for_initrd(void);
void per_cpu_trap_init(void);
void sh_fdt_init(phys_addr_t dt_phys);
#endif /* _SH_SETUP_H */
arch/sh/include/asm/syscalls.h
+1
View File
@@ -8,6 +8,7 @@ asmlinkage int old_mmap(unsigned long addr, unsigned long len,
asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
unsigned long prot, unsigned long flags,
unsigned long fd, unsigned long pgoff);
asmlinkage int sys_cacheflush(unsigned long addr, unsigned long len, int op);
#include <asm/syscalls_32.h>
arch/sh/include/asm/tlb.h
+4
View File
@@ -24,6 +24,10 @@ static inline void tlb_unwire_entry(void)
BUG();
}
#endif /* CONFIG_CPU_SH4 */
asmlinkage int handle_tlbmiss(struct pt_regs *regs, unsigned long error_code,
unsigned long address);
#endif /* CONFIG_MMU */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_TLB_H */
arch/sh/kernel/cpu/sh2a/opcode_helper.c
+2
View File
@@ -8,6 +8,8 @@
*/
#include <linux/kernel.h>
#include <asm/processor.h>
/*
* Instructions on SH are generally fixed at 16-bits, however, SH-2A
* introduces some 32-bit instructions. Since there are no real
arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+3
View File
@@ -14,9 +14,12 @@
#include <linux/sh_timer.h>
#include <linux/sh_intc.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/clock.h>
#include <asm/mmzone.h>
#include <asm/platform_early.h>
#include <cpu/sh7723.h>
/* Serial */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+1
View File
@@ -21,6 +21,7 @@
#include <linux/io.h>
#include <linux/notifier.h>
#include <asm/cacheflush.h>
#include <asm/suspend.h>
#include <asm/clock.h>
#include <asm/mmzone.h>
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+3
View File
@@ -17,8 +17,11 @@
#include <linux/sh_dma.h>
#include <linux/sh_intc.h>
#include <linux/usb/ohci_pdriver.h>
#include <cpu/dma-register.h>
#include <cpu/sh7757.h>
#include <asm/mmzone.h>
#include <asm/platform_early.h>
static struct plat_sci_port scif2_platform_data = {

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