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PCI: tegra: Fixups to avoid unnecessary wakeup from ASPM-L1.2

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sets CLKREQ asserted delay to a higher value to avoid
unnecessary wake up from L1.2.ENTRY state for Tegra210

bug 200420606

Change-Id: Iec2564bfd434897f0e50cd3f0ad6bc76aacc12e8
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1786545
(cherry picked from commit d7785c1e6c98e33a85ba9487d3be6ab7e518a285)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.9/+/2407875
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vidya Sagar
2017-11-12 18:47:53 +05:30
committed by Thomas Makin
parent b011642f03
commit 00f1cf7c84
1 changed files with 19 additions and 0 deletions
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19
drivers/pci/controller/pci-tegra.c
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@@ -183,6 +183,8 @@
#define RP_L1_PM_SUBSTATES_1_CTL 0xc04
#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK 0x1fff
#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY 0x26
#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK (0x1ff << 13)
#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY (0x27 << 13)
#define RP_L1_PM_SUBSTATES_2_CTL 0xc08
#define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK 0x1fff
@@ -377,6 +379,7 @@ struct tegra_pcie_soc {
bool enable_wrap;
bool has_aspm_l1;
bool has_aspm_l1ss;
bool l1ss_rp_wake_fixup;
struct {
struct {
u32 rp_ectl_1_r1;
@@ -869,6 +872,17 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP;
writel(value, port->base + RP_L1_PM_SUBSTATES_2_CTL);
}
if (soc->l1ss_rp_wake_fixup) {
/*
* Set CLKREQ asserted delay greater than Power_Off
* time (2us) to avoid RP wakeup in L1.2.ENTRY
*/
value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL);
value &= ~RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK;
value |= RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY;
writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL);
}
}
static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
@@ -2629,6 +2643,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
.enable_wrap = false,
.has_aspm_l1 = false,
.has_aspm_l1ss = false,
.l1ss_rp_wake_fixup = false,
.ectl.enable = false,
};
@@ -2661,6 +2676,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
.enable_wrap = false,
.has_aspm_l1 = true,
.has_aspm_l1ss = false,
.l1ss_rp_wake_fixup = false,
.ectl.enable = false,
};
@@ -2685,6 +2701,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
.enable_wrap = false,
.has_aspm_l1 = true,
.has_aspm_l1ss = false,
.l1ss_rp_wake_fixup = false,
.ectl.enable = false,
};
@@ -2711,6 +2728,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
.enable_wrap = true,
.has_aspm_l1 = true,
.has_aspm_l1ss = true,
.l1ss_rp_wake_fixup = true,
.ectl = {
.regs = {
.rp_ectl_1_r1 = 0x0000001f,
@@ -2793,6 +2811,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
.enable_wrap = false,
.has_aspm_l1 = true,
.has_aspm_l1ss = true,
.l1ss_rp_wake_fixup = false,
.ectl.enable = false,
};