# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.

maintainers:
  - Andrew Lunn <andrew@lunn.ch>

description:
  This is a special case of a MDIO bus multiplexer.  One or more GPIO
  lines are used to control which child bus is connected.

allOf:
  - $ref: /schemas/net/mdio-mux.yaml#

properties:
  compatible:
    const: mdio-mux-gpio

  gpios:
    description:
      List of GPIOs used to control the multiplexer, least significant bit first.
    minItems: 1
    maxItems: 32

required:
  - compatible
  - gpios

unevaluatedProperties: false

examples:
  - |
    /*
     An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
     pair of GPIO lines.  Child busses 2 and 3 populated with 4
     PHYs each.
     */
    mdio-mux {
        compatible = "mdio-mux-gpio";
        gpios = <&gpio1 3 0>, <&gpio1 4 0>;
        mdio-parent-bus = <&smi1>;
        #address-cells = <1>;
        #size-cells = <0>;

        mdio@2 {
            reg = <2>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-phy@1 {
                reg = <1>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
            ethernet-phy@2 {
                reg = <2>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
            ethernet-phy@3 {
                reg = <3>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
            ethernet-phy@4 {
                reg = <4>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <10 8>; /* Pin 10, active low */
            };
        };

        mdio@3 {
            reg = <3>;
            #address-cells = <1>;
            #size-cells = <0>;

            ethernet-phy@1 {
                reg = <1>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
            ethernet-phy@2 {
                reg = <2>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
            ethernet-phy@3 {
                reg = <3>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
            ethernet-phy@4 {
                reg = <4>;
                marvell,reg-init = <3 0x10 0 0x5777>,
                  <3 0x11 0 0x00aa>,
                  <3 0x12 0 0x4105>,
                  <3 0x13 0 0x0a60>;
                interrupt-parent = <&gpio>;
                interrupts = <12 8>; /* Pin 12, active low */
            };
        };
    };
...
