# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic S4 Peripherals Clock Controller

maintainers:
  - Yu Tu <yu.tu@amlogic.com>

properties:
  compatible:
    const: amlogic,s4-peripherals-clkc

  reg:
    maxItems: 1

  clocks:
    minItems: 14
    items:
      - description: input fixed pll div2
      - description: input fixed pll div2p5
      - description: input fixed pll div3
      - description: input fixed pll div4
      - description: input fixed pll div5
      - description: input fixed pll div7
      - description: input hifi pll
      - description: input gp0 pll
      - description: input mpll0
      - description: input mpll1
      - description: input mpll2
      - description: input mpll3
      - description: input hdmi pll
      - description: input oscillator (usually at 24MHz)
      - description: input external 32kHz reference (optional)

  clock-names:
    minItems: 14
    items:
      - const: fclk_div2
      - const: fclk_div2p5
      - const: fclk_div3
      - const: fclk_div4
      - const: fclk_div5
      - const: fclk_div7
      - const: hifi_pll
      - const: gp0_pll
      - const: mpll0
      - const: mpll1
      - const: mpll2
      - const: mpll3
      - const: hdmi_pll
      - const: xtal
      - const: ext_32k

  "#clock-cells":
    const: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#clock-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>

    clkc_periphs: clock-controller@fe000000 {
      compatible = "amlogic,s4-peripherals-clkc";
      reg = <0xfe000000 0x49c>;
      clocks = <&clkc_pll 3>,
              <&clkc_pll 13>,
              <&clkc_pll 5>,
              <&clkc_pll 7>,
              <&clkc_pll 9>,
              <&clkc_pll 11>,
              <&clkc_pll 17>,
              <&clkc_pll 15>,
              <&clkc_pll 25>,
              <&clkc_pll 27>,
              <&clkc_pll 29>,
              <&clkc_pll 31>,
              <&clkc_pll 20>,
              <&xtal>;
      clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",
                    "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",
                    "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal";
      #clock-cells = <1>;
    };
...
