# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MotorComm yt8xxx Ethernet PHY

maintainers:
  - Frank Sae <frank.sae@motor-comm.com>

allOf:
  - $ref: ethernet-phy.yaml#

properties:
  compatible:
    enum:
      - ethernet-phy-id4f51.e91a
      - ethernet-phy-id4f51.e91b

  rx-internal-delay-ps:
    description: |
      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650,
            1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800,
            2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ]
    default: 1950

  tx-internal-delay-ps:
    description: |
      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
    enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800,
            1950, 2100, 2250 ]
    default: 1950

  motorcomm,clk-out-frequency-hz:
    description: clock output on clock output pin.
    enum: [0, 25000000, 125000000]
    default: 0

  motorcomm,keep-pll-enabled:
    description: |
      If set, keep the PLL enabled even if there is no link. Useful if you
      want to use the clock output without an ethernet link.
    type: boolean

  motorcomm,auto-sleep-disabled:
    description: |
      If set, PHY will not enter sleep mode and close AFE after unplug cable
      for a timer.
    type: boolean

  motorcomm,rx-clk-drv-microamp:
    description: |
      drive strength of rx_clk rgmii pad.
      The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
      be configured with hardware pull-up resistors to match the SOC voltage
      (usually 1.8V).
      The software can read the registers to obtain the LDO voltage and configure
      the legal drive strength(curren).
      =====================================================
      | voltage |        current Available (uA)           |
      |   1.8v  | 1200 2100 2700 2910 3110 3600 3970 4350 |
      |   3.3v  | 3070 4080 4370 4680 5020 5450 5740 6140 |
      =====================================================
    enum: [ 1200, 2100, 2700, 2910, 3070, 3110, 3600, 3970,
            4080, 4350, 4370, 4680, 5020, 5450, 5740, 6140 ]
    default: 2910

  motorcomm,rx-data-drv-microamp:
    description: |
      drive strength of rx_data/rx_ctl rgmii pad.
      The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
      be configured with hardware pull-up resistors to match the SOC voltage
      (usually 1.8V).
      The software can read the registers to obtain the LDO voltage and configure
      the legal drive strength(curren).
      =====================================================
      | voltage |        current Available (uA)           |
      |   1.8v  | 1200 2100 2700 2910 3110 3600 3970 4350 |
      |   3.3v  | 3070 4080 4370 4680 5020 5450 5740 6140 |
      =====================================================
    enum: [ 1200, 2100, 2700, 2910, 3070, 3110, 3600, 3970,
            4080, 4350, 4370, 4680, 5020, 5450, 5740, 6140 ]
    default: 2910

  motorcomm,tx-clk-adj-enabled:
    description: |
      This configuration is mainly to adapt to VF2 with JH7110 SoC.
      Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk.
    type: boolean

  motorcomm,tx-clk-10-inverted:
    description: |
      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
      Transmit PHY Clock delay train configuration when speed is 10Mbps.
    type: boolean

  motorcomm,tx-clk-100-inverted:
    description: |
      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
      Transmit PHY Clock delay train configuration when speed is 100Mbps.
    type: boolean

  motorcomm,tx-clk-1000-inverted:
    description: |
      Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
      Transmit PHY Clock delay train configuration when speed is 1000Mbps.
    type: boolean

unevaluatedProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy-mode = "rgmii-id";
        ethernet-phy@4 {
            /*  Only needed to make DT lint tools work. Do not copy/paste
             *  into real DTS files.
             */
            compatible = "ethernet-phy-id4f51.e91a";

            reg = <4>;
            rx-internal-delay-ps = <2100>;
            tx-internal-delay-ps = <150>;
            motorcomm,clk-out-frequency-hz = <0>;
            motorcomm,keep-pll-enabled;
            motorcomm,auto-sleep-disabled;
        };
    };
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy-mode = "rgmii";
        ethernet-phy@5 {
            /*  Only needed to make DT lint tools work. Do not copy/paste
             *  into real DTS files.
             */
            compatible = "ethernet-phy-id4f51.e91a";

            reg = <5>;
            motorcomm,clk-out-frequency-hz = <125000000>;
            motorcomm,keep-pll-enabled;
            motorcomm,auto-sleep-disabled;
        };
    };
