# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY

maintainers:
  - Krzysztof Kozlowski <krzk@kernel.org>
  - Marek Szyprowski <m.szyprowski@samsung.com>
  - Sylwester Nawrocki <s.nawrocki@samsung.com>

description: |
  For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
  compatible PHYs, the second cell in the PHY specifier identifies the
  PHY id, which is interpreted as follows::
    0 - UTMI+ type phy,
    1 - PIPE3 type phy.

  For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
  'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
  form of usbdrdphyN, N = 0, 1... (depending on number of controllers).

properties:
  compatible:
    enum:
      - google,gs101-usb31drd-phy
      - samsung,exynos5250-usbdrd-phy
      - samsung,exynos5420-usbdrd-phy
      - samsung,exynos5433-usbdrd-phy
      - samsung,exynos7-usbdrd-phy
      - samsung,exynos850-usbdrd-phy

  clocks:
    minItems: 2
    maxItems: 5

  clock-names:
    minItems: 2
    maxItems: 5
    description: |
      At least two clocks::
        - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
          for register access.
        - PHY reference clock (usually crystal clock), used for PHY operations,
          associated by phy name. It is used to determine bit values for clock
          settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
          in the CMU.

  "#phy-cells":
    const: 1

  port:
    $ref: /schemas/graph.yaml#/properties/port
    description:
      Any connector to the data bus of this controller should be modelled using
      the OF graph bindings specified.

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    minItems: 1
    items:
      - const: phy
      - const: pcs
      - const: pma

  samsung,pmu-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to PMU system controller interface.

  vbus-supply:
    description:
      VBUS power source.

  vbus-boost-supply:
    description:
      VBUS Boost 5V power source.

  pll-supply:
    description: Power supply for the USB PLL.
  dvdd-usb20-supply:
    description: DVDD power supply for the USB 2.0 phy.
  vddh-usb20-supply:
    description: VDDh power supply for the USB 2.0 phy.
  vdd33-usb20-supply:
    description: 3.3V power supply for the USB 2.0 phy.
  vdda-usbdp-supply:
    description: VDDa power supply for the USB DP phy.
  vddh-usbdp-supply:
    description: VDDh power supply for the USB DP phy.

required:
  - compatible
  - clocks
  - clock-names
  - "#phy-cells"
  - reg
  - samsung,pmu-syscon

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: google,gs101-usb31drd-phy
    then:
      properties:
        clocks:
          items:
            - description: Gate of main PHY clock
            - description: Gate of PHY reference clock
            - description: Gate of control interface AXI clock
            - description: Gate of control interface APB clock
            - description: Gate of SCL APB clock
        clock-names:
          items:
            - const: phy
            - const: ref
            - const: ctrl_aclk
            - const: ctrl_pclk
            - const: scl_pclk
        reg:
          minItems: 3
        reg-names:
          minItems: 3
      required:
        - reg-names
        - pll-supply
        - dvdd-usb20-supply
        - vddh-usb20-supply
        - vdd33-usb20-supply
        - vdda-usbdp-supply
        - vddh-usbdp-supply

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5433-usbdrd-phy
              - samsung,exynos7-usbdrd-phy
    then:
      properties:
        clocks:
          minItems: 5
          maxItems: 5
        clock-names:
          items:
            - const: phy
            - const: ref
            - const: phy_utmi
            - const: phy_pipe
            - const: itp
        reg:
          maxItems: 1
        reg-names:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - samsung,exynos5250-usbdrd-phy
              - samsung,exynos5420-usbdrd-phy
              - samsung,exynos850-usbdrd-phy
    then:
      properties:
        clocks:
          minItems: 2
          maxItems: 2
        clock-names:
          items:
            - const: phy
            - const: ref
        reg:
          maxItems: 1
        reg-names:
          maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/exynos5420.h>

    phy@12100000 {
        compatible = "samsung,exynos5420-usbdrd-phy";
        reg = <0x12100000 0x100>;
        #phy-cells = <1>;
        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
        clock-names = "phy", "ref";
        samsung,pmu-syscon = <&pmu_system_controller>;
        vbus-supply = <&usb300_vbus_reg>;
    };
