# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM6375 Display MDSS

maintainers:
  - Konrad Dybcio <konradybcio@kernel.org>

description:
  SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
  like DPU display controller, DSI and DP interfaces etc.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,sm6375-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display AHB clock
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: ahb
      - const: core

  iommus:
    maxItems: 1

  interconnects:
    items:
      - description: Interconnect path from mdp0 port to the data bus
      - description: Interconnect path from CPU to the reg bus

  interconnect-names:
    items:
      - const: mdp0-mem
      - const: cpu-cfg

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sm6375-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        items:
          - const: qcom,sm6375-dsi-ctrl
          - const: qcom,mdss-dsi-ctrl

  "^phy@[0-9a-f]+$":
    type: object
    additionalProperties: true

    properties:
      compatible:
        const: qcom,sm6375-dsi-phy-7nm

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/clock/qcom,sm6375-gcc.h>
    #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@5e00000 {
        compatible = "qcom,sm6375-mdss";
        reg = <0x05e00000 0x1000>;
        reg-names = "mdss";

        power-domains = <&dispcc MDSS_GDSC>;

        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
        clock-names = "iface", "ahb", "core";

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x820 0x2>;
        #address-cells = <1>;
        #size-cells = <1>;
        ranges;

        display-controller@5e01000 {
            compatible = "qcom,sm6375-dpu";
            reg = <0x05e01000 0x8e030>,
                  <0x05eb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
                     <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
            clock-names = "bus",
                          "iface",
                          "rot",
                          "lut",
                          "core",
                          "vsync",
                          "throttle";

            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            assigned-clock-rates = <19200000>;

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmpd SM6375_VDDCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
            };
        };

        dsi@5e94000 {
            compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
            reg = <0x05e94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";

            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmpd SM6375_VDDMX>;

            phys = <&mdss_dsi0_phy>;
            phy-names = "dsi";

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
        };

        mdss_dsi0_phy: phy@5e94400 {
            compatible = "qcom,sm6375-dsi-phy-7nm";
            reg = <0x05e94400 0x200>,
                  <0x05e94600 0x280>,
                  <0x05e94900 0x264>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
            clock-names = "iface", "ref";
        };
    };
...
